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UltraSPARC I/II has a 41-bit physical address space, UltraSPARC III/IV has a
43-bit physical address space. The Fujitsu SPARC64-VI extends this to 46 bits.
Adjust the TTE masks to take this into account and adjust some locore code
that truncated physical addresses to 41 bits (fixing a potential bug for
UltraSPARC III/IV too).
While there, fix the locore code for UltraSPARC Architecture 2007 CPUs, which
may support up to 56 bits of physical address space.
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lists; prevents use of ports corresponding to well-known services.
replace a couple of arc4random()%N with arc4random_uniform(N) that
missed the first round.
ok mcbride@
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state key is freed by pf_state_key_attach(). But in the case of NAT,
there are two state keys allocated, so we must free the second key
manually. Fixes a pf_state_key_pl leak seen in certain cases with
pfsync or with pf state-insert errors.
ok mcbride@ henning@
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interface switching, which kind of crashed the device.
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bus_space_{read,write}(). A bug in the code this was based on means that
this is also used for scatter gather maps, which are bus_dma memory, not
pci memory. This obviously fails. Pull them out into a function and
Special case scatter gather to use the mapped virtual address to write
instead. Makes writeback test pass on pci and pci express radeon cards.
Tested by, among others ckuethe@ and sthen@.
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three bits are for the current agp rate. not the lowest two. Otherwise we
preclude agp 4x mode.
It's a bit different for agp 3.0, but we don't have the bits for that yet.
Tested by several as part of a larger diff.
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skipping bitmasks to cover the entire 65536 port space - previously
they covered 512-1024 only.
sysctl needs to be updated to cope with this change; please
"make includes" before rebuilding it.
feedback millert@ ok millert@ deraadt@ markus@
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mfs is using the ffs code and its the same object it would make no sense
having two seperate pools...
ok art@
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pci_matchbyid(). This is the only driver that will match against
this hardware so it is not necessary to return a higher priority
than what pci_matchbyid() returns.
ok mbalmer@
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to all the scsi midlayer code into a local variable.
ok krw@ marco@
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as they're of the subclass SATA and the SiI3512 SATA controller as it is of
the subclass MISC.
ok jsg@
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it only provides the hosts machines clock as a timedelta sensor so far.
getting it into the tree so people can work on it as suggested by fgsch@
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30, 2005). From mjacob via FreeBSD. No known code dependency, and
prepares ground for major isp update.
Tested on a 2312 by dlg@.
ok dlg@ deraadt@
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ok henning@
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E2900/E4900/E6900/E20K/E25K systems). There's a fairly good chance it'll
just work.
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interrupt handler.
This is bad and wrong. So change it so that if we can't immediately grab
the hardware lock, to just leave the task flagged so that we can run it
when we release the lock. The linux implementation uses a similar
scheme.
Tested by guenther@, landry@ and bernd@. Also tested by many a while
ago as part of a larger diff.
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Intel don't publish the EST voltage tables, and they don't
even publish the MSRs for a shipping processor so we
can figure out how to do this in the backwards highest/lowest
way cleanly.
The mapping might look like the Core * one, but who really knows
for sure outside of a few guys at Intel. Other machines with
Atom processors and a different bus clock will have to be added
one by one until this stupidity changes.
Tested by bernd, ok gwk
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we want too load an mbuf; remove a printf that fires in case
we can't load the mbuf (We do error handling and recovery).
ok brad@, dlg@
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only when they are needed. Makes locations like -123d45m,-123d45m fit.
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ok jsg@
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ok jsg@
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better aligned for fast access. i didnt bench, so maybe this does nothing.
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discussed with otto, sthen, ckuethe. ok otto
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ok blambert@
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default interface. Nice side effect; Turns off the cams LED again.
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to be MASS_STORAGE subclass IDE regardless of id, and other
ids depending on the subclass and a known id or a known id
and the override flag.
We really want to check the subclass so we don't attach
pciide to the wrong function of a chip, which happened
last time around before the additional subclasses were
checked in the non override case and the overrides were pulled.
A bunch of the override flags were pulled after some common
subclasses (SATA/RAID) were added. So if we have a known
id and a SATA/RAID subclass we would match. Turns out some
Silicon Image SATA devices claim to be of subclass MISC
so add that as well. Unbreaks one of hennings machines
with 3114 SATA and likely quite a few other machines.
'seems safe enough to me' miod@
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have it.
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Serengeti and Starcat systems.
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systems that provides time of day services and (in the future) console
services.
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This makes the kernel properly enter the prom upon halt on the v1280.
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with it. Makes the bootloader work on the v1280 where the firmware breaks
into the firmware debugger instead of returning failure.
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this automatically, but the braindead firmware on the v1280 doesn't do this
and makes the allocation fail.
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(1 for sun4u, 2 for sun4v).
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entries. This is necessary on the v1280 where the firmware mixes 4MB and 8KB
mappings to map kernel text.
tested by miod@ and nick@
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the firmware on the v1280 doesn't like).
tested by many
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problem by adopting the same encoding used by Solaris for the kernel windows.
Note that this involves rearranging the trap vector tables, both fur sun4u and
for sun4v.
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on the v1280 doesn't like it if we change it behind its back.
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a) we're attempting to wake a specific process which
b) sleeps on a unique address
which means that there's no need to continue traversing the sleep
queue once the process has been found and awakened.
"looks good too me" thib@
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