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the first cpu on dual-cpu boards; this will be fixed later. Just don't
disable it at the prom.
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a complete physical address. Also add proper cpu pa<->device pa for dma
on Origin 200.
This lets xbridge work and route interrupts correctly on Origin 200.
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Otherwise we get stuck interrupted by the ``tx empty'' condition.
Also, on Origin 200 the second interrupt vector has to be computed
differently, which adds to the ``I wish I never had looked at this code''
trauma.
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correctly inherit queue stuff, tag, rtableid from the rule if we have no
state
some logic simplification and removal of redundant checks
ok dlg
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of uvmexp.free.
"yeah, go for it" art@
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From Kirill Timofeev
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for it.
It is very unlikely this still compiles, the hardware is dead. It isn't in any
arch's config file. the sparc sbus code is even commented out in files.sparc.
Not to mention that the code is fucking appauling, doesn't even know that sparc
got bus.h ages ago, still uses vtophys(), defines all types of functions to
arch-specific hacks.
I will miss the bitchy comments, though...
As a note to other drivers: this is the fate that awaits you if you screw up my
ctags on commonly used functions.
"you have my ok" claudio@, "zap zap zap" deraadt@
If i've missed any bits, please remove them.
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when we setmapsize it's not zero.
*sigh*
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zero so that we return an empty map on error.
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I just spent five hours looking in the wrong place because of this.
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binutils,gcc and so on. ok jmc@
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addresses is another diff.
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fraction of the wakeups and sleeps involved here actually grab that
lock. The remainder, on the other hand, always have the fpageq_lock
locked.
So, make this locking correct by switching the other users over to
fpageq_lock, too.
This would probably be better off being a semaphore, but for now at
least it's correct.
"ok, unless you want to implement semaphores" art@
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all other code do. Should fix pr 6121.
ok henning@
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little green slug does not block userland even when hammered with twice as
much traffic it can handle. Almost the same code I came up during h2k8 but
now with two other bugs fixed that where exposed by MCLGETI().
Tested and OK dlg@ sthen@ and a lot of pushing by Theo.
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this prevents an attacker from changing the TTAK (DoS attack) by
sending a frame with a large TSC but with a bad ICV and/or MIC.
now an attacker can only invalidate the cached TTAK.
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For the possibility of sleeping, the first two flags are UVM_PLA_WAITOK
and UVM_PLA_NOWAIT. It is an error not to show intention, so assert that
one of the two is provided. Switch over every caller in the tree to
using the appropriate flag.
ok art@, ariane@
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ok reyk@
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- Split up choosing of cpu between fork and "normal" cases. Fork is
very different and should be treated as such.
- Instead of implicitly choosing a cpu in setrunqueue, do it outside
where it actually makes sense.
- Just because a cpu is marked as idle doesn't mean it will be soon.
There could be a thundering herd effect if we call wakeup from an
interrupt handler, so subtract cpus with queued processes when
deciding which cpu is actually idle.
- some simplifications allowed by the above.
kettenis@ ok (except one bugfix that was not in the intial diff)
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function signature of bnx_tx_encap() such that people don't get weird ideas
like this again.
ok dlg@
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Fix up the one case of lock recursion (which blatantly ignored the
comment right above it saying that we don't need to lock). The rest of
the lock usage has been checked and appears to be correct.
ok ariane@.
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bus address space. Fixes a problem reported by david@.
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some years ago for KL enumeration, building on the existing XBow support
to limit ourselves to a single node for now.
This is a work-in-progress; it currently lacks complete interrupt code,
as well as PCI resource management. And there are likely bugs creeping
inside.
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of the Ethernet address.
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In snaps for a while (way too long, according to deraadt@)
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instead of assuming it is. Makes sure we actually spin up the secondary
CPUs on Serengeti machines with certain firmware revisions.
Tested by Christophe Latt.
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(virtual) machines.
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SuperIO part, the Ethernet part needs a whole driver); kernel now boot
single user (or bsd.rd). Joint work with jsing@
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hog the bus, and also to fake a valid interrupt register. The IOC3 device
is not a PCI device at all, but pretends to be one. Except its own
registers overlap the PCI configuration space, and some flavours do not
support disabling memory space in the control register, violating the PCI
specs. Fun.
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them manually.
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From brad
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specifically crafted IP datagram.
Problem noted by Sebastian Rother.
ok henning@ mcbride@ sthen@
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based on the BIOS memory map.
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processors, so the registers to configure addition HyperTransport links
are absent. Don't try attaching addition pci busses on these processors
to avoid probing non-existant registers.
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