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Right now when mi_switch picks up the same proc, we didn't clear the
flag which would mean that every time we service an AST we would attempt
a context switch. For some architectures, amd64 being probably the
most extreme, that meant attempting to context switch for every
trap and interrupt.
Now we clear_resched explicitly after every context switch, even if it
didn't do anything. Which also allows us to remove some more code
in cpu_switchto (not done yet).
miod@ ok
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the PCI host bridge if we're not running on an UltraBook. Fix allocation of
bus number such that it works on machines that have OpenBoot 4.x.
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asking for (GET_CUR) directly. This gets us better negotation values.
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splbio and won't delay clock interrupts.
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of making it dynamic and the smallest value above the former three. Idea
from NetBSD.
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set their desired image size, and therefore users can manipulate the
image size, too via the application.
Also tested by brad@
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independent executables using the uvm_map_pie() function to
randomize the load address. okay miod@, kettenis@, drahn@
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parameter and returns an aligned random load address for position
independent executables to use. This also adds three new vmparam.h
defines to specify the maximum address, minimum address and minimum
allowed alignment for uvm_map_pie() to use. The PIE address range
for i386 was carefully selected to work well within the i386 W^X
framework.
With much help and feedback from weingart@.
okay weingart@, miod@, kettenis@, drahn@
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o On non-strict alignment archs, dont copy the mbuf, every time, unload it, and send
it up the stack and just get a new one for the rx ring. We still do the copy on
strict alignment archs though...
o create a function to handle mbuf allocation for the rx ring, vr_mbuf_alloc(),
use it to allocate the mbufs and shuffle the bus dma setup around.
ideas/code from vic(4) and sis(4);
ok reyk@, brad@, dlg@
tested by many, been in snapshots for a while.
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chipset revision is not supported yet, so add it commented out.
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until I have time to implement proper fix.
Noted by several folks.
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halfway through. Makes the ISP12160 correctly load its firmware again on
sparc64.
ok krw@
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slightly different from the other chipsets using the BCM5705 ASIC.
ok jsg@
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ok deraadt@
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4 bytes in the new firmware.
To allow this to work on older firmwares add a "short read allowed"
flag to arc_msgbuf(), which will allow short reads by getting
the read length from the header of the response the firmware sends.
Only set the flag on the arc_msgbuf() call that deals with the diskinfo
struct for now.
Discussed with and ok dlg@
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For now, only one such flag is defined, PCKBC_CANT_TRANSLATE. It hints
pckbc that the device does not behave correctly to the ``set translation''
commands.
Set this flag if we are running on a Tadpole Ultrabook machine, which needs it.
This makes the built-in keyboard work correctly on this laptop (with the
help of the software translation pckbd diff).
tested & ok kettenis@
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1; instead, try table 2 first, then 1: some older keyboards, connected to
a castrated 8042, do not know how to talk in table 1 (or worse, will report
they do while they don't).
If automatic translation is not possible, remember which table the keyboard
ended configured in, and convert the scancodes from table 2 to table 1 if
necessary.
ok kettenis@
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gsckbd; the former will cause a proper translation page to be selected by
the keyboard.
Because of this, we no longer depend on the page the keyboard is left in
by the PDC (page 2 for all machines but the PrecisionBook, which is in
page 3), and there is no longer any need to use separate keyboard maps.
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restrict the memory allocation range in _dmamem_alloc().
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ok markus, also tested david sthen
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mode (4KB) for PCIe chips. This resolves the poor TX performance for
the PCIe chips. The result being a bit under double the TX performance
on a Gig connection (roughly 495 Mb/s -> 940 Mb/s).
Tested by reyk@, sthen@, brad@ and a few end users.
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that have it. Initial diff from art@.
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upcoming change.
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address 0x1a and 0x1e, and that's not where the PCIe capability stuff
lives. Potentially it was mucking with an IO BAR (super dangerous).
But probably it was achieving nothing at all.
ok dlg@, marco@, brad@
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Pointed out by Chris Cappuccio, thanks!
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newer PCI Express adapters (ie 8168C*/8102*) work.
V2 Checksum offload format in RTL8102 devices not yet supported.
No objections from brad@. Thanks to everyone who tested.
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sis_newbuf(), so remove the call.
ok and lots of prodding dlg@, brad@
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ok kettenis@
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All cpus are stopped and this cpu blocks all interrupts. It doesn't make
sense to grab locks that ddb can then jump past with longjmp.
Noticed by Pierre Riteau. I just forgot about the bug until reminded
today.
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ok art@
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and signal handlers.
ok kettenis@
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and signal handlers.
ok kettenis@
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problem found by "Adrian M. Whatley" <amw> and "Stephan A. Rickauer"
<stephan.rickauer>, both @ni.phys.ethz.ch
fix by me, ok mpf
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"Commitski!" miod@
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code. This fixes in6_ifloop_request warnings seen on carp interfaces.
OK henning@, found and tested by david@
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can use them later for stuff like VIDIOC_S_FMT (e.g. set custom
resolution).
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upcoming changes and sort list.
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ok dlg
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boot bsd.rd -a and want to mount the ramdisk later on.
ok otto@ krw@ millert@
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assumes that the display device and the agp bridge are the same device.
In almost all cases this is incorrect.
In order to correctly enable the agp device with the correct mode, we
need to set the AGP_COMMAND register on both the display and the bridge
with the right bits. Since agp is currently attaching at vga(4), due to
the problems with the intel integrated graphics (a problem that I still
need to solve, to be honest), for now just provide both pci_attach_args
to the agp init, and get what we need from there to do the enable.
This fixes the "agp bug" which i have been known to rant about, a lot.
So agp radeons now work with dri without needing to be forced to pci
mode.
This wasn't detected before, since the only non-drm consumer of agp is
the intel X driver, the i810 agp driver has its own enable function.
tested by many. ok kettenis@.
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