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curcpu when we were freeing a pmap. Tested and working for a few weeks
now, but I was a bit too busy to commit it earlier.
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we have, in order to pick a widget enumeration order matching the PROM.
This is especially important when the boot path is in dksc() syntax.
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used by onboard IOC chips, by forcing the IOC to trigger this interrupt,
and some help from the PCI bridge driver to report which interrupt has
fired through a fake PCI configuration register.
This works nicely on IP27 and IP35, but on IP30 the interrupt doesn't
happen, for some reason; so keep the existing heuristic in case the above
trick did not give us a valid interrupt number.
In case we got an interrupt, this will also detect IOC configurations where
there is actually one interrupt, should such configurations exist.
<rant style="beck">
I probably deserve to rot in hell for this abomination, but I won't mind
as long as the IOC designers who came with the bright ``let's use more than
one interrupt and defecate on the pci spec'' ideas are there, too.
</rant>
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drivers with callback routines. While there, skip disabled or failed
components.
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confusion. Make sure this function is invoked with interrupts enabled now.
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which may use WLAN too. for Intel Centrino 2 vPro only.
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via PR/6147. Shrink DSP225 while I'm it.
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ok claudio@
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a chip bug, which was supposed to be fixed in that particular revision of
the die but wasn't (tlbhandler.S 1.16).
Being lazy, I did not write a runtime selection of the appropriate TLB
handler code, although this was on my list.
It turns out that this fix confuses the hell of R10000 processors revision 3
(but not earlier 2.x revisions), to the point of making the Origin 200 here
hang so hard it would not even enter the NMI handler (don't ask me how I
figured this was the cause).
So it's time to choose the appropriate TLB handling flavour at runtime,
building the trampoline code from the fixed exception handler location
jumping to the handler address at runtime. As a bonus, kernels linked in
KSEG0 get the address computation optimized and thus a smaller trampoline
than before.
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big-endian arch where vlans were in use. Fix from Brad. Problem reported
and fix tested by Axton Grams, also tested by me. ok dlg@.
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ok jakemsr@
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PCI buses on xbridge.
In addition to this, we now support the limited IOMMU, allowing memory
outside of the 2GB direct window to be used for DMA.
Only tested on XBridge chip so far; this lets an IP35 machine with
physical memory after the 2GB boundary run stable again.
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which require it will provide their own _dmamem_alloc() in their own
bus_dma_tag_t.
While there, rename bus_dma_segment_t ds_vaddr member to _ds_vaddr to make
it clear this is an internal member.
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unsigned, like all the other callers of aps_do_io in aps do.
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Enable for IP/UDP/TCP receipt and IP transmit.
Keep disabled for UDP/TCP transmit because it breaks with pf(4) rdr.
ok sthen@
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of several times throughout the function, in and outside
of a loop.
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- add Pantech UM175 to umsm(4)
from Dan Colish on tech@; ok jsg.
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one new vendor id (Encore).
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from dhill@
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the pte.
This is currently unused, but will be used soon.
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and use those defines.
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similar to the aobj.c changes, this one does vnodes. Vnodes are more
complex because they actaully have to sync to backing store. So firstly,
convert sync to sleep instead of setting released.
Now, for backing store, in the PGO_FREE case, if we set PG_RELEASED
*before* an async io, (nothing else will see it, the page is busy), then
we can ignore the page after the io is done. We could do something
similar for PGO_DEACTIVATE too, but that is another change. On error we
just clear the released flag, nothing else sets it for uobj pages other
than aiodoned.
ok thib@, beck@, ariane@
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added the DDR3 bits. Take into account more of the spd
data and compute DDR3 module size in a way similiar to
NetBSD so it comes out correctly.
Tested by Olivier Cherrier and Christian Stuermer.
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there to trap.c which is its only user. This also cleans up multiple
inclusion of <machine/cpu.h> (because <machine/psl.h> includes it) in many
places.
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