Age | Commit message (Collapse) | Author |
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and sata ref clock in imxccm(4).
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clock in imxccm(4).
ok kettenis@
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Root Complex mode. In its current state it probably only works on the
Marvell Armada 7K and 8K SoCs, but the same core is used on many other cores
as well.
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SPI is already included and adding 32 means we skip the first 32 available
MSI vectors, which is quite disastous if we only have 32 vectors like on
the Marvell Armada 8040.
ok patrick@
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OK millert@ visa@
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OK millert@
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using the "a4x" bus tag for the non-console code in the fdt glue.
ok patrick@
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using the device tree.
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input & ok jsg
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that are mostly NS16550 compatible but use 32-bit instead of 8-bit registers
such as the Synopsys Designware UARTs found on many armv7, arm64 and amd64
SoCs.
tested by florian@, blum@
ok deraadt@
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enable the PLL even if the (optional) "fsl,anatop" property is not
available or if the regmap cannot be found.
Suggested by kettenis@
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calling imxccm using a special function.
ok kettenis@
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the USB charging detect so that we can replace the current code in
imxccm(4).
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from the clock framework, and instead always pass the driver's softc
as function parameter.
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that when we tackle it again.
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has currently not been set correctly. The phy speed is based on
IPG clock, not the Ethernet PLL divisor. Also when we bumped the
frequency base from kHz to Hz, we missed to update the divisor as
well. Clarify the formula being used to calculate the phy speed
and make use of the clock framework.
ok kettenis@
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Fixes softdep+UFS2. Found out the hard way by naddy@
ok visa@ naddy@ deraadt@
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to make it compile when enabled.
from hshoexer@
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support for using U-Boot's network layer. Since arm64 and armv7's
efiboot(8) have the same heritance the diffs from arm64 simply applied
to armv7.
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Network protocol or not.
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makes use of EFI's Simple Network protocol. This allows us to speak
raw network on U-Boot based machines so we can do TFTP boot on those as
well.
ok kettenis@
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endianness for convenience reasons. Especially in code pathes like TFTP
where the source port is read from the received UDP packet and used as
destination port in a new UDP packet this can be very harmful. Luckily
this issue has had no effect on our architectures since they never use
any of the code paths that could be harmful.
ok visa@
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SoCs.
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the mbuf packet header. Otherwise, stale mbuf state related to the
ARP request packet might affect the fate of the ARP reply packet.
For example, I observed that for an ARP request to a carp IP, where the
underlying carpdev interface is part of a bridge, ARP replies were always
sent out on the carpdev interface, even if the corresponding ARP request
was received not on the carpdev but on a different bridge member interface.
This happened because the M_PROTO1 mbuf flag was set on the ARP request mbuf
when it left the bridge towards carp, and was still set on the ARP reply,
which reused the same mbuf, sent back towards the bridge. The bridge's loop
detection saw the M_PROTO1 flag and prevented the ARP reply from entering
the bridge, so the reply was instead sent out directly on the carpdev...
ok bluhm@ mpi@
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arguments for /sbin/init.
For CPU 0 identifycpu() originally got called twice, once very early
from cpu_startup(), then again from cpu_attach(). Now we call
identifycpu() only from cpu_attach() with CPUF_PRIMARY set. So
make sure, that for CPU 0 nothing is skipped. Otherwise, cpu_info
might have different features set for CPU 0 than for all other CPUs.
This is similar to what amd64 does.
from hshoexer@; reported and fix tested by Emilio Perea; OK mlarkin@
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Switching from per PCB TSS to per CPU TSS broke kvm86 calls to the BIOS.
This change fixes the issues.
from hshoexer@; reported and tested by semarie@; OK deraadt@
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- provide a cpu_softc for cpu_attach() etc.
- replace per PCB TSS with per CPU TSS
The first change prepares for cpu_info being embedded in a
cpu_full_info. Therefore during autoconf/cpu_attach we hand down
a softc.
The second change removes the per PCB TSS. We now have one TSS per
CPU, thus in cpu_switchto() we only have to patch the ring 0 stack
pointer instead of loading a new TSS. This also allows for cleaning
up the GDT, so we only have a single slot for the TSS.
from hshoexer@; OK deraadt@
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Add ofw_regulator.c and its dependencies to fix build.
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better now with the FDT framework when we actually tackle PCIe.
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code in imxgpio(4) with splhigh() and splx() which is MI and should be
good enough for the job.
Discussed with kettenis@
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were not needed anymore since we switched to the FDT-based GPIO code.
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OK visa@
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