Age | Commit message (Collapse) | Author |
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ok patrick@
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Mercury, Bowie, Cash, Motorola and DEC all left us.
Just pf still has a default state table limit of 10000.
Had! Now it's a tiny little bit more, 100k.
lead guitar: me
ok chorus: phessler theo claudio benno
background school girl laughing: bob
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ENTRY is a trapsled. Fix a few functions which fall-through into an ENTRY
macro. amd64 binaries now are free of double+-nop sequences (except for one
assember nit in aes-586.pl). Previous changes by guenther got us here.
ok mortimer kettenis
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the state was created on this host, i. e. not for those pfsync-imported.
whether pfsync-imported states should be accounted is a seperate discussion,
but as things are, we only increment the counter in pf_create_state(), and
imported states don't excercise that path.
probably fixes the half-open states accounting underflow-wraparounds that
some people have been seeing.
ok sashan
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callbacks to be able to count dropped packet.
Having more generic statistics will help troubleshooting problems
with specific tunnels. Per-TDB counters are coming once all the
refactoring bits are in.
ok markus@
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why it was necessary.
OK bluhm@
'ok but watch for fallouts' mpi@
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OK kettenis@ visa@ mpi@
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variables can be delared constant.
OK claudio@ mpi@
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ok mpi@
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ok benno sashan
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by pf in the packet header. pf_delay_pkt reads the delay value from the packet
header, schedules a timeout and re-queues the packet when the timeout fires.
ok benno sashan
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seen by the stack.
This will allows us to debug port status changes without relying on
external tools, like lsusb(1), that generate I/O.
While here correct USB3 LS port defines.
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ok visa@, tb@
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ok mlarkin@ deraadt@ mpi@ kettenis@
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instead of passing sendsig() the code+type+val, pass a siginfo_t*
to copy from. Eliminate the indirection through struct emul for
sendsig(); we no longer have a SunOS4-compat version of sendsig()
ok deraadt@
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previously caught later but resulted in a guest termination, now we
use #GP as the SDM recommends.
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ok abieber@
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as it is impossoble to run an anything but a single-CPU machine with it.
ok mpi@, guenther@
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a custom kernel for over 20 years.
testing mlarkin@
ok deraadt@ phessler@ jca@ matthieu@
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the sensors code and user-controllable GPIO bus attachment but at the
same time hooks pcagpio(4) into the OFW GPIO framework so that it can
be used by other device tree based drivers.
Discussed with deraadt@
ok kettenis@
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change to rtsock.c. This simplifies the pfkey code since there is no special
wrapping needed and in general the PRU cases get easier.
OK bluhm@ henning@ mpi@
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route code since there is no more special wrapping needed and in some
places the PRU cases get easier because route(4) for example always connected.
OK bluhm@ henning@ mpi@
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hotpluggable PHYs whose status can either be read using an I2C-connected
PHY, or using in-band status management implemented in the controller
itself over SGMII. With this, 802.3z SFPs work on mvneta(4).
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unhandled exit function.
ok phessler
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problem discovered on bluhm@'s old opteron
ok deraadt@ kettenis@
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OK henning@ benno@
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Sort of a port from freebsd, but I had to write all the interesting bits
myself. Not very complete yet, but good enough to commit over.
ok kettenis@ deraadt@
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as implemented in the SolidRun Clearfog and Turris Omnia.
ok kettenis@
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ok kettenis@
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controllers.
ok kettenis@
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ok kettenis@
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extension to the GIC controller, which is represented as subnode in the
device tree. There can be multiple GICv2Ms, so it makes sense to attach
those to ampintc(4) as some kind of simplebus. The GICv2M is simply an
interrupt generator that can be used by PCIe devices to ring the door
bell. There is no need for further configuration, we only need to find
out which SPIs we are allowed to use for MSI and to register an edge
triggered interrupt on a (randomly) allocated SPI.
Implement support for interrupt types. The GIC only seems to support
level triggered active-high or egdge triggered low-to-high interrupts.
We currently always configure them to be level triggered, which is a
sane default for most controllers. Since MSI interupts on the GIC are
edge triggered, we need to be able to parse the type information and to
configure the interrupt correspondingly.
ok kettenis@
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will be used by the PCIe controller to set up the memory regions for the
PCIe devices. Also export the PCIe IO and MEM address regions. These
will be used to setup the PCIe extents.
ok kettenis@
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the memory in uvm. Another process could use the false 0 then. To
be on the safe side, protect all access to ku_indx and ku_pagecnt
with a mutex. Update ku_indx and ku_pagecnt before calling
uvm_km_free(). Update ksp after uvm_km_free() to keep accounting
correct.
tested by sthen@; OK mpi@ visa@ deraadt@
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ok sthen@
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ok mlarkin@ mortimer@
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ok beck@ deraadt@ guenther@ mpi@
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ok benno@ mpi@
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