Age | Commit message (Collapse) | Author |
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Part of a larger patch by James Hastings.
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So set the appropriate scan capability flags in the ic.
ok sthen@
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a slight priority in cases where good matches exist in either band.
ok sthen@
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corresponding bit in the iwm(4) Tx command regardless of frame length.
ok sthen@
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when fiddling with packets but without the mess that motivated Henning to
remove it. Affects only this one aspect of Henning's checksum work. Also tweak
the basic algorithm and supply a correctness argument.
OK dlg@ deraadt@ sthen@; no objection henning@
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everybody gets to test!
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everybody gets to test!
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value.
Specs from mikeb@, ok dlg@
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IP_SENDSRCADDR == IP_RECVDSTADDR.
OK sthen@ jca@ bluhm@
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filesystem the tree can change behind our back, resulting in stale cache
entries. "The only winning move is not to play."
ok tedu beck mpi
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numbers serve as a warning not to touch them.
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Microsoft has performed a significant clean up and stylistic improvement
of Hyper-V structure definitions and updated FreeBSD port. We update to
stay in sync with the upstream and improve maintainability of this code
in the future.
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from PMON2000 and has not been enabled on OpenBSD.
Suggested by and ok miod@ (after seeing a quad_t cleanup patch of mine)
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These are functionally equivolent so it didn't matter and the resulting
code doesn't change.
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This allows rt_if_remove() to remove RTF_BROACAST routes from down
interfaces.
Issue reported by Dimitris Papastamos on bugs@
ok dlg@, claudio@, phessler@
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This allows glue drivers to set the type based on other information (such as
Oopen Firmware or device tree properties) without going through to risky
code paths.
ok deraadt@, visa@
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A flag which indicates whether HT has been negotiated with a node,
and the current Tx MCS value we use for a node.
This grows struct ieee80211_nodereq. Applications using it must be recompiled.
ok mpi@
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other ARMv7 CPUs have a L2 cache that is larger than 32KB. And some of those
even have L1 caches larger than that. So bailing out after 32KB will leave
the cache partially dirty.
Fixes the SATA problems on Allwinner A20 based boards.
ok patrick@
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main attachment, the serial port is now longer recognized as console.
To fix this, store the OFW node of the initial console and check it
in the attachment driver.
ok kettenis@
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be known as sximmc(4) and is somewhat functional. Still needs proper clock
support and some further cleanup.
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and 1. As a result rgephy(4) attaches twice. Prevent this from happening
by passing the PHY address, which is part of the device tree, down from the
bus-specific glue to the generic driver code.
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This typically works for every simplebus client, but com(4) did not
make use of the supplied bus tag. Instead it references the global
a4x bus tag. This is needed as the ARM com(4) controllers use 4-byte
spaced registers, while com(4) operates on 1-byte. To be able to make
use of the address translation, copy the a4x bus tag and replace the
cookie and map function with the one supplied by simplebus.
ok kettenis@
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rename it to fit the typical scheme of such an attachment driver.
ok kettenis@ jsg@
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IWM_CMD_* values are bit flags. The same was done 2 years ago
in Linux git commit a10229271946731959b2269370d0492d88cfab23.
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ok mpi@ visa@
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ok jsg@
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Tested by Daniel Bolgheroni on a Cubietech Cubieboard2.
ok jsg@
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under the assumption, that fuse_vget() has reasonable semantics, while
this is not the case. fusefs_vget() only functions correctly, if the
file in questions has recently been accessed and is still in the vnode
cache of the userspace daemon associated with the mount point.
As a matter of fact the fuse api doesn't feature a reasonable way to map
inode numbers to a handle at all (see struct fuse_operations).
ok guenther
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already does it.
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for the reference counting.
ok dlg@
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and bpfwrite(), all of which will need to grabe a lock to protect the
buffers.
ok dlg@
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descriptor is referenced before it is inserted in the global list.
ok dlg@
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trigger to 1 character. This fixes a hang seen on the allwinner,sun5i-r8
board during boot when the driver switches to interrupts and no terminal
is attached.
ok kettenis
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by patrick@.
ok deraadt@
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ok kettenis@
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Generic xscale support and support for pxa2x0 used by zaurus remains.
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toggling the bit, clearing it when already set. On Cortex-A7 setting the SMP
bit is essential since without it the CPU doesn't actually use its caches.
The SMP bit supposed to be set before turning on the caches and the MMU, so
move the setting of the Auxiliary Control Register before setting the
System Control Register.
ok jsg@
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ok tedu@
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that support the Execute-Inhibit exception. This makes user space W^X
effective on Octeon Plus and later Octeon versions.
Feedback from miod@, thanks!
No objection from deraadt@
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de is amazing(tm). it really should be cut back and simplified a bit.
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drivers that fill that field in too.
quad types are going away.
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guenther is proposing the removal of u_quad_t. uint64_t is more portable.
tested on a perc5 and perc6, no functional change.
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working gigabit on the Allwinner A20. Probably won't work yet on other
Allwinner SoCs due to differences in how the clocks get set up.
Based on an earlier diff from patrick@.
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ok kettenis@ krw@ natano@ dlg@ espie@
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