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2013-02-08- remove ununsed PCI_ANY_ID macrosJasper Lievisse Adriaanse
ok dlg@
2013-02-08add another DFE-530TX+Jasper Lievisse Adriaanse
ok sthen@
2013-02-08regenJasper Lievisse Adriaanse
2013-02-08add another DFE-530TX+ which happens to have a quirky vendor ID. use that IDJasper Lievisse Adriaanse
instead of going down the PCI_ANY_ID path. as discussed with and ok by sthen@
2013-02-08Insufficient levels of hops in the local brew led to Theo and I muckingPhilip Guenther
up the VFS calls in the error paths in coredump() Pointed out by armani@, ok beck@
2013-02-07Bring back reserve enforcement and page daemon wakeup into uvm_pglistalloc,Bob Beck
It was removed as this function was redone to use pmemrange in mid 2010 with the result that kernel malloc and other users of this function can consume the page daemon reserve and run us out of memory. ok kettenis@
2013-02-07make sure the page daemon considers BUFPAGES_INACT when decidingBob Beck
to do work, just as is done when waking it up. tested by me, phessler@, espie@, landry@ ok kettenis@
2013-02-07Sync.Paul Irofti
2013-02-07Add Radeon HD 7290.Paul Irofti
Found in a dmesg from Carsten Kunze on bugs@. Okay brynet@.
2013-02-07Remove dead code.Martin Pieuchot
ok mikeb@
2013-02-07convert mbuf tags to use pool(9) as a backend storage;Mike Belopuhov
ok markus claudio haesbaert henning
2013-02-06add pppx(4) interfaces to the "pppx" interface group, as done for variousStuart Henderson
other interface types. suggested/tested Mattieu Baptiste, ok dlg@ yasuoka@ giovanni@, ifconfig(8) reminder jmc@
2013-02-06Check for __PIC__, not PIC, as some files in libc will only see the former.Miod Vallat
Fixes the few TEXTREL which crept in libc.so.
2013-02-05Make the inet6 and inet cases in in_pcbrtentry() look similar.Alexander Bluhm
No functional change. OK millert@
2013-02-05netflow v10 omitted the sysUpTime flow set header field fromFlorian Obser
v9. Without it it's not possible to find out at what time a flow started/ended with only flowStartSysUpTime/flowEndSysUpTime. Fix this by using flowStartSeconds/flowEndSeconds for v10. Problem reported by Chris Ivancic and Colin Ligertwood, analyzed by benno@ Tested by benno@ against nprobe (which doesn't care that much one way or the other) Tested by Chris Ivancic against solarwinds collector. OK benno@
2013-02-05Do not profile the various ipi functions. This is a requirement for theMartin Pieuchot
upcoming per-CPU profiling modifications and it does not make much sense to profile such low-level functions anyway. ok kettenis@, miod@
2013-02-04The firmware isn't always happy with the length of the "join BSS" commandMark Kettenis
that we send. It seems to want some extra padding, but it isn't entirely clear how much. So pass the size of the entire buffer that we allocate for this command instead, which seems to always work. ok stsp@
2013-02-04Set sa_len correctly for PF_INET (and be consistent with the PF_INET6Todd C. Miller
case). On our platforms, sizeof(struct sockaddr) matches sizeof(struct sockaddr_in) so this hasn't caused problems but it is still incorrect. From Anthony Low. OK martynas@ bluhm@
2013-02-04some stuff i found in old storedge 3500 disk trays seem to work fine.David Gwynne
2013-02-03Let the octeon kernel link properly.Brian Callahan
ok miod@
2013-02-02- remove product/vendor table and let the driver attach based on class, etc.Federico G. Schwindt
- print what type of device is. tested by sthen@. similar diff tested by jasper@ and gonzalo@. ok mpi@ and sthen@ if you have one of these devices please give it a try and mail the details.
2013-02-02mvme68k ELF bits. Boot block updates heavily based upon the recent mvme88kMiod Vallat
a.out->ELF transition.
2013-02-02hp300 ELF bits. Requires many device and prom related structs to now be declaredMiod Vallat
as packed due to them containing 32-bit types at 16-bit but not 32-bit aligned offsets. The boot block updates (especially mkboot) come straight from NetBSD.
2013-02-02Kernel bits for m68k/ELF, mostly from NetBSD. In addition, the `pmod' symbelMiod Vallat
in fpsp has to be renamed due to a clash with other parts of the kernel.
2013-02-01Rewrite the receive filter handling code and cleanup the ioctl bits.Brad Smith
ok jsg@ krw@
2013-01-31welcome to 5.3-BETAMiod Vallat
2013-01-30In doreadlinkat(), only access auio.uio_resid if it's already beenMatthew Dempsky
initialized. (In the case where it wasn't initialized, the computed *retval ends up getting clobbered by the EINVAL error anyway so it's not an info leak, but it's still technically undefined behavior.) pointed out by Maxime Villard on tech ok guenther
2013-01-30backout 5718/5719/5720 support. the diff breaks the 5704C on my xserve g5David Gwynne
and i cant fix it without breaking a 5721 in another box. sthen@ agrees it is sad.
2013-01-297 &&'ed elements in a single KASSERT involving complex tests is just painfulBob Beck
when you hit it. Separate out these tests. ok millert@ kettenis@, phessler@, with miod@ bikeshedding.
2013-01-29Rewrite the receive filter handling code and cleanup the ioctl bits.Brad Smith
ok sthen@
2013-01-29- Set ENETRESET within myx_ioctl() instead of calling myx_iff() directly, to beBrad Smith
consistent with other drivers. - Clear IFF_ALLMULTI flag early and at the top of myx_iff(). - Set IFF_ALLMULTI when in promisc mode. ok dlg@
2013-01-29Rewrite the receive filter handling code and cleanup the ioctl bits.Brad Smith
Fixes a bug when going in and out of promiscuous mode results in the driver not disabling all multicast mode. Tested by kili@ jasper@
2013-01-29Add the PCI id for the D-Link DFE-520TX C1 board.Brad Smith
ok jsg@
2013-01-29the bus_space api implies that there's a bus endianness that it willDavid Gwynne
swap for you to the hosts endianness. sometimes you dont want this hand holding and just want raw access to the registers. bus_space does have stuff to do this already, but they deal with buffers which can be awkward if you just want to get or set a single register. this adds the following to i386 and amd64: bus_space_read_raw_2() bus_space_read_raw_4() bus_space_read_raw_8() bus_space_write_raw_2() bus_space_write_raw_4() bus_space_write_raw_8() sparc64 already implements this, even though it wasnt part of the official api. how handy. i'll do other archs as i can. kettenis@ and miod@ seem ok with this
2013-01-29big pullup of bge to support the 5718 family of chips including theDavid Gwynne
5719 and 5720 chips that have popped up in a lot of new machines. this diff is largely a merge of the freebsd code. thanks to srebrenko sehic for providing me hardware to do the work on. also, a huge thanks to claudio for trawling through the diff to fix merge issues, understand the changes, and actually make it work. tested by sthen@ naddy@ jmatthew@ claudio@ jj@ and me tested chips include: bge0 at pci2 dev 3 function 0 "Broadcom BCM5704C" rev 0x10, BCM5704 B0 (0x2100): apic 2 int 8, address 00:30:48:59:52:44 brgphy0 at bge0 phy 1: BCM5704 10/100/1000baseT PHY, rev. 0 bge0 at pci3 dev 0 function 0 "Broadcom BCM5723" rev 0x10, BCM5784 A1 (0x5784100): apic 2 int 18, address e4:11:5b:12:bd:d6 brgphy0 at bge0 phy 1: BCM5784 10/100/1000baseT PHY, rev. 4 bge0 at pci3 dev 4 function 0 "Broadcom BCM5714" rev 0xa3, BCM5715 A3 (0x9003): ivec 0x795, address 00:14:4f:a9:34:90 brgphy0 at bge0 phy 1: BCM5714 10/100/1000baseT/SX PHY, rev. 0 bge0 at pci2 dev 0 function 0 "Broadcom BCM5761" rev 0x10, BCM5761 A1 (0x5761100): apic 2 int 18, address 00:10:18:4b:23:b4 brgphy0 at bge0 phy 1: BCM5761 10/100/1000baseT PHY, rev. 0 bge0 at pci0 dev 5 function 0 "Broadcom BCM5702X" rev 0x02, BCM5702/5703 A2 (0x1002): eb164 irq 2, address 00:10:18:00:98:e9 brgphy0 at bge0 phy 1: BCM5703 10/100/1000baseT PHY, rev. 2 bge0 at pci2 dev 2 function 0 "Broadcom BCM5703" rev 0x00, BCM5702/5703 A2 (0x1002): ivec 0x7dc, address 00:14:4f:16:a0:23 and of course: bge1 at pci5 dev 0 function 0 "Broadcom BCM5720" rev 0x00, BCM5720 A0 (0x5720000), APE firmware NCSI 1.0.85.0: apic 0 int 16, address d4:ae:52:a7:05:38 brgphy1 at bge1 phy 1: BCM5720C 10/100/1000baseT PHY, rev. 0 bge2 at pci5 dev 0 function 1 "Broadcom BCM5720" rev 0x00, BCM5720 A0 (0x5720000), APE firmware NCSI 1.0.85.0: apic 0 int 17, address d4:ae:52:a7:05:39 brgphy2 at bge2 phy 2: BCM5720C 10/100/1000baseT PHY, rev. 0 either sthen@ or i will be around to handle any issues after this commit.
2013-01-28Make ulpt(4) upload firmware into HP LaserJet printers which require firmware.Stefan Sperling
ok mpi@
2013-01-28regenStefan Sperling
2013-01-28Add USB device IDs for HP LaserJet printers which require firmware.Stefan Sperling
ok sthen mpi
2013-01-28Add TX interrupt mitigation for vr(4) chips, loosely based on FreeBSD,Darren Tucker
but with tweaks so it works on 6105Ms like those found in pcengines alix and soekris 5501s. ok sthen@, help brad chris mikeb dlg jsing There may be other 610x chips that would benefit from the VR_Q_INTDISABLE quirk, please send me a dmesg if you can confirm it works.
2013-01-27Bump MAXTSIZ to 128 MB, some binaries are quite large.Federico G. Schwindt
Agreed with millert@ and guenther@
2013-01-27Correct the PBA size used for PCH adapters (26KB).Brad Smith
From FreeBSD ok jsg@
2013-01-26Make sure new processes get a clean FPU configuration upon startup, byMiod Vallat
resetting the appropriate register in setregs(). Similar in spirit to what m68k does (restoring a null frame), and necessary since m88k doesn't do lazy fpu switching.
2013-01-25Add _KERNEL guard to hide dprintf macro from userland.Brad Smith
ok millert@
2013-01-25Updates for beagle/panda work. OK patrick@ and miod@Brandon Mercer
2013-01-25the event type is a 16bit value, not 32bit. use htole16 instead of htole32.David Gwynne
mpii(4) works on sparc64 with this.
2013-01-25we go to a lot of effort to post the first tx descriptor last, but weDavid Gwynne
really should be trying to post everything except the flags field in the first tx descriptor. this shuffles things around so the rest of that first txd is posted as part of the "everything else" before its flags field.
2013-01-25the myx_dmamem struct doesnt need a name.David Gwynne
2013-01-23ARMv7 doesn't support the atomic SWP instruction anymore. Use the atomicPatrick Wildt
load and store instructions instead. ok miod@
2013-01-23Add instruction fault register functions, which will be needed for furtherPatrick Wildt
ARMv7 support. ok miod@
2013-01-23Change interface and span interface lists from LIST to TAILQ.Camiel Dobbelaar
This way the configuration order is preserved. Order matters because MAC address are not unique: vlan interfaces can have the same MAC as their parent. Frames destined for the bridge itself are now delivered to the first-configured interface that matches the MAC instead of the last-configured. This means that the bridge behavior does not suddenly change anymore when adding a vlan interface. ok henning reyk (a while ago)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 21:36:58 +0000