From 09cb1063a99b711d222f0052c0b5fdb2729cbaa5 Mon Sep 17 00:00:00 2001 From: Jonathan Gray Date: Tue, 29 Jan 2019 05:51:31 +0000 Subject: add AMDGPUCodeGen --- gnu/usr.bin/clang/libLLVMAMDGPUCodeGen/Makefile | 102 ++++++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 gnu/usr.bin/clang/libLLVMAMDGPUCodeGen/Makefile diff --git a/gnu/usr.bin/clang/libLLVMAMDGPUCodeGen/Makefile b/gnu/usr.bin/clang/libLLVMAMDGPUCodeGen/Makefile new file mode 100644 index 00000000000..b73a4c35a9c --- /dev/null +++ b/gnu/usr.bin/clang/libLLVMAMDGPUCodeGen/Makefile @@ -0,0 +1,102 @@ +# $OpenBSD: Makefile,v 1.1 2019/01/29 05:51:30 jsg Exp $ + +LIB= LLVMAMDGPUCodeGen +NOPIC= +NOPROFILE= + +CPPFLAGS+= -I${.OBJDIR}/../include/llvm/AMDGPU \ + -I${LLVM_SRCS}/lib/Target/AMDGPU + +.include +SRCS= AMDGPUAliasAnalysis.cpp \ + AMDGPUAlwaysInlinePass.cpp \ + AMDGPUAnnotateKernelFeatures.cpp \ + AMDGPUAnnotateUniformValues.cpp \ + AMDGPUArgumentUsageInfo.cpp \ + AMDGPUAsmPrinter.cpp \ + AMDGPUCallLowering.cpp \ + AMDGPUCodeGenPrepare.cpp \ + AMDGPUFrameLowering.cpp \ + AMDGPUHSAMetadataStreamer.cpp \ + AMDGPUInstrInfo.cpp \ + AMDGPUInstructionSelector.cpp \ + AMDGPUIntrinsicInfo.cpp \ + AMDGPUISelDAGToDAG.cpp \ + AMDGPUISelLowering.cpp \ + AMDGPULegalizerInfo.cpp \ + AMDGPULibCalls.cpp \ + AMDGPULibFunc.cpp \ + AMDGPULowerIntrinsics.cpp \ + AMDGPULowerKernelArguments.cpp \ + AMDGPULowerKernelAttributes.cpp \ + AMDGPUMachineCFGStructurizer.cpp \ + AMDGPUMachineFunction.cpp \ + AMDGPUMachineModuleInfo.cpp \ + AMDGPUMacroFusion.cpp \ + AMDGPUMCInstLower.cpp \ + AMDGPUOpenCLEnqueuedBlockLowering.cpp \ + AMDGPUPromoteAlloca.cpp \ + AMDGPURegAsmNames.inc.cpp \ + AMDGPURegisterBankInfo.cpp \ + AMDGPURegisterInfo.cpp \ + AMDGPURewriteOutArguments.cpp \ + AMDGPUSubtarget.cpp \ + AMDGPUTargetMachine.cpp \ + AMDGPUTargetObjectFile.cpp \ + AMDGPUTargetTransformInfo.cpp \ + AMDGPUUnifyDivergentExitNodes.cpp \ + AMDGPUUnifyMetadata.cpp \ + AMDGPUInline.cpp \ + AMDGPUPerfHintAnalysis.cpp \ + AMDILCFGStructurizer.cpp \ + GCNHazardRecognizer.cpp \ + GCNIterativeScheduler.cpp \ + GCNMinRegStrategy.cpp \ + GCNRegPressure.cpp \ + GCNSchedStrategy.cpp \ + R600AsmPrinter.cpp \ + R600ClauseMergePass.cpp \ + R600ControlFlowFinalizer.cpp \ + R600EmitClauseMarkers.cpp \ + R600ExpandSpecialInstrs.cpp \ + R600FrameLowering.cpp \ + R600InstrInfo.cpp \ + R600ISelLowering.cpp \ + R600MachineFunctionInfo.cpp \ + R600MachineScheduler.cpp \ + R600OpenCLImageTypeLoweringPass.cpp \ + R600OptimizeVectorRegisters.cpp \ + R600Packetizer.cpp \ + R600RegisterInfo.cpp \ + SIAnnotateControlFlow.cpp \ + SIDebuggerInsertNops.cpp \ + SIFixSGPRCopies.cpp \ + SIFixVGPRCopies.cpp \ + SIFixWWMLiveness.cpp \ + SIFoldOperands.cpp \ + SIFormMemoryClauses.cpp \ + SIFrameLowering.cpp \ + SIInsertSkips.cpp \ + SIInsertWaitcnts.cpp \ + SIInstrInfo.cpp \ + SIISelLowering.cpp \ + SILoadStoreOptimizer.cpp \ + SILowerControlFlow.cpp \ + SILowerI1Copies.cpp \ + SIMachineFunctionInfo.cpp \ + SIMachineScheduler.cpp \ + SIMemoryLegalizer.cpp \ + SIOptimizeExecMasking.cpp \ + SIOptimizeExecMaskingPreRA.cpp \ + SIPeepholeSDWA.cpp \ + SIRegisterInfo.cpp \ + SIShrinkInstructions.cpp \ + SIWholeQuadMode.cpp \ + GCNILPSched.cpp + +.PATH: ${.CURDIR}/../../../llvm/lib/Target/AMDGPU + +install: + @# Nothing here so far ... + +.include -- cgit v1.2.3