From 18668e4eb3bcc3172992ccebe28df6e9a0ce9766 Mon Sep 17 00:00:00 2001 From: Kenneth R Westerback Date: Thu, 29 Jun 2000 00:04:33 +0000 Subject: Sync adw files with (almost) latest NetBSD versions: adw.c synched with v1.23 (from v1.14) adw.h v1.9 ( v1.5 ) adwlib.c v1.17 ( v1.7 ) adwlib.h v1.13 ( v1.7 ) adwmcode.c v1.5 ( v1.2 ) adwmcode.h v1.5 ( v1.2 ) microcode for cards is updated to latest version, loss of carrier problems are solved in a more robust manner than before, lots of code cleanup. first support for upcoming U3W cards added, as a result of which the driver is now too large for RAMDISK and has been moved to RAMDISKB. Most of the work done by dante@ NetBSD. --- sys/dev/ic/adw.c | 636 +++++++----- sys/dev/ic/adw.h | 59 +- sys/dev/ic/adwlib.c | 2675 +++++++++++++++++++++++-------------------------- sys/dev/ic/adwlib.h | 654 +++++------- sys/dev/ic/adwmcode.c | 2077 +++++++++++++++++++++++++------------- sys/dev/ic/adwmcode.h | 183 +++- 6 files changed, 3493 insertions(+), 2791 deletions(-) diff --git a/sys/dev/ic/adw.c b/sys/dev/ic/adw.c index bad2cdfe30b..d0a6fd54d6b 100644 --- a/sys/dev/ic/adw.c +++ b/sys/dev/ic/adw.c @@ -1,5 +1,5 @@ -/* $OpenBSD: adw.c,v 1.6 2000/04/29 21:05:32 krw Exp $ */ -/* $NetBSD: adw.c,v 1.14 2000/02/12 19:19:42 thorpej Exp $ */ +/* $OpenBSD: adw.c,v 1.7 2000/06/29 00:04:31 krw Exp $ */ +/* $NetBSD: adw.c,v 1.23 2000/05/27 18:24:50 dante Exp $ */ /* * Generic driver for the Advanced Systems Inc. SCSI controllers @@ -49,6 +49,7 @@ #include #include #include +#include #include #include @@ -61,6 +62,7 @@ #include #include +#include #include #ifndef DDB @@ -75,8 +77,6 @@ static struct scsi_xfer *adw_dequeue __P((ADW_SOFTC *)); static int adw_alloc_controls __P((ADW_SOFTC *)); static int adw_alloc_carriers __P((ADW_SOFTC *)); -static int adw_create_carriers __P((ADW_SOFTC *)); -static int adw_init_carrier __P((ADW_SOFTC *, ADW_CARRIER *)); static int adw_create_ccbs __P((ADW_SOFTC *, ADW_CCB *, int)); static void adw_free_ccb __P((ADW_SOFTC *, ADW_CCB *)); static void adw_reset_ccb __P((ADW_CCB *)); @@ -91,8 +91,11 @@ static void adwminphys __P((struct buf *)); static void adw_isr_callback __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); static void adw_async_callback __P((ADW_SOFTC *, u_int8_t)); +static void adw_print_info __P((ADW_SOFTC *, int)); + static int adw_poll __P((ADW_SOFTC *, struct scsi_xfer *, int)); static void adw_timeout __P((void *)); +static void adw_reset_bus __P((ADW_SOFTC *)); /******************************************************************************/ @@ -102,7 +105,7 @@ struct cfdriver adw_cd = { NULL, "adw", DV_DULL }; -/* the below structure is so we have a default dev struct for out link struct */ +/* the below structure is so we have a default dev struct for our link struct */ struct scsi_device adw_dev = { NULL, /* Use default error handler */ @@ -112,10 +115,6 @@ struct scsi_device adw_dev = }; -#define ADW_ABORT_TIMEOUT 10000 /* time to wait for abort (mSec) */ -#define ADW_WATCH_TIMEOUT 10000 /* time to wait for watchdog (mSec) */ - - /******************************************************************************/ /* scsi_xfer queue routines */ /******************************************************************************/ @@ -162,7 +161,7 @@ adw_dequeue(sc) } /******************************************************************************/ -/* Control Blocks routines */ +/* DMA Mapping for Control Blocks */ /******************************************************************************/ @@ -222,23 +221,23 @@ adw_alloc_carriers(sc) /* * Allocate the control structure. */ - sc->sc_control->carriers = malloc(ADW_CARRIER_SIZE * ADW_MAX_CARRIER, + sc->sc_control->carriers = malloc(sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, M_DEVBUF, M_WAITOK); if(!sc->sc_control->carriers) { - printf("%s: malloc() failed in allocating carrier structures," - " error = %d\n", sc->sc_dev.dv_xname, error); - return (error); + printf("%s: malloc() failed in allocating carrier structures\n", + sc->sc_dev.dv_xname); + return (ENOMEM); } if ((error = bus_dmamem_alloc(sc->sc_dmat, - ADW_CARRIER_SIZE * ADW_MAX_CARRIER, - NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { + sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, + 0x10, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { printf("%s: unable to allocate carrier structures," " error = %d\n", sc->sc_dev.dv_xname, error); return (error); } if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, - ADW_CARRIER_SIZE * ADW_MAX_CARRIER, + sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, (caddr_t *) &sc->sc_control->carriers, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { printf("%s: unable to map carrier structures," @@ -250,8 +249,8 @@ adw_alloc_carriers(sc) * Create and load the DMA map used for the control blocks. */ if ((error = bus_dmamap_create(sc->sc_dmat, - ADW_CARRIER_SIZE * ADW_MAX_CARRIER, 1, - ADW_CARRIER_SIZE * ADW_MAX_CARRIER, 0, BUS_DMA_NOWAIT, + sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 1, + sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 0,BUS_DMA_NOWAIT, &sc->sc_dmamap_carrier)) != 0) { printf("%s: unable to create carriers DMA map," " error = %d\n", sc->sc_dev.dv_xname, error); @@ -259,109 +258,20 @@ adw_alloc_carriers(sc) } if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_carrier, sc->sc_control->carriers, - ADW_CARRIER_SIZE * ADW_MAX_CARRIER, NULL, + sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, NULL, BUS_DMA_NOWAIT)) != 0) { printf("%s: unable to load carriers DMA map," " error = %d\n", sc->sc_dev.dv_xname, error); return (error); } - error = bus_dmamap_create(sc->sc_dmat, ADW_CARRIER_SIZE* ADW_MAX_CARRIER, - 1, ADW_CARRIER_SIZE * ADW_MAX_CARRIER, - 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, - &sc->sc_control->dmamap_xfer); - if (error) { - printf("%s: unable to create Carrier DMA map, error = %d\n", - sc->sc_dev.dv_xname, error); - return (error); - } - return (0); } -/* - * Create a set of Carriers and add them to the free list. Called once - * by adw_init(). We return the number of Carriers successfully created. - */ -static int -adw_create_carriers(sc) - ADW_SOFTC *sc; -{ - ADW_CARRIER *carr; - u_int32_t carr_next = NULL; - int i, error; - - for(i=0; i < ADW_MAX_CARRIER; i++) { - carr = (ADW_CARRIER *)(((u_int8_t *)sc->sc_control->carriers) + - (ADW_CARRIER_SIZE * i)); - if ((error = adw_init_carrier(sc, carr)) != 0) { - printf("%s: unable to initialize carrier, error = %d\n", - sc->sc_dev.dv_xname, error); - return (i); - } - carr->next_vpa = carr_next; - carr_next = carr->carr_pa; - carr->id = i; - } - sc->carr_freelist = carr; - return (i); -} - - -static int -adw_init_carrier(sc, carr) - ADW_SOFTC *sc; - ADW_CARRIER *carr; -{ - u_int32_t carr_pa; - int /*error, */hashnum; - - /* - * Create the DMA map for all of the Carriers. - */ -/* error = bus_dmamap_create(sc->sc_dmat, ADW_CARRIER_SIZE, - 1, ADW_CARRIER_SIZE, - 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, - &carr->dmamap_xfer); - if (error) { - printf("%s: unable to create Carrier DMA map, error = %d\n", - sc->sc_dev.dv_xname, error); - return (error); - } -*/ - /* - * put in the phystokv hash table - * Never gets taken out. - */ - carr_pa = ADW_CARRIER_ADDR(sc, carr); - carr->carr_pa = carr_pa; - hashnum = CARRIER_HASH(carr_pa); - carr->nexthash = sc->sc_carrhash[hashnum]; - sc->sc_carrhash[hashnum] = carr; - - return(0); -} - - -/* - * Given a physical address, find the Carrier that it corresponds to. - */ -ADW_CARRIER * -adw_carrier_phys_kv(sc, carr_phys) - ADW_SOFTC *sc; - u_int32_t carr_phys; -{ - int hashnum = CARRIER_HASH(carr_phys); - ADW_CARRIER *carr = sc->sc_carrhash[hashnum]; - - while (carr) { - if (carr->carr_pa == carr_phys) - break; - carr = carr->nexthash; - } - return (carr); -} +/******************************************************************************/ +/* Control Blocks routines */ +/******************************************************************************/ /* @@ -455,6 +365,7 @@ adw_init_ccb(sc, ccb) hashnum = CCB_HASH(ccb->hashkey); ccb->nexthash = sc->sc_ccbhash[hashnum]; sc->sc_ccbhash[hashnum] = ccb; + timeout_set( &ccb->to, adw_timeout, ccb ); adw_reset_ccb(ccb); return (0); } @@ -528,14 +439,15 @@ adw_queue_ccb(sc, ccb, retry) ADW_CCB *ccb; int retry; { - int errcode; + int errcode = ADW_SUCCESS; - if(!retry) + if(!retry) { TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain); + } while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) { - errcode = AdvExeScsiQueue(sc, &ccb->scsiq); + errcode = AdwExeScsiQueue(sc, &ccb->scsiq); switch(errcode) { case ADW_SUCCESS: break; @@ -551,9 +463,10 @@ adw_queue_ccb(sc, ccb, retry) } TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain); + TAILQ_INSERT_TAIL(&sc->sc_pending_ccb, ccb, chain); if ((ccb->xs->flags & SCSI_POLL) == 0) - timeout(adw_timeout, ccb, (ccb->timeout * hz) / 1000); + timeout_add(&ccb->to, (ccb->timeout * hz) / 1000); } return(errcode); @@ -561,7 +474,7 @@ adw_queue_ccb(sc, ccb, retry) /******************************************************************************/ -/* SCSI layer interfacing routines */ +/* SCSI layer interfacing routines */ /******************************************************************************/ @@ -583,17 +496,15 @@ adw_init(sc) if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) { panic("adw_init: adw_find_signature failed"); } else { - AdvResetChip(sc->sc_iot, sc->sc_ioh); + AdwResetChip(sc->sc_iot, sc->sc_ioh); - warn_code = (sc->chip_type == ADV_CHIP_ASC3550)? - AdvInitFrom3550EEP(sc) : - AdvInitFrom38C0800EEP(sc); + warn_code = AdwInitFromEEPROM(sc); - if (warn_code & ASC_WARN_EEPROM_CHKSUM) + if (warn_code & ADW_WARN_EEPROM_CHKSUM) printf("%s: Bad checksum found. " "Setting default values\n", sc->sc_dev.dv_xname); - if (warn_code & ASC_WARN_EEPROM_TERMINATION) + if (warn_code & ADW_WARN_EEPROM_TERMINATION) printf("%s: Bad bus termination setting." "Using automatic termination.\n", sc->sc_dev.dv_xname); @@ -602,7 +513,7 @@ adw_init(sc) sc->isr_callback = (ADW_CALLBACK) adw_isr_callback; sc->async_callback = (ADW_CALLBACK) adw_async_callback; - return (0); + return 0; } @@ -615,6 +526,7 @@ adw_attach(sc) TAILQ_INIT(&sc->sc_free_ccb); TAILQ_INIT(&sc->sc_waiting_ccb); + TAILQ_INIT(&sc->sc_pending_ccb); LIST_INIT(&sc->sc_queue); @@ -648,53 +560,57 @@ adw_attach(sc) if (error) return; /* (error) */ ; - bzero(sc->sc_control->carriers, ADW_CARRIER_SIZE * ADW_MAX_CARRIER); - - i = adw_create_carriers(sc); - if (i == 0) { - printf("%s: unable to create Carriers\n", - sc->sc_dev.dv_xname); - return; /* (ENOMEM) */ ; - } else if (i != ADW_MAX_CARRIER) { - printf("%s: WARNING: only %d of %d Carriers created\n", - sc->sc_dev.dv_xname, i, ADW_MAX_CARRIER); - } - + /* + * Zero's the freeze_device status + */ + bzero(sc->sc_freeze_dev, sizeof(sc->sc_freeze_dev)); /* - * Initialize the ASC3550. + * Initialize the adapter */ - error = (sc->chip_type == ADV_CHIP_ASC3550)? - AdvInitAsc3550Driver(sc) : - AdvInitAsc38C0800Driver(sc); - switch (error) { - case ASC_IERR_MCODE_CHKSUM: + switch (AdwInitDriver(sc)) { + case ADW_IERR_BIST_PRE_TEST: + panic("%s: BIST pre-test error", + sc->sc_dev.dv_xname); + break; + + case ADW_IERR_BIST_RAM_TEST: + panic("%s: BIST RAM test error", + sc->sc_dev.dv_xname); + break; + + case ADW_IERR_MCODE_CHKSUM: panic("%s: Microcode checksum error", sc->sc_dev.dv_xname); break; - case ASC_IERR_ILLEGAL_CONNECTION: + case ADW_IERR_ILLEGAL_CONNECTION: panic("%s: All three connectors are in use", sc->sc_dev.dv_xname); break; - case ASC_IERR_REVERSED_CABLE: + case ADW_IERR_REVERSED_CABLE: panic("%s: Cable is reversed", sc->sc_dev.dv_xname); break; - case ASC_IERR_SINGLE_END_DEVICE: + case ADW_IERR_HVD_DEVICE: + panic("%s: HVD attached to LVD connector", + sc->sc_dev.dv_xname); + break; + + case ADW_IERR_SINGLE_END_DEVICE: panic("%s: single-ended device is attached to" " one of the connectors", sc->sc_dev.dv_xname); break; - case ASC_IERR_NO_CARRIER: - panic("%s: no carrier", + case ADW_IERR_NO_CARRIER: + panic("%s: unable to create Carriers", sc->sc_dev.dv_xname); break; - case ASC_WARN_BUSRESET_ERROR: + case ADW_WARN_BUSRESET_ERROR: printf("%s: WARNING: Bus Reset Error\n", sc->sc_dev.dv_xname); break; @@ -752,10 +668,20 @@ adw_scsi_cmd(xs) * called with the first queue entry as our argument. */ if (xs == sc->sc_queue.lh_first) { + if(sc->sc_freeze_dev[xs->sc_link->target]) { + splx(s); + return (TRY_AGAIN_LATER); + } + xs = adw_dequeue(sc); fromqueue = 1; nowait = 1; } else { + if(sc->sc_freeze_dev[xs->sc_link->target]) { + splx(s); + xs->error = XS_DRIVER_STUFFUP; + return (TRY_AGAIN_LATER); + } /* Polled requests can't be queued for later. */ dontqueue = xs->flags & SCSI_POLL; @@ -827,7 +753,6 @@ retryagain: case ADW_ERROR: xs->error = XS_DRIVER_STUFFUP; return (COMPLETE); - } /* @@ -879,8 +804,13 @@ adw_build_req(xs, ccb, flags) /* * Set CDB length and copy it to the request structure. + * For wide boards a CDB length maximum of 16 bytes + * is supported. */ - bcopy(xs->cmd, &scsiqp->cdb, scsiqp->cdb_len = xs->cmdlen); + bcopy(xs->cmd, &scsiqp->cdb, ((scsiqp->cdb_len = xs->cmdlen) <= 12)? + xs->cmdlen : 12 ); + if(xs->cmdlen > 12) + bcopy(&(xs->cmd[12]), &scsiqp->cdb16, xs->cmdlen - 12); scsiqp->target_id = sc_link->target; scsiqp->target_lun = sc_link->lun; @@ -888,9 +818,7 @@ adw_build_req(xs, ccb, flags) scsiqp->vsense_addr = &ccb->scsi_sense; scsiqp->sense_addr = sc->sc_dmamap_control->dm_segs[0].ds_addr + ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense); -/* scsiqp->sense_addr = ccb->hashkey + - offsetof(struct adw_ccb, scsi_sense); -*/ scsiqp->sense_len = sizeof(struct scsi_sense_data); + scsiqp->sense_len = sizeof(struct scsi_sense_data); /* * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command. @@ -1003,6 +931,11 @@ adw_build_sglist(ccb, scsiqp, sg_block) } +/******************************************************************************/ +/* Interrupts and TimeOut routines */ +/******************************************************************************/ + + int adw_intr(arg) void *arg; @@ -1011,7 +944,7 @@ adw_intr(arg) struct scsi_xfer *xs; - if(AdvISR(sc) != ADW_FALSE) { + if(AdwISR(sc) != ADW_FALSE) { /* * If there are queue entries in the software queue, try to * run the first one. We should be more or less guaranteed @@ -1067,43 +1000,200 @@ adw_timeout(arg) s = splbio(); - /* - * If it has been through before, then a previous abort has failed, - * don't try abort again, reset the bus instead. - */ if (ccb->flags & CCB_ABORTED) { /* * Abort Timed Out - * Lets try resetting the bus! + * + * No more opportunities. Lets try resetting the bus and + * reinitialize the host adapter. */ + timeout_del( &ccb->to ); printf(" AGAIN. Resetting SCSI Bus\n"); - ccb->flags &= ~CCB_ABORTED; - /* AdvResetSCSIBus() will call sbreset_callback() */ - AdvResetSCSIBus(sc); + adw_reset_bus(sc); + splx(s); + return; + } else if (ccb->flags & CCB_ABORTING) { + /* + * Abort the operation that has timed out. + * + * Second opportunity. + */ + printf("\n"); + xs->error = XS_TIMEOUT; + ccb->flags |= CCB_ABORTED; +#if 0 + /* + * - XXX - 3.3a microcode is BROKEN!!! + * + * We cannot abort a CCB, so we can only hope the command + * get completed before the next timeout, otherwise a + * Bus Reset will arrive inexorably. + */ + /* + * ADW_ABORT_CCB() makes the board to generate an interrupt + * + * - XXX - The above assertion MUST be verified (and this + * code changed as well [callout_*()]), when the + * ADW_ABORT_CCB will be working again + */ + ADW_ABORT_CCB(sc, ccb); +#endif + /* + * waiting for multishot callout_reset() let's restart it + * by hand so the next time a timeout event will occour + * we will reset the bus. + */ + timeout_add( &ccb->to, (ccb->timeout * hz) / 1000); } else { /* - * Abort the operation that has timed out + * Abort the operation that has timed out. + * + * First opportunity. */ printf("\n"); xs->error = XS_TIMEOUT; ccb->flags |= CCB_ABORTING; - /* ADW_ABORT_CCB() will implicitly call isr_callback() */ +#if 0 + /* + * - XXX - 3.3a microcode is BROKEN!!! + * + * We cannot abort a CCB, so we can only hope the command + * get completed before the next 2 timeout, otherwise a + * Bus Reset will arrive inexorably. + */ + /* + * ADW_ABORT_CCB() makes the board to generate an interrupt + * + * - XXX - The above assertion MUST be verified (and this + * code changed as well [callout_*()]), when the + * ADW_ABORT_CCB will be working again + */ ADW_ABORT_CCB(sc, ccb); +#endif + /* + * waiting for multishot callout_reset() let's restart it + * by hand so to give a second opportunity to the command + * which timed-out. + */ + timeout_add( &ccb->to, (ccb->timeout * hz) / 1000); } splx(s); } +static void +adw_reset_bus(sc) + ADW_SOFTC *sc; +{ + ADW_CCB *ccb; + int s; + + s = splbio(); + AdwResetSCSIBus(sc); + while((ccb = TAILQ_LAST(&sc->sc_pending_ccb, + adw_pending_ccb)) != NULL) { + timeout_del( &ccb->to ); + TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); + TAILQ_INSERT_HEAD(&sc->sc_waiting_ccb, ccb, chain); + } + adw_queue_ccb(sc, TAILQ_FIRST(&sc->sc_waiting_ccb), 1); + splx(s); +} + + /******************************************************************************/ -/* WIDE boards Interrupt callbacks */ +/* Host Adapter and Peripherals Information Routines */ +/******************************************************************************/ + + +static void +adw_print_info(sc, tid) + ADW_SOFTC *sc; + int tid; +{ +#ifdef ADW_DEBUG + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; + u_int16_t wdtr_able, wdtr_done, wdtr; + u_int16_t sdtr_able, sdtr_done, sdtr, period; + static int wdtr_reneg = 0, sdtr_reneg = 0; + + if (tid == 0){ + wdtr_reneg = sdtr_reneg = 0; + } +#endif + + printf("%s: target %d ", sc->sc_dev.dv_xname, tid); + +#ifdef ADW_DEBUG + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, wdtr_able); + if(wdtr_able & ADW_TID_TO_TIDMASK(tid)) { + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, wdtr_done); + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE + + (2 * tid), wdtr); + printf("using %d-bits wide, ", (wdtr & 0x8000)? 16 : 8); + if((wdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0) + wdtr_reneg = 1; + } else { + printf("wide transfers disabled, "); + } + + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); + if(sdtr_able & ADW_TID_TO_TIDMASK(tid)) { + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, sdtr_done); + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE + + (2 * tid), sdtr); + sdtr &= ~0x8000; + if((sdtr & 0x1F) != 0) { + if((sdtr & 0x1F00) == 0x1100){ + printf("80.0 MHz"); + } else if((sdtr & 0x1F00) == 0x1000){ + printf("40.0 MHz"); + } else { + /* <= 20.0 MHz */ + period = (((sdtr >> 8) * 25) + 50)/4; + if(period == 0) { + /* Should never happen. */ + printf("? MHz"); + } else { + printf("%d.%d MHz", 250/period, + ADW_TENTHS(250, period)); + } + } + printf(" synchronous transfers\n"); + } else { + printf("asynchronous transfers\n"); + } + if((sdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0) + sdtr_reneg = 1; + } else { + printf("synchronous transfers disabled\n"); + } + + if(wdtr_reneg || sdtr_reneg) { + printf("%s: target %d %s", sc->sc_dev.dv_xname, tid, + (wdtr_reneg)? ((sdtr_reneg)? "wide/sync" : "wide") : + ((sdtr_reneg)? "sync" : "") ); + printf(" renegotiation pending before next command.\n"); + } +#endif +} + + +/******************************************************************************/ +/* WIDE boards Interrupt callbacks */ /******************************************************************************/ /* - * adw_isr_callback() - Second Level Interrupt Handler called by AdvISR() + * adw_isr_callback() - Second Level Interrupt Handler called by AdwISR() * * Interrupt callback function for the Wide SCSI Adv Library. + * + * Notice: + * Interrupts are disabled by the caller (AdwISR() function), and will be + * enabled at the end of the caller. */ static void adw_isr_callback(sc, scsiq) @@ -1114,23 +1204,12 @@ adw_isr_callback(sc, scsiq) ADW_CCB *ccb; struct scsi_xfer *xs; struct scsi_sense_data *s1, *s2; -// int s; ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); - untimeout(adw_timeout, ccb); + timeout_del( &ccb->to ); -/* if(ccb->flags & CCB_ABORTING) { - printf("Retrying request\n"); - ccb->flags &= ~CCB_ABORTING; - ccb->flags |= CCB_ABORTED; - s = splbio(); - adw_queue_ccb(sc, ccb); - splx(s); - return; - } -*/ xs = ccb->xs; /* @@ -1143,90 +1222,162 @@ adw_isr_callback(sc, scsiq) BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(dmat, ccb->dmamap_xfer); } + if ((ccb->flags & CCB_ALLOC) == 0) { printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname); Debugger(); return; } - /* - * Check for an underrun condition. - */ - /* - * if (xs->request_bufflen != 0 && scsiqp->data_cnt != 0) { - * ASC_DBG1(1, "adw_isr_callback: underrun condition %lu bytes\n", - * scsiqp->data_cnt); underrun = ASC_TRUE; } - */ + /* * 'done_status' contains the command's ending status. + * 'host_status' conatins the host adapter status. + * 'scsi_status' contains the scsi peripheral status. */ - switch (scsiq->done_status) { - case QD_NO_ERROR: + if ((scsiq->host_status == QHSTA_NO_ERROR) && + ((scsiq->done_status == QD_NO_ERROR) || + (scsiq->done_status == QD_WITH_ERROR))) { switch (scsiq->host_status) { - case QHSTA_NO_ERROR: + case SCSI_STATUS_GOOD: + if ((scsiq->cdb[0] == INQUIRY) && + (scsiq->target_lun == 0)) { + adw_print_info(sc, scsiq->target_id); + } xs->error = XS_NOERROR; - xs->resid = 0; + xs->resid = scsiq->data_cnt; + sc->sc_freeze_dev[scsiq->target_id] = 0; break; + + case SCSI_STATUS_CHECK_CONDITION: + case SCSI_STATUS_CMD_TERMINATED: + s1 = &ccb->scsi_sense; + s2 = &xs->sense; + *s2 = *s1; + xs->error = XS_SENSE; + sc->sc_freeze_dev[scsiq->target_id] = 1; + break; + default: - /* QHSTA error occurred. */ - xs->error = XS_DRIVER_STUFFUP; + xs->error = XS_BUSY; + sc->sc_freeze_dev[scsiq->target_id] = 1; break; } - break; - - case QD_WITH_ERROR: + } else if (scsiq->done_status == QD_ABORTED_BY_HOST) { + xs->error = XS_DRIVER_STUFFUP; + } else { switch (scsiq->host_status) { - case QHSTA_NO_ERROR: - switch(scsiq->scsi_status) { - case SS_CHK_CONDITION: - case SS_CMD_TERMINATED: - s1 = &ccb->scsi_sense; - s2 = &xs->sense; - *s2 = *s1; - xs->error = XS_SENSE; - break; - case SS_TARGET_BUSY: - case SS_RSERV_CONFLICT: - case SS_QUEUE_FULL: - xs->error = XS_DRIVER_STUFFUP; - break; - case SS_CONDITION_MET: - case SS_INTERMID: - case SS_INTERMID_COND_MET: - xs->error = XS_DRIVER_STUFFUP; - break; - case SS_GOOD: - break; - } + case QHSTA_M_SEL_TIMEOUT: + xs->error = XS_SELTIMEOUT; break; - case QHSTA_M_SEL_TIMEOUT: + case QHSTA_M_SXFR_OFF_UFLW: + case QHSTA_M_SXFR_OFF_OFLW: + case QHSTA_M_DATA_OVER_RUN: + printf("%s: Overrun/Overflow/Underflow condition\n", + sc->sc_dev.dv_xname); xs->error = XS_DRIVER_STUFFUP; break; - default: - /* Some other QHSTA error occurred. */ + case QHSTA_M_SXFR_DESELECTED: + case QHSTA_M_UNEXPECTED_BUS_FREE: + printf("%s: Unexpected BUS free\n",sc->sc_dev.dv_xname); xs->error = XS_DRIVER_STUFFUP; break; - } - break; - case QD_ABORTED_BY_HOST: - xs->error = XS_DRIVER_STUFFUP; - break; + case QHSTA_M_SCSI_BUS_RESET: + case QHSTA_M_SCSI_BUS_RESET_UNSOL: + printf("%s: BUS Reset\n", sc->sc_dev.dv_xname); + xs->error = XS_DRIVER_STUFFUP; + break; - default: - xs->error = XS_DRIVER_STUFFUP; - break; + case QHSTA_M_BUS_DEVICE_RESET: + printf("%s: Device Reset\n", sc->sc_dev.dv_xname); + xs->error = XS_DRIVER_STUFFUP; + break; + + case QHSTA_M_QUEUE_ABORTED: + printf("%s: Queue Aborted\n", sc->sc_dev.dv_xname); + xs->error = XS_DRIVER_STUFFUP; + break; + + case QHSTA_M_SXFR_SDMA_ERR: + case QHSTA_M_SXFR_SXFR_PERR: + case QHSTA_M_RDMA_PERR: + /* + * DMA Error. This should *NEVER* happen! + * + * Lets try resetting the bus and reinitialize + * the host adapter. + */ + printf("%s: DMA Error. Reseting bus\n", + sc->sc_dev.dv_xname); + TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); + adw_reset_bus(sc); + xs->error = XS_BUSY; + goto done; + + case QHSTA_M_WTM_TIMEOUT: + case QHSTA_M_SXFR_WD_TMO: + /* The SCSI bus hung in a phase */ + printf("%s: Watch Dog timer expired. Reseting bus\n", + sc->sc_dev.dv_xname); + TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); + adw_reset_bus(sc); + xs->error = XS_BUSY; + goto done; + + case QHSTA_M_SXFR_XFR_PH_ERR: + printf("%s: Transfer Error\n", sc->sc_dev.dv_xname); + xs->error = XS_DRIVER_STUFFUP; + break; + + case QHSTA_M_BAD_CMPL_STATUS_IN: + /* No command complete after a status message */ + printf("%s: Bad Completion Status\n", + sc->sc_dev.dv_xname); + xs->error = XS_DRIVER_STUFFUP; + break; + + case QHSTA_M_AUTO_REQ_SENSE_FAIL: + printf("%s: Auto Sense Failed\n", sc->sc_dev.dv_xname); + xs->error = XS_DRIVER_STUFFUP; + break; + + case QHSTA_M_INVALID_DEVICE: + printf("%s: Invalid Device\n", sc->sc_dev.dv_xname); + xs->error = XS_DRIVER_STUFFUP; + break; + + case QHSTA_M_NO_AUTO_REQ_SENSE: + /* + * User didn't request sense, but we got a + * check condition. + */ + printf("%s: Unexpected Check Condition\n", + sc->sc_dev.dv_xname); + xs->error = XS_DRIVER_STUFFUP; + break; + + case QHSTA_M_SXFR_UNKNOWN_ERROR: + printf("%s: Unknown Error\n", sc->sc_dev.dv_xname); + xs->error = XS_DRIVER_STUFFUP; + break; + + default: + panic("%s: Unhandled Host Status Error %x", + sc->sc_dev.dv_xname, scsiq->host_status); + } } - adw_free_ccb(sc, ccb); + TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain); +done: adw_free_ccb(sc, ccb); xs->flags |= ITSDONE; scsi_done(xs); } /* - * adv_async_callback() - Adv Library asynchronous event callback function. + * adw_async_callback() - Adv Library asynchronous event callback function. */ static void adw_async_callback(sc, code) @@ -1235,25 +1386,30 @@ adw_async_callback(sc, code) { switch (code) { case ADV_ASYNC_SCSI_BUS_RESET_DET: - /* - * The firmware detected a SCSI Bus reset. - */ + /* The firmware detected a SCSI Bus reset. */ + printf("%s: SCSI Bus reset detected\n", sc->sc_dev.dv_xname); break; case ADV_ASYNC_RDMA_FAILURE: /* * Handle RDMA failure by resetting the SCSI Bus and - * possibly the chip if it is unresponsive. Log the error - * with a unique code. + * possibly the chip if it is unresponsive. */ - AdvResetSCSIBus(sc); + printf("%s: RDMA failure. Resetting the SCSI Bus and" + " the adapter\n", sc->sc_dev.dv_xname); + AdwResetSCSIBus(sc); break; case ADV_HOST_SCSI_BUS_RESET: - /* - * Host generated SCSI bus reset occurred. - */ - break; + /* Host generated SCSI bus reset occurred. */ + printf("%s: Host generated SCSI bus reset occurred\n", + sc->sc_dev.dv_xname); + break; + + case ADV_ASYNC_CARRIER_READY_FAILURE: + /* Carrier Ready failure. */ + printf("%s: Carrier Ready failure!\n", sc->sc_dev.dv_xname); + break; default: break; diff --git a/sys/dev/ic/adw.h b/sys/dev/ic/adw.h index 0012ddb0eb6..546fd34dfb6 100644 --- a/sys/dev/ic/adw.h +++ b/sys/dev/ic/adw.h @@ -1,5 +1,5 @@ -/* $OpenBSD: adw.h,v 1.4 2000/04/29 20:15:59 krw Exp $ */ -/* $NetBSD: adw.h,v 1.5 2000/02/03 20:29:15 dante Exp $ */ +/* $OpenBSD: adw.h,v 1.5 2000/06/29 00:04:31 krw Exp $ */ +/* $NetBSD: adw.h,v 1.9 2000/05/26 15:13:43 dante Exp $ */ /* * Generic driver definitions and exported functions for the Advanced @@ -48,47 +48,6 @@ typedef int (* ADW_ISR_CALLBACK) (ADW_SOFTC *, ADW_SCSI_REQ_Q *); typedef void (* ADW_ASYNC_CALLBACK) (ADW_SOFTC *, u_int8_t); -/* - * Every adw_carrier structure _MUST_ always be aligned on a 16 bytes boundary - */ -struct adw_carrier { -/* ---------- the microcode wants the field below ---------- */ - u_int32_t unused; /* Carrier Virtual Address -UNUSED- */ - u_int32_t carr_pa; /* Carrier Physical Address */ - u_int32_t areq_vpa; /* ADW_SCSI_REQ_Q Physical Address */ - /* - * next_vpa [31:4] Carrier Physical Next Pointer - * - * next_vpa [3:1] Reserved Bits - * next_vpa [0] Done Flag set in Response Queue. - */ - u_int32_t next_vpa; -/* ---------- ---------- */ - struct adw_carrier *nexthash; /* Carrier Virtual Address */ - - int id; - /* - * This DMA map maps the buffer involved in the carrier transfer. - */ -// bus_dmamap_t dmamap_xfer; -}; - -typedef struct adw_carrier ADW_CARRIER; - -#define ADW_CARRIER_SIZE ((((int)((sizeof(ADW_CARRIER)-1)/16))+1)*16) - - -/* - * Mask used to eliminate low 4 bits of carrier 'next_vpa' field. - */ -#define ASC_NEXT_VPA_MASK 0xFFFFFFF0 - -#define ASC_RQ_DONE 0x00000001 -#define ASC_CQ_STOPPER 0x00000000 - -#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK) - - /* * per request scatter-gather element limit * We could have up to 256 SG lists. @@ -110,8 +69,6 @@ struct adw_ccb { ADW_SCSI_REQ_Q scsiq; ADW_SG_BLOCK sg_block[ADW_NUM_SG_BLOCK]; - ADW_CARRIER *carr_list; /* carriers involved */ - struct scsi_sense_data scsi_sense; TAILQ_ENTRY(adw_ccb) chain; @@ -122,6 +79,8 @@ struct adw_ccb { int flags; /* see below */ int timeout; + struct timeout to; + /* * This DMA map maps the buffer involved in the transfer. */ @@ -136,20 +95,13 @@ typedef struct adw_ccb ADW_CCB; #define CCB_ABORTED 0x04 -#define ADW_MAX_CARRIER 20 /* Max. number of host commands (253) */ -#define ADW_MAX_CCB 16 /* Max. number commands per device (63) */ +#define ADW_MAX_CCB 63 /* Max. number commands per device (63) */ struct adw_control { ADW_CCB ccbs[ADW_MAX_CCB]; /* all our control blocks */ ADW_CARRIER *carriers; /* all our carriers */ - bus_dmamap_t dmamap_xfer; }; -/* - * Offset of a carrier from the beginning of the carriers DMA mapping. - */ -#define ADW_CARRIER_ADDR(sc, x) ((sc)->sc_dmamap_carrier->dm_segs[0].ds_addr + \ - (((u_long)x) - ((u_long)(sc)->sc_control->carriers))) /* * Offset of a CCB from the beginning of the control DMA mapping. */ @@ -162,7 +114,6 @@ int adw_init __P((ADW_SOFTC *sc)); void adw_attach __P((ADW_SOFTC *sc)); int adw_intr __P((void *arg)); ADW_CCB *adw_ccb_phys_kv __P((ADW_SOFTC *, u_int32_t)); -ADW_CARRIER *adw_carrier_phys_kv __P((ADW_SOFTC *, u_int32_t)); /******************************************************************************/ diff --git a/sys/dev/ic/adwlib.c b/sys/dev/ic/adwlib.c index a3f86d6759c..d55eb20c8d5 100644 --- a/sys/dev/ic/adwlib.c +++ b/sys/dev/ic/adwlib.c @@ -1,5 +1,5 @@ -/* $OpenBSD: adwlib.c,v 1.8 2000/04/29 21:07:17 krw Exp $ */ -/* $NetBSD: adwlib.c,v 1.7 2000/02/03 20:29:15 dante Exp $ */ +/* $OpenBSD: adwlib.c,v 1.9 2000/06/29 00:04:31 krw Exp $ */ +/* $NetBSD: adwlib.c,v 1.17 2000/05/27 18:24:50 dante Exp $ */ /* * Low level routines for the Advanced Systems Inc. SCSI controllers chips @@ -43,7 +43,7 @@ /* * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters * - * Copyright (c) 1995-1999 Advanced System Products, Inc. + * Copyright (c) 1995-2000 Advanced System Products, Inc. * All Rights Reserved. * * Redistribution and use in source and binary forms, with or without @@ -73,26 +73,32 @@ #include #include -#include #include +#include /* Static Functions */ -static u_int16_t AdvGet3550EEPConfig __P((bus_space_tag_t, bus_space_handle_t, - ADW_EEP_3550_CONFIG *)); -static u_int16_t AdvGet38C0800EEPConfig __P((bus_space_tag_t, bus_space_handle_t, - ADW_EEP_38C0800_CONFIG *)); -static u_int16_t AdvReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int)); -static void AdvWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); -static void AdvSet3550EEPConfig __P((bus_space_tag_t, bus_space_handle_t, - ADW_EEP_3550_CONFIG *)); -static void AdvSet38C0800EEPConfig __P((bus_space_tag_t, bus_space_handle_t, - ADW_EEP_38C0800_CONFIG *)); -static void AdvInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); +int AdwRamSelfTest __P((bus_space_tag_t, bus_space_handle_t, u_int8_t)); +int AdwLoadMCode __P((bus_space_tag_t, bus_space_handle_t, u_int16_t *, + u_int8_t)); +int AdwASC3550Cabling __P((bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *)); +int AdwASC38C0800Cabling __P((bus_space_tag_t, bus_space_handle_t, + ADW_DVC_CFG *)); +int AdwASC38C1600Cabling __P((bus_space_tag_t, bus_space_handle_t, + ADW_DVC_CFG *)); + +static u_int16_t AdwGetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t, + ADW_EEPROM *)); +static void AdwSetEEPROMConfig __P((bus_space_tag_t, bus_space_handle_t, + ADW_EEPROM *)); +static u_int16_t AdwReadEEPWord __P((bus_space_tag_t, bus_space_handle_t, int)); +static void AdwWaitEEPCmd __P((bus_space_tag_t, bus_space_handle_t)); + +static void AdwInquiryHandling __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); -static void AdvSleepMilliSecond __P((u_int32_t)); -static void AdvDelayMicroSecond __P((u_int32_t)); +static void AdwSleepMilliSecond __P((u_int32_t)); +static void AdwDelayMicroSecond __P((u_int32_t)); /* @@ -103,51 +109,49 @@ static void AdvDelayMicroSecond __P((u_int32_t)); * Additional structure information can be found in adwlib.h where * the structure is defined. */ -static ADW_EEP_3550_CONFIG -Default_3550_EEPROM_Config = { - ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */ - 0x0000, /* cfg_msw */ - 0xFFFF, /* disc_enable */ - 0xFFFF, /* wdtr_able */ - 0xFFFF, /* sdtr_able */ - 0xFFFF, /* start_motor */ - 0xFFFF, /* tagqng_able */ - 0xFFFF, /* bios_scan */ - 0, /* scam_tolerant */ - 7, /* adapter_scsi_id */ - 0, /* bios_boot_delay */ - 3, /* scsi_reset_delay */ - 0, /* bios_id_lun */ - 0, /* termination */ - 0, /* reserved1 */ - 0xFFE7, /* bios_ctrl */ - 0xFFFF, /* ultra_able */ - 0, /* reserved2 */ - ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ - ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ - 0, /* dvc_cntl */ - 0, /* bug_fix */ - 0, /* serial_number_word1 */ - 0, /* serial_number_word2 */ - 0, /* serial_number_word3 */ - 0, /* check_sum */ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* oem_name[16] */ - 0, /* dvc_err_code */ - 0, /* adv_err_code */ - 0, /* adv_err_addr */ - 0, /* saved_dvc_err_code */ - 0, /* saved_adv_err_code */ - 0, /* saved_adv_err_addr */ - 0 /* num_of_err */ +const static ADW_EEPROM adw_3550_Default_EEPROM = { + ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ + 0x0000, /* 01 cfg_msw */ + 0xFFFF, /* 02 disc_enable */ + 0xFFFF, /* 03 wdtr_able */ + { 0xFFFF }, /* 04 sdtr_able */ + 0xFFFF, /* 05 start_motor */ + 0xFFFF, /* 06 tagqng_able */ + 0xFFFF, /* 07 bios_scan */ + 0, /* 08 scam_tolerant */ + 7, /* 09 adapter_scsi_id */ + 0, /* bios_boot_delay */ + 3, /* 10 scsi_reset_delay */ + 0, /* bios_id_lun */ + 0, /* 11 termination */ + 0, /* reserved1 */ + 0xFFE7, /* 12 bios_ctrl */ + { 0xFFFF }, /* 13 ultra_able */ + { 0 }, /* 14 reserved2 */ + ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ + ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ + 0, /* 16 dvc_cntl */ + { 0 }, /* 17 bug_fix */ + { 0,0,0 }, /* 18-20 serial_number[3] */ + 0, /* 21 check_sum */ + { /* 22-29 oem_name[16] */ + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0 + }, + 0, /* 30 dvc_err_code */ + 0, /* 31 adv_err_code */ + 0, /* 32 adv_err_addr */ + 0, /* 33 saved_dvc_err_code */ + 0, /* 34 saved_adv_err_code */ + 0 /* 35 saved_adv_err_addr */ }; -static ADW_EEP_38C0800_CONFIG -Default_38C0800_EEPROM_Config = { +const static ADW_EEPROM adw_38C0800_Default_EEPROM = { ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 0x0000, /* 01 cfg_msw */ 0xFFFF, /* 02 disc_enable */ 0xFFFF, /* 03 wdtr_able */ - 0x4444, /* 04 sdtr_speed1 */ + { 0x4444 }, /* 04 sdtr_speed1 */ 0xFFFF, /* 05 start_motor */ 0xFFFF, /* 06 tagqng_able */ 0xFFFF, /* 07 bios_scan */ @@ -159,259 +163,560 @@ Default_38C0800_EEPROM_Config = { 0, /* 11 termination_se */ 0, /* termination_lvd */ 0xFFE7, /* 12 bios_ctrl */ - 0x4444, /* 13 sdtr_speed2 */ - 0x4444, /* 14 sdtr_speed3 */ - ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ - ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ + { 0x4444 }, /* 13 sdtr_speed2 */ + { 0x4444 }, /* 14 sdtr_speed3 */ + ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ + ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 0, /* 16 dvc_cntl */ - 0x4444, /* 17 sdtr_speed4 */ - 0, /* 18 serial_number_word1 */ - 0, /* 19 serial_number_word2 */ - 0, /* 20 serial_number_word3 */ + { 0x4444 }, /* 17 sdtr_speed4 */ + { 0,0,0 }, /* 18-20 serial_number[3] */ 0, /* 21 check_sum */ - { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */ + { /* 22-29 oem_name[16] */ + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0 + }, 0, /* 30 dvc_err_code */ 0, /* 31 adv_err_code */ 0, /* 32 adv_err_addr */ 0, /* 33 saved_dvc_err_code */ 0, /* 34 saved_adv_err_code */ 0, /* 35 saved_adv_err_addr */ - 0, /* 36 reserved */ - 0, /* 37 reserved */ - 0, /* 38 reserved */ - 0, /* 39 reserved */ - 0, /* 40 reserved */ - 0, /* 41 reserved */ - 0, /* 42 reserved */ - 0, /* 43 reserved */ - 0, /* 44 reserved */ - 0, /* 45 reserved */ - 0, /* 46 reserved */ - 0, /* 47 reserved */ - 0, /* 48 reserved */ - 0, /* 49 reserved */ - 0, /* 50 reserved */ - 0, /* 51 reserved */ - 0, /* 52 reserved */ - 0, /* 53 reserved */ - 0, /* 54 reserved */ - 0, /* 55 reserved */ + { /* 36-55 reserved1[16] */ + 0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0 + }, 0, /* 56 cisptr_lsw */ 0, /* 57 cisprt_msw */ PCI_VENDOR_ADVSYS, /* 58 subsysvid */ PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ - 0, /* 60 reserved */ - 0, /* 61 reserved */ - 0, /* 62 reserved */ - 0 /* 63 reserved */ + { 0,0,0,0 } /* 60-63 reserved2[4] */ +}; + +const static ADW_EEPROM adw_38C1600_Default_EEPROM = { + ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ + 0x0000, /* 01 cfg_msw */ + 0xFFFF, /* 02 disc_enable */ + 0xFFFF, /* 03 wdtr_able */ + { 0x5555 }, /* 04 sdtr_speed1 */ + 0xFFFF, /* 05 start_motor */ + 0xFFFF, /* 06 tagqng_able */ + 0xFFFF, /* 07 bios_scan */ + 0, /* 08 scam_tolerant */ + 7, /* 09 adapter_scsi_id */ + 0, /* bios_boot_delay */ + 3, /* 10 scsi_reset_delay */ + 0, /* bios_id_lun */ + 0, /* 11 termination_se */ + 0, /* termination_lvd */ + 0xFFE7, /* 12 bios_ctrl */ + { 0x5555 }, /* 13 sdtr_speed2 */ + { 0x5555 }, /* 14 sdtr_speed3 */ + ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ + ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ + 0, /* 16 dvc_cntl */ + { 0x5555 }, /* 17 sdtr_speed4 */ + { 0,0,0 }, /* 18-20 serial_number[3] */ + 0, /* 21 check_sum */ + { /* 22-29 oem_name[16] */ + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0 + }, + 0, /* 30 dvc_err_code */ + 0, /* 31 adv_err_code */ + 0, /* 32 adv_err_addr */ + 0, /* 33 saved_dvc_err_code */ + 0, /* 34 saved_adv_err_code */ + 0, /* 35 saved_adv_err_addr */ + { /* 36-55 reserved1[16] */ + 0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0 + }, + 0, /* 56 cisptr_lsw */ + 0, /* 57 cisprt_msw */ + PCI_VENDOR_ADVSYS, /* 58 subsysvid */ + PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ + { 0,0,0,0 } /* 60-63 reserved2[4] */ }; + /* - * Initialize the ASC3550. - * - * On failure set the ADW_SOFTC field 'err_code' and return ADW_ERROR. + * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and + * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while + * all of this is done. * * For a non-fatal error return a warning code. If there are no warnings * then 0 is returned. + * + * Note: Chip is stopped on entry. */ int -AdvInitAsc3550Driver(sc) +AdwInitFromEEPROM(sc) ADW_SOFTC *sc; { bus_space_tag_t iot = sc->sc_iot; bus_space_handle_t ioh = sc->sc_ioh; - u_int16_t warn_code; - u_int32_t sum; - int begin_addr; - int end_addr; - u_int16_t code_sum; - int word; - int i, j; - int adv_asc3550_expanded_size; - u_int16_t scsi_cfg1; - u_int8_t tid; - u_int16_t bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory - 0x40-0x8F. */ - u_int16_t wdtr_able = 0, sdtr_able, tagqng_able; - u_int8_t max_cmd[ADW_MAX_TID + 1]; + ADW_EEPROM eep_config; + u_int16_t warn_code; + u_int16_t sdtr_speed = 0; + u_int8_t tid, termination; + int i, j; warn_code = 0; /* - * Save the RISC memory BIOS region before writing the microcode. - * The BIOS may already be loaded and using its RISC LRAM region - * so its region must be saved and restored. + * Read the board's EEPROM configuration. * - * Note: This code makes the assumption, which is currently true, - * that a chip reset does not clear RISC LRAM. + * Set default values if a bad checksum is found. + * + * XXX - Don't handle big-endian access to EEPROM yet. */ - for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2*i), bios_mem[i]); - } + if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) { + warn_code |= ADW_WARN_EEPROM_CHKSUM; - /* - * Save current per TID negotiated values. - */ - if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA) { + /* + * Set EEPROM default values. + */ + switch(sc->chip_type) { + case ADW_CHIP_ASC3550: + eep_config = adw_3550_Default_EEPROM; + break; + case ADW_CHIP_ASC38C0800: + eep_config = adw_38C0800_Default_EEPROM; + break; + case ADW_CHIP_ASC38C1600: + eep_config = adw_38C1600_Default_EEPROM; - u_int16_t bios_version, major, minor; +// XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { + if (sc->cfg.pci_slot_info != 0) { + u_int8_t lsw_msb; - bios_version = bios_mem[(ASC_MC_BIOS_VERSION-ASC_MC_BIOSMEM)/2]; - major = (bios_version >> 12) & 0xF; - minor = (bios_version >> 8) & 0xF; - if (major < 3 || (major == 3 && minor == 1)) { - /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */ - ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); - } else { - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); + lsw_msb = eep_config.cfg_lsw >> 8; + /* + * Set Function 1 EEPROM Word 0 MSB + * + * Clear the BIOS_ENABLE (bit 14) and + * INTAB (bit 11) EEPROM bits. + * + * Disable Bit 14 (BIOS_ENABLE) to fix + * SPARC Ultra 60 and old Mac system booting + * problem. The Expansion ROM must + * be disabled in Function 1 for these systems. + */ + lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE | + ADW_EEPROM_INTAB) >> 8) & 0xFF); + /* + * Set the INTAB (bit 11) if the GPIO 0 input + * indicates the Function 1 interrupt line is + * wired to INTA. + * + * Set/Clear Bit 11 (INTAB) from + * the GPIO bit 0 input: + * 1 - Function 1 intr line wired to INT A. + * 0 - Function 1 intr line wired to INT B. + * + * Note: Adapter boards always have Function 0 + * wired to INTA. + * Put all 5 GPIO bits in input mode and then + * read their input values. + */ + ADW_WRITE_BYTE_REGISTER(iot, ioh, + IOPB_GPIO_CNTL, 0); + if (ADW_READ_BYTE_REGISTER(iot, ioh, + IOPB_GPIO_DATA) & 0x01) { + /* + * Function 1 interrupt wired to INTA; + * Set EEPROM bit. + */ + lsw_msb |= (ADW_EEPROM_INTAB >> 8) + & 0xFF; + } + eep_config.cfg_lsw &= 0x00FF; + eep_config.cfg_lsw |= lsw_msb << 8; + } + break; + } + + /* + * Assume the 6 byte board serial number that was read + * from EEPROM is correct even if the EEPROM checksum + * failed. + */ + for (i=2, j=1; i>=0; i--, j++) { + eep_config.serial_number[i] = + AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - j); } - } - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); - for (tid = 0; tid <= ADW_MAX_TID; tid++) { - ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, - max_cmd[tid]); - } + AdwSetEEPROMConfig(iot, ioh, &eep_config); + } /* - * Load the Microcode + * Set sc and sc->cfg variables from the EEPROM configuration + * that was read. * - * Write the microcode image to RISC memory starting at address 0. + * This is the mapping of EEPROM fields to Adw Library fields. */ - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); + sc->wdtr_able = eep_config.wdtr_able; + if (sc->chip_type == ADW_CHIP_ASC3550) { + sc->sdtr_able = eep_config.sdtr1.sdtr_able; + sc->ultra_able = eep_config.sdtr2.ultra_able; + } else { + sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1; + sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2; + sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3; + sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4; + } + sc->ppr_able = 0; + sc->tagqng_able = eep_config.tagqng_able; + sc->cfg.disc_enable = eep_config.disc_enable; + sc->max_host_qng = eep_config.max_host_qng; + sc->max_dvc_qng = eep_config.max_dvc_qng; + sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); + sc->start_motor = eep_config.start_motor; + sc->scsi_reset_wait = eep_config.scsi_reset_delay; + sc->bios_ctrl = eep_config.bios_ctrl; + sc->no_scam = eep_config.scam_tolerant; + sc->cfg.serial1 = eep_config.serial_number[0]; + sc->cfg.serial2 = eep_config.serial_number[1]; + sc->cfg.serial3 = eep_config.serial_number[2]; + + if (sc->chip_type == ADW_CHIP_ASC38C0800 || + sc->chip_type == ADW_CHIP_ASC38C1600) { + sc->sdtr_able = 0; + for (tid = 0; tid <= ADW_MAX_TID; tid++) { + if (tid == 0) { + sdtr_speed = sc->sdtr_speed1; + } else if (tid == 4) { + sdtr_speed = sc->sdtr_speed2; + } else if (tid == 8) { + sdtr_speed = sc->sdtr_speed3; + } else if (tid == 12) { + sdtr_speed = sc->sdtr_speed4; + } + if (sdtr_speed & ADW_MAX_TID) { + sc->sdtr_able |= (1 << tid); + } + sdtr_speed >>= 4; + } + } - /* Assume the following compressed format of the microcode buffer: - * - * 254 word (508 byte) table indexed by byte code followed - * by the following byte codes: - * - * 1-Byte Code: - * 00: Emit word 0 in table. - * 01: Emit word 1 in table. - * . - * FD: Emit word 253 in table. - * - * Multi-Byte Code: - * FE WW WW: (3 byte code) Word to emit is the next word WW WW. - * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. + /* + * Set the host maximum queuing (max. 253, min. 16) and the per device + * maximum queuing (max. 63, min. 4). */ - word = 0; - for (i = 253 * 2; i < adv_asc3550_mcode_size; i++) { - if (adv_asc3550_mcode[i] == 0xff) { - for (j = 0; j < adv_asc3550_mcode[i + 1]; j++) { - ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, - (((u_int16_t)adv_asc3550_mcode[i + 3] << 8) | - adv_asc3550_mcode[i + 2])); - word++; - } - i += 3; - } else if (adv_asc3550_mcode[i] == 0xfe) { - ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, - (((u_int16_t)adv_asc3550_mcode[i + 2] << 8) | - adv_asc3550_mcode[i + 1])); - i += 2; - word++; + if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { + eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; + } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) + { + /* If the value is zero, assume it is uninitialized. */ + if (eep_config.max_host_qng == 0) { + eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; } else { - ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) - adv_asc3550_mcode[(adv_asc3550_mcode[i] * 2) + 1] <<8) | - adv_asc3550_mcode[adv_asc3550_mcode[i] * 2])); - word++; + eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; + } + } + + if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { + eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; + } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { + /* If the value is zero, assume it is uninitialized. */ + if (eep_config.max_dvc_qng == 0) { + eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; + } else { + eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; } } /* - * Set 'word' for later use to clear the rest of memory and save - * the expanded mcode size. + * If 'max_dvc_qng' is greater than 'max_host_qng', then + * set 'max_dvc_qng' to 'max_host_qng'. */ - word *= 2; - adv_asc3550_expanded_size = word; + if (eep_config.max_dvc_qng > eep_config.max_host_qng) { + eep_config.max_dvc_qng = eep_config.max_host_qng; + } /* - * Clear the rest of ASC-3550 Internal RAM (8KB). + * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' + * values based on possibly adjusted EEPROM values. */ - for (; word < ADV_3550_MEMSIZE; word += 2) { - ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); - } + sc->max_host_qng = eep_config.max_host_qng; + sc->max_dvc_qng = eep_config.max_dvc_qng; + /* - * Verify the microcode checksum. + * If the EEPROM 'termination' field is set to automatic (0), then set + * the ADV_DVC_CFG 'termination' field to automatic also. + * + * If the termination is specified with a non-zero 'termination' + * value check that a legal value is set and set the ADV_DVC_CFG + * 'termination' field appropriately. */ - sum = 0; - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); - for (word = 0; word < adv_asc3550_expanded_size; word += 2) { - sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); - } + switch(sc->chip_type) { + case ADW_CHIP_ASC3550: + sc->cfg.termination = 0; /* auto termination */ + switch(eep_config.termination_se) { + case 3: + /* Enable manual control with low on / high on. */ + sc->cfg.termination |= ADW_TERM_CTL_L; + case 2: + /* Enable manual control with low off / high on. */ + sc->cfg.termination |= ADW_TERM_CTL_H; + case 1: + /* Enable manual control with low off / high off. */ + sc->cfg.termination |= ADW_TERM_CTL_SEL; + case 0: + break; + default: + warn_code |= ADW_WARN_EEPROM_TERMINATION; + } + break; + + case ADW_CHIP_ASC38C0800: + case ADW_CHIP_ASC38C1600: + switch(eep_config.termination_se) { + case 0: + /* auto termination for SE */ + termination = 0; + break; + case 1: + /* Enable manual control with low off / high off. */ + termination = 0; + break; + case 2: + /* Enable manual control with low off / high on. */ + termination = ADW_TERM_SE_HI; + break; + case 3: + /* Enable manual control with low on / high on. */ + termination = ADW_TERM_SE; + break; + default: + /* + * The EEPROM 'termination_se' field contains a + * bad value. Use automatic termination instead. + */ + termination = 0; + warn_code |= ADW_WARN_EEPROM_TERMINATION; + } - if (sum != adv_asc3550_mcode_chksum) { - return ASC_IERR_MCODE_CHKSUM; + switch(eep_config.termination_lvd) { + case 0: + /* auto termination for LVD */ + sc->cfg.termination = termination; + break; + case 1: + /* Enable manual control with low off / high off. */ + sc->cfg.termination = termination; + break; + case 2: + /* Enable manual control with low off / high on. */ + sc->cfg.termination = termination | ADW_TERM_LVD_HI; + break; + case 3: + /* Enable manual control with low on / high on. */ + sc->cfg.termination = termination | ADW_TERM_LVD; + break; + default: + /* + * The EEPROM 'termination_lvd' field contains a + * bad value. Use automatic termination instead. + */ + sc->cfg.termination = termination; + warn_code |= ADW_WARN_EEPROM_TERMINATION; + } + break; } + return warn_code; +} + + +/* + * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600. + * + * On failure return the error code. + */ +int +AdwInitDriver(sc) +ADW_SOFTC *sc; +{ + bus_space_tag_t iot = sc->sc_iot; + bus_space_handle_t ioh = sc->sc_ioh; + u_int16_t error_code; + int word; + int i; + u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory + 0x40-0x8F. */ + u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able; + u_int8_t max_cmd[ADW_MAX_TID + 1]; + u_int8_t tid; + + + error_code = 0; + /* - * Restore the RISC memory BIOS region. + * Save the RISC memory BIOS region before writing the microcode. + * The BIOS may already be loaded and using its RISC LRAM region + * so its region must be saved and restored. + * + * Note: This code makes the assumption, which is currently true, + * that a chip reset does not clear RISC LRAM. */ - for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { - ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), - bios_mem[i]); + for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); } /* - * Calculate and write the microcode code checksum to the microcode - * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). + * Save current per TID negotiated values. */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); - code_sum = 0; - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); - for (word = begin_addr; word < end_addr; word += 2) { - code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); + switch (sc->chip_type) { + case ADW_CHIP_ASC3550: + if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){ + + u_int16_t bios_version, major, minor; + + bios_version = bios_mem[(ADW_MC_BIOS_VERSION - + ADW_MC_BIOSMEM) / 2]; + major = (bios_version >> 12) & 0xF; + minor = (bios_version >> 8) & 0xF; + if (major < 3 || (major == 3 && minor == 1)) { + /* + * BIOS 3.1 and earlier location of + * 'wdtr_able' variable. + */ + ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); + } else { + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, + wdtr_able); + } + } + break; + + case ADW_CHIP_ASC38C1600: + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); + /* FALLTHROUGH */ + case ADW_CHIP_ASC38C0800: + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); + break; + } + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); + for (tid = 0; tid <= ADW_MAX_TID; tid++) { + ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, + max_cmd[tid]); } - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CODE_CHK_SUM, code_sum); /* - * Read and save microcode version and date. + * Perform a RAM Built-In Self Test */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_DATE, - sc->cfg.mcode_date); - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_NUM, - sc->cfg.mcode_version); + if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) { + return error_code; + } /* - * Set the chip type to indicate the ASC3550. + * Load the Microcode */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550); + ; + if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) { + return error_code; + } /* - * If the PCI Configuration Command Register "Parity Error Response + * Read microcode version and date. + */ + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date); + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version); + + /* + * If the PCI Configuration Command Register "Parity Error Response * Control" Bit was clear (0), then set the microcode variable * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode * to ignore DMA parity errors. */ if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, + word | CONTROL_FLAG_IGNORE_PERR); + } + + switch (sc->chip_type) { + case ADW_CHIP_ASC3550: /* - * Note: Don't remove the use of a temporary variable in - * the following code, otherwise some C compiler - * might turn the following lines into a no-op. + * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a + * FIFO threshold of 128 bytes. + * This register is only accessible to the host. */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); - word |= CONTROL_FLAG_IGNORE_PERR; - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); - } + ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, + START_CTL_EMFU | READ_CMD_MRM); + break; - /* - * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO - * threshold of 128 bytes. This register is only accessible to the host. - */ - ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, - START_CTL_EMFU | READ_CMD_MRM); + case ADW_CHIP_ASC38C0800: + /* + * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. + * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current + * cable detection and then we are able to read C_DET[3:0]. + * + * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 + * Microcode Default Value' section below. + */ + ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, + ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) + | ADW_DIS_TERM_DRV); + + /* + * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and + * START_CTL_TH [3:2] bits for the default FIFO threshold. + * + * Note: ASC-38C0800 FIFO threshold has been changed to + * 256 bytes. + * + * For DMA Errata #4 set the BC_THRESH_ENB bit. + */ + ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, + BC_THRESH_ENB | FIFO_THRESH_80B + | START_CTL_TH | READ_CMD_MRM); + break; + + case ADW_CHIP_ASC38C1600: + /* + * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. + * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current + * cable detection and then we are able to read C_DET[3:0]. + * + * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 + * Microcode Default Value' section below. + */ + ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, + ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) + | ADW_DIS_TERM_DRV); + + /* + * If the BIOS control flag AIPP (Asynchronous Information + * Phase Protection) disable bit is not set, then set the + * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to + * enable AIPP checking and encoding. + */ + if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, + word | CONTROL_FLAG_ENABLE_AIPP); + } + + /* + * For ASC-38C1600 use DMA_CFG0 default values: + * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2]. + */ + ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, + FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); + break; + } /* * Microcode operating variables for WDTR, SDTR, and command tag * queuing will be set in AdvInquiryHandling() based on what a * device reports it is capable of in Inquiry byte 7. * - * If SCSI Bus Resets haev been disabled, then directly set + * If SCSI Bus Resets have been disabled, then directly set * SDTR and WDTR from the EEPROM configuration. This will allow * the BIOS and warm boot to work without a SCSI bus hang on * the Inquiry caused by host and target mismatched DTR values. @@ -419,10 +724,8 @@ ADW_SOFTC *sc; * be assumed to be in Asynchronous, Narrow mode. */ if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, - sc->wdtr_able); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, - sc->sdtr_able); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); } /* @@ -434,51 +737,64 @@ ADW_SOFTC *sc; * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them * without determining here whether the device supports SDTR. - * - * 4-bit speed SDTR speed name - * =========== =============== - * 0000b (0x0) SDTR disabled - * 0001b (0x1) 5 Mhz - * 0010b (0x2) 10 Mhz - * 0011b (0x3) 20 Mhz (Ultra) - * 0100b (0x4) 40 Mhz (LVD/Ultra2) - * 0101b (0x5) 80 Mhz (LVD2/Ultra3) - * 0110b (0x6) Undefined - * . - * 1111b (0xF) Undefined */ - word = 0; - for (tid = 0; tid <= ADW_MAX_TID; tid++) { - if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { - /* Set Ultra speed for TID 'tid'. */ - word |= (0x3 << (4 * (tid % 4))); - } else { - /* Set Fast speed for TID 'tid'. */ - word |= (0x2 << (4 * (tid % 4))); - } - /* Check if done with sdtr_speed1. */ - if (tid == 3) { - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED1, word); - word = 0; - /* Check if done with sdtr_speed2. */ - } else if (tid == 7) { - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED2, word); - word = 0; - /* Check if done with sdtr_speed3. */ - } else if (tid == 11) { - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED3, word); - word = 0; - /* Check if done with sdtr_speed4. */ - } else if (tid == 15) { - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED4, word); - /* End of loop. */ + switch (sc->chip_type) { + case ADW_CHIP_ASC3550: + word = 0; + for (tid = 0; tid <= ADW_MAX_TID; tid++) { + if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { + /* Set Ultra speed for TID 'tid'. */ + word |= (0x3 << (4 * (tid % 4))); + } else { + /* Set Fast speed for TID 'tid'. */ + word |= (0x2 << (4 * (tid % 4))); + } + /* Check if done with sdtr_speed1. */ + if (tid == 3) { + ADW_WRITE_WORD_LRAM(iot, ioh, + ADW_MC_SDTR_SPEED1, word); + word = 0; + /* Check if done with sdtr_speed2. */ + } else if (tid == 7) { + ADW_WRITE_WORD_LRAM(iot, ioh, + ADW_MC_SDTR_SPEED2, word); + word = 0; + /* Check if done with sdtr_speed3. */ + } else if (tid == 11) { + ADW_WRITE_WORD_LRAM(iot, ioh, + ADW_MC_SDTR_SPEED3, word); + word = 0; + /* Check if done with sdtr_speed4. */ + } else if (tid == 15) { + ADW_WRITE_WORD_LRAM(iot, ioh, + ADW_MC_SDTR_SPEED4, word); + /* End of loop. */ + } } - } - /* - * Set microcode operating variable for the disconnect per TID bitmask. - */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DISC_ENABLE, sc->cfg.disc_enable); + /* + * Set microcode operating variable for the + * disconnect per TID bitmask. + */ + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, + sc->cfg.disc_enable); + break; + + case ADW_CHIP_ASC38C0800: + /* FALLTHROUGH */ + case ADW_CHIP_ASC38C1600: + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, + sc->cfg.disc_enable); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, + sc->sdtr_speed1); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, + sc->sdtr_speed2); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, + sc->sdtr_speed3); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, + sc->sdtr_speed4); + break; + } /* @@ -487,188 +803,99 @@ ADW_SOFTC *sc; * The microcode will set the SCSI_CFG0 register using this value * after it is started below. */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, - ADW_PARITY_EN | ADW_SEL_TMO_LONG | ADW_OUR_ID_EN | - sc->chip_scsi_id); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, + ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | + ADW_OUR_ID_EN | sc->chip_scsi_id); - /* - * Determine SCSI_CFG1 Microcode Default Value. - * - * The microcode will set the SCSI_CFG1 register using this value - * after it is started below. - */ - /* Read current SCSI_CFG1 Register value. */ - scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); + switch(sc->chip_type) { + case ADW_CHIP_ASC3550: + error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg); + break; - /* - * If all three connectors are in use, return an error. - */ - if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || - (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { - return ASC_IERR_ILLEGAL_CONNECTION; - } + case ADW_CHIP_ASC38C0800: + error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg); + break; - /* - * If the internal narrow cable is reversed all of the SCSI_CTRL - * register signals will be set. Check for and return an error if - * this condition is found. - */ - if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == - 0x3F07) { - return ASC_IERR_REVERSED_CABLE; + case ADW_CHIP_ASC38C1600: + error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg); + break; } - - /* - * If this is a differential board and a single-ended device - * is attached to one of the connectors, return an error. - */ - if ((scsi_cfg1 & ADW_DIFF_MODE) && (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { - return ASC_IERR_SINGLE_END_DEVICE; + if(error_code) { + return error_code; } /* - * If automatic termination control is enabled, then set the - * termination value based on a table listed in a_condor.h. + * Set SEL_MASK Microcode Default Value * - * If manual termination was specified with an EEPROM setting - * then 'termination' was set-up in AdvInitFrom3550EEPROM() and - * is ready to be 'ored' into SCSI_CFG1. + * The microcode will set the SEL_MASK register using this value + * after it is started below. */ - if (sc->cfg.termination == 0) { - /* - * The software always controls termination by setting TERM_CTL_SEL. - * If TERM_CTL_SEL were set to 0, the hardware would set termination. - */ - sc->cfg.termination |= ADW_TERM_CTL_SEL; - - switch(scsi_cfg1 & ADW_CABLE_DETECT) { - /* TERM_CTL_H: on, TERM_CTL_L: on */ - case 0x3: case 0x7: case 0xB: case 0xD: case 0xE: case 0xF: - sc->cfg.termination |= (ADW_TERM_CTL_H | ADW_TERM_CTL_L); - break; - - /* TERM_CTL_H: on, TERM_CTL_L: off */ - case 0x1: case 0x5: case 0x9: case 0xA: case 0xC: - sc->cfg.termination |= ADW_TERM_CTL_H; - break; - - /* TERM_CTL_H: off, TERM_CTL_L: off */ - case 0x2: case 0x6: - break; - } - } + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, + ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); /* - * Clear any set TERM_CTL_H and TERM_CTL_L bits. + * Create and Initialize Host->RISC Carrier lists */ - scsi_cfg1 &= ~ADW_TERM_CTL; + sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier, + sc->sc_control->carriers); /* - * Invert the TERM_CTL_H and TERM_CTL_L bits and then - * set 'scsi_cfg1'. The TERM_POL bit does not need to be - * referenced, because the hardware internally inverts - * the Termination High and Low bits if TERM_POL is set. + * Set-up the Host->RISC Initiator Command Queue (ICQ). */ - scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~sc->cfg.termination & ADW_TERM_CTL)); - /* - * Set SCSI_CFG1 Microcode Default Value - * - * Set filter value and possibly modified termination control - * bits in the Microcode SCSI_CFG1 Register Value. - * - * The microcode will set the SCSI_CFG1 register using this value - * after it is started below. - */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, - ADW_FLTR_DISABLE | scsi_cfg1); + if ((sc->icq_sp = sc->carr_freelist) == NULL) { + return ADW_IERR_NO_CARRIER; + } + sc->carr_freelist = ADW_CARRIER_VADDR(sc, + ASC_GET_CARRP(sc->icq_sp->next_ba)); /* - * Set MEM_CFG Microcode Default Value - * - * The microcode will set the MEM_CFG register using this value - * after it is started below. - * - * MEM_CFG may be accessed as a word or byte, but only bits 0-7 - * are defined. - * - * ASC-3550 has 8KB internal memory. + * The first command issued will be placed in the stopper carrier. */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_MEM_CFG, - ADW_BIOS_EN | ADW_RAM_SZ_8KB); + sc->icq_sp->next_ba = ASC_CQ_STOPPER; /* - * Set SEL_MASK Microcode Default Value - * - * The microcode will set the SEL_MASK register using this value - * after it is started below. + * Set RISC ICQ physical address start value. */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, - ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); - + ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, sc->icq_sp->carr_ba); /* - * Set-up the Host->RISC Initiator Command Queue (ICQ) if - * one is not already set up, i.e. this is the first - * time through as opposed to a bus reset. + * Initialize the COMMA register to the same value otherwise + * the RISC will prematurely detect a command is available. */ - - if (sc->icq_sp == NULL) { - sc->carr_pending_cnt = 0; - if ((sc->icq_sp = sc->carr_freelist) == NULL) { - return ASC_IERR_NO_CARRIER; - } - sc->carr_freelist = adw_carrier_phys_kv(sc, - ASC_GET_CARRP(sc->icq_sp->next_vpa)); - - /* - * The first command issued will be placed in the stopper carrier. - */ - sc->icq_sp->next_vpa = ASC_CQ_STOPPER; + if(sc->chip_type == ADW_CHIP_ASC38C1600) { + ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, + sc->icq_sp->carr_ba); } /* - * Set RISC ICQ physical address start value. + * Set-up the RISC->Host Initiator Response Queue (IRQ). */ - ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_ICQ, sc->icq_sp->carr_pa); + if ((sc->irq_sp = sc->carr_freelist) == NULL) { + return ADW_IERR_NO_CARRIER; + } + sc->carr_freelist = ADW_CARRIER_VADDR(sc, + ASC_GET_CARRP(sc->irq_sp->next_ba)); /* - * Set-up the RISC->Host Initiator Response Queue (IRQ) if - * one is not already set up, i.e. this is the first - * time through as opposed to a bus reset. + * The first command completed by the RISC will be placed in + * the stopper. + * + * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is + * completed the RISC will set the ASC_RQ_DONE bit. */ - if (sc->irq_sp == NULL) { - if ((sc->irq_sp = sc->carr_freelist) == NULL) { - return ASC_IERR_NO_CARRIER; - } - sc->carr_freelist = adw_carrier_phys_kv(sc, - ASC_GET_CARRP(sc->irq_sp->next_vpa)); - - /* - * The first command completed by the RISC will be placed in - * the stopper. - * - * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is - * completed the RISC will set the ASC_RQ_DONE bit. - */ - sc->irq_sp->next_vpa = ASC_CQ_STOPPER; - } + sc->irq_sp->next_ba = ASC_CQ_STOPPER; /* - * Set RISC IRQ physical address start value. - */ - ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IRQ, sc->irq_sp->carr_pa); + * Set RISC IRQ physical address start value. + */ + ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, sc->irq_sp->carr_ba); + sc->carr_pending_cnt = 0; ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); - - /* - * Note: Don't remove the use of a temporary variable in - * the following code, otherwise some C compiler - * might turn the following lines into a no-op. - */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, word); + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); /* finally, finally, gentlemen, start your engine */ @@ -686,158 +913,167 @@ ADW_SOFTC *sc; * BIOS Handshake Configuration Table and do not perform * a SCSI Bus Reset. */ - if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == + if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 0x55AA) { /* * Restore per TID negotiated values. */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); for (tid = 0; tid <= ADW_MAX_TID; tid++) { ADW_WRITE_BYTE_LRAM(iot, ioh, - ASC_MC_NUMBER_OF_MAX_CMD + tid, - max_cmd[tid]); + ADW_MC_NUMBER_OF_MAX_CMD + tid, + max_cmd[tid]); } } else { - if (AdvResetCCB(sc) != ADW_TRUE) { - warn_code = ASC_WARN_BUSRESET_ERROR; + if (AdwResetCCB(sc) != ADW_TRUE) { + error_code = ADW_WARN_BUSRESET_ERROR; } } } - return warn_code; + return error_code; } -/* - * Initialize the ASC-38C0800. - * - * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. - * - * For a non-fatal error return a warning code. If there are no warnings - * then 0 is returned. - */ + int -AdvInitAsc38C0800Driver(sc) -ADW_SOFTC *sc; +AdwRamSelfTest(iot, ioh, chip_type) + bus_space_tag_t iot; + bus_space_handle_t ioh; + u_int8_t chip_type; { - bus_space_tag_t iot = sc->sc_iot; - bus_space_handle_t ioh = sc->sc_ioh; - u_int16_t warn_code; - u_int32_t sum; - int begin_addr; - int end_addr; - u_int16_t code_sum; - int word; - int i, j; - int adv_asc38C0800_expanded_size; - u_int16_t scsi_cfg1; + int i; u_int8_t byte; - u_int8_t tid; - u_int16_t bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory - 0x40-0x8F. */ - u_int16_t wdtr_able, sdtr_able, tagqng_able; - u_int8_t max_cmd[ADW_MAX_TID + 1]; - warn_code = 0; + if ((chip_type == ADW_CHIP_ASC38C0800) || + (chip_type == ADW_CHIP_ASC38C1600)) { + /* + * RAM BIST (RAM Built-In Self Test) + * + * Address : I/O base + offset 0x38h register (byte). + * Function: Bit 7-6(RW) : RAM mode + * Normal Mode : 0x00 + * Pre-test Mode : 0x40 + * RAM Test Mode : 0x80 + * Bit 5 : unused + * Bit 4(RO) : Done bit + * Bit 3-0(RO) : Status + * Host Error : 0x08 + * Int_RAM Error : 0x04 + * RISC Error : 0x02 + * SCSI Error : 0x01 + * No Error : 0x00 + * + * Note: RAM BIST code should be put right here, before loading + * the microcode and after saving the RISC memory BIOS region. + */ - /* - * Save the RISC memory BIOS region before writing the microcode. - * The BIOS may already be loaded and using its RISC LRAM region - * so its region must be saved and restored. - * - * Note: This code makes the assumption, which is currently true, - * that a chip reset does not clear RISC LRAM. - */ - for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]); - } + /* + * LRAM Pre-test + * + * Write PRE_TEST_MODE (0x40) to register and wait for + * 10 milliseconds. + * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), + * return an error. Reset to NORMAL_MODE (0x00) and do again. + * If cannot reset to NORMAL_MODE, return an error too. + */ + for (i = 0; i < 2; i++) { + ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, + PRE_TEST_MODE); + /* Wait for 10ms before reading back. */ + AdwSleepMilliSecond(10); + byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); + if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != + PRE_TEST_VALUE) { + return ADW_IERR_BIST_PRE_TEST; + } - /* - * Save current per TID negotiated values. - */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); - for (tid = 0; tid <= ADW_MAX_TID; tid++) { - ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, - max_cmd[tid]); - } + ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, + NORMAL_MODE); + /* Wait for 10ms before reading back. */ + AdwSleepMilliSecond(10); + if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) + != NORMAL_VALUE) { + return ADW_IERR_BIST_PRE_TEST; + } + } - /* - * RAM BIST (RAM Built-In Self Test) - * - * Address : I/O base + offset 0x38h register (byte). - * Function: Bit 7-6(RW) : RAM mode - * Normal Mode : 0x00 - * Pre-test Mode : 0x40 - * RAM Test Mode : 0x80 - * Bit 5 : unused - * Bit 4(RO) : Done bit - * Bit 3-0(RO) : Status - * Host Error : 0x08 - * Int_RAM Error : 0x04 - * RISC Error : 0x02 - * SCSI Error : 0x01 - * No Error : 0x00 - * - * Note: RAM BIST code should be put right here, before loading the - * microcode and after saving the RISC memory BIOS region. - */ + /* + * LRAM Test - It takes about 1.5 ms to run through the test. + * + * Write RAM_TEST_MODE (0x80) to register and wait for + * 10 milliseconds. + * If Done bit not set or Status not 0, save register byte, + * set the err_code, and return an error. + */ + ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); + /* Wait for 10ms before checking status. */ + AdwSleepMilliSecond(10); - /* - * LRAM Pre-test - * - * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. - * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return - * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset - * to NORMAL_MODE, return an error too. - */ - for (i = 0; i < 2; i++) { - ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, PRE_TEST_MODE); - AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); - if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != - PRE_TEST_VALUE) { - return ASC_IERR_BIST_PRE_TEST; + if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) { + /* Get here if Done bit not set or Status not 0. */ + return ADW_IERR_BIST_RAM_TEST; } + /* We need to reset back to normal mode after LRAM test passes*/ ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); - AdvSleepMilliSecond(10); /* Wait for 10ms before reading back. */ - if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) - != NORMAL_VALUE) { - return ASC_IERR_BIST_PRE_TEST; - } } - /* - * LRAM Test - It takes about 1.5 ms to run through the test. - * - * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. - * If Done bit not set or Status not 0, save register byte, set the - * err_code, and return an error. - */ - ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); - AdvSleepMilliSecond(10); /* Wait for 10ms before checking status. */ + return 0; +} + + +int +AdwLoadMCode(iot, ioh, bios_mem, chip_type) + bus_space_tag_t iot; + bus_space_handle_t ioh; + u_int16_t *bios_mem; + u_int8_t chip_type; +{ + u_int8_t *mcode_data; + u_int32_t mcode_chksum; + u_int16_t mcode_size; + u_int32_t sum; + u_int16_t code_sum; + int begin_addr; + int end_addr; + int word; + int adw_memsize; + int adw_mcode_expanded_size; + int i, j; - byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); - if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { - /* Get here if Done bit not set or Status not 0. */ - return ASC_IERR_BIST_RAM_TEST; - } - /* We need to reset back to normal mode after LRAM test passes. */ - ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); + switch(chip_type) { + case ADW_CHIP_ASC3550: + mcode_data = (u_int8_t *)adw_asc3550_mcode_data.mcode_data; + mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum; + mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size; + adw_memsize = ADW_3550_MEMSIZE; + break; + + case ADW_CHIP_ASC38C0800: + mcode_data = (u_int8_t *)adw_asc38C0800_mcode_data.mcode_data; + mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum; + mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size; + adw_memsize = ADW_38C0800_MEMSIZE; + break; + + case ADW_CHIP_ASC38C1600: + mcode_data = (u_int8_t *)adw_asc38C1600_mcode_data.mcode_data; + mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum; + mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size; + adw_memsize = ADW_38C1600_MEMSIZE; + break; + } /* - * Load the Microcode - * * Write the microcode image to RISC memory starting at address 0. - * */ ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); @@ -857,26 +1093,25 @@ ADW_SOFTC *sc; * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. */ word = 0; - for (i = 253 * 2; i < adv_asc38C0800_mcode_size; i++) { - if (adv_asc38C0800_mcode[i] == 0xff) { - for (j = 0; j < adv_asc38C0800_mcode[i + 1]; j++) { + for (i = 253 * 2; i < mcode_size; i++) { + if (mcode_data[i] == 0xff) { + for (j = 0; j < mcode_data[i + 1]; j++) { ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, - (((u_int16_t) - adv_asc38C0800_mcode[i + 3] << 8) | - adv_asc38C0800_mcode[i + 2])); + (((u_int16_t)mcode_data[i + 3] << 8) | + mcode_data[i + 2])); word++; } i += 3; - } else if (adv_asc38C0800_mcode[i] == 0xfe) { - ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) - adv_asc38C0800_mcode[i + 2] << 8) | - adv_asc38C0800_mcode[i + 1])); + } else if (mcode_data[i] == 0xfe) { + ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, + (((u_int16_t)mcode_data[i + 2] << 8) | + mcode_data[i + 1])); i += 2; word++; } else { ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) - adv_asc38C0800_mcode[(adv_asc38C0800_mcode[i] * 2) + 1] << 8) | - adv_asc38C0800_mcode[adv_asc38C0800_mcode[i] * 2])); + mcode_data[(mcode_data[i] * 2) + 1] <<8) | + mcode_data[mcode_data[i] * 2])); word++; } } @@ -886,12 +1121,12 @@ ADW_SOFTC *sc; * the expanded mcode size. */ word *= 2; - adv_asc38C0800_expanded_size = word; + adw_mcode_expanded_size = word; /* - * Clear the rest of ASC-38C0800 Internal RAM (16KB). + * Clear the rest of the Internal RAM. */ - for (; word < ADV_38C0800_MEMSIZE; word += 2) { + for (; word < adw_memsize; word += 2) { ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); } @@ -901,129 +1136,182 @@ ADW_SOFTC *sc; sum = 0; ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); - for (word = 0; word < adv_asc38C0800_expanded_size; word += 2) { + for (word = 0; word < adw_mcode_expanded_size; word += 2) { sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); } - if (sum != adv_asc38C0800_mcode_chksum) { - return ASC_IERR_MCODE_CHKSUM; + if (sum != mcode_chksum) { + return ADW_IERR_MCODE_CHKSUM; } /* * Restore the RISC memory BIOS region. */ - for (i = 0; i < ASC_MC_BIOSLEN/2; i++) { - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOSMEM + (2 * i), - bios_mem[i]); + for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { + if(chip_type == ADW_CHIP_ASC3550) { + ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), + bios_mem[i]); + } else { + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), + bios_mem[i]); + } } /* * Calculate and write the microcode code checksum to the microcode - * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). + * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, begin_addr); - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_END_ADDR, end_addr); + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); code_sum = 0; ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); for (word = begin_addr; word < end_addr; word += 2) { code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); } - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CODE_CHK_SUM, code_sum); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); /* - * Read microcode version and date. + * Set the chip type. */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_DATE, - sc->cfg.mcode_date); - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_VERSION_NUM, - sc->cfg.mcode_version); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type); + + return 0; +} + + +int +AdwASC3550Cabling(iot, ioh, cfg) + bus_space_tag_t iot; + bus_space_handle_t ioh; + ADW_DVC_CFG *cfg; +{ + u_int16_t scsi_cfg1; - /* - * Set the chip type to indicate the ASC38C0800. - */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800); /* - * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. - * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current - * cable detection and then we are able to read C_DET[3:0]. + * Determine SCSI_CFG1 Microcode Default Value. * - * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 - * Microcode Default Value' section below. + * The microcode will set the SCSI_CFG1 register using this value + * after it is started below. */ + + /* Read current SCSI_CFG1 Register value. */ scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, - scsi_cfg1 | ADW_DIS_TERM_DRV); /* - * If the PCI Configuration Command Register "Parity Error Response - * Control" Bit was clear (0), then set the microcode variable - * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode - * to ignore DMA parity errors. + * If all three connectors are in use in ASC3550, return an error. */ - if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { - /* - * Note: Don't remove the use of a temporary variable in - * the following code, otherwise some C compiler - * might turn the following lines into a no-op. - */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); - word |= CONTROL_FLAG_IGNORE_PERR; - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_CONTROL_FLAG, word); + if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || + (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { + return ADW_IERR_ILLEGAL_CONNECTION; } /* - * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2] - * bits for the default FIFO threshold. - * - * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. - * - * For DMA Errata #4 set the BC_THRESH_ENB bit. + * If the cable is reversed all of the SCSI_CTRL register signals + * will be set. Check for and return an error if this condition is + * found. */ - ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, - BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); + if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ + return ADW_IERR_REVERSED_CABLE; + } /* - * Microcode operating variables for WDTR, SDTR, and command tag - * queuing will be set in AdvInquiryHandling() based on what a - * device reports it is capable of in Inquiry byte 7. - * - * If SCSI Bus Resets have been disabled, then directly set - * SDTR and WDTR from the EEPROM configuration. This will allow - * the BIOS and warm boot to work without a SCSI bus hang on - * the Inquiry caused by host and target mismatched DTR values. - * Without the SCSI Bus Reset, before an Inquiry a device can't - * be assumed to be in Asynchronous, Narrow mode. + * If this is a differential board and a single-ended device + * is attached to one of the connectors, return an error. */ - if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, sc->wdtr_able); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sc->sdtr_able); + if ((scsi_cfg1 & ADW_DIFF_MODE) && + (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { + return ADW_IERR_SINGLE_END_DEVICE; } /* - * Set microcode operating variables for DISC and SDTR_SPEED1, - * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM - * configuration values. + * If automatic termination control is enabled, then set the + * termination value based on a table listed in a_condor.h. * - * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, - * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them - * without determining here whether the device supports SDTR. + * If manual termination was specified with an EEPROM setting + * then 'termination' was set-up in AdwInitFromEEPROM() and + * is ready to be 'ored' into SCSI_CFG1. */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DISC_ENABLE, sc->cfg.disc_enable); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED1, sc->sdtr_speed1); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED2, sc->sdtr_speed2); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED3, sc->sdtr_speed3); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_SPEED4, sc->sdtr_speed4); + if (cfg->termination == 0) { + /* + * The software always controls termination by setting + * TERM_CTL_SEL. + * If TERM_CTL_SEL were set to 0, the hardware would set + * termination. + */ + cfg->termination |= ADW_TERM_CTL_SEL; + + switch(scsi_cfg1 & ADW_CABLE_DETECT) { + /* TERM_CTL_H: on, TERM_CTL_L: on */ + case 0x3: case 0x7: case 0xB: + case 0xD: case 0xE: case 0xF: + cfg->termination |= + (ADW_TERM_CTL_H | ADW_TERM_CTL_L); + break; + + /* TERM_CTL_H: on, TERM_CTL_L: off */ + case 0x1: case 0x5: case 0x9: + case 0xA: case 0xC: + cfg->termination |= ADW_TERM_CTL_H; + break; + + /* TERM_CTL_H: off, TERM_CTL_L: off */ + case 0x2: case 0x6: + break; + } + } /* - * Set SCSI_CFG0 Microcode Default Value. + * Clear any set TERM_CTL_H and TERM_CTL_L bits. + */ + scsi_cfg1 &= ~ADW_TERM_CTL; + + /* + * Invert the TERM_CTL_H and TERM_CTL_L bits and then + * set 'scsi_cfg1'. The TERM_POL bit does not need to be + * referenced, because the hardware internally inverts + * the Termination High and Low bits if TERM_POL is set. + */ + scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL)); + + /* + * Set SCSI_CFG1 Microcode Default Value * - * The microcode will set the SCSI_CFG0 register using this value + * Set filter value and possibly modified termination control + * bits in the Microcode SCSI_CFG1 Register Value. + * + * The microcode will set the SCSI_CFG1 register using this value * after it is started below. */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG0, - ADW_PARITY_EN | ADW_SEL_TMO_LONG | ADW_OUR_ID_EN | - sc->chip_scsi_id); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, + ADW_FLTR_DISABLE | scsi_cfg1); + + /* + * Set MEM_CFG Microcode Default Value + * + * The microcode will set the MEM_CFG register using this value + * after it is started below. + * + * MEM_CFG may be accessed as a word or byte, but only bits 0-7 + * are defined. + * + * ASC-3550 has 8KB internal memory. + */ + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, + ADW_BIOS_EN | ADW_RAM_SZ_8KB); + + return 0; +} + + +int +AdwASC38C0800Cabling(iot, ioh, cfg) + bus_space_tag_t iot; + bus_space_handle_t ioh; + ADW_DVC_CFG *cfg; +{ + u_int16_t scsi_cfg1; + /* * Determine SCSI_CFG1 Microcode Default Value. @@ -1036,26 +1324,29 @@ ADW_SOFTC *sc; scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); /* - * If the internal narrow cable is reversed all of the SCSI_CTRL - * register signals will be set. Check for and return an error if - * this condition is found. + * If the cable is reversed all of the SCSI_CTRL register signals + * will be set. Check for and return an error if this condition is + * found. */ - if ((ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CTRL) & 0x3F07) == - 0x3F07) { - return ASC_IERR_REVERSED_CABLE; + if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ + return ADW_IERR_REVERSED_CABLE; } /* - * All kind of combinations of devices attached to one of four connectors - * are acceptable except HVD device attached. For example, LVD device can - * be attached to SE connector while SE device attached to LVD connector. - * If LVD device attached to SE connector, it only runs up to Ultra speed. + * All kind of combinations of devices attached to one of four + * connectors are acceptable except HVD device attached. + * For example, LVD device can be attached to SE connector while + * SE device attached to LVD connector. + * If LVD device attached to SE connector, it only runs up to + * Ultra speed. * - * If an HVD device is attached to one of LVD connectors, return an error. - * However, there is no way to detect HVD device attached to SE connectors. + * If an HVD device is attached to one of LVD connectors, return + * an error. + * However, there is no way to detect HVD device attached to + * SE connectors. */ if (scsi_cfg1 & ADW_HVD) { - return ASC_IERR_HVD_DEVICE; + return ADW_IERR_HVD_DEVICE; } /* @@ -1063,30 +1354,30 @@ ADW_SOFTC *sc; * set the termination value based on a table listed in a_condor.h. * * If manual termination was specified with an EEPROM setting then - * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready to - * be 'ored' into SCSI_CFG1. + * 'termination' was set-up in AdwInitFromEEPROM() and is ready + * to be 'ored' into SCSI_CFG1. */ - if ((sc->cfg.termination & ADW_TERM_SE) == 0) { + if ((cfg->termination & ADW_TERM_SE) == 0) { /* SE automatic termination control is enabled. */ switch(scsi_cfg1 & ADW_C_DET_SE) { /* TERM_SE_HI: on, TERM_SE_LO: on */ case 0x1: case 0x2: case 0x3: - sc->cfg.termination |= ADW_TERM_SE; + cfg->termination |= ADW_TERM_SE; break; /* TERM_SE_HI: on, TERM_SE_LO: off */ case 0x0: - sc->cfg.termination |= ADW_TERM_SE_HI; + cfg->termination |= ADW_TERM_SE_HI; break; } } - if ((sc->cfg.termination & ADW_TERM_LVD) == 0) { + if ((cfg->termination & ADW_TERM_LVD) == 0) { /* LVD automatic termination control is enabled. */ switch(scsi_cfg1 & ADW_C_DET_LVD) { /* TERM_LVD_HI: on, TERM_LVD_LO: on */ case 0x4: case 0x8: case 0xC: - sc->cfg.termination |= ADW_TERM_LVD; + cfg->termination |= ADW_TERM_LVD; break; /* TERM_LVD_HI: off, TERM_LVD_LO: off */ @@ -1103,15 +1394,15 @@ ADW_SOFTC *sc; /* * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. */ - scsi_cfg1 |= (~sc->cfg.termination & 0xF0); + scsi_cfg1 |= (~cfg->termination & 0xF0); /* - * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits - * and set possibly modified termination control bits in the Microcode - * SCSI_CFG1 Register Value. + * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and + * HVD/LVD/SE bits and set possibly modified termination control bits + * in the Microcode SCSI_CFG1 Register Value. */ scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & - ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); + ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); /* * Set SCSI_CFG1 Microcode Default Value @@ -1122,499 +1413,147 @@ ADW_SOFTC *sc; * The microcode will set the SCSI_CFG1 register using this value * after it is started below. */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); /* * Set MEM_CFG Microcode Default Value * - * The microcode will set the MEM_CFG register using this value - * after it is started below. - * - * MEM_CFG may be accessed as a word or byte, but only bits 0-7 - * are defined. - * - * ASC-38C0800 has 16KB internal memory. - */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_MEM_CFG, - ADW_BIOS_EN | ADW_RAM_SZ_16KB); - - /* - * Set SEL_MASK Microcode Default Value - * - * The microcode will set the SEL_MASK register using this value - * after it is started below. - */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_DEFAULT_SEL_MASK, - ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); - - - /* - * Set-up the Host->RISC Initiator Command Queue (ICQ) if - * one is not already set up, i.e. this is the first - * time through as opposed to a bus reset. - */ - - if (sc->icq_sp == NULL) { - sc->carr_pending_cnt = 0; - if ((sc->icq_sp = sc->carr_freelist) == NULL) { - return ASC_IERR_NO_CARRIER; - } - sc->carr_freelist = adw_carrier_phys_kv(sc, - ASC_GET_CARRP(sc->icq_sp->next_vpa)); - - - /* - * The first command issued will be placed in the stopper carrier. - */ - sc->icq_sp->next_vpa = ASC_CQ_STOPPER; - } - - /* - * Set RISC ICQ physical address start value. - */ - ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_ICQ, sc->icq_sp->carr_pa); - - /* - * Set-up the RISC->Host Initiator Response Queue (IRQ) if - * one is not already set up, i.e. this is the first - * time through as opposed to a bus reset. - */ - if (sc->irq_sp == NULL) { - if ((sc->irq_sp = sc->carr_freelist) == NULL) { - return ASC_IERR_NO_CARRIER; - } - sc->carr_freelist = adw_carrier_phys_kv(sc, - ASC_GET_CARRP(sc->irq_sp->next_vpa)); - - /* - * The first command completed by the RISC will be placed in - * the stopper. - * - * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is - * completed the RISC will set the ASC_RQ_DONE bit. - */ - sc->irq_sp->next_vpa = ASC_CQ_STOPPER; - } - - /* - * Set RISC IRQ physical address start value. - */ - ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IRQ, sc->irq_sp->carr_pa); - - ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, - (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); - /* - * Note: Don't remove the use of a temporary variable in - * the following code, otherwise some C compiler - * might turn the following lines into a no-op. - */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_CODE_BEGIN_ADDR, word); - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); - - /* finally, finally, gentlemen, start your engine */ - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); - - /* - * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus - * Resets should be performed. The RISC has to be running - * to issue a SCSI Bus Reset. - */ - if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { - /* - * If the BIOS Signature is present in memory, restore the - * BIOS Handshake Configuration Table and do not perform - * a SCSI Bus Reset. - */ - if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == - 0x55AA) { - /* - * Restore per TID negotiated values. - */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, - tagqng_able); - for (tid = 0; tid <= ADW_MAX_TID; tid++) { - ADW_WRITE_BYTE_LRAM(iot, ioh, - ASC_MC_NUMBER_OF_MAX_CMD + tid, - max_cmd[tid]); - } - } else { - if (AdvResetCCB(sc) != ADW_TRUE) { - warn_code = ASC_WARN_BUSRESET_ERROR; - } - } - } - - return warn_code; -} - - -/* - * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and - * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while - * all of this is done. - * - * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. - * - * For a non-fatal error return a warning code. If there are no warnings - * then 0 is returned. - * - * Note: Chip is stopped on entry. - */ -int -AdvInitFrom3550EEP(sc) -ADW_SOFTC *sc; -{ - bus_space_tag_t iot = sc->sc_iot; - bus_space_handle_t ioh = sc->sc_ioh; - u_int16_t warn_code; - ADW_EEP_3550_CONFIG eep_config; - int i; - - - warn_code = 0; - - /* - * Read the board's EEPROM configuration. - * - * Set default values if a bad checksum is found. - */ - if (AdvGet3550EEPConfig(iot, ioh, &eep_config) != eep_config.check_sum){ - warn_code |= ASC_WARN_EEPROM_CHKSUM; - - /* - * Set EEPROM default values. - */ - for (i = 0; i < sizeof(ADW_EEP_3550_CONFIG); i++) { - *((u_int8_t *) &eep_config + i) = - *((u_int8_t *) &Default_3550_EEPROM_Config + i); - } - - /* - * Assume the 6 byte board serial number that was read - * from EEPROM is correct even if the EEPROM checksum - * failed. - */ - eep_config.serial_number_word3 = - AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); - - eep_config.serial_number_word2 = - AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); - - eep_config.serial_number_word1 = - AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); - - AdvSet3550EEPConfig(iot, ioh, &eep_config); - } - /* - * Set sc_VAR and sc_CFG variables from the - * EEPROM configuration that was read. - * - * This is the mapping of EEPROM fields to Adv Library fields. - */ - sc->wdtr_able = eep_config.wdtr_able; - sc->sdtr_able = eep_config.sdtr_able; - sc->ultra_able = eep_config.ultra_able; - sc->tagqng_able = eep_config.tagqng_able; - sc->cfg.disc_enable = eep_config.disc_enable; - sc->max_host_qng = eep_config.max_host_qng; - sc->max_dvc_qng = eep_config.max_dvc_qng; - sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); - sc->start_motor = eep_config.start_motor; - sc->scsi_reset_wait = eep_config.scsi_reset_delay; - sc->bios_ctrl = eep_config.bios_ctrl; - sc->no_scam = eep_config.scam_tolerant; - sc->cfg.serial1 = eep_config.serial_number_word1; - sc->cfg.serial2 = eep_config.serial_number_word2; - sc->cfg.serial3 = eep_config.serial_number_word3; - - /* - * Set the host maximum queuing (max. 253, min. 16) and the per device - * maximum queuing (max. 63, min. 4). - */ - if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { - eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; - } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) - { - /* If the value is zero, assume it is uninitialized. */ - if (eep_config.max_host_qng == 0) { - eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; - } else { - eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; - } - } - - if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { - eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; - } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { - /* If the value is zero, assume it is uninitialized. */ - if (eep_config.max_dvc_qng == 0) { - eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; - } else { - eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; - } - } - - /* - * If 'max_dvc_qng' is greater than 'max_host_qng', then - * set 'max_dvc_qng' to 'max_host_qng'. - */ - if (eep_config.max_dvc_qng > eep_config.max_host_qng) { - eep_config.max_dvc_qng = eep_config.max_host_qng; - } - - /* - * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' - * values based on possibly adjusted EEPROM values. - */ - sc->max_host_qng = eep_config.max_host_qng; - sc->max_dvc_qng = eep_config.max_dvc_qng; - - - /* - * If the EEPROM 'termination' field is set to automatic (0), then set - * the ADV_DVC_CFG 'termination' field to automatic also. - * - * If the termination is specified with a non-zero 'termination' - * value check that a legal value is set and set the ADV_DVC_CFG - * 'termination' field appropriately. - */ - if (eep_config.termination == 0) { - sc->cfg.termination = 0; /* auto termination */ - } else { - /* Enable manual control with low off / high off. */ - if (eep_config.termination == 1) { - sc->cfg.termination = ADW_TERM_CTL_SEL; - - /* Enable manual control with low off / high on. */ - } else if (eep_config.termination == 2) { - sc->cfg.termination = ADW_TERM_CTL_SEL | ADW_TERM_CTL_H; - - /* Enable manual control with low on / high on. */ - } else if (eep_config.termination == 3) { - sc->cfg.termination = ADW_TERM_CTL_SEL | - ADW_TERM_CTL_H | ADW_TERM_CTL_L; - } else { - /* - * The EEPROM 'termination' field contains a bad value. Use - * automatic termination instead. - */ - sc->cfg.termination = 0; - warn_code |= ASC_WARN_EEPROM_TERMINATION; - } - } - - return warn_code; -} - - -/* - * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and - * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while - * all of this is done. - * - * On failure set the ADV_DVC_VAR field 'err_code' and return ADW_ERROR. - * - * For a non-fatal error return a warning code. If there are no warnings - * then 0 is returned. - * - * Note: Chip is stopped on entry. - */ -int -AdvInitFrom38C0800EEP(sc) -ADW_SOFTC *sc; -{ - bus_space_tag_t iot = sc->sc_iot; - bus_space_handle_t ioh = sc->sc_ioh; - u_int16_t warn_code; - ADW_EEP_38C0800_CONFIG eep_config; - int i; - u_int8_t tid, termination; - u_int16_t sdtr_speed = 0; - - - warn_code = 0; - - /* - * Read the board's EEPROM configuration. + * The microcode will set the MEM_CFG register using this value + * after it is started below. * - * Set default values if a bad checksum is found. + * MEM_CFG may be accessed as a word or byte, but only bits 0-7 + * are defined. + * + * ASC-38C0800 has 16KB internal memory. */ - if (AdvGet38C0800EEPConfig(iot, ioh, &eep_config) != - eep_config.check_sum) { - warn_code |= ASC_WARN_EEPROM_CHKSUM; + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, + ADW_BIOS_EN | ADW_RAM_SZ_16KB); - /* - * Set EEPROM default values. - */ - for (i = 0; i < sizeof(ADW_EEP_38C0800_CONFIG); i++) { - *((u_int8_t *) &eep_config + i) = - *((u_int8_t *)&Default_38C0800_EEPROM_Config+i); - } + return 0; +} - /* - * Assume the 6 byte board serial number that was read - * from EEPROM is correct even if the EEPROM checksum - * failed. - */ - eep_config.serial_number_word3 = - AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 1); - eep_config.serial_number_word2 = - AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 2); +int +AdwASC38C1600Cabling(iot, ioh, cfg) + bus_space_tag_t iot; + bus_space_handle_t ioh; + ADW_DVC_CFG *cfg; +{ + u_int16_t scsi_cfg1; - eep_config.serial_number_word1 = - AdvReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - 3); - AdvSet38C0800EEPConfig(iot, ioh, &eep_config); - } /* - * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the - * EEPROM configuration that was read. + * Determine SCSI_CFG1 Microcode Default Value. * - * This is the mapping of EEPROM fields to Adv Library fields. + * The microcode will set the SCSI_CFG1 register using this value + * after it is started below. + * Each ASC-38C1600 function has only two cable detect bits. + * The bus mode override bits are in IOPB_SOFT_OVER_WR. */ - sc->wdtr_able = eep_config.wdtr_able; - sc->sdtr_speed1 = eep_config.sdtr_speed1; - sc->sdtr_speed2 = eep_config.sdtr_speed2; - sc->sdtr_speed3 = eep_config.sdtr_speed3; - sc->sdtr_speed4 = eep_config.sdtr_speed4; - sc->tagqng_able = eep_config.tagqng_able; - sc->cfg.disc_enable = eep_config.disc_enable; - sc->max_host_qng = eep_config.max_host_qng; - sc->max_dvc_qng = eep_config.max_dvc_qng; - sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); - sc->start_motor = eep_config.start_motor; - sc->scsi_reset_wait = eep_config.scsi_reset_delay; - sc->bios_ctrl = eep_config.bios_ctrl; - sc->no_scam = eep_config.scam_tolerant; - sc->cfg.serial1 = eep_config.serial_number_word1; - sc->cfg.serial2 = eep_config.serial_number_word2; - sc->cfg.serial3 = eep_config.serial_number_word3; + + /* Read current SCSI_CFG1 Register value. */ + scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); /* - * For every Target ID if any of its 'sdtr_speed[1234]' bits - * are set, then set an 'sdtr_able' bit for it. + * If the cable is reversed all of the SCSI_CTRL register signals + * will be set. Check for and return an error if this condition is + * found. */ - sc->sdtr_able = 0; - for (tid = 0; tid <= ADW_MAX_TID; tid++) { - if (tid == 0) { - sdtr_speed = sc->sdtr_speed1; - } else if (tid == 4) { - sdtr_speed = sc->sdtr_speed2; - } else if (tid == 8) { - sdtr_speed = sc->sdtr_speed3; - } else if (tid == 12) { - sdtr_speed = sc->sdtr_speed4; - } - if (sdtr_speed & ADW_MAX_TID) { - sc->sdtr_able |= (1 << tid); - } - sdtr_speed >>= 4; + if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ + return ADW_IERR_REVERSED_CABLE; } /* - * Set the host maximum queuing (max. 253, min. 16) and the per device - * maximum queuing (max. 63, min. 4). + * Each ASC-38C1600 function has two connectors. Only an HVD device + * can not be connected to either connector. An LVD device or SE device + * may be connected to either connecor. If an SE device is connected, + * then at most Ultra speed (20 Mhz) can be used on both connectors. + * + * If an HVD device is attached, return an error. */ - if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { - eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; - } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { - /* If the value is zero, assume it is uninitialized. */ - if (eep_config.max_host_qng == 0) { - eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; - } else { - eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; - } - } - - if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { - eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; - } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { - /* If the value is zero, assume it is uninitialized. */ - if (eep_config.max_dvc_qng == 0) { - eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; - } else { - eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; - } + if (scsi_cfg1 & ADW_HVD) { + return ADW_IERR_HVD_DEVICE; } /* - * If 'max_dvc_qng' is greater than 'max_host_qng', then - * set 'max_dvc_qng' to 'max_host_qng'. + * Each function in the ASC-38C1600 uses only the SE cable detect and + * termination because there are two connectors for each function. + * Each function may use either LVD or SE mode. + * Corresponding the SE automatic termination control EEPROM bits are + * used for each function. + * Each function has its own EEPROM. If SE automatic control is enabled + * for the function, then set the termination value based on a table + * listed in adwlib.h. + * + * If manual termination is specified in the EEPROM for the function, + * then 'termination' was set-up in AdwInitFromEEPROM() and is + * ready to be 'ored' into SCSI_CFG1. */ - if (eep_config.max_dvc_qng > eep_config.max_host_qng) { - eep_config.max_dvc_qng = eep_config.max_host_qng; + if ((cfg->termination & ADW_TERM_SE) == 0) { + /* SE automatic termination control is enabled. */ + switch(scsi_cfg1 & ADW_C_DET_SE) { + /* TERM_SE_HI: on, TERM_SE_LO: on */ + case 0x1: case 0x2: case 0x3: + cfg->termination |= ADW_TERM_SE; + break; + + case 0x0: + /* !!!!TODO!!!! */ +// if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) { + /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ +// } +// else +// { + /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ + cfg->termination |= ADW_TERM_SE_HI; +// } + break; + } } /* - * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' - * values based on possibly adjusted EEPROM values. + * Clear any set TERM_SE bits. */ - sc->max_host_qng = eep_config.max_host_qng; - sc->max_dvc_qng = eep_config.max_dvc_qng; + scsi_cfg1 &= ~ADW_TERM_SE; /* - * If the EEPROM 'termination' field is set to automatic (0), then set - * the ADV_DVC_CFG 'termination' field to automatic also. - * - * If the termination is specified with a non-zero 'termination' - * value check that a legal value is set and set the ADV_DVC_CFG - * 'termination' field appropriately. + * Invert the TERM_SE bits and then set 'scsi_cfg1'. */ - if (eep_config.termination_se == 0) { - termination = 0; /* auto termination for SE */ - } else { - /* Enable manual control with low off / high off. */ - if (eep_config.termination_se == 1) { - termination = 0; - - /* Enable manual control with low off / high on. */ - } else if (eep_config.termination_se == 2) { - termination = ADW_TERM_SE_HI; - - /* Enable manual control with low on / high on. */ - } else if (eep_config.termination_se == 3) { - termination = ADW_TERM_SE; - } else { - /* - * The EEPROM 'termination_se' field contains - * a bad value. - * Use automatic termination instead. - */ - termination = 0; - warn_code |= ASC_WARN_EEPROM_TERMINATION; - } - } + scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE); - if (eep_config.termination_lvd == 0) { - /* auto termination for LVD */ - sc->cfg.termination = termination; - } else - { - /* Enable manual control with low off / high off. */ - if (eep_config.termination_lvd == 1) { - sc->cfg.termination = termination; + /* + * Clear Big Endian and Terminator Polarity bits and set possibly + * modified termination control bits in the Microcode SCSI_CFG1 + * Register Value. + */ + scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); - /* Enable manual control with low off / high on. */ - } else if (eep_config.termination_lvd == 2) { - sc->cfg.termination = termination | ADW_TERM_LVD_HI; + /* + * Set SCSI_CFG1 Microcode Default Value + * + * Set possibly modified termination control bits in the Microcode + * SCSI_CFG1 Register Value. + * + * The microcode will set the SCSI_CFG1 register using this value + * after it is started below. + */ + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); - /* Enable manual control with low on / high on. */ - } else if (eep_config.termination_lvd == 3) { - sc->cfg.termination = termination | ADW_TERM_LVD; - } else { - /* - * The EEPROM 'termination_lvd' field contains a bad value. - * Use automatic termination instead. - */ - sc->cfg.termination = termination; - warn_code |= ASC_WARN_EEPROM_TERMINATION; - } - } + /* + * Set MEM_CFG Microcode Default Value + * + * The microcode will set the MEM_CFG register using this value + * after it is started below. + * + * MEM_CFG may be accessed as a word or byte, but only bits 0-7 + * are defined. + * + * ASC-38C1600 has 32KB internal memory. + */ + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, + ADW_BIOS_EN | ADW_RAM_SZ_32KB); - return warn_code; + return 0; } @@ -1624,10 +1563,10 @@ ADW_SOFTC *sc; * Return a checksum based on the EEPROM configuration read. */ static u_int16_t -AdvGet3550EEPConfig(iot, ioh, cfg_buf) +AdwGetEEPROMConfig(iot, ioh, cfg_buf) bus_space_tag_t iot; bus_space_handle_t ioh; - ADW_EEP_3550_CONFIG *cfg_buf; + ADW_EEPROM *cfg_buf; { u_int16_t wval, chksum; u_int16_t *wbuf; @@ -1638,58 +1577,19 @@ AdvGet3550EEPConfig(iot, ioh, cfg_buf) chksum = 0; for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; - eep_addr < ASC_EEP_DVC_CFG_END; - eep_addr++, wbuf++) { - wval = AdvReadEEPWord(iot, ioh, eep_addr); - chksum += wval; - *wbuf = wval; - } - - *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); - wbuf++; - for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; - eep_addr < ASC_EEP_MAX_WORD_ADDR; - eep_addr++, wbuf++) { - *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); - } - - return chksum; -} - - -/* - * Read EEPROM configuration into the specified buffer. - * - * Return a checksum based on the EEPROM configuration read. - */ -static u_int16_t -AdvGet38C0800EEPConfig(iot, ioh, cfg_buf) - bus_space_tag_t iot; - bus_space_handle_t ioh; - ADW_EEP_38C0800_CONFIG *cfg_buf; -{ - u_int16_t wval, chksum; - u_int16_t *wbuf; - int eep_addr; - - - wbuf = (u_int16_t *) cfg_buf; - chksum = 0; - - for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; - eep_addr < ASC_EEP_DVC_CFG_END; - eep_addr++, wbuf++) { - wval = AdvReadEEPWord(iot, ioh, eep_addr); + eep_addr < ASC_EEP_DVC_CFG_END; + eep_addr++, wbuf++) { + wval = AdwReadEEPWord(iot, ioh, eep_addr); chksum += wval; *wbuf = wval; } - *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); + *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); wbuf++; for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; eep_addr < ASC_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { - *wbuf = AdvReadEEPWord(iot, ioh, eep_addr); + *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); } return chksum; @@ -1700,14 +1600,14 @@ AdvGet38C0800EEPConfig(iot, ioh, cfg_buf) * Read the EEPROM from specified location */ static u_int16_t -AdvReadEEPWord(iot, ioh, eep_word_addr) +AdwReadEEPWord(iot, ioh, eep_word_addr) bus_space_tag_t iot; bus_space_handle_t ioh; int eep_word_addr; { ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_READ | eep_word_addr); - AdvWaitEEPCmd(iot, ioh); + AdwWaitEEPCmd(iot, ioh); return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); } @@ -1717,7 +1617,7 @@ AdvReadEEPWord(iot, ioh, eep_word_addr) * Wait for EEPROM command to complete */ static void -AdvWaitEEPCmd(iot, ioh) +AdwWaitEEPCmd(iot, ioh) bus_space_tag_t iot; bus_space_handle_t ioh; { @@ -1729,7 +1629,7 @@ AdvWaitEEPCmd(iot, ioh) ASC_EEP_CMD_DONE) { break; } - AdvSleepMilliSecond(1); + AdwSleepMilliSecond(1); } ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); @@ -1740,70 +1640,10 @@ AdvWaitEEPCmd(iot, ioh) * Write the EEPROM from 'cfg_buf'. */ static void -AdvSet3550EEPConfig(iot, ioh, cfg_buf) - bus_space_tag_t iot; - bus_space_handle_t ioh; - ADW_EEP_3550_CONFIG *cfg_buf; -{ - u_int16_t *wbuf; - u_int16_t addr, chksum; - - - wbuf = (u_int16_t *) cfg_buf; - chksum = 0; - - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); - AdvWaitEEPCmd(iot, ioh); - - /* - * Write EEPROM from word 0 to word 20 - */ - for (addr = ASC_EEP_DVC_CFG_BEGIN; - addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { - chksum += *wbuf; - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, - ASC_EEP_CMD_WRITE | addr); - AdvWaitEEPCmd(iot, ioh); - AdvSleepMilliSecond(ASC_EEP_DELAY_MS); - } - - /* - * Write EEPROM checksum at word 21 - */ - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, - ASC_EEP_CMD_WRITE | addr); - AdvWaitEEPCmd(iot, ioh); - wbuf++; /* skip over check_sum */ - - /* - * Write EEPROM OEM name at words 22 to 29 - */ - for (addr = ASC_EEP_DVC_CTL_BEGIN; - addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, - ASC_EEP_CMD_WRITE | addr); - AdvWaitEEPCmd(iot, ioh); - } - - ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, - ASC_EEP_CMD_WRITE_DISABLE); - AdvWaitEEPCmd(iot, ioh); - - return; -} - - -/* - * Write the EEPROM from 'cfg_buf'. - */ -static void -AdvSet38C0800EEPConfig(iot, ioh, cfg_buf) +AdwSetEEPROMConfig(iot, ioh, cfg_buf) bus_space_tag_t iot; bus_space_handle_t ioh; - ADW_EEP_38C0800_CONFIG *cfg_buf; + ADW_EEPROM *cfg_buf; { u_int16_t *wbuf; u_int16_t addr, chksum; @@ -1813,7 +1653,7 @@ AdvSet38C0800EEPConfig(iot, ioh, cfg_buf) chksum = 0; ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); - AdvWaitEEPCmd(iot, ioh); + AdwWaitEEPCmd(iot, ioh); /* * Write EEPROM from word 0 to word 20 @@ -1824,8 +1664,8 @@ AdvSet38C0800EEPConfig(iot, ioh, cfg_buf) ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); - AdvWaitEEPCmd(iot, ioh); - AdvSleepMilliSecond(ASC_EEP_DELAY_MS); + AdwWaitEEPCmd(iot, ioh); + AdwSleepMilliSecond(ASC_EEP_DELAY_MS); } /* @@ -1834,7 +1674,7 @@ AdvSet38C0800EEPConfig(iot, ioh, cfg_buf) ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); - AdvWaitEEPCmd(iot, ioh); + AdwWaitEEPCmd(iot, ioh); wbuf++; /* skip over check_sum */ /* @@ -1845,19 +1685,19 @@ AdvSet38C0800EEPConfig(iot, ioh, cfg_buf) ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); - AdvWaitEEPCmd(iot, ioh); + AdwWaitEEPCmd(iot, ioh); } ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); - AdvWaitEEPCmd(iot, ioh); + AdwWaitEEPCmd(iot, ioh); return; } /* - * AdvExeScsiQueue() - Send a request to the RISC microcode program. + * AdwExeScsiQueue() - Send a request to the RISC microcode program. * * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, * add the carrier to the ICQ (Initiator Command Queue), and tickle the @@ -1874,7 +1714,7 @@ AdvSet38C0800EEPConfig(iot, ioh, cfg_buf) * host IC error. */ int -AdvExeScsiQueue(sc, scsiq) +AdwExeScsiQueue(sc, scsiq) ADW_SOFTC *sc; ADW_SCSI_REQ_Q *scsiq; { @@ -1883,9 +1723,7 @@ ADW_SCSI_REQ_Q *scsiq; ADW_CCB *ccb; long req_size; u_int32_t req_paddr; - ADW_CARRIER *new_carrp, *new_freep/*, *ccb_carr; - int i*/; - + ADW_CARRIER *new_carrp; /* * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. @@ -1896,29 +1734,28 @@ ADW_SCSI_REQ_Q *scsiq; return ADW_ERROR; } + /* + * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair + */ + ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); - ccb->carr_list = sc->icq_sp; /* - * Allocate a carrier ensuring at least one carrier always - * remains on the freelist and initialize fields. + * Allocate a carrier and initialize fields. */ - new_carrp = sc->carr_freelist; - new_freep = adw_carrier_phys_kv( sc, - ASC_GET_CARRP( new_carrp->next_vpa) ); - - if (new_freep == NULL) { + if ((new_carrp = sc->carr_freelist) == NULL) { return ADW_BUSY; } - sc->carr_freelist = new_freep; + sc->carr_freelist = ADW_CARRIER_VADDR(sc, + ASC_GET_CARRP(new_carrp->next_ba)); sc->carr_pending_cnt++; /* - * Set the carrier to be a stopper by setting 'next_vpa' + * Set the carrier to be a stopper by setting 'next_ba' * to the stopper value. The current stopper will be changed * below to point to the new stopper. */ - new_carrp->next_vpa = ASC_CQ_STOPPER; + new_carrp->next_ba = ASC_CQ_STOPPER; req_size = sizeof(ADW_SCSI_REQ_Q); req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + @@ -1928,81 +1765,73 @@ ADW_SCSI_REQ_Q *scsiq; scsiq->scsiq_rptr = req_paddr; /* - * Every ADV_CARR_T.carr_pa is byte swapped to little-endian + * Every ADV_CARR_T.carr_ba is byte swapped to little-endian * order during initialization. */ - scsiq->carr_pa = sc->icq_sp->carr_pa; - scsiq->carr_va = sc->icq_sp->carr_pa; + scsiq->carr_ba = sc->icq_sp->carr_ba; + scsiq->carr_va = sc->icq_sp->carr_ba; /* * Use the current stopper to send the ADW_SCSI_REQ_Q command to * the microcode. The newly allocated stopper will become the new * stopper. */ - sc->icq_sp->areq_vpa = req_paddr; + sc->icq_sp->areq_ba = req_paddr; /* - * Set the 'next_vpa' pointer for the old stopper to be the + * Set the 'next_ba' pointer for the old stopper to be the * physical address of the new stopper. The RISC can only * follow physical addresses. */ - sc->icq_sp->next_vpa = new_carrp->carr_pa; + sc->icq_sp->next_ba = new_carrp->carr_ba; +#if ADW_DEBUG + printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", + sc->icq_sp->carr_id, + sc->icq_sp->carr_ba, + sc->icq_sp->areq_ba, + sc->icq_sp->next_ba); +#endif /* * Set the host adapter stopper pointer to point to the new carrier. */ sc->icq_sp = new_carrp; -/* ccb_carr = ccb->carr_list; - while(ccb_carr != ASC_CQ_STOPPER) { - bus_dmamap_load(sc->sc_dmat, ccb_carr->dmamap_xfer, - ccb_carr, ADW_CARRIER_SIZE, - NULL, BUS_DMA_NOWAIT); - bus_dmamap_sync(sc->sc_dmat, ccb_carr->dmamap_xfer, 0, - ccb_carr->dmamap_xfer->dm_mapsize, - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - ccb_carr = adw_carrier_phys_kv(sc, - ASC_GET_CARRP(ccb_carr->next_vpa)); - } - - ccb_carr = sc->irq_sp; - for(i=0; i<2 && ccb_carr != ASC_CQ_STOPPER; i++) { - bus_dmamap_load(sc->sc_dmat, ccb_carr->dmamap_xfer, - ccb_carr, ADW_CARRIER_SIZE, - NULL, BUS_DMA_NOWAIT); - bus_dmamap_sync(sc->sc_dmat, ccb_carr->dmamap_xfer, 0, - ccb_carr->dmamap_xfer->dm_mapsize, - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - ccb_carr = adw_carrier_phys_kv(sc, - ASC_GET_CARRP(ccb_carr->next_vpa)); - } -*/ - bus_dmamap_load(sc->sc_dmat, sc->sc_control->dmamap_xfer, - sc->sc_control->carriers, ADW_CARRIER_SIZE * ADW_MAX_CARRIER, - NULL, BUS_DMA_NOWAIT); - bus_dmamap_sync(sc->sc_dmat, sc->sc_control->dmamap_xfer, - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - - /* - * Tickle the RISC to tell it to read its Command Queue Head pointer. - */ - ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_A); - if (sc->chip_type == ADV_CHIP_ASC3550) - { + if (sc->chip_type == ADW_CHIP_ASC3550 || + sc->chip_type == ADW_CHIP_ASC38C0800) { /* - * Clear the tickle value. In the ASC-3550 the RISC flag - * command 'clr_tickle_a' does not work unless the host - * value is cleared. + * Tickle the RISC to tell it to read its Command Queue Head + * pointer. */ - ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_NOP); + ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_A); + if (sc->chip_type == ADW_CHIP_ASC3550) { + /* + * Clear the tickle value. In the ASC-3550 the RISC flag + * command 'clr_tickle_a' does not work unless the host + * value is cleared. + */ + ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, + ADV_TICKLE_NOP); + } + } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { + /* + * Notify the RISC a carrier is ready by writing the physical + * address of the new carrier stopper to the COMMA register. + */ + ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, + new_carrp->carr_ba); } + /* + * End of CRITICAL SECTION: Must be protected within splbio/splx pair + */ + return ADW_SUCCESS; } void -AdvResetChip(iot, ioh) +AdwResetChip(iot, ioh) bus_space_tag_t iot; bus_space_handle_t ioh; { @@ -2012,7 +1841,7 @@ AdvResetChip(iot, ioh) */ ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, ADW_CTRL_REG_CMD_RESET); - AdvSleepMilliSecond(100); + AdwSleepMilliSecond(100); ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG); } @@ -2028,7 +1857,7 @@ AdvResetChip(iot, ioh) * may be hung which requires driver recovery. */ int -AdvResetCCB(sc) +AdwResetCCB(sc) ADW_SOFTC *sc; { int status; @@ -2037,9 +1866,8 @@ ADW_SOFTC *sc; * Send the SCSI Bus Reset idle start idle command which asserts * the SCSI Bus Reset signal. */ - status = AdvSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); - if (status != ADW_TRUE) - { + status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); + if (status != ADW_TRUE) { return status; } @@ -2049,19 +1877,18 @@ ADW_SOFTC *sc; * The hold time delay is done on the host because the RISC has no * microsecond accurate timer. */ - AdvDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); + AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); /* * Send the SCSI Bus Reset end idle command which de-asserts * the SCSI Bus Reset signal and purges any pending requests. */ - status = AdvSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); - if (status != ADW_TRUE) - { + status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); + if (status != ADW_TRUE) { return status; } - AdvSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); + AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); return status; } @@ -2075,13 +1902,13 @@ ADW_SOFTC *sc; * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. */ int -AdvResetSCSIBus(sc) +AdwResetSCSIBus(sc) ADW_SOFTC *sc; { bus_space_tag_t iot = sc->sc_iot; bus_space_handle_t ioh = sc->sc_ioh; int status; - u_int16_t wdtr_able, sdtr_able, tagqng_able; + u_int16_t wdtr_able, sdtr_able, ppr_able, tagqng_able; u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; u_int16_t bios_sig; @@ -2089,23 +1916,25 @@ ADW_SOFTC *sc; /* * Save current per TID negotiated values. */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); - for (tid = 0; tid <= ADW_MAX_TID; tid++) - { - ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); + if (sc->chip_type == ADW_CHIP_ASC38C1600) { + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); + } + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); + for (tid = 0; tid <= ADW_MAX_TID; tid++) { + ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, max_cmd[tid]); } /* - * Force the AdvInitAsc3550/38C0800Driver() function to - * perform a SCSI Bus Reset by clearing the BIOS signature word. + * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset + * by clearing the BIOS signature word. * The initialization functions assumes a SCSI Bus Reset is not * needed if the BIOS signature word is present. */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, bios_sig); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, 0); + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); /* * Stop chip and reset it. @@ -2113,40 +1942,33 @@ ADW_SOFTC *sc; ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, ADW_CTRL_REG_CMD_RESET); - AdvSleepMilliSecond(100); + AdwSleepMilliSecond(100); ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG); /* * Reset Adv Library error code, if any, and try * re-initializing the chip. + * Then translate initialization return value to status value. */ - if (sc->chip_type == ADV_CHIP_ASC38C0800) { - status = AdvInitAsc38C0800Driver(sc); - } else { - status = AdvInitAsc3550Driver(sc); - } - - /* Translate initialization return value to status value. */ - if (status == 0) { - status = ADW_TRUE; - } else { - status = ADW_FALSE; - } + status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE; /* * Restore the BIOS signature word. */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_BIOS_SIGNATURE, bios_sig); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); /* * Restore per TID negotiated values. */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, wdtr_able); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, sdtr_able); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, tagqng_able); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); + if (sc->chip_type == ADW_CHIP_ASC38C1600) { + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); + } + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); for (tid = 0; tid <= ADW_MAX_TID; tid++) { - ADW_WRITE_BYTE_LRAM(iot, ioh, ASC_MC_NUMBER_OF_MAX_CMD + tid, + ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, max_cmd[tid]); } @@ -2163,7 +1985,7 @@ ADW_SOFTC *sc; * When a microcode idle command is completed, the ADV_DVC_VAR * 'idle_cmd_done' field is set to ADW_TRUE. * - * Note: AdvISR() can be called when interrupts are disabled or even + * Note: AdwISR() can be called when interrupts are disabled or even * when there is no hardware interrupt condition present. It will * always check for completed idle commands and microcode requests. * This is an important feature that shouldn't be changed because it @@ -2174,7 +1996,7 @@ ADW_SOFTC *sc; * ADW_FALSE(0) - no interrupt was pending */ int -AdvISR(sc) +AdwISR(sc) ADW_SOFTC *sc; { bus_space_tag_t iot = sc->sc_iot; @@ -2185,46 +2007,41 @@ ADW_SOFTC *sc; u_int32_t irq_next_pa; ADW_SCSI_REQ_Q *scsiq; ADW_CCB *ccb; -// int i; + int s; + s = splbio(); + /* Reading the register clears the interrupt. */ int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | ADW_INTR_STATUS_INTRC)) == 0) { + splx(s); return ADW_FALSE; } - bus_dmamap_sync(sc->sc_dmat, sc->sc_control->dmamap_xfer, - BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); - bus_dmamap_unload(sc->sc_dmat, sc->sc_control->dmamap_xfer); - -/* ccb_carr = sc->irq_sp; - for(i=0; i<2 && ccb_carr != ASC_CQ_STOPPER; i++) { - bus_dmamap_sync(sc->sc_dmat, ccb_carr->dmamap_xfer, 0, - ccb_carr->dmamap_xfer->dm_mapsize, - BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); - bus_dmamap_unload(sc->sc_dmat, ccb_carr->dmamap_xfer); - ccb_carr = adw_carrier_phys_kv(sc, - ASC_GET_CARRP(ccb_carr->next_vpa)); - } -*/ /* * Notify the driver of an asynchronous microcode condition by * calling the ADV_DVC_VAR.async_callback function. The function - * is passed the microcode ASC_MC_INTRB_CODE byte value. + * is passed the microcode ADW_MC_INTRB_CODE byte value. */ if (int_stat & ADW_INTR_STATUS_INTRB) { u_int8_t intrb_code; - ADW_READ_BYTE_LRAM(iot, ioh, ASC_MC_INTRB_CODE, intrb_code); - if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && - sc->carr_pending_cnt != 0) { - ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_A); - if (sc->chip_type == ADV_CHIP_ASC3550) { - ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_NOP); - } + ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); + + if (sc->chip_type == ADW_CHIP_ASC3550 || + sc->chip_type == ADW_CHIP_ASC38C0800) { + if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && + sc->carr_pending_cnt != 0) { + ADW_WRITE_BYTE_REGISTER(iot, ioh, + IOPB_TICKLE, ADV_TICKLE_A); + if (sc->chip_type == ADW_CHIP_ASC3550) { + ADW_WRITE_BYTE_REGISTER(iot, ioh, + IOPB_TICKLE, ADV_TICKLE_NOP); + } + } } if (sc->async_callback != 0) { @@ -2235,45 +2052,50 @@ ADW_SOFTC *sc; /* * Check if the IRQ stopper carrier contains a completed request. */ - while (((irq_next_pa = sc->irq_sp->next_vpa) & ASC_RQ_DONE) != 0) + while (((irq_next_pa = sc->irq_sp->next_ba) & ASC_RQ_DONE) != 0) { +#if ADW_DEBUG + printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", + sc->irq_sp->carr_id, + sc->irq_sp->carr_ba, + sc->irq_sp->areq_ba, + sc->irq_sp->next_ba); +#endif /* - * Get a pointer to the newly completed ADW_SCSI_REQ_Q structure. - * The RISC will have set 'areq_vpa' to a virtual address. + * Get a pointer to the newly completed ADW_SCSI_REQ_Q + * structure. + * The RISC will have set 'areq_ba' to a virtual address. * * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr - * field to the carrier ADV_CARR_T.areq_vpa field. The conversion - * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr' - * in AdvExeScsiQueue(). + * field to the carrier ADV_CARR_T.areq_ba field. + * The conversion below complements the conversion of + * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue(). */ - ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_vpa); + ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); scsiq = &ccb->scsiq; - scsiq->ccb_ptr = sc->irq_sp->areq_vpa; - -/* ccb_carr = ccb->carr_list; - while(ccb_carr != ASC_CQ_STOPPER) { - bus_dmamap_sync(sc->sc_dmat, ccb_carr->dmamap_xfer, 0, - ccb_carr->dmamap_xfer->dm_mapsize, - BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); - bus_dmamap_unload(sc->sc_dmat, ccb_carr->dmamap_xfer); - ccb_carr = adw_carrier_phys_kv(sc, - ASC_GET_CARRP(ccb_carr->next_vpa)); + scsiq->ccb_ptr = sc->irq_sp->areq_ba; + + /* + * Request finished with good status and the queue was not + * DMAed to host memory by the firmware. Set all status fields + * to indicate good status. + */ + if ((irq_next_pa & ASC_RQ_GOOD) != 0) { + scsiq->done_status = QD_NO_ERROR; + scsiq->host_status = scsiq->scsi_status = 0; + scsiq->data_cnt = 0L; } - bus_dmamap_sync(sc->sc_dmat, sc->irq_sp->dmamap_xfer, 0, - sc->irq_sp->dmamap_xfer->dm_mapsize, - BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); - bus_dmamap_unload(sc->sc_dmat, sc->irq_sp->dmamap_xfer); -*/ /* * Advance the stopper pointer to the next carrier * ignoring the lower four bits. Free the previous * stopper carrier. */ free_carrp = sc->irq_sp; - sc->irq_sp = adw_carrier_phys_kv(sc, ASC_GET_CARRP(irq_next_pa)); + sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa)); - free_carrp->next_vpa = sc->carr_freelist->carr_pa; + free_carrp->next_ba = (sc->carr_freelist == NULL)? NULL + : sc->carr_freelist->carr_ba; sc->carr_freelist = free_carrp; sc->carr_pending_cnt--; @@ -2294,9 +2116,9 @@ ADW_SOFTC *sc; * command information for the device. */ if (scsiq->done_status == QD_NO_ERROR && - scsiq->cdb[0] == INQUIRY && - scsiq->target_lun == 0) { - AdvInquiryHandling(sc, scsiq); + scsiq->cdb[0] == INQUIRY && + scsiq->target_lun == 0) { + AdwInquiryHandling(sc, scsiq); } /* @@ -2313,6 +2135,8 @@ ADW_SOFTC *sc; */ } + splx(s); + return ADW_TRUE; } @@ -2332,25 +2156,23 @@ ADW_SOFTC *sc; * ADW_ERROR - command timed out */ int -AdvSendIdleCmd(sc, idle_cmd, idle_cmd_parameter) +AdwSendIdleCmd(sc, idle_cmd, idle_cmd_parameter) ADW_SOFTC *sc; u_int16_t idle_cmd; u_int32_t idle_cmd_parameter; { bus_space_tag_t iot = sc->sc_iot; bus_space_handle_t ioh = sc->sc_ioh; - int result; - u_int32_t s, i, j; - + u_int16_t result; + u_int32_t i, j, s; + s = splbio(); /* * Clear the idle command status which is set by the microcode * to a non-zero value to indicate when the command is completed. - * The non-zero result is one of the IDLE_CMD_STATUS_* values - * defined in a_advlib.h. */ - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_STATUS, (u_int16_t) 0); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); /* * Write the idle command value after the idle command parameter @@ -2358,15 +2180,15 @@ u_int32_t idle_cmd_parameter; * followed, the microcode may process the idle command before the * parameters have been written to LRAM. */ - ADW_WRITE_DWORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_PARAMETER, - idle_cmd_parameter); - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD, idle_cmd); + ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, + idle_cmd_parameter); + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); /* * Tickle the RISC to tell it to process the idle command. */ ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADV_TICKLE_B); - if (sc->chip_type == ADV_CHIP_ASC3550) { + if (sc->chip_type == ADW_CHIP_ASC3550) { /* * Clear the tickle value. In the ASC-3550 the RISC flag * command 'clr_tickle_b' does not work unless the host @@ -2379,12 +2201,13 @@ u_int32_t idle_cmd_parameter; for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { /* Poll once each microsecond for command completion. */ for (j = 0; j < SCSI_US_PER_MSEC; j++) { - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_IDLE_CMD_STATUS, result); + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, + result); if (result != 0) { splx(s); return result; } - AdvDelayMicroSecond(1); + AdwDelayMicroSecond(1); } } @@ -2401,7 +2224,7 @@ u_int32_t idle_cmd_parameter; * Queuing. */ static void -AdvInquiryHandling(sc, scsiq) +AdwInquiryHandling(sc, scsiq) ADW_SOFTC *sc; ADW_SCSI_REQ_Q *scsiq; { @@ -2415,7 +2238,7 @@ ADW_SCSI_REQ_Q *scsiq; /* - * AdvInquiryHandling() requires up to INQUIRY information Byte 7 + * AdwInquiryHandling() requires up to INQUIRY information Byte 7 * to be available. * * If less than 8 bytes of INQUIRY information were requested or less @@ -2430,12 +2253,13 @@ ADW_SCSI_REQ_Q *scsiq; tid = scsiq->target_id; - inq = (ADW_SCSI_INQUIRY *) scsiq->vdata_addr; + inq = (ADW_SCSI_INQUIRY *) scsiq->vdata_addr; /* * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. */ - if (inq->rsp_data_fmt < 2 && inq->ansi_apr_ver < 2) { + if ((inq->rsp_data_fmt < 2) /*SCSI-1 | CCS*/ && + (inq->ansi_apr_ver < 2)) { return; } else { /* @@ -2461,29 +2285,30 @@ ADW_SCSI_REQ_Q *scsiq; if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) #endif /* SCSI_ADW_WDTR_DISABLE */ if ((sc->wdtr_able & tidmask) && inq->WBus16) { - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, cfg_word); if ((cfg_word & tidmask) == 0) { cfg_word |= tidmask; - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_ABLE, + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, cfg_word); /* - * Clear the microcode "SDTR negotiation" and "WDTR - * negotiation" done indicators for the target to cause - * it to negotiate with the new setting set above. + * Clear the microcode "SDTR negotiation" and + * "WDTR negotiation" done indicators for the + * target to cause it to negotiate with the new + * setting set above. * WDTR when accepted causes the target to enter - * asynchronous mode, so SDTR must be negotiated. + * asynchronous mode, so SDTR must be negotiated */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, cfg_word); cfg_word &= ~tidmask; - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, cfg_word); - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, cfg_word); cfg_word &= ~tidmask; - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_WDTR_DONE, + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, cfg_word); } } @@ -2499,24 +2324,48 @@ ADW_SCSI_REQ_Q *scsiq; if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) #endif /* SCSI_ADW_SDTR_DISABLE */ if ((sc->sdtr_able & tidmask) && inq->Sync) { - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, cfg_word); + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word); if ((cfg_word & tidmask) == 0) { cfg_word |= tidmask; - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_ABLE, + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, cfg_word); /* - * Clear the microcode "SDTR negotiation" done indicator - * for the target to cause it to negotiate with the new - * setting set above. + * Clear the microcode "SDTR negotiation" + * done indicator for the target to cause it + * to negotiate with the new setting set above. */ - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, cfg_word); cfg_word &= ~tidmask; - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_SDTR_DONE, + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, cfg_word); } } + /* + * If the Inquiry data included enough space for the SPI-3 + * Clocking field, then check if DT mode is supported. + */ + if (sc->chip_type == ADW_CHIP_ASC38C1600 && + (scsiq->cdb[4] >= 57 || + (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { + /* + * PPR (Parallel Protocol Request) Capable + * + * If the device supports DT mode, then it must be + * PPR capable. + * The PPR message will be used in place of the SDTR + * and WDTR messages to negotiate synchronous speed + * and offset, transfer width, and protocol options. + */ + if((inq->Clocking) & INQ_CLOCKING_DT_ONLY){ + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, + sc->ppr_able); + sc->ppr_able |= tidmask; + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, + sc->ppr_able); + } + } /* * If the EEPROM enabled Tag Queuing for the device and the @@ -2534,14 +2383,14 @@ ADW_SCSI_REQ_Q *scsiq; if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) #endif /* SCSI_ADW_TAGQ_DISABLE */ if ((sc->tagqng_able & tidmask) && inq->CmdQue) { - ADW_READ_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, + ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, cfg_word); cfg_word |= tidmask; - ADW_WRITE_WORD_LRAM(iot, ioh, ASC_MC_TAGQNG_ABLE, + ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, cfg_word); ADW_WRITE_BYTE_LRAM(iot, ioh, - ASC_MC_NUMBER_OF_MAX_CMD + tid, + ADW_MC_NUMBER_OF_MAX_CMD + tid, sc->max_dvc_qng); } } @@ -2550,7 +2399,7 @@ ADW_SCSI_REQ_Q *scsiq; static void -AdvSleepMilliSecond(n) +AdwSleepMilliSecond(n) u_int32_t n; { @@ -2559,7 +2408,7 @@ u_int32_t n; static void -AdvDelayMicroSecond(n) +AdwDelayMicroSecond(n) u_int32_t n; { diff --git a/sys/dev/ic/adwlib.h b/sys/dev/ic/adwlib.h index 9aee6d7ed0e..68d5205aba0 100644 --- a/sys/dev/ic/adwlib.h +++ b/sys/dev/ic/adwlib.h @@ -1,5 +1,5 @@ -/* $OpenBSD: adwlib.h,v 1.3 2000/04/29 21:12:31 krw Exp $ */ -/* $NetBSD: adwlib.h,v 1.7 2000/02/03 20:29:16 dante Exp $ */ +/* $OpenBSD: adwlib.h,v 1.4 2000/06/29 00:04:31 krw Exp $ */ +/* $NetBSD: adwlib.h,v 1.13 2000/05/27 18:24:50 dante Exp $ */ /* * Definitions for low level routines and data structures @@ -43,10 +43,10 @@ */ /* * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters - * - * Copyright (c) 1995-1996 Advanced System Products, Inc. + * + * Copyright (c) 1995-2000 Advanced System Products, Inc. * All Rights Reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that redistributions of source * code retain the above copyright notice and this comment without @@ -62,11 +62,18 @@ */ #define ADW_LIB_VERSION_MAJOR 5 -#define ADW_LIB_VERSION_MINOR 2 +#define ADW_LIB_VERSION_MINOR 8 + + +/* If the result wraps when calculating tenths, return 0. */ +#define ADW_TENTHS(num, den) \ + (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \ + 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den))))) + /* * Define Adv Reset Hold Time grater than 25 uSec. - * See AdvResetSCSIBus() for more info. + * See AdwResetSCSIBus() for more info. */ #define ASC_SCSI_RESET_HOLD_TIME_US 60 @@ -101,8 +108,7 @@ * this field may be set, but later if a device is found to be incapable * of the feature, the field is cleared. * - * Default values are maintained in a_init.c in the structure - * Default_EEPROM_Config. + * Default values are maintained in the structure Default_EEPROM_Config. */ #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ @@ -114,7 +120,20 @@ #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */ -typedef struct adw_eep_3550_config +/* + * ASC38C1600 Bit 11 + * + * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify + * INT A in the PCI Configuration Space Int Pin field. If it is 1, then + * Function 0 will specify INT B. + * + * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify + * INT B in the PCI Configuration Space Int Pin field. If it is 1, then + * Function 1 will specify INT A. + */ +#define ADW_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */ + +typedef struct adw_eeprom { /* Word Offset, Description */ @@ -122,80 +141,13 @@ typedef struct adw_eep_3550_config /* bit 13 set - Term Polarity Control */ /* bit 14 set - BIOS Enable */ /* bit 15 set - Big Endian Mode */ - u_int16_t cfg_msw; /* 01 unused */ - u_int16_t disc_enable; /* 02 disconnect enable */ - u_int16_t wdtr_able; /* 03 Wide DTR able */ - u_int16_t sdtr_able; /* 04 Synchronous DTR able */ - u_int16_t start_motor; /* 05 send start up motor */ - u_int16_t tagqng_able; /* 06 tag queuing able */ - u_int16_t bios_scan; /* 07 BIOS device control */ - u_int16_t scam_tolerant; /* 08 no scam */ - - u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ - u_int8_t bios_boot_delay; /* power up wait */ - - u_int8_t scsi_reset_delay; /* 10 reset delay */ - u_int8_t bios_id_lun; /* first boot device scsi id & lun */ - /* high nibble is lun */ - /* low nibble is scsi id */ - - u_int8_t termination; /* 11 0 - automatic */ - /* 1 - low off / high off */ - /* 2 - low off / high on */ - /* 3 - low on / high on */ - /* There is no low on / high off */ - - u_int8_t reserved1; /* reserved byte (not used) */ - - u_int16_t bios_ctrl; /* 12 BIOS control bits */ - /* bit 0 set: BIOS don't act as initiator. */ - /* bit 1 set: BIOS > 1 GB support */ - /* bit 2 set: BIOS > 2 Disk Support */ - /* bit 3 set: BIOS don't support removables */ - /* bit 4 set: BIOS support bootable CD */ - /* bit 5 set: */ - /* bit 6 set: BIOS support multiple LUNs */ - /* bit 7 set: BIOS display of message */ - /* bit 8 set: */ - /* bit 9 set: Reset SCSI bus during init. */ - /* bit 10 set: */ - /* bit 11 set: No verbose initialization. */ - /* bit 12 set: SCSI parity enabled */ - /* bit 13 set: */ - /* bit 14 set: */ - /* bit 15 set: */ - u_int16_t ultra_able; /* 13 ULTRA speed able */ - u_int16_t reserved2; /* 14 reserved */ - u_int8_t max_host_qng; /* 15 maximum host queuing */ - u_int8_t max_dvc_qng; /* maximum per device queuing */ - u_int16_t dvc_cntl; /* 16 control bit for driver */ - u_int16_t bug_fix; /* 17 control bit for bug fix */ - u_int16_t serial_number_word1; /* 18 Board serial number word 1 */ - u_int16_t serial_number_word2; /* 19 Board serial number word 2 */ - u_int16_t serial_number_word3; /* 20 Board serial number word 3 */ - u_int16_t check_sum; /* 21 EEP check sum */ - u_int8_t oem_name[16]; /* 22 OEM name */ - u_int16_t dvc_err_code; /* 30 last device driver error code */ - u_int16_t adv_err_code; /* 31 last uc and Adv Lib error code */ - u_int16_t adv_err_addr; /* 32 last uc error address */ - u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ - u_int16_t saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ - u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ - u_int16_t num_of_err; /* 36 number of error */ -} ADW_EEP_3550_CONFIG; - -typedef struct adw_eep_38C0800_config -{ - /* Word Offset, Description */ - - u_int16_t cfg_lsw; /* 00 power up initialization */ - /* bit 13 set - Load CIS */ - /* bit 14 set - BIOS Enable */ - /* bit 15 set - Big Endian Mode */ - u_int16_t cfg_msw; /* 01 unused */ + u_int16_t cfg_msw; /* 01 unused */ u_int16_t disc_enable; /* 02 disconnect enable */ u_int16_t wdtr_able; /* 03 Wide DTR able */ - u_int16_t sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ + union { + u_int16_t sdtr_able; /* 04 Synchronous DTR able */ + u_int16_t sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ + } sdtr1; u_int16_t start_motor; /* 05 send start up motor */ u_int16_t tagqng_able; /* 06 tag queuing able */ u_int16_t bios_scan; /* 07 BIOS device control */ @@ -222,68 +174,54 @@ typedef struct adw_eep_38C0800_config /* There is no low on / high off */ u_int16_t bios_ctrl; /* 12 BIOS control bits */ - /* bit 0 set: BIOS don't act as initiator. */ - /* bit 1 set: BIOS > 1 GB support */ - /* bit 2 set: BIOS > 2 Disk Support */ - /* bit 3 set: BIOS don't support removables */ - /* bit 4 set: BIOS support bootable CD */ - /* bit 5 set: BIOS scan enabled */ - /* bit 6 set: BIOS support multiple LUNs */ - /* bit 7 set: BIOS display of message */ - /* bit 8 set: */ - /* bit 9 set: Reset SCSI bus during init. */ - /* bit 10 set: */ - /* bit 11 set: No verbose initialization. */ - /* bit 12 set: SCSI parity enabled */ - /* bit 13 set: */ - /* bit 14 set: */ - /* bit 15 set: */ - u_int16_t sdtr_speed2; /* 13 SDTR speed TID 4-7 */ - u_int16_t sdtr_speed3; /* 14 SDTR speed TID 8-11 */ - u_int8_t max_host_qng; /* 15 maximum host queueing */ + /* bit 0 BIOS don't act as initiator. */ + /* bit 1 BIOS > 1 GB support */ + /* bit 2 BIOS > 2 Disk Support */ + /* bit 3 BIOS don't support removables */ + /* bit 4 BIOS support bootable CD */ + /* bit 5 BIOS scan enabled */ + /* bit 6 BIOS support multiple LUNs */ + /* bit 7 BIOS display of message */ + /* bit 8 SCAM disabled */ + /* bit 9 Reset SCSI bus during init. */ + /* bit 10 */ + /* bit 11 No verbose initialization. */ + /* bit 12 SCSI parity enabled */ + /* bit 13 */ + /* bit 14 */ + /* bit 15 */ + union { + u_int16_t ultra_able; /* 13 ULTRA speed able */ + u_int16_t sdtr_speed2; /* 13 SDTR speed TID 4-7 */ + } sdtr2; + union { + u_int16_t reserved2; /* 14 reserved */ + u_int16_t sdtr_speed3; /* 14 SDTR speed TID 8-11 */ + } sdtr3; + u_int8_t max_host_qng; /* 15 maximum host queuing */ u_int8_t max_dvc_qng; /* maximum per device queuing */ u_int16_t dvc_cntl; /* 16 control bit for driver */ - u_int16_t sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ - u_int16_t serial_number_word1; /* 18 Board serial number word 1 */ - u_int16_t serial_number_word2; /* 19 Board serial number word 2 */ - u_int16_t serial_number_word3; /* 20 Board serial number word 3 */ + union { + u_int16_t bug_fix; /* 17 control bit for bug fix */ + u_int16_t sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ + } sdtr4; + u_int16_t serial_number[3]; /* 18 - 20 Board serial number */ u_int16_t check_sum; /* 21 EEP check sum */ u_int8_t oem_name[16]; /* 22 OEM name */ u_int16_t dvc_err_code; /* 30 last device driver error code */ u_int16_t adv_err_code; /* 31 last uc and Adv Lib error code */ u_int16_t adv_err_addr; /* 32 last uc error address */ - u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ + u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ u_int16_t saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ - u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ - u_int16_t reserved36; /* 36 reserved */ - u_int16_t reserved37; /* 37 reserved */ - u_int16_t reserved38; /* 38 reserved */ - u_int16_t reserved39; /* 39 reserved */ - u_int16_t reserved40; /* 40 reserved */ - u_int16_t reserved41; /* 41 reserved */ - u_int16_t reserved42; /* 42 reserved */ - u_int16_t reserved43; /* 43 reserved */ - u_int16_t reserved44; /* 44 reserved */ - u_int16_t reserved45; /* 45 reserved */ - u_int16_t reserved46; /* 46 reserved */ - u_int16_t reserved47; /* 47 reserved */ - u_int16_t reserved48; /* 48 reserved */ - u_int16_t reserved49; /* 49 reserved */ - u_int16_t reserved50; /* 50 reserved */ - u_int16_t reserved51; /* 51 reserved */ - u_int16_t reserved52; /* 52 reserved */ - u_int16_t reserved53; /* 53 reserved */ - u_int16_t reserved54; /* 54 reserved */ - u_int16_t reserved55; /* 55 reserved */ - u_int16_t cisptr_lsw; /* 56 CIS PTR LSW */ - u_int16_t cisprt_msw; /* 57 CIS PTR MSW */ + u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ + u_int16_t reserved1[20]; /* 36 - 55 reserved */ + u_int16_t cisptr_lsw; /* 56 CIS PTR LSW */ + u_int16_t cisprt_msw; /* 57 CIS PTR MSW */ u_int16_t subsysvid; /* 58 SubSystem Vendor ID */ u_int16_t subsysid; /* 59 SubSystem ID */ - u_int16_t reserved60; /* 60 reserved */ - u_int16_t reserved61; /* 61 reserved */ - u_int16_t reserved62; /* 62 reserved */ - u_int16_t reserved63; /* 63 reserved */ -} ADW_EEP_38C0800_CONFIG; + u_int16_t reserved2[4]; /* 60 - 63 reserved */ +} ADW_EEPROM; + /* * EEPROM Commands @@ -311,16 +249,17 @@ typedef struct adw_eep_38C0800_config #define BIOS_CTRL_RESET_SCSI_BUS 0x0200 #define BIOS_CTRL_INIT_VERBOSE 0x0800 #define BIOS_CTRL_SCSI_PARITY 0x1000 +#define BIOS_CTRL_AIPP_DIS 0x2000 -#define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ -#define ADV_3550_IOLEN 0x40 /* I/O Port Range in bytes */ +#define ADW_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ +#define ADW_3550_IOLEN 0x40 /* I/O Port Range in bytes */ -#define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ -#define ADV_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */ +#define ADW_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ +#define ADW_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */ -#define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */ -#define ADV_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */ -#define ADV_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */ +#define ADW_38C1600_MEMSIZE 0x8000 /* 32 KB Internal Memory */ +#define ADW_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */ +#define ADW_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */ /* * Byte I/O register address from base of 'iop_base'. @@ -532,6 +471,14 @@ typedef struct adw_eep_38C0800_config /* * Addendum for ASC-38C0800 Chip + * + * The ASC-38C1600 Chip uses the same definitions except that the + * bus mode override bits [12:10] have been moved to byte register + * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in + * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV) + * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only. + * Also each ASC-38C1600 function or channel uses only cable bits [5:4] + * and [1:0]. Bits [14], [7:6], [3:2] are unused. */ #define ADW_DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */ #define ADW_HVD_LVD_SE 0x1C00 /* Device Detect Bits */ @@ -640,6 +587,37 @@ typedef struct adw_eep_38C0800_config #define PRE_TEST_VALUE 0x05 #define NORMAL_VALUE 0x00 +/* + * ASC38C1600 Definitions + * + * IOPB_PCI_INT_CFG Bit Field Definitions + */ + +#define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */ + +/* + * Bit 1 can be set to change the interrupt for the Function to operate in + * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in + * Open Drain mode. Both functions of the ASC38C1600 must be set to the same + * mode, otherwise the operating mode is undefined. + */ +#define TOTEMPOLE 0x02 + +/* + * Bit 0 can be used to change the Int Pin for the Function. The value is + * 0 by default for both Functions with Function 0 using INT A and Function + * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set, + * INT A is used. + * + * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin + * value specified in the PCI Configuration Space. + */ +#define INTAB 0x01 + + +#define ADW_MAX_TID 15 /* max. target identifier */ +#define ADW_MAX_LUN 7 /* max. logical unit number */ + /* * Adv Library Status Definitions @@ -653,76 +631,31 @@ typedef struct adw_eep_38C0800_config /* - * ASC_DVC_VAR 'warn_code' values - */ -#define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ -#define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ -#define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ -#define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */ -#define ASC_WARN_ERROR 0xFFFF /* ADW_ERROR return */ - -#define ADW_MAX_TID 15 /* max. target identifier */ -#define ADW_MAX_LUN 7 /* max. logical unit number */ - - -/* - * AscInitGetConfig() and AscInitAsc1000Driver() Definitions - * - * Error code values are set in ASC_DVC_VAR 'err_code'. + * Warning code values for AdwInitFrom*EEP() functions */ -#define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */ -#define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ -#define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */ -#define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ -#define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */ -#define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ -#define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */ -#define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ -#define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */ -#define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */ -#define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */ -#define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */ -#define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */ -#define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */ +#define ADW_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ +#define ADW_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ +#define ADW_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ +#define ADW_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */ +#define ADW_WARN_ERROR 0xFFFF /* ADW_ERROR return */ /* - * Fixed locations of microcode operating variables. + * Error code values for AdwInitAsc*Driver() functions */ -#define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ -#define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */ -#define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ -#define ASC_MC_VERSION_DATE 0x0038 /* microcode version */ -#define ASC_MC_VERSION_NUM 0x003A /* microcode number */ -#define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ -#define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ -#define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ -#define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */ -#define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ -#define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ -#define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ -#define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ -#define ASC_MC_CHIP_TYPE 0x009A -#define ASC_MC_INTRB_CODE 0x009B -#define ASC_MC_WDTR_ABLE 0x009C -#define ASC_MC_SDTR_ABLE 0x009E -#define ASC_MC_TAGQNG_ABLE 0x00A0 -#define ASC_MC_DISC_ENABLE 0x00A2 -#define ASC_MC_IDLE_CMD_STATUS 0x00A4 -#define ASC_MC_IDLE_CMD 0x00A6 -#define ASC_MC_IDLE_CMD_PARAMETER 0x00A8 -#define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC -#define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE -#define ASC_MC_DEFAULT_MEM_CFG 0x00B0 -#define ASC_MC_DEFAULT_SEL_MASK 0x00B2 -#define ASC_MC_SDTR_DONE 0x00B6 -#define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0 -#define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0 -#define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100 -#define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ -#define ASC_MC_WDTR_DONE 0x0124 -#define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ -#define ASC_MC_ICQ 0x0160 -#define ASC_MC_IRQ 0x0164 +#define ADW_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */ +#define ADW_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ +#define ADW_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */ +#define ADW_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ +#define ADW_IERR_CHIP_VERSION 0x0040 /* wrong chip version */ +#define ADW_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ +#define ADW_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */ +#define ADW_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ +#define ADW_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */ +#define ADW_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */ +#define ADW_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */ +#define ADW_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */ +#define ADW_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */ +#define ADW_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */ /* * BIOS LRAM variable absolute offsets. @@ -733,46 +666,11 @@ typedef struct adw_eep_38C0800_config #define BIOS_VERSION 0x5A /* - * Microcode Control Flags - * - * Flags set by the Adv Library in RISC variable 'control_flag' (0x122) - * and handled by the microcode. - */ -#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */ - -/* - * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format - */ -#define HSHK_CFG_WIDE_XFR 0x8000 -#define HSHK_CFG_RATE 0x0F00 -#define HSHK_CFG_OFFSET 0x001F - -#define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */ -#define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */ -#define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */ -#define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */ - -#define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */ -#define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ -#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ -#define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ -#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */ - -#define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ -#define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ -#define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */ -#define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ -#define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */ -/* - * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or - * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. + * Chip Type flag values */ -#define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ -#define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ - -#define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ -#define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ -#define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ +#define ADW_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ +#define ADW_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ +#define ADW_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ /* * Adapter temporary configuration structure @@ -788,15 +686,16 @@ typedef struct adw_eep_38C0800_config typedef struct adw_dvc_cfg { u_int16_t disc_enable; /* enable disconnection */ u_int8_t chip_version; /* chip version */ - u_int8_t termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */ + u_int8_t termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 */ u_int16_t pci_device_id; /* PCI device code number */ u_int16_t lib_version; /* Adv Library version number */ u_int16_t control_flag; /* Microcode Control Flag */ u_int16_t mcode_date; /* Microcode date */ u_int16_t mcode_version; /* Microcode version */ - u_int16_t pci_slot_info; /* high byte device/function number */ - /* bits 7-3 device num., bits 2-0 function num. */ - /* low byte bus num. */ + u_int16_t pci_slot_info; /* high byte device/function number + bits 7-3 device num., + bits 2-0 function num. + low byte bus num. */ u_int16_t serial1; /* EEPROM serial number word 1 */ u_int16_t serial2; /* EEPROM serial number word 2 */ u_int16_t serial3; /* EEPROM serial number word 3 */ @@ -834,10 +733,6 @@ typedef struct adw_sg_block { #define CCB_HASH_SHIFT 9 #define CCB_HASH(x) ((((x)) >> CCB_HASH_SHIFT) & (CCB_HASH_SIZE - 1)) -#define CARRIER_HASH_SIZE 32 /* hash table size for phystokv */ -#define CARRIER_HASH_SHIFT 9 -#define CARRIER_HASH(x) ((((x)) >> CARRIER_HASH_SHIFT) & (CARRIER_HASH_SIZE - 1)) - typedef int (* ADW_CALLBACK) (int); typedef struct adw_softc { @@ -853,17 +748,19 @@ typedef struct adw_softc { struct adw_control *sc_control; /* control structures */ - struct adw_carrier *sc_carrhash[CARRIER_HASH_SIZE]; struct adw_ccb *sc_ccbhash[CCB_HASH_SIZE]; TAILQ_HEAD(, adw_ccb) sc_free_ccb, sc_waiting_ccb; + TAILQ_HEAD(adw_pending_ccb, adw_ccb) sc_pending_ccb; struct scsi_link sc_link; /* prototype for devs */ struct scsi_adapter sc_adapter; LIST_HEAD(, scsi_xfer) sc_queue; struct scsi_xfer *sc_queuelast; - ADW_CALLBACK isr_callback; /* pointer to function, called in AdvISR() */ - ADW_CALLBACK async_callback; /* pointer to function, called in AdvISR() */ + int sc_freeze_dev[ADW_MAX_TID + 1]; + + ADW_CALLBACK isr_callback; /* pointer to function, called in AdwISR() */ + ADW_CALLBACK async_callback; /* pointer to function, called in AdwISR() */ u_int16_t bios_ctrl; /* BIOS control word, EEPROM word 12 */ u_int16_t wdtr_able; /* try WDTR for a device */ u_int16_t sdtr_able; /* try SDTR for a device */ @@ -873,6 +770,7 @@ typedef struct adw_softc { u_int16_t sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */ u_int16_t sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */ u_int16_t tagqng_able; /* try tagged queuing with a device */ + u_int16_t ppr_able; /* PPR message capable per TID bitmask. */ u_int16_t start_motor; /* start motor command allowed */ u_int8_t max_dvc_qng; /* maximum number of tagged commands per device */ u_int8_t scsi_reset_wait; /* delay in seconds after scsi bus reset */ @@ -905,26 +803,26 @@ typedef struct adw_softc { * coordinating the change with the microcode. */ typedef struct adw_scsi_req_q { - u_int8_t cntl; /* Ucode flags and state (ASC_MC_QC_*). */ + u_int8_t cntl; /* Ucode flags and state (ADW_MC_QC_*). */ u_int8_t target_cmd; u_int8_t target_id; /* Device target identifier. */ u_int8_t target_lun; /* Device target logical unit number. */ u_int32_t data_addr; /* Data buffer physical address. */ u_int32_t data_cnt; /* Data count. Ucode sets to residual. */ u_int32_t sense_addr; /* Sense buffer physical address. */ - u_int32_t carr_pa; /* Carrier p-address */ + u_int32_t carr_ba; /* Carrier p-address */ u_int8_t mflag; /* Adv Library flag field. */ u_int8_t sense_len; /* Auto-sense length. uCode sets to residual. */ - u_int8_t cdb_len; /* SCSI CDB length. */ + u_int8_t cdb_len; /* SCSI CDB length. Must <= 16 bytes. */ u_int8_t scsi_cntl; - u_int8_t done_status; /* Completion status. */ + u_int8_t done_status; /* Completion status. (see below) */ u_int8_t scsi_status; /* SCSI status byte. (see below) */ - u_int8_t host_status; /* Ucode host status. */ - u_int8_t sg_working_ix; /* Ucode working SG variable. */ - u_int8_t cdb[12]; /* SCSI command block. */ + u_int8_t host_status; /* ,uCode host status. (see below) */ + u_int8_t sg_working_ix; /* ,uCode working SG variable. */ + u_int8_t cdb[12]; /* SCSI CDB bytes 0-11. */ u_int32_t sg_real_addr; /* SG list physical address. */ u_int32_t scsiq_rptr; /* Iternal pointer to ADW_SCSI_REQ_Q */ - u_int32_t sg_working_data_cnt; + u_int8_t cdb16[4]; /* SCSI CDB bytes 12-15. */ u_int32_t ccb_ptr; /* CCB Physical Address */ u_int32_t carr_va; /* Carrier v-address (unused) */ /* @@ -933,10 +831,62 @@ typedef struct adw_scsi_req_q { */ struct scsi_sense_data *vsense_addr; /* Sense buffer virtual address. */ u_char *vdata_addr; /* Data buffer virtual address. */ - u_int8_t orig_sense_len; /* Original length of sense buffer. */ - u_int8_t pads[3]; /* padding bytes (align to long) */ } ADW_SCSI_REQ_Q; +/* + * ASC_SCSI_REQ_Q 'done_status' return values. + */ +#define QD_NO_STATUS 0x00 /* Request not completed yet. */ +#define QD_NO_ERROR 0x01 +#define QD_ABORTED_BY_HOST 0x02 +#define QD_WITH_ERROR 0x04 + +/* + * ASC_SCSI_REQ_Q 'host_status' return values. + */ +#define QHSTA_NO_ERROR 0x00 +#define QHSTA_M_SEL_TIMEOUT 0x11 +#define QHSTA_M_DATA_OVER_RUN 0x12 +#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 +#define QHSTA_M_QUEUE_ABORTED 0x15 +#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ +#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ +#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ +#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ +#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ +#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ +#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ +/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ +#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ +#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ +#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ +#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ +#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ +#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ +#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ +#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ +#define QHSTA_M_WTM_TIMEOUT 0x41 +#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 +#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 +#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 +#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ +#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ +#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ + +/* + * ASC_SCSI_REQ_Q 'scsi_status' return values. + */ +#define SCSI_STATUS_GOOD 0x00 +#define SCSI_STATUS_CHECK_CONDITION 0x02 +#define SCSI_STATUS_CONDITION_MET 0x04 +#define SCSI_STATUS_TARGET_BUSY 0x08 +#define SCSI_STATUS_INTERMID 0x10 +#define SCSI_STATUS_INTERMID_COND_MET 0x14 +#define SCSI_STATUS_RSERV_CONFLICT 0x18 +#define SCSI_STATUS_CMD_TERMINATED 0x22 +#define SCSI_STATUS_QUEUE_FULL 0x28 + + /* * Microcode idle loop commands */ @@ -954,7 +904,7 @@ typedef struct adw_scsi_req_q { #define IDLE_CMD_STATUS_FAILURE 0x0002 /* - * AdvSendIdleCmd() flag definitions. + * AdwSendIdleCmd() flag definitions. */ #define ADW_NOWAIT 0x01 @@ -990,6 +940,10 @@ typedef struct adw_scsi_req_q { #define ADW_WRITE_WORD_REGISTER(iot, ioh, reg_off, word) \ bus_space_write_2((iot), (ioh), (reg_off), (word)) +/* Write double word (4 bytes) to a register. */ +#define ADW_WRITE_DWORD_REGISTER(iot, ioh, reg_off, dword) \ + bus_space_write_4((iot), (ioh), (reg_off), (dword)) + /* Read byte from LRAM. */ #define ADW_READ_BYTE_LRAM(iot, ioh, addr, byte) \ do { \ @@ -1071,7 +1025,7 @@ do { \ * ADW_FALSE(0) - Queue was not found on the active queue list. */ #define ADW_ABORT_CCB(sc, ccb_ptr) \ - AdvSendIdleCmd((sc), (u_int16_t) IDLE_CMD_ABORT, (ccb_ptr)->hashkey) + AdwSendIdleCmd((sc), (u_int16_t) IDLE_CMD_ABORT, (ccb_ptr)->hashkey) /* * Send a Bus Device Reset Message to the specified target ID. @@ -1085,7 +1039,7 @@ do { \ * are not purged. */ #define ADW_RESET_DEVICE(sc, target_id) \ - AdvSendIdleCmd((sc), (u_int16_t) IDLE_CMD_DEVICE_RESET, (target_id), 0) + AdwSendIdleCmd((sc), (u_int16_t) IDLE_CMD_DEVICE_RESET, (target_id), 0) /* * SCSI Wide Type definition. @@ -1104,46 +1058,12 @@ do { \ #define ADW_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADW_MAX_TID)) /* - * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values. + * SCSI Inquiry structure */ -#define QD_NO_STATUS 0x00 /* Request not completed yet. */ -#define QD_NO_ERROR 0x01 -#define QD_ABORTED_BY_HOST 0x02 -#define QD_WITH_ERROR 0x04 - -#define QHSTA_NO_ERROR 0x00 -#define QHSTA_M_SEL_TIMEOUT 0x11 -#define QHSTA_M_DATA_OVER_RUN 0x12 -#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 -#define QHSTA_M_QUEUE_ABORTED 0x15 -#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ -#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ -#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ -#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ -#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ -#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ -#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ -/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ -#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ -#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ -#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ -#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ -#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ -#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ -#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ -#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ -#define QHSTA_M_WTM_TIMEOUT 0x41 -#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 -#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 -#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 -#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ -#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ -#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ - -/* - * SCSI Iquiry structure - */ +#define INQ_CLOCKING_ST_ONLY 0x0 +#define INQ_CLOCKING_DT_ONLY 0x1 +#define INQ_CLOCKING_ST_AND_DT 0x3 typedef struct { u_int8_t peri_dvc_type : 5; /* peripheral device type */ @@ -1162,16 +1082,23 @@ typedef struct { u_int8_t TemIOP : 1; /* terminate I/O process bit (see 5.6.22) */ u_int8_t aenc : 1; /* asynch. event notification (processor) */ u_int8_t add_len; /* additional length */ - u_int8_t res2; /* reserved */ - u_int8_t res3; /* reserved */ - u_int8_t StfRe : 1; /* soft reset implemented */ - u_int8_t CmdQue : 1; /* command queuing */ - u_int8_t res4 : 1; /* reserved */ - u_int8_t Linked : 1; /* linked command for this logical unit */ - u_int8_t Sync : 1; /* synchronous data transfer */ - u_int8_t WBus16 : 1; /* wide bus 16 bit data transfer */ - u_int8_t WBus32 : 1; /* wide bus 32 bit data transfer */ - u_int8_t RelAdr : 1; /* relative addressing mode */ + u_int8_t res2 : 7; /* reserved */ + u_int8_t SCC : 1; + u_int8_t Addr16 : 1; + u_int8_t res3 : 2; /* reserved */ + u_int8_t MChngr : 1; + u_int8_t MultiPort: 1; + u_int8_t res4 : 1; + u_int8_t EncServ : 1; + u_int8_t BaseQue : 1; + u_int8_t StfRe : 1; /* soft reset implemented */ + u_int8_t CmdQue : 1; /* command queuing */ + u_int8_t res5 : 1; /* reserved */ + u_int8_t Linked : 1; /* linked command for this logical unit */ + u_int8_t Sync : 1; /* synchronous data transfer */ + u_int8_t WBus16 : 1; /* wide bus 16 bit data transfer */ + u_int8_t WBus32 : 1; /* wide bus 32 bit data transfer */ + u_int8_t RelAdr : 1; /* relative addressing mode */ u_int8_t vendor_id[8]; /* vendor identification */ u_int8_t product_id[16]; /* product identification */ u_int8_t product_rev_level[4]; /* product revision level */ @@ -1179,90 +1106,23 @@ typedef struct { u_int8_t IUS : 1; /* information unit supported */ u_int8_t QAS : 1; /* quick arbitrate supported */ u_int8_t Clocking : 2; /* clocking field */ - u_int8_t res5 : 4; /* reserved */ - u_int8_t res6; /* reserved */ -} ADW_SCSI_INQUIRY; /* 58 bytes */ - -#define SS_GOOD 0x00 -#define SS_CHK_CONDITION 0x02 -#define SS_CONDITION_MET 0x04 -#define SS_TARGET_BUSY 0x08 -#define SS_INTERMID 0x10 -#define SS_INTERMID_COND_MET 0x14 -#define SS_RSERV_CONFLICT 0x18 -#define SS_CMD_TERMINATED 0x22 -#define SS_QUEUE_FULL 0x28 -#define MS_CMD_DONE 0x00 -#define MS_EXTEND 0x01 -#define MS_SDTR_LEN 0x03 -#define MS_SDTR_CODE 0x01 -#define MS_WDTR_LEN 0x02 -#define MS_WDTR_CODE 0x03 -#define MS_MDP_LEN 0x05 -#define MS_MDP_CODE 0x00 -#define M1_SAVE_DATA_PTR 0x02 -#define M1_RESTORE_PTRS 0x03 -#define M1_DISCONNECT 0x04 -#define M1_INIT_DETECTED_ERR 0x05 -#define M1_ABORT 0x06 -#define M1_MSG_REJECT 0x07 -#define M1_NO_OP 0x08 -#define M1_MSG_PARITY_ERR 0x09 -#define M1_LINK_CMD_DONE 0x0A -#define M1_LINK_CMD_DONE_WFLAG 0x0B -#define M1_BUS_DVC_RESET 0x0C -#define M1_ABORT_TAG 0x0D -#define M1_CLR_QUEUE 0x0E -#define M1_INIT_RECOVERY 0x0F -#define M1_RELEASE_RECOVERY 0x10 -#define M1_KILL_IO_PROC 0x11 -#define M2_QTAG_MSG_SIMPLE 0x20 -#define M2_QTAG_MSG_HEAD 0x21 -#define M2_QTAG_MSG_ORDERED 0x22 -#define M2_IGNORE_WIDE_RESIDUE 0x23 - - -#define ASC_MAX_SENSE_LEN 32 -#define ASC_MIN_SENSE_LEN 14 - -typedef struct asc_req_sense { - u_int8_t err_code:7; - u_int8_t info_valid:1; - u_int8_t segment_no; - u_int8_t sense_key:4; - u_int8_t reserved_bit:1; - u_int8_t sense_ILI:1; - u_int8_t sense_EOM:1; - u_int8_t file_mark:1; - u_int8_t info1[4]; - u_int8_t add_sense_len; - u_int8_t cmd_sp_info[4]; - u_int8_t asc; - u_int8_t ascq; - u_int8_t fruc; - u_int8_t sks_byte0:7; - u_int8_t sks_valid:1; - u_int8_t sks_bytes[2]; - u_int8_t notused[2]; - u_int8_t ex_sense_code; - u_int8_t info2[4]; -} ASC_REQ_SENSE; - + u_int8_t res6 : 4; /* reserved */ + u_int8_t res7; /* reserved */ + u_int8_t version_descriptor[8][2]; +} ADW_SCSI_INQUIRY; /* 74 bytes */ /* * Adv Library functions available to drivers. */ -int AdvInitAsc3550Driver __P((ADW_SOFTC *)); -int AdvInitAsc38C0800Driver __P((ADW_SOFTC *)); -int AdvInitFrom3550EEP __P((ADW_SOFTC *)); -int AdvInitFrom38C0800EEP __P((ADW_SOFTC *)); -int AdvExeScsiQueue __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); -int AdvISR __P((ADW_SOFTC *)); -void AdvResetChip __P((bus_space_tag_t, bus_space_handle_t)); -int AdvSendIdleCmd __P((ADW_SOFTC *, u_int16_t, u_int32_t)); -int AdvResetSCSIBus __P((ADW_SOFTC *)); -int AdvResetCCB __P((ADW_SOFTC *)); +int AdwInitFromEEPROM __P((ADW_SOFTC *)); +int AdwInitDriver __P((ADW_SOFTC *)); +int AdwExeScsiQueue __P((ADW_SOFTC *, ADW_SCSI_REQ_Q *)); +int AdwISR __P((ADW_SOFTC *)); +void AdwResetChip __P((bus_space_tag_t, bus_space_handle_t)); +int AdwSendIdleCmd __P((ADW_SOFTC *, u_int16_t, u_int32_t)); +int AdwResetSCSIBus __P((ADW_SOFTC *)); +int AdwResetCCB __P((ADW_SOFTC *)); #define offsetof(type, member) ((size_t)(&((type *)0)->member)) diff --git a/sys/dev/ic/adwmcode.c b/sys/dev/ic/adwmcode.c index 4c4f055a211..25e5f580fb3 100644 --- a/sys/dev/ic/adwmcode.c +++ b/sys/dev/ic/adwmcode.c @@ -1,5 +1,5 @@ -/* $OpenBSD: adwmcode.c,v 1.3 2000/04/29 21:12:31 krw Exp $ */ -/* $NetBSD: adwmcode.c,v 1.2 2000/02/03 20:29:16 dante Exp $ */ +/* $OpenBSD: adwmcode.c,v 1.4 2000/06/29 00:04:32 krw Exp $ */ +/* $NetBSD: adwmcode.c,v 1.5 2000/05/27 18:24:50 dante Exp $ */ /* * Generic driver definitions and exported functions for the Advanced @@ -44,7 +44,7 @@ /* * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters * - * Copyright (c) 1995-1998 Advanced System Products, Inc. + * Copyright (c) 1995-2000 Advanced System Products, Inc. * All Rights Reserved. * * Redistribution and use in source and binary forms, with or without @@ -55,691 +55,1416 @@ */ +#include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include -/* - * This is the uCode for the Wide board RISC cpu. - * This code is loaded into Lram during initializzation procedure. - */ -u_int8_t adv_asc3550_mcode[] = { - 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x00, 0xfc, 0x48, 0xe4, 0x01, 0x00, 0x18, 0xe4, - 0x00, 0xf6, 0x01, 0xf6, 0x18, 0x80, 0x48, 0x19, 0x02, 0x00, 0xff, 0xff, 0x03, 0xf6, 0x00, 0xfa, - 0xff, 0x00, 0x82, 0xe7, 0x01, 0xfa, 0x9e, 0xe7, 0x09, 0xe7, 0x3a, 0x0e, 0x00, 0xea, 0x01, 0xe6, - 0x55, 0xf0, 0x03, 0x00, 0x08, 0x00, 0x18, 0xf4, 0x3e, 0x01, 0x3e, 0x57, 0x04, 0x00, 0x85, 0xf0, - 0x00, 0xe6, 0x00, 0xec, 0x1e, 0xf0, 0x32, 0xf0, 0x34, 0x19, 0x86, 0xf0, 0xd0, 0x01, 0xd5, 0xf0, - 0xde, 0x0c, 0x98, 0x57, 0xbc, 0x00, 0x0c, 0x1c, 0x0e, 0x13, 0x38, 0x54, 0xb1, 0xf0, 0xb4, 0x00, - 0x01, 0xfc, 0x03, 0xfc, 0xd8, 0x0c, 0x00, 0x57, 0x01, 0xf0, 0x02, 0x13, 0x03, 0xe6, 0x10, 0x00, - 0x18, 0x40, 0x3e, 0x1c, 0x6c, 0x01, 0x6e, 0x01, 0xbd, 0x00, 0xe0, 0x00, 0x02, 0x48, 0x02, 0x80, - 0x08, 0x12, 0x30, 0xe4, 0x3c, 0x00, 0x4e, 0x01, 0x64, 0x12, 0x80, 0x00, 0x9c, 0x15, 0xbb, 0x00, - 0x00, 0x4e, 0x01, 0x01, 0x01, 0xea, 0x04, 0x12, 0x9e, 0x0f, 0xb6, 0x00, 0xb9, 0x54, 0xe2, 0x0f, - 0x00, 0x80, 0x06, 0xf7, 0x10, 0x44, 0x24, 0x01, 0x28, 0x01, 0x32, 0x00, 0x3c, 0x01, 0x3c, 0x56, - 0x3e, 0x00, 0x4b, 0xe4, 0x4c, 0x1c, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, - 0x76, 0x01, 0x78, 0x01, 0xe2, 0x0c, 0x00, 0x01, 0x02, 0xee, 0x02, 0xfc, 0x03, 0x58, 0x03, 0xf7, - 0x04, 0x80, 0x05, 0xfc, 0x08, 0x44, 0x09, 0xf0, 0x0f, 0x00, 0x1b, 0x80, 0x20, 0x01, 0x38, 0x1c, - 0x40, 0x00, 0x40, 0x15, 0x4b, 0xf4, 0x4e, 0x1c, 0x5b, 0xf0, 0x5d, 0xf0, 0xaa, 0x00, 0xbb, 0x55, - 0xbe, 0x00, 0xc0, 0x00, 0xe0, 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0xeb, 0xfe, 0x0b, 0x00, - 0x74, 0xfe, 0xd2, 0x18, 0x04, 0xfe, 0x94, 0x00, 0xc7, 0x1a, 0xfe, 0x08, 0x10, 0x04, 0xfe, 0x96, - 0x00, 0xc7, 0x85, 0xfe, 0x4e, 0x45, 0xd1, 0xfe, 0x0a, 0x45, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1, - 0x10, 0x1b, 0x6c, 0x03, 0x05, 0x80, 0xfe, 0x5a, 0xf0, 0xfe, 0xfe, 0x18, 0x20, 0xfe, 0x09, 0x00, - 0xfe, 0x34, 0x10, 0x05, 0x1e, 0xfe, 0x5a, 0xf0, 0xfe, 0x0c, 0x19, 0x20, 0xcd, 0xfe, 0x26, 0x10, - 0x05, 0x19, 0x83, 0x20, 0x85, 0xd8, 0x05, 0x0c, 0x83, 0x20, 0x88, 0xfe, 0x0e, 0x10, 0x05, 0x06, - 0x83, 0x20, 0x55, 0xc6, 0xaf, 0x03, 0x17, 0xfe, 0x09, 0x00, 0x01, 0x44, 0x2e, 0xfe, 0x3c, 0x19, - 0x04, 0x6e, 0xb0, 0x03, 0x22, 0xfe, 0x54, 0x19, 0xfe, 0x14, 0xf0, 0x0b, 0x2e, 0xfe, 0x50, 0x19, - 0x03, 0xff, 0x15, 0x00, 0x00, -}; +#include +#include +#include + +#include "adwmcode.h" -u_int16_t adv_asc3550_mcode_size = sizeof(adv_asc3550_mcode); /* 0x13E5 */ +/******************************************************************************/ /* - * This checksum is used to compare with that one that will be calculated - * at run time. - * This is performed to ensure the uCode is correctly loaded into the Lram. + * Initialize a set of Carriers and add them to the free list. */ -u_int32_t adv_asc3550_mcode_chksum = 0x04FFFF0E; +ADW_CARRIER * +AdwInitCarriers(carr_dmap, carriers) + bus_dmamap_t carr_dmap; + ADW_CARRIER *carriers; +{ + ADW_CARRIER *carr; + u_int32_t carr_next = NULL; + int i; + bzero(carriers, sizeof(ADW_CARRIER) * ADW_MAX_CARRIER); + for(i=0; i < ADW_MAX_CARRIER; i++) { + carr = (ADW_CARRIER *)(((u_int8_t *)carriers) + + (sizeof(ADW_CARRIER) * i)); + carr->carr_ba = ADW_CARRIER_BADDR(carr_dmap, carriers, carr); + carr->carr_id = i; + carr->next_ba = carr_next; + carr_next = carr->carr_ba; + } + return (carr); +} -u_int8_t adv_asc38C0800_mcode[] = { - 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x00, 0xfc, 0x48, 0xe4, 0x01, 0x00, 0x18, 0xe4, - 0x00, 0xf6, 0x01, 0xf6, 0x18, 0x80, 0x02, 0x00, 0x40, 0x1a, 0x00, 0xfa, 0xff, 0xff, 0x03, 0xf6, - 0xff, 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correctly loaded into the Lram. + * This is the uCode for the Wide board RISC cpu. + * This code is loaded into Lram during initialization procedure. */ -u_int32_t adv_asc38C0800_mcode_chksum = 0x053503A5; +const u_int8_t adw_asc3550_mcode[] = { + 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xf0, 0x00, 0xfc, 0x01, 0x00, + 0x48, 0xe4, 0x58, 0x18, 0x03, 0xf6, 0x18, 0xe4, 0x02, 0x00, 0x18, 0x80, + 0x00, 0xfa, 0xff, 0xff, 0x9e, 0xe7, 0xff, 0x00, 0xcc, 0x0d, 0x82, 0xe7, + 0x00, 0xf6, 0x00, 0xea, 0x09, 0xe7, 0x01, 0xf6, 0x08, 0x00, 0x01, 0xe6, + 0x55, 0xf0, 0x01, 0xfa, 0x03, 0x00, 0x18, 0xf4, 0x04, 0x00, 0x00, 0xec, + 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x70, 0x0c, 0x38, 0x54, 0x00, 0xe6, + 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01, 0x0c, 0x1c, + 0x3e, 0x1c, 0x10, 0x00, 0xbb, 0x00, 0x44, 0x18, 0x02, 0x80, 0x32, 0xf0, + 0x01, 0xfc, 0x6a, 0x0c, 0x64, 0x12, 0x02, 0x13, 0x18, 0x40, 0x00, 0x57, + 0x3c, 0x00, 0xc0, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, 0x00, 0x80, + 0x03, 0xe6, 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0x10, 0xfe, 0x4e, 0xe4, + 0xbe, 0x60, 0xfe, 0xd0, 0x17, 0x04, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, + 0x1c, 0xda, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x60, 0xfe, 0xe2, 0x17, + 0x04, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x16, 0xfe, 0x08, 0x10, 0x04, + 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x66, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, + 0x12, 0xed, 0xff, 0x04, 0x68, 0x54, 0xdc, 0x1b, 0x67, 0x02, 0x06, 0x65, + 0xfe, 0x5a, 0xf0, 0xfe, 0x0e, 0x18, 0x23, 0xfe, 0x09, 0x00, 0xfe, 0x34, + 0x10, 0x06, 0x1c, 0xfe, 0x5a, 0xf0, 0xfe, 0x1c, 0x18, 0x23, 0xbf, 0xfe, + 0x26, 0x10, 0x06, 0x1a, 0x5a, 0x23, 0x66, 0xda, 0x06, 0x0a, 0x5a, 0x23, + 0x91, 0xd9, 0x06, 0x05, 0x5a, 0x23, 0x4b, 0x9b, 0xa9, 0x02, 0x17, 0xfe, + 0x09, 0x00, 0x01, 0x32, 0xfe, 0x04, 0xfe, 0x7b, 0x04, 0x7d, 0xf9, 0x02, + 0x24, 0xfe, 0x64, 0x18, 0xfe, 0x14, 0xf0, 0x07, 0x61, 0xfe, 0x60, 0x18, + 0x02, 0xff, 0x0d, 0x00, 0x00, +}; +const struct adw_mcode adw_asc3550_mcode_data = +{ + adw_asc3550_mcode, + 0x04BE1ABDUL, /* Expanded checksum. */ + sizeof(adw_asc3550_mcode) /* 0x1361 */ +}; + +const u_int8_t adw_asc38C0800_mcode[] = { + 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x01, 0x00, + 0x48, 0xe4, 0x03, 0xf6, 0x18, 0xe4, 0x02, 0x00, 0x18, 0x80, 0x68, 0x19, + 0x00, 0xfa, 0xff, 0xff, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00, 0xc0, 0x0e, + 0x82, 0xe7, 0x00, 0xea, 0x09, 0xe7, 0x01, 0xf6, 0x01, 0xfa, 0x03, 0x00, + 0x01, 0xe6, 0x55, 0xf0, 0x04, 0x00, 0x1e, 0xf0, 0x85, 0xf0, 0x18, 0xf4, + 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0, 0x64, 0x0d, + 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc, 0xb4, 0x00, + 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x10, 0x00, 0x3c, 0x00, 0xbb, 0x00, + 0x00, 0x10, 0x54, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x5e, 0x0d, 0x02, 0x13, + 0x58, 0x13, 0x18, 0x40, 0x00, 0x57, 0x02, 0xfc, 0x03, 0xfc, 0x3e, 0x00, + 0xc0, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0x6c, 0x10, + 0xb4, 0x10, 0xb9, 0x54, 0x00, 0x80, 0x03, 0xe6, 0x01, 0xea, 0xb6, 0x00, + 0x01, 0x01, 0x3e, 0x01, 0x7a, 0x01, 0xae, 0x08, 0x04, 0x12, 0xbb, 0x55, + 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, + 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00, 0x40, 0x00, 0x80, 0x00, + 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, + 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x68, 0x0d, 0x08, 0x12, 0x06, 0x13, + 0x4c, 0x1c, 0x02, 0x4a, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x05, 0x00, + 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01, 0xbe, 0x10, + 0xfa, 0x15, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44, 0x00, 0x4c, + 0x04, 0x80, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa, + 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, + 0x2e, 0x0b, 0x26, 0x0c, 0xb6, 0x0e, 0x0c, 0x10, 0xc0, 0x10, 0x0a, 0x12, + 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54, 0x44, 0x55, + 0xbd, 0x56, 0x00, 0xdc, 0x4a, 0xe4, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, + 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc, 0x05, 0xfc, + 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, + 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xac, 0x0e, 0x02, 0x10, 0x04, 0x10, + 0x0a, 0x10, 0x0a, 0x13, 0x12, 0x13, 0xc2, 0x13, 0xd2, 0x13, 0xa2, 0x15, + 0xa6, 0x15, 0x42, 0x17, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, + 0x91, 0x44, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55, + 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x06, 0x83, 0x19, 0xe4, + 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, + 0x0a, 0x00, 0x1c, 0x00, 0x3f, 0x00, 0x9b, 0x00, 0x9e, 0x00, 0xa8, 0x00, + 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, + 0xc4, 0x01, 0xc6, 0x01, 0x74, 0x02, 0x5a, 0x03, 0xd6, 0x03, 0xd2, 0x04, + 0x7e, 0x06, 0xdc, 0x07, 0x68, 0x08, 0x69, 0x08, 0xba, 0x08, 0xe9, 0x09, + 0xde, 0x0b, 0xd2, 0x0e, 0x0e, 0x10, 0x1a, 0x10, 0xc8, 0x10, 0xed, 0x10, + 0xf1, 0x10, 0x06, 0x12, 0x0c, 0x12, 0x0c, 0x13, 0x10, 0x13, 0x16, 0x13, + 0x1e, 0x13, 0xe4, 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0x6b, 0xfe, 0x5a, + 0xf0, 0xfe, 0x1e, 0x19, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, 0x06, + 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x2c, 0x19, 0x24, 0xc6, 0xfe, 0x26, 0x10, + 0x06, 0x17, 0x65, 0x24, 0x6c, 0xe1, 0x06, 0x09, 0x65, 0x24, 0x9d, 0xe0, + 0x06, 0x05, 0x65, 0x24, 0x57, 0xa6, 0xb3, 0x04, 0x18, 0xfe, 0x09, 0x00, + 0x01, 0x36, 0xfe, 0x04, 0xfe, 0x80, 0x03, 0x82, 0xfe, 0x40, 0x5c, 0x04, + 0x1b, 0xf2, 0xfe, 0x14, 0xf0, 0x0b, 0x26, 0xfe, 0x70, 0x19, 0x1b, 0xf2, + 0x7b, 0xf2, 0xfe, 0x82, 0xf0, 0xfe, 0x74, 0x19, 0x04, 0xff, 0xff, 0x00, + 0x00, +}; + +const struct adw_mcode adw_asc38C0800_mcode_data = +{ + adw_asc38C0800_mcode, + 0x04F62935UL, /* Expanded checksum. */ + sizeof(adw_asc38C0800_mcode) /* 0x1489 */ +}; + +const u_int8_t adw_asc38C1600_mcode[] = { + 0x00, 0x00, 0x00, 0xf2, 0x00, 0xfc, 0x00, 0x16, 0x00, 0xf0, 0x01, 0x00, + 0xc6, 0x1b, 0x48, 0xe4, 0x18, 0xe4, 0x03, 0xf6, 0x02, 0x00, 0x18, 0x80, + 0x00, 0xfa, 0xff, 0xff, 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, + 0x85, 0xf0, 0x86, 0xf0, 0x9e, 0xe7, 0xff, 0x00, 0xac, 0x0e, 0x55, 0xf0, + 0x01, 0xf6, 0x03, 0x00, 0x98, 0x57, 0x00, 0xec, 0x18, 0xf4, 0x01, 0xe6, + 0x00, 0xea, 0x01, 0xfa, 0x08, 0x00, 0xb2, 0x1b, 0x38, 0x54, 0x32, 0xf0, + 0x64, 0x0d, 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, + 0xb1, 0xf0, 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xd8, 0x01, 0x00, 0x10, + 0x06, 0x13, 0x0c, 0x1c, 0xb9, 0x54, 0x00, 0x57, 0x00, 0x80, 0x02, 0x80, + 0x1b, 0x80, 0x01, 0xfc, 0x10, 0x00, 0xbe, 0x00, 0x5e, 0x0d, 0xa4, 0x10, + 0x5c, 0x10, 0xb6, 0x13, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x5c, 0xf0, + 0x0f, 0x00, 0x20, 0x00, 0xc0, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, + 0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x01, 0xea, 0x40, 0x00, + 0xb6, 0x00, 0xbb, 0x00, 0x00, 0x01, 0x01, 0x01, 0x3e, 0x01, 0x70, 0x09, + 0x0a, 0x12, 0x4c, 0x1c, 0x3e, 0x57, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, + 0x3c, 0x00, 0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, + 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, + 0x7c, 0x01, 0x62, 0x0a, 0x68, 0x0d, 0x0c, 0x10, 0xae, 0x10, 0xb0, 0x10, + 0x08, 0x12, 0x02, 0x18, 0x4e, 0x1c, 0x02, 0x4a, 0x3a, 0x55, 0x4a, 0xe4, + 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x05, 0x00, + 0x06, 0x00, 0x3f, 0x00, 0xe1, 0x00, 0xa2, 0x0e, 0x2e, 0x14, 0x04, 0x18, + 0x58, 0x18, 0x30, 0x1c, 0x32, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x02, 0x48, + 0x00, 0x4c, 0xb0, 0x57, 0x04, 0x80, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, + 0xa7, 0xf0, 0x04, 0xf6, 0x02, 0xfc, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00, + 0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00, + 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0xa0, 0x08, 0x26, 0x0c, 0x02, 0x10, + 0x04, 0x10, 0x0c, 0x12, 0x0a, 0x13, 0x5a, 0x14, 0x36, 0x17, 0x00, 0x4e, + 0x00, 0x54, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, + 0x0e, 0xf7, 0x0a, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, + 0xd0, 0x00, 0xe7, 0x00, 0x69, 0x08, 0xe9, 0x09, 0x1e, 0x0b, 0x98, 0x0e, + 0x0a, 0x10, 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+}; + +const struct adw_mcode adw_asc38C1600_mcode_data = +{ + adw_asc38C1600_mcode, + 0x0572AE4FUL, /* Expanded checksum. */ + sizeof(adw_asc38C1600_mcode) /* 0x164C */ +}; diff --git a/sys/dev/ic/adwmcode.h b/sys/dev/ic/adwmcode.h index 70c11bfadfd..7043b85da0a 100644 --- a/sys/dev/ic/adwmcode.h +++ b/sys/dev/ic/adwmcode.h @@ -1,5 +1,5 @@ -/* $OpenBSD: adwmcode.h,v 1.3 2000/04/29 21:12:32 krw Exp $ */ -/* $NetBSD: adwmcode.h,v 1.2 2000/02/03 20:29:17 dante Exp $ */ +/* $OpenBSD: adwmcode.h,v 1.4 2000/06/29 00:04:32 krw Exp $ */ +/* $NetBSD: adwmcode.h,v 1.5 2000/05/27 18:24:51 dante Exp $ */ /* * Generic driver definitions and exported functions for the Advanced @@ -39,15 +39,176 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef ADV_MCODE_H -#define ADV_MCODE_H +#ifndef ADW_MCODE_H +#define ADW_MCODE_H -extern u_int8_t adv_asc3550_mcode[]; -extern u_int16_t adv_asc3550_mcode_size; -extern u_int32_t adv_asc3550_mcode_chksum; +/******************************************************************************/ -extern u_int8_t adv_asc38C0800_mcode[]; -extern u_int16_t adv_asc38C0800_mcode_size; -extern u_int32_t adv_asc38C0800_mcode_chksum; +#define ADW_MAX_CARRIER 253 /* Max. number of host commands (253) */ -#endif /* ADV_MCODE_H */ +/* + * ADW_CARRIER must be exactly 16 BYTES + * Every adw_carrier structure _MUST_ always be aligned on a 16 bytes boundary + */ +struct adw_carrier { +/* ---------- the microcode wants the field below ---------- */ + u_int32_t carr_id; /* Carrier ID */ + u_int32_t carr_ba; /* Carrier Bus Address */ + u_int32_t areq_ba; /* ADW_SCSI_REQ_Q Bus Address */ + /* + * next_ba [31:4] Carrier Physical Next Pointer + * + * next_ba [3:1] Reserved Bits + * next_ba [0] Done Flag set in Response Queue. + */ + u_int32_t next_ba; /* see next_ba flags below */ +/* ---------- ---------- */ +}; + +typedef struct adw_carrier ADW_CARRIER; + +/* + * next_ba flags + */ +#define ASC_RQ_DONE 0x00000001 +#define ASC_RQ_GOOD 0x00000002 +#define ASC_CQ_STOPPER 0x00000000 + +/* + * Mask used to eliminate low 4 bits of carrier 'next_ba' field. + */ +#define ASC_NEXT_BA_MASK 0xFFFFFFF0 +#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_BA_MASK) + +/* + * Bus Address of a Carrier. + * ba = base_ba + v_address - base_va + */ +#define ADW_CARRIER_BADDR(dmamap, carriers, x) ((dmamap)->dm_segs[0].ds_addr +\ + (((u_long)x) - ((u_long)(carriers)))) +/* + * Virtual Address of a Carrier. + * va = base_va + bus_address - base_ba + */ +#define ADW_CARRIER_VADDR(sc, x) ((ADW_CARRIER *) \ + (((u_int8_t *)(sc)->sc_control->carriers) + \ + ((u_long)x) - \ + (sc)->sc_dmamap_carrier->dm_segs[0].ds_addr)) + +/******************************************************************************/ + +struct adw_mcode { + const u_int8_t *mcode_data; + const u_int32_t mcode_chksum; + const u_int16_t mcode_size; +}; + + +/******************************************************************************/ + +/* + * Fixed locations of microcode operating variables. + */ +#define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ +#define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */ +#define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ +#define ADW_MC_VERSION_DATE 0x0038 /* microcode version */ +#define ADW_MC_VERSION_NUM 0x003A /* microcode number */ +#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ +#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ +#define ADW_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ +#define ADW_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */ + +#define ADW_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ +#define ADW_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ +#define ADW_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ +#define ADW_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ + /* + * 4-bit speed SDTR speed name + * =========== =============== + * 0000b (0x0) SDTR disabled + * 0001b (0x1) 5 Mhz + * 0010b (0x2) 10 Mhz + * 0011b (0x3) 20 Mhz (Ultra) + * 0100b (0x4) 40 Mhz (LVD/Ultra2) + * 0101b (0x5) 80 Mhz (LVD2/Ultra3) + * 0110b (0x6) Undefined + * ... + * 1111b (0xF) Undefined + */ +#define ADW_MC_CHIP_TYPE 0x009A +#define ADW_MC_INTRB_CODE 0x009B +#define ADW_MC_WDTR_ABLE 0x009C +#define ADW_MC_SDTR_ABLE 0x009E +#define ADW_MC_TAGQNG_ABLE 0x00A0 +#define ADW_MC_DISC_ENABLE 0x00A2 +#define ADW_MC_IDLE_CMD_STATUS 0x00A4 +#define ADW_MC_IDLE_CMD 0x00A6 +#define ADW_MC_IDLE_CMD_PARAMETER 0x00A8 +#define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC +#define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE +#define ADW_MC_DEFAULT_MEM_CFG 0x00B0 +#define ADW_MC_DEFAULT_SEL_MASK 0x00B2 +#define ADW_MC_SDTR_DONE 0x00B6 +#define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0 +#define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0 +#define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100 +#define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ +#define ADW_MC_WDTR_DONE 0x0124 +#define ADW_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ +#define ADW_MC_ICQ 0x0160 +#define ADW_MC_IRQ 0x0164 +#define ADW_MC_PPR_ABLE 0x017A + + +/* + * Microcode Control Flags + * + * Flags set by the Adw Library in RISC variable 'control_flag' (0x122) + * and handled by the microcode. + */ +#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */ +#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */ + + +/* + * ADW_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format + */ +#define HSHK_CFG_WIDE_XFR 0x8000 +#define HSHK_CFG_RATE 0x0F00 +#define HSHK_CFG_OFFSET 0x001F + +#define ADW_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */ +#define ADW_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */ +#define ADW_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */ +#define ADW_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */ + +#define ADW_QC_DATA_CHECK 0x01 /* Require ADW_QC_DATA_OUT set or clear. */ +#define ADW_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ +#define ADW_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ +#define ADW_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ +#define ADW_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request.XXX TBD*/ + +#define ADW_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ +#define ADW_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ +#define ADW_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */ +#define ADW_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ +#define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */ +/* + * Note: If a Tag Message is to be sent and neither ADW_QSC_HEAD_TAG or + * ADW_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. + */ +#define ADW_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ +#define ADW_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ + + +/******************************************************************************/ + +ADW_CARRIER *AdwInitCarriers __P((bus_dmamap_t, ADW_CARRIER *)); + +extern const struct adw_mcode adw_asc3550_mcode_data; +extern const struct adw_mcode adw_asc38C0800_mcode_data; +extern const struct adw_mcode adw_asc38C1600_mcode_data; +/******************************************************************************/ + +#endif /* ADW_MCODE_H */ -- cgit v1.2.3