From 858e68db6a84849e08604401cd78424b24e40935 Mon Sep 17 00:00:00 2001 From: Owain Ainsworth Date: Thu, 5 Mar 2009 23:08:24 +0000 Subject: De-macro the ring manipulation macros in favour of functions. Saves a large pile of space. Tested by several, thanks. --- sys/dev/pci/drm/r300_cmdbuf.c | 17 ------- sys/dev/pci/drm/radeon_cp.c | 31 +++++------- sys/dev/pci/drm/radeon_drv.c | 64 ++++++++++++++++++++++++ sys/dev/pci/drm/radeon_drv.h | 110 +++++++++++------------------------------ sys/dev/pci/drm/radeon_irq.c | 1 - sys/dev/pci/drm/radeon_state.c | 28 +++-------- 6 files changed, 113 insertions(+), 138 deletions(-) diff --git a/sys/dev/pci/drm/r300_cmdbuf.c b/sys/dev/pci/drm/r300_cmdbuf.c index 23de74f4ff6..7bd46d0ee01 100644 --- a/sys/dev/pci/drm/r300_cmdbuf.c +++ b/sys/dev/pci/drm/r300_cmdbuf.c @@ -87,7 +87,6 @@ r300_emit_cliprects(drm_radeon_private_t *dev_priv, struct drm_clip_rect box; int nr; int i; - RING_LOCALS; nr = cmdbuf->nbox - n; if (nr > R300_SIMULTANEOUS_CLIPRECTS) @@ -320,7 +319,6 @@ r300_emit_carefully_checked_packet0(drm_radeon_private_t *dev_priv, int sz; int i; int values[64]; - RING_LOCALS; sz = header.packet0.count; reg = (header.packet0.reghi << 8) | header.packet0.reglo; @@ -374,7 +372,6 @@ r300_emit_packet0(drm_radeon_private_t *dev_priv, { int reg; int sz; - RING_LOCALS; sz = header.packet0.count; reg = (header.packet0.reghi << 8) | header.packet0.reglo; @@ -421,7 +418,6 @@ r300_emit_vpu(drm_radeon_private_t *dev_priv, drm_radeon_kcmd_buffer_t *cmdbuf, { int sz; int addr; - RING_LOCALS; sz = header.vpu.count; addr = (header.vpu.adrhi << 8) | header.vpu.adrlo; @@ -469,8 +465,6 @@ int r300_emit_clear(drm_radeon_private_t *dev_priv, drm_radeon_kcmd_buffer_t *cmdbuf) { - RING_LOCALS; - if (8 * 4 > cmdbuf->bufsz) return EINVAL; @@ -504,7 +498,6 @@ r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, #define MAX_ARRAY_PACKET 64 u32 payload[MAX_ARRAY_PACKET]; u32 narrays; - RING_LOCALS; count = (header >> 16) & 0x3fff; @@ -570,7 +563,6 @@ r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv, { u32 *cmd = (u32 *) cmdbuf->buf; int count, ret; - RING_LOCALS; count=(cmd[0]>>16) & 0x3fff; @@ -617,7 +609,6 @@ r300_emit_draw_indx_2(drm_radeon_private_t *dev_priv, u32 *cmd; int count; int expected_count; - RING_LOCALS; cmd = (u32 *) cmdbuf->buf; count = (cmd[0]>>16) & 0x3fff; @@ -692,7 +683,6 @@ r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, { u32 header; int count; - RING_LOCALS; if (4 > cmdbuf->bufsz) return EINVAL; @@ -840,7 +830,6 @@ void r300_pacify(drm_radeon_private_t *dev_priv) { uint32_t cache_z, cache_3d, cache_2d; - RING_LOCALS; cache_z = R300_ZC_FLUSH; cache_2d = R300_RB2D_DC_FLUSH; @@ -908,7 +897,6 @@ void r300_cmd_wait(drm_radeon_private_t * dev_priv, drm_r300_cmd_header_t header) { u32 wait_until; - RING_LOCALS; if (!header.wait.flags) return; @@ -951,7 +939,6 @@ r300_scratch(drm_radeon_private_t *dev_priv, drm_radeon_kcmd_buffer_t *cmdbuf, { u32 *ref_age_base; u32 i, buf_idx, h_pending; - RING_LOCALS; if (cmdbuf->bufsz < sizeof(uint64_t) + header.scratch.n_bufs * sizeof(buf_idx) ) { return EINVAL; @@ -1016,7 +1003,6 @@ r300_emit_r500fp(drm_radeon_private_t *dev_priv, int type; int clamp; int stride; - RING_LOCALS; sz = header.r500fp.count; /* address is 9 bits 0 - 8, bit 1 of flags is part of address */ @@ -1137,7 +1123,6 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, DRM_DEBUG("R300_CMD_CP_DELAY\n"); { int i; - RING_LOCALS; BEGIN_RING(header.delay.count); for (i = 0; i < header.delay.count; i++) @@ -1217,8 +1202,6 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, * are written inside the pacifier bracket. */ if (emit_dispatch_age) { - RING_LOCALS; - /* Emit the vertex buffer age */ BEGIN_RING(2); RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch); diff --git a/sys/dev/pci/drm/radeon_cp.c b/sys/dev/pci/drm/radeon_cp.c index 3ca5d12d523..e3f40db24fc 100644 --- a/sys/dev/pci/drm/radeon_cp.c +++ b/sys/dev/pci/drm/radeon_cp.c @@ -436,7 +436,6 @@ radeon_cp_load_microcode(drm_radeon_private_t *dev_priv) int radeon_do_cp_idle(drm_radeon_private_t *dev_priv) { - RING_LOCALS; DRM_DEBUG("\n"); BEGIN_RING(6); @@ -456,9 +455,6 @@ radeon_do_cp_idle(drm_radeon_private_t *dev_priv) void radeon_do_cp_start(drm_radeon_private_t *dev_priv) { - RING_LOCALS; - DRM_DEBUG("\n"); - radeon_do_wait_for_idle(dev_priv); RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); @@ -1166,19 +1162,18 @@ radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init) DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", dev_priv->gart_buffers_offset); - dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; - dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle - + init->ring_size / sizeof(u32)); - dev_priv->ring.size = init->ring_size; - dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); - - dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; - dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); - - dev_priv->ring.fetch_size = /* init->fetch_size */ 32; - dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); + dev_priv->ring.start = (u_int32_t *)dev_priv->cp_ring->handle; + dev_priv->ring.size = init->ring_size / sizeof(u_int32_t); + dev_priv->ring.end = ((u_int32_t *)dev_priv->cp_ring->handle + + dev_priv->ring.size); + dev_priv->ring.tail_mask = dev_priv->ring.size - 1; - dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; + /* Parameters for ringbuffer initialisation */ + dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); + dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ + 4096 / 8); + dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ + 32 / 16); #if __OS_HAS_AGP if (dev_priv->flags & RADEON_IS_AGP) { @@ -1603,9 +1598,9 @@ radeon_wait_ring(drm_radeon_private_t *dev_priv, int n) u32 last_head = GET_RING_HEAD(dev_priv); for (i = 0; i < dev_priv->usec_timeout; i++) { - u32 head = GET_RING_HEAD(dev_priv); + u_int32_t head = GET_RING_HEAD(dev_priv); - ring->space = (head - ring->tail) * sizeof(u32); + ring->space = head - ring->tail; if (ring->space <= 0) ring->space += ring->size; if (ring->space > n) diff --git a/sys/dev/pci/drm/radeon_drv.c b/sys/dev/pci/drm/radeon_drv.c index 3a463d73d20..5f566195bb3 100644 --- a/sys/dev/pci/drm/radeon_drv.c +++ b/sys/dev/pci/drm/radeon_drv.c @@ -685,3 +685,67 @@ radeondrm_ioctl(struct drm_device *dev, u_long cmd, caddr_t data, } return (EINVAL); } + +void +radeondrm_begin_ring(struct drm_radeon_private *dev_priv, int ncmd) +{ + RADEON_VPRINTF("%d\n", ncmd); + if (dev_priv->ring.space <= ncmd) { + radeondrm_commit_ring(dev_priv); + radeon_wait_ring(dev_priv, ncmd); + } + dev_priv->ring.space -= ncmd; + dev_priv->ring.wspace = ncmd; + dev_priv->ring.woffset = dev_priv->ring.tail; +} + +void +radeondrm_advance_ring(struct drm_radeon_private *dev_priv) +{ + RADEON_VPRINTF("wr=0x%06x, tail = 0x%06x\n", dev_priv->ring.woffset, + dev_priv->ring.tail); + if (((dev_priv->ring.tail + dev_priv->ring.wspace) & + dev_priv->ring.tail_mask) != dev_priv->ring.woffset) { + DRM_ERROR("mismatch: nr %x, write %x\n", ((dev_priv->ring.tail + + dev_priv->ring.wspace) & dev_priv->ring.tail_mask), + dev_priv->ring.woffset); + } else + dev_priv->ring.tail = dev_priv->ring.woffset; +} + +void +radeondrm_commit_ring(struct drm_radeon_private *dev_priv) +{ + /* flush write combining buffer and writes to ring */ + DRM_MEMORYBARRIER(); + GET_RING_HEAD(dev_priv); + RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); + /* read from PCI bus to ensure correct posting */ + RADEON_READ(RADEON_CP_RB_RPTR); +} + +void +radeondrm_out_ring(struct drm_radeon_private *dev_priv, u_int32_t x) +{ + RADEON_VPRINTF("0x%08x at 0x%x\n", x, dev_priv->ring.woffset); + dev_priv->ring.start[dev_priv->ring.woffset++] = x; + dev_priv->ring.woffset &= dev_priv->ring.tail_mask; +} + +void +radeondrm_out_ring_table(struct drm_radeon_private *dev_priv, u_int32_t *table, + int size) +{ + if (dev_priv->ring.woffset + size > dev_priv->ring.tail_mask) { + int i = dev_priv->ring.tail_mask + 1 - dev_priv->ring.woffset; + + size -= i; + while (i--) + dev_priv->ring.start[dev_priv->ring.woffset++] = + *table++; + dev_priv->ring.woffset = 0; + } + while (size--) + dev_priv->ring.start[dev_priv->ring.woffset++] = *table++; + dev_priv->ring.woffset &= dev_priv->ring.tail_mask; +} diff --git a/sys/dev/pci/drm/radeon_drv.h b/sys/dev/pci/drm/radeon_drv.h index b124c410bfa..bc229dea96f 100644 --- a/sys/dev/pci/drm/radeon_drv.h +++ b/sys/dev/pci/drm/radeon_drv.h @@ -166,20 +166,19 @@ typedef struct drm_radeon_freelist { } drm_radeon_freelist_t; typedef struct drm_radeon_ring_buffer { - u32 *start; - u32 *end; - int size; /* Double Words */ - int size_l2qw; /* log2 Quad Words */ - - int rptr_update; /* Double Words */ - int rptr_update_l2qw; /* log2 Quad Words */ - - int fetch_size; /* Double Words */ - int fetch_size_l2ow; /* log2 Oct Words */ - - u32 tail; - u32 tail_mask; - int space; + u_int32_t *start; + u_int32_t *end; + int size; /* in u_int32_ts */ + + int size_l2qw; /* log2 Quad Words */ + int rptr_update_l2qw; /* log2 Quad Words */ + int fetch_size_l2ow; /* log2 Oct Words */ + + int space; + int wspace; + u_int32_t tail; + u_int32_t tail_mask; /* For making write pointer wrap */ + u_int32_t woffset; } drm_radeon_ring_buffer_t; typedef struct drm_radeon_depth_clear_t { @@ -325,6 +324,12 @@ static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, (off >= gart_start && off <= gart_end)); } +void radeondrm_begin_ring(struct drm_radeon_private *, int); +void radeondrm_advance_ring(struct drm_radeon_private *); +void radeondrm_commit_ring(struct drm_radeon_private *); +void radeondrm_out_ring(struct drm_radeon_private *, u_int32_t); +void radeondrm_out_ring_table(struct drm_radeon_private *, u_int32_t *, int); + /* radeon_cp.c */ extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); @@ -1350,81 +1355,26 @@ do { \ */ #define RADEON_VERBOSE 0 +#if RADEON_VERBOSE > 0 +#define RADEON_VPRINTF(fmt, args...) DRM_INFO(fmt, ##args) +#else +#define RADEON_VPRINTF(fmt, args...) +#endif -#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; - -#define BEGIN_RING( n ) do { \ - if ( RADEON_VERBOSE ) { \ - DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ - } \ - if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ - COMMIT_RING(); \ - radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ - } \ - _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ - ring = dev_priv->ring.start; \ - write = dev_priv->ring.tail; \ - mask = dev_priv->ring.tail_mask; \ -} while (0) +#define BEGIN_RING( n ) radeondrm_begin_ring(dev_priv, n) -#define ADVANCE_RING() do { \ - if ( RADEON_VERBOSE ) { \ - DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ - write, dev_priv->ring.tail ); \ - } \ - if (((dev_priv->ring.tail + _nr) & mask) != write) { \ - DRM_ERROR( \ - "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ - ((dev_priv->ring.tail + _nr) & mask), \ - write, __LINE__); \ - } else \ - dev_priv->ring.tail = write; \ -} while (0) +#define ADVANCE_RING() radeondrm_advance_ring(dev_priv) -#define COMMIT_RING() do { \ - /* Flush writes to ring */ \ - DRM_MEMORYBARRIER(); \ - GET_RING_HEAD( dev_priv ); \ - RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ - /* read from PCI bus to ensure correct posting */ \ - RADEON_READ( RADEON_CP_RB_RPTR ); \ -} while (0) +#define COMMIT_RING() radeondrm_commit_ring(dev_priv) -#define OUT_RING( x ) do { \ - if ( RADEON_VERBOSE ) { \ - DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ - (unsigned int)(x), write ); \ - } \ - ring[write++] = (x); \ - write &= mask; \ -} while (0) +#define OUT_RING( x ) radeondrm_out_ring(dev_priv, x) #define OUT_RING_REG( reg, val ) do { \ OUT_RING( CP_PACKET0( reg, 0 ) ); \ OUT_RING( val ); \ } while (0) -#define OUT_RING_TABLE( tab, sz ) do { \ - int _size = (sz); \ - int *_tab = (int *)(tab); \ - \ - if (write + _size > mask) { \ - int _i = (mask+1) - write; \ - _size -= _i; \ - while (_i > 0) { \ - *(int *)(ring + write) = *_tab++; \ - write++; \ - _i--; \ - } \ - write = 0; \ - _tab += _i; \ - } \ - while (_size > 0) { \ - *(ring + write) = *_tab++; \ - write++; \ - _size--; \ - } \ - write &= mask; \ -} while (0) +#define OUT_RING_TABLE( tab, sz ) \ + radeondrm_out_ring_table(dev_priv, (u_int32_t *)tab, sz) #endif /* __RADEON_DRV_H__ */ diff --git a/sys/dev/pci/drm/radeon_irq.c b/sys/dev/pci/drm/radeon_irq.c index dbfd1e6df95..fa18ba8dc40 100644 --- a/sys/dev/pci/drm/radeon_irq.c +++ b/sys/dev/pci/drm/radeon_irq.c @@ -229,7 +229,6 @@ radeon_emit_irq(struct drm_device * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; unsigned int ret; - RING_LOCALS; atomic_inc(&dev_priv->swi_emitted); ret = atomic_read(&dev_priv->swi_emitted); diff --git a/sys/dev/pci/drm/radeon_state.c b/sys/dev/pci/drm/radeon_state.c index f4418c25693..f6f8f8044d3 100644 --- a/sys/dev/pci/drm/radeon_state.c +++ b/sys/dev/pci/drm/radeon_state.c @@ -206,7 +206,6 @@ radeon_check_and_fixup_packets(drm_radeon_private_t *dev_priv, break; case R200_EMIT_VAP_CTL: { - RING_LOCALS; BEGIN_RING(2); OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); ADVANCE_RING(); @@ -463,8 +462,6 @@ radeon_check_and_fixup_packet3(drm_radeon_private_t *dev_priv, void radeon_emit_clip_rect(drm_radeon_private_t *dev_priv, struct drm_clip_rect *box) { - RING_LOCALS; - DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n", box->x1, box->y1, box->x2, box->y2); @@ -601,7 +598,7 @@ radeon_cp_dispatch_clear(struct drm_device * dev, drm_radeon_clear_t * clear, unsigned int flags = clear->flags; u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0; int i; - RING_LOCALS; + DRM_DEBUG("flags = 0x%x\n", flags); if (dev_priv->sarea_priv->pfCurrentPage == 1) { @@ -1089,7 +1086,7 @@ radeon_cp_dispatch_swap(struct drm_device *dev) int nbox = sarea_priv->nbox; struct drm_clip_rect *pbox = sarea_priv->boxes; int i; - RING_LOCALS; + DRM_DEBUG("\n"); /* Wait for the 3D stream to idle before dispatching the bitblt. @@ -1161,9 +1158,8 @@ radeon_cp_dispatch_flip(struct drm_device *dev) struct drm_sarea *sarea = (struct drm_sarea *) dev_priv->sarea->handle; int offset = (dev_priv->sarea_priv->pfCurrentPage == 1) ? dev_priv->front_offset : dev_priv->back_offset; - RING_LOCALS; - DRM_DEBUG("pfCurrentPage=%d\n", - dev_priv->sarea_priv->pfCurrentPage); + + DRM_DEBUG("pfCurrentPage=%d\n", dev_priv->sarea_priv->pfCurrentPage); /* Update the frame offsets for both CRTCs */ @@ -1199,7 +1195,6 @@ radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; - RING_LOCALS; buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; @@ -1217,7 +1212,7 @@ radeon_cp_dispatch_indirect(struct drm_device *dev, struct drm_buf *buf, int start, int end) { drm_radeon_private_t *dev_priv = dev->dev_private; - RING_LOCALS; + DRM_DEBUG("buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); if (start != end && start < end) { @@ -1263,7 +1258,6 @@ radeon_cp_dispatch_texture(struct drm_device *dev, struct drm_file *file_priv, int i; u32 texpitch, microtile; u32 offset, byte_offset; - RING_LOCALS; if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { DRM_ERROR("Invalid destination offset\n"); @@ -1494,7 +1488,7 @@ radeon_cp_dispatch_stipple(struct drm_device *dev, u32 *stipple) { drm_radeon_private_t *dev_priv = dev->dev_private; int i; - RING_LOCALS; + DRM_DEBUG("\n"); BEGIN_RING(35); @@ -1748,7 +1742,6 @@ int radeon_do_init_pageflip(struct drm_device *dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - RING_LOCALS; DRM_DEBUG("\n"); @@ -1864,7 +1857,6 @@ radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_device_dma *dma = dev->dma; struct drm_buf *buf; drm_radeon_indirect_t *indirect = data; - RING_LOCALS; LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -1934,7 +1926,6 @@ radeon_emit_packets(drm_radeon_private_t * dev_priv, struct drm_file *file_priv, int id = (int)header.packet.packet_id; int sz, reg; int *data = (int *)cmdbuf->buf; - RING_LOCALS; if (id >= RADEON_MAX_STATE_PACKETS) return EINVAL; @@ -1969,7 +1960,6 @@ radeon_emit_scalars(drm_radeon_private_t *dev_priv, int sz = header.scalars.count; int start = header.scalars.offset; int stride = header.scalars.stride; - RING_LOCALS; BEGIN_RING(3 + sz); OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); @@ -1990,7 +1980,6 @@ radeon_emit_scalars2(drm_radeon_private_t *dev_priv, { int sz = header.scalars.count; int start = ((unsigned int)header.scalars.offset) + 0x100; int stride = header.scalars.stride; - RING_LOCALS; BEGIN_RING(3 + sz); OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); @@ -2010,7 +1999,6 @@ radeon_emit_vectors(drm_radeon_private_t *dev_priv, int sz = header.vectors.count; int start = header.vectors.offset; int stride = header.vectors.stride; - RING_LOCALS; BEGIN_RING(5 + sz); OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); @@ -2031,7 +2019,6 @@ radeon_emit_veclinear(drm_radeon_private_t *dev_priv, { int sz = header.veclinear.count * 4; int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8); - RING_LOCALS; if (!sz) return 0; @@ -2058,7 +2045,6 @@ radeon_emit_packet3(struct drm_device * dev, struct drm_file *file_priv, drm_radeon_private_t *dev_priv = dev->dev_private; unsigned int cmdsz; int ret; - RING_LOCALS; DRM_DEBUG("\n"); @@ -2087,7 +2073,6 @@ radeon_emit_packet3_cliprect(struct drm_device *dev, struct drm_file *file_priv, int ret; struct drm_clip_rect __user *boxes = cmdbuf->boxes; int i = 0; - RING_LOCALS; DRM_DEBUG("\n"); @@ -2142,7 +2127,6 @@ int radeon_emit_wait(struct drm_device *dev, int flags) { drm_radeon_private_t *dev_priv = dev->dev_private; - RING_LOCALS; DRM_DEBUG("%x\n", flags); switch (flags) { -- cgit v1.2.3