From 9c0ecc25a6e356710bfceeea556fb1a07753bc06 Mon Sep 17 00:00:00 2001 From: Miod Vallat Date: Sun, 3 Aug 2003 23:34:10 +0000 Subject: Resistance is futile, you will be KNF'ed. And then it will be easier to debug this mess (no functional change yet). --- sys/arch/mvme88k/mvme88k/eh.S | 2679 ++++++++++++------------ sys/arch/mvme88k/mvme88k/locore.S | 188 +- sys/arch/mvme88k/mvme88k/locore_asm_routines.S | 569 +++-- sys/arch/mvme88k/mvme88k/process.S | 66 +- 4 files changed, 1722 insertions(+), 1780 deletions(-) diff --git a/sys/arch/mvme88k/mvme88k/eh.S b/sys/arch/mvme88k/mvme88k/eh.S index dd4bcee2dc6..eea70201cc5 100644 --- a/sys/arch/mvme88k/mvme88k/eh.S +++ b/sys/arch/mvme88k/mvme88k/eh.S @@ -1,4 +1,4 @@ -/* $OpenBSD: eh.S,v 1.29 2003/01/14 03:20:16 miod Exp $ */ +/* $OpenBSD: eh.S,v 1.30 2003/08/03 23:34:09 miod Exp $ */ /* * Mach Operating System * Copyright (c) 1993-1991 Carnegie Mellon University @@ -31,32 +31,27 @@ /* * HISTORY * 1. Should get rid of SR0 reference for thread stuff. - * 2. Make up my mind what is _kstack. I think it - * should be p->p_addr+UPAGES. (p_addr - * is pointing to user struct and swapin is - * making sure it is updated) + * 2. Make up my mind what is _kstack. I think it should be p->p_addr+UPAGES. + * (p_addr is pointing to user struct and swapin is making sure it is + * updated) * Whatever is _kstack, its usage in this file should be * revisited. */ - - /* - **************************************************************RCS****** + +/* + * In the following discussion, references are made to: + * MC88100 - RISC MICROPROCESSOR USER'S MANUAL + * (second edition). Reference in []s refer to section numbers. * - * ------------------------------------------------------------------- - * ; In the following discussion, references are made to: ; - * ; MC88100 - RISC MICROPROCESSOR USER'S MANUAL ; - * ; (second edition). Reference in []s refer to section numbers. ; - * ; ; - * ; This discussion assumes that you are at least vaguely familiar ; - * ; with 88100 exception handling (chapter 6), the MACH kernel, and ; - * ; that you have a brain (and use it while reading this). ; - * ; ; - * ; I also assume (and hope) that you're not offended by ; - * ; frequent misspellings. ; - * ; ; - * ; Jeffrey Friedl ; - * ; jfriedl@rna.ncl.omron.co.jp ; - * ; December, 1989 ; + * This discussion assumes that you are at least vaguely familiar with 88100 + * exception handling (chapter 6), the MACH kernel, and that you have a brain + * (and use it while reading this). + * + * I also assume (and hope) that you're not offended by frequent misspellings. + * + * Jeffrey Friedl + * jfriedl@rna.ncl.omron.co.jp + * December, 1989 * ------------------------------------------------------------------- * * EXCEPTIONS, INTERRUPTS, and TRAPS @@ -214,10 +209,11 @@ */ #include "assym.h" + #include #include -#include /* CPU_ and BRD_ defines */ -#include /* for T_ defines */ +#include /* CPU_ and BRD_ defines */ +#include /* for T_ defines */ #include /* @@ -225,47 +221,51 @@ * a bit outdated and needs to be changed. Until then, we'll define some * pseudo-fields there for our needs. * - * EF_SR3 A place to save the exception-time SR3 from just after the - * time when an exception is raised until just after the FPU - * has been restarted. This does not necessarly conflict with - * the general registers (though it can if you're not careful) - * and so we can use a spot later used to save a general register. + * EF_SR3 + * A place to save the exception-time SR3 from just after the + * time when an exception is raised until just after the FPU + * has been restarted. This does not necessarly conflict with + * the general registers (though it can if you're not careful) + * and so we can use a spot later used to save a general register. * - * EF_FLAGS This is just the old EF_MODE. "EF_MODE" isn't a very good name. + * EF_FLAGS + * This is just the old EF_MODE. "EF_MODE" isn't a very good name. */ -#define EF_SR3 (EF_R0 + 5) -#define EF_FLAGS EF_MODE +#define EF_SR3 (EF_R0 + 5) +#define EF_FLAGS EF_MODE + +/* Define this to make interrupts use their own stack */ +#undef INTSTACK -#define INTSTACK 0 /* To make interupts use their own stack */ data align 4 sbadcpupanic: - string "eh.S: bad cpu number in FLAGS" - + string "eh.S: bad cpu number in FLAGS" + text align 8 Lbadcpupanic: - or.u r2, r0, hi16(sbadcpupanic) - or r2, r2, lo16(sbadcpupanic) - bsr _C_LABEL(panic) + or.u r2, r0, hi16(sbadcpupanic) + or r2, r2, lo16(sbadcpupanic) + bsr _C_LABEL(panic) align 8 -#define OFF_VEC 0 -#define OFF_EPSR 4 -#define OFF_EXIP 8 -#define OFF_ENIP 12 -#define OFF_DSR 16 -#define OFF_DLAR 20 -#define OFF_DPAR 24 -#define OFF_ISR 28 -#define OFF_ILAR 32 -#define OFF_IPAR 36 -#define OFF_TMP 40 +#define OFF_VEC 0 +#define OFF_EPSR 4 +#define OFF_EXIP 8 +#define OFF_ENIP 12 +#define OFF_DSR 16 +#define OFF_DLAR 20 +#define OFF_DPAR 24 +#define OFF_ISR 28 +#define OFF_ILAR 32 +#define OFF_IPAR 36 +#define OFF_TMP 40 -#define SAVE_CTX ; \ +#define SAVE_CTX \ stcr r31, SRX ; \ or.u r31, r0, hi16(_save_frame) ; \ or r31, r31, lo16(_save_frame) ; \ @@ -314,133 +314,126 @@ Lbadcpupanic: ldcr r2, IUAP ; \ st r1, r31, REG_OFF(EF_ISAP) ; \ st r2, r31, REG_OFF(EF_IUAP) ; \ - /* Restore r1, r2, r3, and r31 */ ; \ + /* Restore r1, r2, r3, and r31 */ ; \ ld r1 , r31, GENREG_OFF(1) ; \ ld.d r2 , r31, GENREG_OFF(2) ; \ ld r31, r31, GENREG_OFF(31) -/*************************************************************************** - *************************************************************************** - ** - ** #define PREP(NAME, NUM, BIT, SSBR_STUFF, FLAG_CHECK) - ** - ** This is the "exception processing preparaton" common to all exception - ** processing. It is used in the following manor: - ** - ** ASGLOBAL(foo_handler) - ** PREP("foo", 11, DEBUG_FOO_BIT, No_SSBR_Stuff, No_Precheck) - ** CALL(_C_LABEL(trapXXX), T_FOO_FAULT, r31) - ** DONE(DEBUG_FOO_BIT) - ** - ** This defines the exception handler for the "foo" exception. - ** The arguments ro PREP(): - ** NAME - String for debugging (more info later) - ** NUM - The exception number [see the manual, Table 6-1] - ** BIT - Bit to check in eh_debug for debugging (more info later) - ** SSBR_STUFF - - ** If the exception might leave some bits in the SSBR set, - ** this should indicate how they are cleared. - ** FLAG_PRECHECK - - ** This is for the data access exception only. See it for - ** more info. - ** - ** - ** What's in between PREP() and DONE() (usually a CALL) is the actual - ** servicing of the interrupt. During this time, any register may - ** be used freely as they've all been saved in the exception frame - ** (which is pointed-to by r31). - **/ +/* + * + * #define PREP(NAME, NUM, BIT, SSBR_STUFF, FLAG_CHECK) + * + * This is the "exception processing preparaton" common to all exception + * processing. It is used in the following manor: + * + * ASGLOBAL(foo_handler) + * PREP("foo", 11, DEBUG_FOO_BIT, No_SSBR_Stuff, No_Precheck) + * CALL(_C_LABEL(trapXXX), T_FOO_FAULT, r31) + * DONE(DEBUG_FOO_BIT) + * + * This defines the exception handler for the "foo" exception. + * The arguments ro PREP(): + * NAME + * String for debugging (more info later) + * NUM + * The exception number [see the manual, Table 6-1] + * BIT + * Bit to check in eh_debug for debugging (more info later) + * SSBR_STUFF + * If the exception might leave some bits in the SSBR set, + * this should indicate how they are cleared. + * FLAG_PRECHECK + * This is for the data access exception only. See it for + * more info. + * + * What's in between PREP() and DONE() (usually a CALL) is the actual + * servicing of the interrupt. During this time, any register may + * be used freely as they've all been saved in the exception frame + * (which is pointed-to by r31). + */ #ifdef M88100 -#define PREP(NAME, NUM, BIT, SSBR_STUFF, FLAG_PRECHECK) ; \ +#define PREP(NAME, NUM, BIT, SSBR_STUFF, FLAG_PRECHECK) \ xcr FLAGS, FLAGS, SR1 ; \ FLAG_PRECHECK ; \ - ; \ /* the bsr later clobbers r1, so save now */ ; \ - stcr r1, SR2 /* r1 now free */ ; \ + stcr r1, SR2 /* r1 now free */ ; \ /* set or clear the FLAG_FROM_KERNEL bit */ ; \ ldcr r1, EPSR ; \ bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f ; \ - clr FLAGS, FLAGS, 1 ; \ + clr FLAGS, FLAGS, 1 ; \ set FLAGS, FLAGS, 1 ; \ - ; \ /* get a stack (exception frame) */ ; \ 1: bsr setup_phase_one ; \ - ; \ /* TMP2 now free -- use to set EF_VECTOR */ ; \ or TMP2, r0, NUM ; \ st TMP2, r31, REG_OFF(EF_VECTOR) ; \ /* TMP3 also free -- use to set last_vector */ ; \ or.u TMP3, r0, hi16(_last_vector) ; \ st TMP2, TMP3, lo16(_last_vector) ; \ - ; \ /* Clear any bits in the SSBR (held in TMP) */ ; \ /* SSBR_STUFF may be empty, though. */ ; \ SSBR_STUFF ; \ - ; \ /* call setup_phase_two to restart the FPU */ ; \ /* and to save all general registers. */ ; \ bsr setup_phase_two ; \ - ; \ /* All general regs free -- do any debugging */ ; \ PREP_DEBUG(BIT, NAME) -#endif /* m88100 */ +#endif #ifdef M88110 -#define PREP2(NAME, NUM, BIT, SSBR_STUFF, FLAG_PRECHECK); \ +#define PREP2(NAME, NUM, BIT, SSBR_STUFF, FLAG_PRECHECK) \ SAVE_CTX ; \ xcr FLAGS, FLAGS, SR1 ; \ FLAG_PRECHECK ; \ /* the bsr later clobbers r1, so save now */ ; \ - stcr r1, SR2 /* r1 now free */ ; \ + stcr r1, SR2 /* r1 now free */ ; \ /* set or clear the FLAG_FROM_KERNEL bit */ ; \ - ldcr r1, EPSR ; \ - bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f ; \ - clr FLAGS, FLAGS, 1 ; \ - set FLAGS, FLAGS, 1 ; \ - ; \ + ldcr r1, EPSR ; \ + bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f ; \ + clr FLAGS, FLAGS, 1 ; \ + set FLAGS, FLAGS, 1 ; \ /* get a stack (exception frame) */ ; \ 1: bsr m88110_setup_phase_one ; \ - ; \ /* TMP2 now free -- use to set EF_VECTOR */ ; \ or TMP2, r0, NUM ; \ st TMP2, r31, REG_OFF(EF_VECTOR) ; \ - ; \ /* call setup_phase_two to restart the FPU */ ; \ /* and to save all general registers. */ ; \ bsr m88110_setup_phase_two ; \ - ; \ /* All general regs free -- do any debugging */ ; \ PREP_DEBUG(BIT, NAME) -#endif /* M88110 */ +#endif /* Some defines for use with PREP() */ -#define No_SSBR_Stuff /* empty */ -#define Clear_SSBR_Dest bsr clear_dest_ssbr_bit -#define No_Precheck /* empty */ -#define Data_Precheck \ - bb1.n FLAG_IGNORE_DATA_EXCEPTION, FLAGS, ignore_data_exception -#define M88110_Data_Precheck \ - bb1.n FLAG_IGNORE_DATA_EXCEPTION, FLAGS, m88110_ignore_data_exception +#define No_SSBR_Stuff /* empty */ +#define Clear_SSBR_Dest \ + bsr clear_dest_ssbr_bit +#define No_Precheck /* empty */ +#define Data_Precheck \ + bb1.n FLAG_IGNORE_DATA_EXCEPTION, FLAGS, ignore_data_exception +#define M88110_Data_Precheck \ + bb1.n FLAG_IGNORE_DATA_EXCEPTION, FLAGS, m88110_ignore_data_exception #ifdef EH_DEBUG - /* - * If we allow debugging, there is a variable "eh_debug" - * in which there is a bit for each exception. If the bit - * is set for an exception, debugging information is printed - * about that exception whenever it occurs. - * - * The bits are defined in "asm.h" - */ - -GLOBAL(eh_debug) word 0x00000000 - - /* - * additional pre-servicing preparation to be done when - * debugging... check eh_debug and make the call if - * need be. - */ -#define PREP_DEBUG(DebugNumber, Name) \ +/* + * If we allow debugging, there is a variable "eh_debug" + * in which there is a bit for each exception. If the bit + * is set for an exception, debugging information is printed + * about that exception whenever it occurs. + * + * The bits are defined in "asm.h" + */ + +GLOBAL(eh_debug) + word 0x00000000 + +/* + * additional pre-servicing preparation to be done when + * debugging... check eh_debug and make the call if + * need be. + */ +#define PREP_DEBUG(DebugNumber, Name) \ or.u r2, r0, hi16(_eh_debug) ; \ ld r3, r2, lo16(_eh_debug) ; \ bb0 DebugNumber, r3, 4f ; \ @@ -451,25 +444,25 @@ GLOBAL(eh_debug) word 0x00000000 or.u r5, r0, hi16(2f) ; \ or r5, r5, lo16(2f) ; \ bsr.n _MY_info ; \ - subu r31, r31, 40 ; \ + subu r31, r31, 40 ; \ br.n 4f ; \ - addu r31, r31, 40 ; \ + addu r31, r31, 40 ; \ data ; \ - 2: string Name ; \ +2: string Name ; \ byte 0 ; \ align 4 ; \ text ; \ - 4: +4: - /* - * Post-servicing work to be done. - * When debugging, check "eh_debug" and call the - * debug routined if neeed be. - * - * Then, return from the interrupt handler. - */ -#define DONE(DebugNumber) \ +/* + * Post-servicing work to be done. + * When debugging, check "eh_debug" and call the + * debug routined if neeed be. + * + * Then, return from the interrupt handler. + */ +#define DONE(DebugNumber) \ or.u r2, r0, hi16(_eh_debug) ; \ ld r3, r2, lo16(_eh_debug) ; \ bb0 DebugNumber, r3, 2f ; \ @@ -477,18 +470,19 @@ GLOBAL(eh_debug) word 0x00000000 CALL(_MY_info_done, r31, r4) ; \ 2: br return_from_exception_handler #else - /* - * If not debugging, then no debug-prep to do. - * Also, when you're done, you're done! (no debug check). - */ -#define PREP_DEBUG(bit, name) -#define DONE(num) br return_from_exception_handler -#endif +/* + * If not debugging, then no debug-prep to do. + * Also, when you're done, you're done! (no debug check). + */ +#define PREP_DEBUG(bit, name) +#define DONE(num) \ + br return_from_exception_handler +#endif /* EH_DEBUG */ #ifdef M88100 -/*#########################################################################*/ -/*#### THE ACTUAL EXCEPTION HANDLER ENTRY POINTS for MVME18x ##############*/ -/*#########################################################################*/ +/* + * MVME18x exception handlers + */ /* unknown exception handler */ GLOBAL(unknown_handler) @@ -536,13 +530,13 @@ GLOBAL(unimplemented_handler) * it is false. If so, just return. The code before PREP handles this.... */ GLOBAL(privilege_handler) - stcr r1, SR2 /* hold r1 for a moment */ - ldcr r1, SXIP /* look at the sxip... valid bit set? */ - bb1.n RTE_VALID_BIT, r1, 1f /*skip over return if a valid exception*/ - ldcr r1, SR2 /* restore r1 */ + stcr r1, SR2 /* hold r1 for a moment */ + ldcr r1, SXIP /* look at the sxip... valid bit set? */ + bb1.n RTE_VALID_BIT, r1, 1f /* skip over if a valid exception */ + ldcr r1, SR2 /* restore r1 */ RTE 1: PREP("privilege", 6, DEBUG_PRIVILEGE_BIT, Clear_SSBR_Dest, No_Precheck) - CALL(_C_LABEL(m88100_trap), T_PRIVINFLT, r30) + CALL(_C_LABEL(m88100_trap), T_PRIVINFLT, r30) DONE(DEBUG_PRIVILEGE_BIT) /* @@ -567,31 +561,33 @@ GLOBAL(overflow_handler) DONE(DEBUG_OVERFLOW_BIT) /* Floating-point precise handler */ -#define FPp_SSBR_STUFF bsr clear_FPp_ssbr_bit +#define FPp_SSBR_STUFF \ + bsr clear_FPp_ssbr_bit GLOBAL(fp_precise_handler) PREP("FPU precise", 114, DEBUG_FPp_BIT, FPp_SSBR_STUFF, No_Precheck) - CALL(_m88100_Xfp_precise, r0, r30) /* call fp_precise(??, exception_frame)*/ + CALL(_m88100_Xfp_precise, r0, r30) DONE(DEBUG_FPp_BIT) /* Floating-point imprecise handler */ -#define FPi_SSBR_STUFF bsr clear_FPi_ssbr_bit +#define FPi_SSBR_STUFF \ + bsr clear_FPi_ssbr_bit GLOBAL(fp_imprecise_handler) PREP("FPU imprecise", 115, DEBUG_FPi_BIT, FPi_SSBR_STUFF, No_Precheck) - CALL(_Xfp_imprecise, r0, r30) /*call fp_imprecise(??,exception_frame)*/ + CALL(_Xfp_imprecise, r0, r30) DONE(DEBUG_FPi_BIT) /* All standard system calls. */ GLOBAL(syscall_handler) PREP("syscall", 128, DEBUG_SYSCALL_BIT, No_SSBR_Stuff, No_Precheck) - ld r13, r30, GENREG_OFF(13) - CALL(_m88100_syscall, r13, r30) /* system call no. is in r13 */ + ld r13, r30, GENREG_OFF(13) + CALL(_m88100_syscall, r13, r30) /* system call no. is in r13 */ DONE(DEBUG_SYSCALL_BIT) /* trap 496 comes here */ GLOBAL(bugtrap) PREP("bugsyscall", 496, DEBUG_BUGCALL_BIT, No_SSBR_Stuff, No_Precheck) - ld r9, r30, GENREG_OFF(9) - CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */ + ld r9, r30, GENREG_OFF(9) + CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */ DONE(DEBUG_BUGCALL_BIT) GLOBAL(sigsys) @@ -614,7 +610,7 @@ GLOBAL(userbpt) CALL(_C_LABEL(m88100_trap), T_USERBPT, r30) DONE(DEBUG_SIGTRAP_BIT) -#if DDB +#ifdef DDB GLOBAL(break) PREP("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck) CALL(_C_LABEL(m88100_trap), T_KDB_BREAK, r30) @@ -629,8 +625,7 @@ GLOBAL(entry) PREP("kdb", 132, DEBUG_KDB_BIT, No_SSBR_Stuff, No_Precheck) CALL(_C_LABEL(m88100_trap), T_KDB_ENTRY, r30) DONE(DEBUG_KDB_BIT) - -#else /* else not DDB */ +#else GLOBAL(break) PREP("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck) CALL(_C_LABEL(m88100_trap), T_UNKNOWNFLT, r30) @@ -645,9 +640,7 @@ GLOBAL(entry) PREP("unknown", 132, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck) CALL(_C_LABEL(m88100_trap), T_UNKNOWNFLT, r30) DONE(DEBUG_KDB_BIT) -#endif /* DDB */ - -/*--------------------------------------------------------------------------*/ +#endif /* * The error exception handler. @@ -661,8 +654,8 @@ GLOBAL(entry) * since they aren't generally used. */ GLOBAL(error_handler) - /* pick up the slavestack */ - or r26, r0, r31 /* save old stack */ + /* pick up the slavestack */ + or r26, r0, r31 /* save old stack */ or.u r31, r0, hi16(_intstack_end) or r31, r31, lo16(_intstack_end) @@ -670,35 +663,35 @@ GLOBAL(error_handler) or.u r27, r0, hi16(_intstack) or r27, r27, lo16(_intstack) 1: cmp r28, r27, r31 - bb1 ge, r28, 2f /* branch if at the end of the stack */ + bb1 ge, r28, 2f /* branch if at the end of the stack */ st r0, r0, r27 br.n 1b - addu r27, r27, 4 /* bump up */ -2: /* stack has been cleared */ - - /* ensure that stack is 8-byte aligned */ - clr r31, r31, 3<0> /* round down to 8-byte boundary */ - - /* create exception frame on stack */ - subu r31, r31, SIZEOF_EF /* r31 now our E.F. */ - - /* save old R31 and other R registers */ - st.d r0 , r31, GENREG_OFF(0) - st.d r2 , r31, GENREG_OFF(2) - st.d r4 , r31, GENREG_OFF(4) - st.d r6 , r31, GENREG_OFF(6) - st.d r8 , r31, GENREG_OFF(8) - st.d r10, r31, GENREG_OFF(10) - st.d r12, r31, GENREG_OFF(12) - st.d r14, r31, GENREG_OFF(14) - st.d r16, r31, GENREG_OFF(16) - st.d r18, r31, GENREG_OFF(18) - st.d r20, r31, GENREG_OFF(20) - st.d r22, r31, GENREG_OFF(22) - st.d r24, r31, GENREG_OFF(24) - st r30, r31, GENREG_OFF(30) + addu r27, r27, 4 /* bump up */ +2: /* stack has been cleared */ + + /* ensure that stack is 8-byte aligned */ + clr r31, r31, 3<0> /* round down to 8-byte boundary */ + + /* create exception frame on stack */ + subu r31, r31, SIZEOF_EF /* r31 now our E.F. */ + + /* save old R31 and other R registers */ + st.d r0 , r31, GENREG_OFF(0) + st.d r2 , r31, GENREG_OFF(2) + st.d r4 , r31, GENREG_OFF(4) + st.d r6 , r31, GENREG_OFF(6) + st.d r8 , r31, GENREG_OFF(8) + st.d r10, r31, GENREG_OFF(10) + st.d r12, r31, GENREG_OFF(12) + st.d r14, r31, GENREG_OFF(14) + st.d r16, r31, GENREG_OFF(16) + st.d r18, r31, GENREG_OFF(18) + st.d r20, r31, GENREG_OFF(20) + st.d r22, r31, GENREG_OFF(22) + st.d r24, r31, GENREG_OFF(24) + st r30, r31, GENREG_OFF(30) st r26, r31, GENREG_OFF(31) - + /* save shadow registers (are OLD if error_handler, though) */ ldcr r10, EPSR st r10, r31, REG_OFF(EF_EPSR) @@ -712,7 +705,7 @@ GLOBAL(error_handler) st r10, r31, REG_OFF(EF_SFIP) ldcr r10, SSBR st r10, r31, REG_OFF(EF_SSBR) - stcr r0, SSBR /* won't want shadow bits bothering us later */ + stcr r0, SSBR /* won't want shadow bits bothering us later */ ldcr r10, DMT0 st r10, r31, REG_OFF(EF_DMT0) ldcr r11, DMD0 @@ -733,7 +726,7 @@ GLOBAL(error_handler) st r11, r31, REG_OFF(EF_DMD2) ldcr r12, DMA2 st r12, r31, REG_OFF(EF_DMA2) - + /* shove sr2 into EF_FPLS1 */ ldcr r10, SR2 st r10, r31, REG_OFF(EF_FPLS1) @@ -747,60 +740,61 @@ GLOBAL(error_handler) st r10, r31, REG_OFF(EF_VECTOR) #if 0 /* MVME188 */ -#define IST_REG 0xfff84040 /* interrupt status addr */ +#define IST_REG 0xfff84040 /* interrupt status addr */ /* check if it's a mvme188 */ or.u r10, r0, hi16(_brdtyp) ld r11, r10, lo16(_brdtyp) cmp r10, r11, BRD_188 bb1 ne, r10, 3f - or.u r10, r0, hi16(IST_REG) /* interrupt status register */ + or.u r10, r0, hi16(IST_REG) /* interrupt status register */ ld r11, r10, lo16(IST_REG) - st r11, r31, REG_OFF(EF_MASK) /* put in EF_MASK for regdump */ -#endif /* MVME188 */ + st r11, r31, REG_OFF(EF_MASK) /* put in EF_MASK for regdump */ +#endif /* MVME188 */ /* * Cheap way to enable FPU and start shadowing again. */ -3: ldcr r10, PSR - clr r10, r10, 1 /* enable the FPU */ - clr r10, r10, 1 /* also enable shadowing */ - stcr r10, PSR /* bang */ +3: ldcr r10, PSR + clr r10, r10, 1 /* enable the FPU */ + clr r10, r10, 1 /* and shadowing */ + stcr r10, PSR FLUSH_PIPELINE /* put pointer to regs into r30... r31 will become a simple stack */ or r30, r31, r0 - subu r31, r31, 0x10 /* make some breathing space */ - st r30, r31, 0x0c /* store frame pointer on the st */ - st r30, r31, 0x08 /* store again for the debugger to recognize */ + subu r31, r31, 0x10 /* make some breathing space */ + st r30, r31, 0x0c /* store frame pointer on the st */ + st r30, r31, 0x08 /* store again for the debugger to recognize */ or.u r20, r0, hi16(0x87654321) or r20, r20, lo16(0x87654321) st r20, r31, 0x04 st r20, r31, 0x00 - CALL(_C_LABEL(error_fault), r30, r30) + CALL(_C_LABEL(error_fault), r30, r30) - /* TURN INTERUPTS back on */ - ldcr r1, PSR - clr r1, r1, 1 - stcr r1, PSR - FLUSH_PIPELINE + /* turn interupts back on */ + ldcr r1, PSR + clr r1, r1, 1 + stcr r1, PSR + FLUSH_PIPELINE -GLOBAL(error_loop) bsr _error_loop - /* never returns*/ +GLOBAL(error_loop) + bsr _error_loop + /* never returns*/ /* * The reset exception handler. - * The reset exception is raised when the RST signal is asserted (machine - * is reset), the value of VBR is changed after exceptions are enabled, + * The reset exception is raised when the RST signal is asserted (machine + * is reset), the value of VBR is changed after exceptions are enabled, * or when a jmp, br/bsr to addr 0 (accidents do happen :-) * * To tell the difference, you should check the value of r1 and the valid * bit of SXIP. * - * Upon a real reset, VBR is set to zero (0), so code must be at addr 0 - * to handle it!!! + * Upon a real reset, VBR is set to zero (0), so code must be at addr 0 + * to handle it!!! * - * This is totaly different than _error_handler. Shadowing might or + * This is totaly different than _error_handler. Shadowing might or * might not be on. * R1-R31 could tell u alot about what happend, so we'll save them. * @@ -808,8 +802,8 @@ GLOBAL(error_loop) bsr _error_loop * since they aren't generally used. */ GLOBAL(reset_handler) - /* pick up the slavestack */ - or r26, r0, r31 /* save old stack */ + /* pick up the slavestack */ + or r26, r0, r31 /* save old stack */ or.u r31, r0, hi16(_intstack_end) or r31, r31, lo16(_intstack_end) @@ -817,17 +811,17 @@ GLOBAL(reset_handler) or.u r27, r0, hi16(_intstack) or r27, r27, lo16(_intstack) 1: cmp r28, r27, r31 - bb1 ge, r28, 2f /* branch if at the end of the stack */ + bb1 ge, r28, 2f /* branch if at the end of the stack */ st r0, r0, r27 br.n 1b - addu r27, r27, 4 /* bump up */ + addu r27, r27, 4 /* bump up */ 2: /* stack has been cleared */ /* ensure that stack is 8-byte aligned */ - clr r31, r31, 3<0> /* round down to 8-byte boundary */ + clr r31, r31, 3<0> /* round down to 8-byte boundary */ /* create exception frame on stack */ - subu r31, r31, SIZEOF_EF /* r31 now our E.F. */ + subu r31, r31, SIZEOF_EF /* r31 now our E.F. */ /* save old R31 and other R registers */ st.d r0 , r31, GENREG_OFF(0) @@ -859,7 +853,7 @@ GLOBAL(reset_handler) st r10, r31, REG_OFF(EF_SFIP) ldcr r10, SSBR st r10, r31, REG_OFF(EF_SSBR) - stcr r0, SSBR /* won't want shadow bits bothering us later */ + stcr r0, SSBR /* won't want shadow bits bothering us later */ ldcr r10, DMT0 st r10, r31, REG_OFF(EF_DMT0) @@ -897,19 +891,19 @@ GLOBAL(reset_handler) /* * Cheap way to enable FPU and start shadowing again. */ - ldcr r10, PSR - clr r10, r10, 1 /* enable the FPU */ - clr r10, r10, 1 /* also enable shadowing */ - - stcr r10, PSR /* bang */ + ldcr r10, PSR + clr r10, r10, 1 /* enable the FPU */ + clr r10, r10, 1 /* and shadowing */ + + stcr r10, PSR FLUSH_PIPELINE /* put pointer to regs into r30... r31 will become a simple stack */ or r30, r31, r0 - subu r31, r31, 0x10 /* make some breathing space */ - st r30, r31, 0x0c /* store frame pointer on the st */ - st r30, r31, 0x08 /* store again for the debugger to recognize */ + subu r31, r31, 0x10 /* make some breathing space */ + st r30, r31, 0x0c /* store frame pointer on the st */ + st r30, r31, 0x08 /* store again for the debugger to recognize */ or.u r20, r0, hi16(0x87654321) or r20, r20, lo16(0x87654321) st r20, r31, 0x04 @@ -917,27 +911,28 @@ GLOBAL(reset_handler) CALL(_C_LABEL(error_reset), r30, r30) - /* TURN INTERUPTS back on */ - ldcr r1, PSR - clr r1, r1, 1 - stcr r1, PSR + /* turn interupts back on */ + ldcr r1, PSR + clr r1, r1, 1 + stcr r1, PSR FLUSH_PIPELINE -GLOBAL(error_loop2) bsr _error_loop2 -/* never returns*/ +GLOBAL(error_loop2) + bsr _error_loop2 + /* never returns*/ /* * This is part of baddadr (below). */ ASGLOBAL(ignore_data_exception) - /******************************************************\ - * SR0: pointer to the current thread structure * - * SR1: previous FLAGS reg * - * SR2: free * - * SR3: must presere * - * FLAGS: CPU status flags * - \******************************************************/ - xcr FLAGS, FLAGS, SR1 /* replace SR1, FLAGS */ + /* + * SR0: pointer to the current thread structure + * SR1: previous FLAGS reg + * SR2: free + * SR3: must presere + * FLAGS: CPU status flags + */ + xcr FLAGS, FLAGS, SR1 /* replace SR1, FLAGS */ /* * For more info, see badaddr() below. @@ -952,13 +947,12 @@ ASGLOBAL(ignore_data_exception) /* the "+2" below is to set the VALID bit. */ or.u r2, r0, hi16(badaddr__return_nonzero + 2) or r2, r2, lo16(badaddr__return_nonzero + 2) - stcr r2, SNIP /* Make it the next instruction to execute */ - - addu r2, r2, 4 - stcr r2, SFIP /* and the next one after that, too. */ - stcr r0, SSBR /* make the scoreboard happy. */ -1: + stcr r2, SNIP /* Make it the next instruction to execute */ + addu r2, r2, 4 + stcr r2, SFIP /* and the next one after that, too. */ + stcr r0, SSBR /* make the scoreboard happy. */ +1: /* the following jumps to "badaddr__return_nonzero" in below */ RTE #endif /* m88100 */ @@ -968,14 +962,14 @@ ASGLOBAL(ignore_data_exception) * This is part of baddadr (below). */ ASGLOBAL(m88110_ignore_data_exception) - /******************************************************\ - * SR0: pointer to the current thread structure * - * SR1: previous FLAGS reg * - * SR2: free * - * SR3: must preserve * - * FLAGS: CPU status flags * - \******************************************************/ - xcr FLAGS, FLAGS, SR1 /* replace SR1, FLAGS */ + /* + * SR0: pointer to the current thread structure + * SR1: previous FLAGS reg + * SR2: free + * SR3: must preserve + * FLAGS: CPU status flags + */ + xcr FLAGS, FLAGS, SR1 /* replace SR1, FLAGS */ /* * For more info, see badaddr() below. @@ -989,13 +983,12 @@ ASGLOBAL(m88110_ignore_data_exception) or.u r2, r0, hi16(m88110_badaddr__return_nonzero) or r2, r2, lo16(m88110_badaddr__return_nonzero) - stcr r2, EXIP /* Make it the next instruction to execute */ - - /* the following jumps to "m88110_badaddr__return_nonzero" below */ + stcr r2, EXIP /* Make it the next instruction to execute */ + + /* the following jumps to "m88110_badaddr__return_nonzero" below */ NOP RTE #endif /* M88110 */ - /* * extern boolean_t badaddr(unsigned addr, unsigned len) @@ -1038,14 +1031,14 @@ GLOBAL(badaddr) */ sub r6, r3, 4 bcnd.n ne0, r6, badaddr__maybe_halfword - stcr r5, SR1 + stcr r5, SR1 FLUSH_PIPELINE /* * It's a bad address if it's misaligned. */ - bb1 0, r2, badaddr__return_nonzero - bb1 1, r2, badaddr__return_nonzero + bb1 0, r2, badaddr__return_nonzero + bb1 1, r2, badaddr__return_nonzero /* * The next line will either fault or not. If it faults, execution * will go to: data_access_handler (see above) @@ -1055,57 +1048,57 @@ GLOBAL(badaddr) * * If there is no fault, execution just continues as normal. */ - ld r5, r2, 0 + ld r5, r2, 0 FLUSH_PIPELINE - br.n badaddr__return - or r2, r0, r0 /* indicate a zero (address not bad) return.*/ + br.n badaddr__return + or r2, r0, r0 /* indicate a zero (address not bad) return.*/ badaddr__maybe_halfword: /* More or less like the code for checking a word above */ - sub r6, r3, 2 - bcnd ne0, r6, badaddr__maybe_byte + sub r6, r3, 2 + bcnd ne0, r6, badaddr__maybe_byte /* it's bad if it's misaligned */ - bb1 0, r2, badaddr__return_nonzero + bb1 0, r2, badaddr__return_nonzero FLUSH_PIPELINE - ld.h r5, r2, 0 + ld.h r5, r2, 0 FLUSH_PIPELINE - br.n badaddr__return - or r2, r0, r0 + br.n badaddr__return + or r2, r0, r0 badaddr__maybe_byte: /* More or less like the code for checking a word above */ - sub r6, r3, 1 - bcnd ne0, r6, badaddr__unknown_size + sub r6, r3, 1 + bcnd ne0, r6, badaddr__unknown_size FLUSH_PIPELINE - ld.b r5, r2, 0 + ld.b r5, r2, 0 FLUSH_PIPELINE - br.n badaddr__return - or r2, r0, r0 + br.n badaddr__return + or r2, r0, r0 badaddr__unknown_size: -#ifndef NDEBUG +#ifdef DEBUG data 1: string "bad length (%d) to badaddr() from 0x%x" text - or.u r2, r0, hi16(1b) - or r2, r2, lo16(1b) - or r4, r0, r1 - bsr _C_LABEL(printf) - or.u r2, r0, hi16(1b) - or r2, r2, lo16(1b) - bsr _C_LABEL(panic) + or.u r2, r0, hi16(1b) + or r2, r2, lo16(1b) + or r4, r0, r1 + bsr _C_LABEL(printf) + or.u r2, r0, hi16(1b) + or r2, r2, lo16(1b) + bsr _C_LABEL(panic) /*NOTREACHED*/ #endif ASGLOBAL(badaddr__return_nonzero) - or r2, r0, 1 + or r2, r0, 1 /* fall through to badaddr__return */ ASGLOBAL(badaddr__return) - ldcr r4, SR1 - clr r4, r4, 1 - stcr r4, SR1 + ldcr r4, SR1 + clr r4, r4, 1 + stcr r4, SR1 /* * Restore the PSR to what it was before. @@ -1115,44 +1108,37 @@ ASGLOBAL(badaddr__return) * where we saved it. */ FLUSH_PIPELINE - stcr r8, PSR - jmp r1 + stcr r8, PSR + jmp r1 ASGLOBAL(m88110_badaddr__return_nonzero) - /* - * On mc88110, we possibly took an exception + /* + * On mc88110, we possibly took an exception * and we have to clear DSR after the rte - * instruction clears the EFRZ bit in - * the PSR. + * instruction clears the EFRZ bit in + * the PSR. */ - stcr r0, DSR /* Clear DSR reg on mc88110 */ - stcr r0, DLAR /* Clear DLAR reg on mc88110 */ - br.n badaddr__return_nonzero - stcr r0, DPAR /* Clear DPAR reg on mc88110 */ + stcr r0, DSR /* Clear DSR reg on mc88110 */ + stcr r0, DLAR /* Clear DLAR reg on mc88110 */ + br.n badaddr__return_nonzero + stcr r0, DPAR /* Clear DPAR reg on mc88110 */ -/* -****************************************************************************** -****************************************************************************** -****************************************************************************** -*/ - -#ifdef M88100 +#ifdef M88100 ASGLOBAL(setup_phase_one) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread (if any, null if not) * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: saved copy of exception-time r1 * - * SR3: must be preserved .. may be the exception-time stack * - * r1: return address to calling exception handler * - * FLAGS: CPU status flags * - *************************************************** * - * immediate goal: * - * Decide where we're going to put the exception frame. * - * Might be at the end of R31, SR3, or the thread's * - * pcb. * - \***************************************************************/ - + /* + * SR0: current thread (if any, null if not) + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: saved copy of exception-time r1 + * SR3: must be preserved .. may be the exception-time stack + * r1: return address to calling exception handler + * FLAGS: CPU status flags + * + * immediate goal: + * Decide where we're going to put the exception frame. + * Might be at the end of R31, SR3, or the thread's pcb. + */ + /* Check if we are coming in from a FPU restart exception. If so, the pcb will be in SR3 */ NOP @@ -1167,71 +1153,68 @@ ASGLOBAL(setup_phase_one) /* Interrupt in kernel mode, not FPU restart */ ASGLOBAL(already_on_kernel_stack) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread (if any, null if not) * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: return address to the calling exception handler * - * SR3: must be preserved; may be important for other exceptions * - * FLAGS: CPU status flags * - *************************************************** * - * immediate goal: * - * We're already on the kernel stack, but not having * - * needed to use SR3. We can just make room on the * - * stack (r31) for our exception frame. * - \***************************************************************/ - subu r31, r31, SIZEOF_EF /* r31 now our E.F. */ - st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */ - st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/ - - ldcr r1, SR3 /* save previous SR3 */ + /* + * SR0: current thread (if any, null if not) + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: return address to the calling exception handler + * SR3: must be preserved; may be important for other exceptions + * FLAGS: CPU status flags + * + * immediate goal: + * We're already on the kernel stack, but not having + * needed to use SR3. We can just make room on the + * stack (r31) for our exception frame. + */ + subu r31, r31, SIZEOF_EF /* r31 now our E.F. */ + st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */ + st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/ + + ldcr r1, SR3 /* save previous SR3 */ st r1, r31, REG_OFF(EF_SR3) - addu r1, r31, SIZEOF_EF /* save previous r31 */ + addu r1, r31, SIZEOF_EF /* save previous r31 */ br.n have_pcb - st r1, r31, GENREG_OFF(31) - + st r1, r31, GENREG_OFF(31) ASGLOBAL(use_SR3_pcb) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread (if any, null if not) * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: return address to the calling exception handler * - * SR3: must be preserved; exception-time stack pointer * - * FLAGS: CPU status flags * - *************************************************** * - * immediate goal: * - * An exception occured while enabling the FPU. Since r31 * - * is the user's r31 while enabling the FPU, we had put * - * our pcb pointer into SR3, so make room from * - * there for our stack pointer. * - * We need to check if SR3 is the old stack pointer or the * - * pointer off to the user pcb. If it pointing to the user * - * pcb, we need to pick up the kernel stack. Otherwise * - * we need to allocate a frame upon it. * - * We look at the EPSR to see if it was from user mode * - * Unfortunately, we have no registers free at the moment * - * But we know register 0 in the pcb frame will always be * - * zero, so we can use it as scratch storage. * - * * - * * - \***************************************************************/ - xcr r30, r30, SR3 /* r30 = old exception frame */ - st r1, r30, GENREG_OFF(0) /* free up r1 */ - ld r1, r30, REG_OFF(EF_EPSR) /* get back the epsr */ - bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f /* if user mode */ - ld r1, r30, GENREG_OFF(0) /* restore r1 */ + /* + * SR0: current thread (if any, null if not) + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: return address to the calling exception handler + * SR3: must be preserved; exception-time stack pointer + * FLAGS: CPU status flags + * + * immediate goal: + * An exception occured while enabling the FPU. Since r31 + * is the user's r31 while enabling the FPU, we had put + * our pcb pointer into SR3, so make room from + * there for our stack pointer. + * We need to check if SR3 is the old stack pointer or the + * pointer off to the user pcb. If it pointing to the user + * pcb, we need to pick up the kernel stack. Otherwise + * we need to allocate a frame upon it. + * We look at the EPSR to see if it was from user mode + * Unfortunately, we have no registers free at the moment + * But we know register 0 in the pcb frame will always be + * zero, so we can use it as scratch storage. + */ + xcr r30, r30, SR3 /* r30 = old exception frame */ + st r1, r30, GENREG_OFF(0) /* free up r1 */ + ld r1, r30, REG_OFF(EF_EPSR) /* get back the epsr */ + bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f /* if user mode */ + ld r1, r30, GENREG_OFF(0) /* restore r1 */ /* we were in kernel mode - dump frame upon the stack */ - st r0, r30, GENREG_OFF(0) /* repair old frame */ - subu r30, r30, SIZEOF_EF /* r30 now our E.F. */ - st FLAGS,r30, REG_OFF(EF_FLAGS) /* save flags */ - st r1, r30, GENREG_OFF(1) /* save prev. r1 (now r1 free) */ - - st r31, r30, GENREG_OFF(31) /* save previous r31 */ - or r31, r0, r30 /* make r31 our pointer. */ - addu r30, r30, SIZEOF_EF /* r30 now has previous SR3 */ - st r30, r31, REG_OFF(EF_SR3) /* save previous SR3 */ + st r0, r30, GENREG_OFF(0) /* repair old frame */ + subu r30, r30, SIZEOF_EF /* r30 now our E.F. */ + st FLAGS,r30, REG_OFF(EF_FLAGS) /* save flags */ + st r1, r30, GENREG_OFF(1) /* save prev r1 (now free) */ + + st r31, r30, GENREG_OFF(31) /* save previous r31 */ + or r31, r0, r30 /* make r31 our pointer. */ + addu r30, r30, SIZEOF_EF /* r30 now has previous SR3 */ + st r30, r31, REG_OFF(EF_SR3) /* save previous SR3 */ br.n have_pcb - xcr r30, r30, SR3 /* restore r30 */ + xcr r30, r30, SR3 /* restore r30 */ 1: /* we took an exception while restarting the FPU from user space. * Consequently, we never picked up a stack. Do so now. @@ -1240,59 +1223,59 @@ ASGLOBAL(use_SR3_pcb) or.u r1, r0, hi16(_kstack) ld r1, r1, lo16(_kstack) addu r1, r1, USIZE-SIZEOF_EF - st FLAGS,r1, REG_OFF(EF_FLAGS) /* store flags */ - st r31, r1, GENREG_OFF(31) /* store r31 - now free */ - st r30, r1, REG_OFF(EF_SR3) /* store old SR3 (pcb) */ - or r31, r1, r0 /* make r31 our exception frame pointer */ - ld r1, r30, GENREG_OFF(0) /* restore old r1 */ - st r0, r30, GENREG_OFF(0) /* repair that frame */ - st r1, r31, GENREG_OFF(1) /* store r1 in its proper place */ + st FLAGS,r1, REG_OFF(EF_FLAGS) /* store flags */ + st r31, r1, GENREG_OFF(31) /* store r31 - now free */ + st r30, r1, REG_OFF(EF_SR3) /* store old SR3 (pcb) */ + or r31, r1, r0 /* make r31 our exception fp */ + ld r1, r30, GENREG_OFF(0) /* restore old r1 */ + st r0, r30, GENREG_OFF(0) /* repair that frame */ + st r1, r31, GENREG_OFF(1) /* store r1 */ br.n have_pcb - xcr r30, r30, SR3 /* restore r30 */ + xcr r30, r30, SR3 /* restore r30 */ ASGLOBAL(pickup_stack) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: return address to the calling exception handler * - * SR3: free * - * FLAGS: CPU status flags * - *************************************************** * - * immediate goal: * - * Since we're servicing an exception from user mode, we * - * know that SR3 is free. We use it to free up a temp. * - * register to be used in getting the thread's pcb * - \***************************************************************/ - stcr r31, SR3 /* save previous r31 */ + /* + * SR0: current thread + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: return address to the calling exception handler + * SR3: free + * FLAGS: CPU status flags + * + * immediate goal: + * Since we're servicing an exception from user mode, we + * know that SR3 is free. We use it to free up a temp. + * register to be used in getting the thread's pcb + */ + stcr r31, SR3 /* save previous r31 */ /* switch to the thread's kernel stack. */ or.u r31, r0, hi16(_curpcb) ld r31, r31, lo16(_curpcb) - addu r31, r31, PCB_USER_STATE /* point to user save area */ - st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */ - st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/ - ldcr r1, SR3 /* save previous r31 */ + addu r31, r31, PCB_USER_STATE /* point to user save area */ + st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */ + st r1, r31, GENREG_OFF(1) /* save prev. r1 (now free) */ + ldcr r1, SR3 /* save previous r31 */ st r1, r31, GENREG_OFF(31) - /*FALLTHROUGH */ + /* FALLTHROUGH */ ASGLOBAL(have_pcb) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: return address to the calling exception handler * - * SR3: free * - * r1: free * - * FLAGS: CPU status flags * - * r31: our exception frame * - * Valid in the exception frame: * - * Exception-time r1, r31, FLAGS. * - * Exception SR3, if appropriate. * - *************************************************** * - * immediate goal: * - * Save the shadow registers that need to be saved to * - * the exception frame. * - \***************************************************************/ - stcr TMP, SR3 /* free up TMP, TMP2, TMP3 */ + /* + * SR0: current thread + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: return address to the calling exception handler + * SR3: free + * r1: free + * FLAGS: CPU status flags + * r31: our exception frame + * Valid in the exception frame: + * Exception-time r1, r31, FLAGS. + * Exception SR3, if appropriate. + * + * immediate goal: + * Save the shadow registers that need to be saved to + * the exception frame. + */ + stcr TMP, SR3 /* free up TMP, TMP2, TMP3 */ SAVE_TMP2 SAVE_TMP3 @@ -1303,10 +1286,10 @@ ASGLOBAL(have_pcb) st TMP3, r31, REG_OFF(EF_SNIP) ldcr TMP2, SFIP st TMP2, r31, REG_OFF(EF_SFIP) - /* get and store the cpu number */ - extu TMP, FLAGS, FLAG_CPU_FIELD_WIDTH<0> /* TMP = cpu# */ + /* get and store the cpu number */ + extu TMP, FLAGS, FLAG_CPU_FIELD_WIDTH<0> /* TMP = cpu# */ st TMP, r31, REG_OFF(EF_CPU) - + /* * Save Pbus fault status register from data and inst CMMU. */ @@ -1316,18 +1299,18 @@ ASGLOBAL(have_pcb) ld TMP2, TMP, lo16(_brdtyp) cmp TMP, TMP2, BRD_188 bb1 ne, TMP, 5f - + extu TMP, FLAGS, FLAG_CPU_FIELD_WIDTH<0> /* TMP = cpu# */ - cmp TMP2, TMP, 0x0 /* CPU0 ? */ + cmp TMP2, TMP, 0x0 /* CPU0 ? */ bb1 eq, TMP2, 1f - cmp TMP2, TMP, 0x1 /* CPU1 ? */ + cmp TMP2, TMP, 0x1 /* CPU1 ? */ bb1 eq, TMP2, 2f - cmp TMP2, TMP, 0x2 /* CPU2 ? */ + cmp TMP2, TMP, 0x2 /* CPU2 ? */ bb1 eq, TMP2, 3f - cmp TMP2, TMP, 0x3 /* CPU3 ? */ + cmp TMP2, TMP, 0x3 /* CPU3 ? */ bb1 eq, TMP2, 4f - /* Arrrrg! bad cpu# */ - br Lbadcpupanic + /* Arrrrg! bad cpu# */ + br Lbadcpupanic 1: /* must be CPU0 */ or.u TMP, r0, hi16(VME_CMMU_I0) @@ -1364,9 +1347,9 @@ ASGLOBAL(have_pcb) ld TMP2, TMP, lo16(VME_CMMU_D3) + 0x108 st TMP2, r31, REG_OFF(EF_DPFSR) br pfsr_done -5: +5: #endif /* MVME188 */ - /* it's a single processor SBC */ + /* it's a single processor SBC */ or.u TMP, r0, hi16(SBC_CMMU_I) ld TMP2, TMP, lo16(SBC_CMMU_I) + 0x108 st TMP2, r31, REG_OFF(EF_IPFSR) @@ -1379,32 +1362,32 @@ ASGLOBAL(pfsr_done) ldcr TMP2, SXIP ldcr TMP3, DMT0 st TMP2, r31, REG_OFF(EF_SXIP) - + #if 0 - /* - * The following is a kludge so that - * a core file will have a copy of - * DMT0 so that 'sim' can display it - * correctly. - * After a data fault has been noticed, - * the real EF_DTM0 is cleared, so I need - * to throw this somewhere. - * There's no special reason I chose this - * register (FPIT)... it's just one of many - * for which it causes no pain to do this. - */ +/* + * The following is a kludge so that + * a core file will have a copy of + * DMT0 so that 'sim' can display it + * correctly. + * After a data fault has been noticed, + * the real EF_DTM0 is cleared, so I need + * to throw this somewhere. + * There's no special reason I chose this + * register (FPIT)... it's just one of many + * for which it causes no pain to do this. + */ st TMP3, r31, REG_OFF(EF_FPIT) #endif - /* - * The above shadow registers are obligatory for any and all - * exceptions. Now, if the data access pipeline is not clear, - * we must save the DMx shadow registers, as well as clear - * the appropriate SSBR bits for the destination registers of - * loads or xmems. - */ +/* + * The above shadow registers are obligatory for any and all + * exceptions. Now, if the data access pipeline is not clear, + * we must save the DMx shadow registers, as well as clear + * the appropriate SSBR bits for the destination registers of + * loads or xmems. + */ bb0.n DMT_VALID_BIT, TMP3, DMT_check_finished - st TMP3, r31, REG_OFF(EF_DMT0) + st TMP3, r31, REG_OFF(EF_DMT0) ldcr TMP2, DMT1 ldcr TMP3, DMT2 @@ -1427,16 +1410,16 @@ ASGLOBAL(pfsr_done) st TMP2, r31, REG_OFF(EF_DMD1) st TMP3, r31, REG_OFF(EF_DMD2) - /* - *--------------------------------------------------------------- - * need to clear "appropriate" bits in the SSBR before - * we restart the FPU - */ +/* + * need to clear "appropriate" bits in the SSBR before + * we restart the FPU + */ ASGLOBAL(check_DMT0) ldcr TMP2, DMT0 bb0.n DMT_VALID_BIT, TMP2, DMT_check_finished - stcr r0, DMT0 /* so an exception at fpu_enable doesn't see our DMT0*/ + /* make sure an exception in fpu_enable will not see our DMT0 */ + stcr r0, DMT0 bb1 DMT_LOCK_BIT, TMP2, do_DMT0 bb1 DMT_WRITE_BIT, TMP2, check_DMT1 @@ -1466,7 +1449,7 @@ ASGLOBAL(check_DMT2) ASGLOBAL(do_DMT2_single) extu TMP2, TMP2, DMT_DREG_WIDTH br.n 1f - set TMP2, TMP2, 1<5> + set TMP2, TMP2, 1<5> ASGLOBAL(do_DMT2_double) extu TMP2, TMP2, DMT_DREG_WIDTH @@ -1474,42 +1457,39 @@ ASGLOBAL(do_DMT2_double) 1: clr TMP, TMP, TMP2 ASGLOBAL(DMT_check_finished) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: return address to the calling exception handler * - * SR3: saved TMP * - * r1: free * - * TMP: possibly revised SSBR * - * TMP2: free * - * TMP3: free * - * FLAGS: CPU status flags * - * r31: exception frame * - * Valid in the exception frame: * - * Exception-time r1, r31, FLAGS. * - * Exception-time TMP2, TMP3. * - * Exception-time espr, sfip, snip, sxip. * - * Dmt0. * - * Other data pipeline control registers, if appropriate. * - * Exception SR3, if appropriate. * - \***************************************************************/ + /* + * SR0: current thread + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: return address to the calling exception handler + * SR3: saved TMP + * r1: free + * TMP: possibly revised SSBR + * TMP2: free + * TMP3: free + * FLAGS: CPU status flags + * r31: exception frame + * Valid in the exception frame: + * Exception-time r1, r31, FLAGS. + * Exception-time TMP2, TMP3. + * Exception-time espr, sfip, snip, sxip. + * Dmt0. + * Other data pipeline control registers, if appropriate. + * Exception SR3, if appropriate. + */ ldcr r1, SR2 - jmp r1 /* return to allow the handler to clear more SSBR bits */ + jmp r1 /* allow the handler to clear more SSBR bits */ -#endif /* m88100 */ - -/************************************************************************/ -/************************************************************************/ +#endif /* M88100 */ ASGLOBAL(clear_FPi_ssbr_bit) /* * Clear floatingpont-imprecise ssbr bits. * Also, save appropriate FPU control registers to the E.F. * - * r1: return address to calling exception handler - * TMP : (possibly) revised ssbr - * TMP2 : free - * TMP3 : free + * r1: return address to calling exception handler + * TMP: (possibly) revised ssbr + * TMP2: free + * TMP3: free */ fldcr TMP2, FPSR fldcr TMP3, FPCR @@ -1532,16 +1512,12 @@ ASGLOBAL(clear_FPi_ssbr_bit) */ #define FPIT_SIZE_BIT 10 bb0 FPIT_SIZE_BIT, TMP2, not_double_fpi - extu TMP2, TMP2, 5<0> /* get the reg. */ - set TMP2, TMP2, 1<6> /* set width (width=2 will clear two bits) */ - clr TMP, TMP, TMP2 + extu TMP2, TMP2, 5<0> /* get the reg. */ + set TMP2, TMP2, 1<6> /* set width */ + clr TMP, TMP, TMP2 ASGLOBAL(not_double_fpi) - jmp r1 - - -/************************************************************************/ -/************************************************************************/ + jmp r1 ASGLOBAL(clear_FPp_ssbr_bit) @@ -1549,44 +1525,41 @@ ASGLOBAL(clear_FPp_ssbr_bit) * Clear floating pont precise ssbr bits. * Also, save appropriate FPU control registers to the E.F. * - * r1: return address to calling exception handler - * TMP : (possibly) revised ssbr - * TMP2 : free - * TMP3 : free + * r1: return address to calling exception handler + * TMP: (possibly) revised ssbr + * TMP2: free + * TMP3: free */ - fldcr TMP2, FPSR - fldcr TMP3, FPCR - st TMP2, r31, REG_OFF(EF_FPSR) - st TMP3, r31, REG_OFF(EF_FPCR) - - fldcr TMP3, FPECR - st TMP3, r31, REG_OFF(EF_FPECR) - fldcr TMP2, FPHS1 - fldcr TMP3, FPHS2 - st TMP2, r31, REG_OFF(EF_FPHS1) - st TMP3, r31, REG_OFF(EF_FPHS2) - - fldcr TMP2, FPLS1 - fldcr TMP3, FPLS2 - st TMP2, r31, REG_OFF(EF_FPLS1) - st TMP3, r31, REG_OFF(EF_FPLS2) - - fldcr TMP2, FPPT - st TMP2, r31, REG_OFF(EF_FPPT) -1: + fldcr TMP2, FPSR + fldcr TMP3, FPCR + st TMP2, r31, REG_OFF(EF_FPSR) + st TMP3, r31, REG_OFF(EF_FPCR) -#define FPPT_SIZE_BIT 5 - bb1.n FPPT_SIZE_BIT, TMP2, 2f - extu TMP3, TMP2, 5<0> /* get FP operation dest reg */ - br.n 3f - set TMP3, TMP3, 1<5> /* set size=1 -- clear one bit for "float" */ -2: set TMP3, TMP3, 1<6> /* set size=2 -- clear two bit for "double" */ -3: clr TMP, TMP, TMP3 /* clear bit(s) in ssbr. */ -4: jmp r1 + fldcr TMP3, FPECR + st TMP3, r31, REG_OFF(EF_FPECR) + fldcr TMP2, FPHS1 + fldcr TMP3, FPHS2 + st TMP2, r31, REG_OFF(EF_FPHS1) + st TMP3, r31, REG_OFF(EF_FPHS2) + + fldcr TMP2, FPLS1 + fldcr TMP3, FPLS2 + st TMP2, r31, REG_OFF(EF_FPLS1) + st TMP3, r31, REG_OFF(EF_FPLS2) + + fldcr TMP2, FPPT + st TMP2, r31, REG_OFF(EF_FPPT) +1: +#define FPPT_SIZE_BIT 5 + bb1.n FPPT_SIZE_BIT, TMP2, 2f + extu TMP3, TMP2, 5<0> /* get FP operation dest reg */ + br.n 3f + set TMP3, TMP3, 1<5> /* size=1 - clear one bit for float */ +2: set TMP3, TMP3, 1<6> /* size=2 - clear two bit for double */ +3: clr TMP, TMP, TMP3 /* clear bit(s) in ssbr. */ +4: jmp r1 -/************************************************************************/ -/************************************************************************/ ASGLOBAL(clear_dest_ssbr_bit) /* @@ -1610,33 +1583,33 @@ ASGLOBAL(clear_dest_ssbr_bit) * * At the moment.... * r1: return address to calling exception handler - * TMP : (possibly) revised ssbr - * TMP2 : free - * TMP3 : free + * TMP: (possibly) revised ssbr + * TMP2: free + * TMP3: free */ - - ldcr TMP3, EPSR /* going to check: user or system memory? */ - ldcr TMP2, SXIP /* get the instruction's address */ - bb1.n PSR_SUPERVISOR_MODE_BIT, TMP3, 2f - clr TMP2, TMP2, 2<0> /* get rid of valid and error bits. */ - + + ldcr TMP3, EPSR /* going to check: user or system memory? */ + ldcr TMP2, SXIP /* get the instruction's address */ + bb1.n PSR_SUPERVISOR_MODE_BIT, TMP3, 2f + clr TMP2, TMP2, 2<0> /* get rid of valid and error bits. */ + 1: /* user space load here */ #if ERRATA__XXX_USR NOP - ld.usr TMP2,TMP2, r0 /* get the instruction itself */ + ld.usr TMP2,TMP2, r0 /* get the instruction itself */ NOP NOP NOP br 3f #else br.n 3f - ld.usr TMP2,TMP2, r0 /* get the instruction itself */ + ld.usr TMP2,TMP2, r0 /* get the instruction itself */ #endif 2: /* system space load here */ - ld TMP2, TMP2, r0 /* get the instruction itself */ + ld TMP2, TMP2, r0 /* get the instruction itself */ -3: /* now have the instruction..... */ +3: /* now we have the instruction..... */ /* * Now see if it's a double load * There are three forms of double load [IMM16, scaled, unscaled], @@ -1656,298 +1629,293 @@ ASGLOBAL(clear_dest_ssbr_bit) * } */ /* check the first pattern for ld.d */ - extu TMP3, TMP2, 16<16> /* get the upper 16 bits */ - mask TMP3, TMP3, 0xFC00 /* apply the mask */ - cmp TMP3, TMP3, 0x1000 /* if this is equal, it's a load double */ - bb1 eq, TMP3, misaligned_double - + extu TMP3, TMP2, 16<16> /* get the upper 16 bits */ + mask TMP3, TMP3, 0xFC00 /* apply the mask */ + cmp TMP3, TMP3, 0x1000 /* if equal, it's a load double */ + bb1 eq, TMP3, misaligned_double + /* still could be -- check the second pattern for ld.d */ /* look at the upper 16 bits first */ - extu TMP3, TMP2, 16<16> /* get the upper 16 bits */ - mask TMP3, TMP3, 0xFC00 /* apply the mask */ - cmp TMP3, TMP3, 0xF400 /* if equal, it might be a load double */ - bb1 ne, TMP3, misaligned_single /* not equal, so must be single */ - + extu TMP3, TMP2, 16<16> /* get the upper 16 bits */ + mask TMP3, TMP3, 0xFC00 /* apply the mask */ + cmp TMP3, TMP3, 0xF400 /* if equal, might be a load double */ + bb1 ne, TMP3, misaligned_single /* not equal, must be single */ + /* now look at the lower 16 bits */ - extu TMP3, TMP2, 16<0> /* get the lower 16 bits */ - mask TMP3, TMP3, 0xFCE0 /* apply the mask */ - cmp TMP3, TMP3, 0x1000 /* if this is equal, it's a load double */ - bb1 eq, TMP3, misaligned_double - + extu TMP3, TMP2, 16<0> /* get the lower 16 bits */ + mask TMP3, TMP3, 0xFCE0 /* apply the mask */ + cmp TMP3, TMP3, 0x1000 /* if equal, it's a load double */ + bb1 eq, TMP3, misaligned_double + ASGLOBAL(misaligned_single) - extu TMP2, TMP2, 5<21> /* get the destination register */ - br.n 1f - set TMP2, TMP2, 1<5> /* set size=1 */ + extu TMP2, TMP2, 5<21> /* get the destination register */ + br.n 1f + set TMP2, TMP2, 1<5> /* set size=1 */ ASGLOBAL(misaligned_double) - extu TMP2, TMP2, 5<21> /* get the destination register */ - set TMP2, TMP2, 1<6> /* set size=2 -- clear two bit for "ld.d" */ + extu TMP2, TMP2, 5<21> /* get the destination register */ + set TMP2, TMP2, 1<6> /* set size=2 -- clear two bits */ -1: jmp.n r1 - clr TMP, TMP, TMP2 /* clear bit(s) in ssbr. */ - -/************************************************************************/ -/************************************************************************/ +1: jmp.n r1 + clr TMP, TMP, TMP2 /* clear bit(s) in ssbr. */ #ifdef M88100 ASGLOBAL(setup_phase_two) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: saved return address to calling exception handler * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: free * - * SR3: saved TMP * - * r1: return address to calling exception handler * - * TMP: possibly revised SSBR * - * TMP2: free * - * TMP3: free * - * FLAGS: CPU status flags * - * r31: our exception frame * - * Valid in the exception frame: * - * Exception-time r1, r31, FLAGS. * - * Exception-time TMP2, TMP3. * - * Exception-time espr, sfip, snip, sxip. * - * Exception number (EF_VECTOR). * - * Dmt0 * - * Other data pipeline control registers, if appropriate. * - * FPU control registers, if appropriate. * - * Exception SR3, if appropriate. * - *************************************************** * - * immediate goal: * - * restore the system to the exception-time state (except * - * SR3 will be OUR stack pointer) so that we may resart the FPU. * - \***************************************************************/ - /*stcr r1, SR0*/ /* save return address */ - - stcr TMP, SSBR /* done with SSBR, TMP now free */ - RESTORE_TMP2 /* done with extra temp regs */ - RESTORE_TMP3 /* done with extra temp regs */ - + /* + * SR0: saved return address to calling exception handler + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: free + * SR3: saved TMP + * r1: return address to calling exception handler + * TMP: possibly revised SSBR + * TMP2: free + * TMP3: free + * FLAGS: CPU status flags + * r31: our exception frame + * Valid in the exception frame: + * Exception-time r1, r31, FLAGS. + * Exception-time TMP2, TMP3. + * Exception-time espr, sfip, snip, sxip. + * Exception number (EF_VECTOR). + * Dmt0 + * Other data pipeline control registers, if appropriate. + * FPU control registers, if appropriate. + * Exception SR3, if appropriate. + * + * immediate goal: + * restore the system to the exception-time state (except + * SR3 will be OUR stack pointer) so that we may resart the FPU. + */ + /*stcr r1, SR0*/ /* save return address */ + + stcr TMP, SSBR /* done with SSBR, TMP now free */ + RESTORE_TMP2 /* done with extra temp regs */ + RESTORE_TMP3 /* done with extra temp regs */ + /* Get the current PSR and modify for the rte to enable the FPU */ #if 1 - ldcr TMP, PSR - clr TMP, TMP, 1 /* enable the FPU */ - clr TMP, TMP, 1 /* also enable shadowing */ - stcr TMP, EPSR - + ldcr TMP, PSR + clr TMP, TMP, 1 /* enable the FPU */ + clr TMP, TMP, 1 /* and shadowing */ + stcr TMP, EPSR + /* the "+2" below is to set the VALID_BIT */ - or.u TMP, r0, hi16(fpu_enable +2) - or TMP, TMP, lo16(fpu_enable +2) - stcr TMP, SNIP /* jump to here fpu_enable */ - addu TMP, TMP, 4 - stcr TMP, SFIP /* and then continue after that */ + or.u TMP, r0, hi16(fpu_enable +2) + or TMP, TMP, lo16(fpu_enable +2) + stcr TMP, SNIP /* jump to here fpu_enable */ + addu TMP, TMP, 4 + stcr TMP, SFIP /* and then continue after that */ #else - ldcr TMP, PSR - or.u TMP, TMP, 0x8000 /* set supervisor mode */ - and TMP, TMP, 0xfff7 /* also enable shadowing */ - stcr TMP, EPSR - stcr r0, SXIP /* clear valid bit */ - stcr r0, SNIP /* clear valid bit */ - or.u TMP, r0, hi16(fpu_enable) - or TMP, TMP, lo16(fpu_enable) - or TMP, TMP, 0x2 /* set the VALID_BIT and clear Exception bit */ - stcr TMP, SFIP /* jump to here fpu_enable */ + ldcr TMP, PSR + or.u TMP, TMP, 0x8000 /* set supervisor mode */ + and TMP, TMP, 0xfff7 /* also enable shadowing */ + stcr TMP, EPSR + stcr r0, SXIP /* clear valid bit */ + stcr r0, SNIP /* clear valid bit */ + or.u TMP, r0, hi16(fpu_enable) + or TMP, TMP, lo16(fpu_enable) + or TMP, TMP, 0x2 /* set the VALID_BIT and clear Exception bit */ + stcr TMP, SFIP /* jump to here fpu_enable */ #endif setup_phase_two_cont: - set FLAGS, FLAGS, 1 /* note what we're doing.*/ - xcr FLAGS, FLAGS, SR1 - st r1, r31, REG_OFF(EF_RET) /* save the return address */ - ld r1, r31, GENREG_OFF(1) /* get original r1 */ - - xcr TMP, r31, SR3 /* TMP now restored. R31 now saved in SR3 */ - ld r31, r31, GENREG_OFF(31) /* get original r31 */ - - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread * - * SR1: CPU flags * - * SR2: free * - * SR3: pointer to our exception frame (our stack pointer) * - * r1 through r31: original exception-time values * - * * - * Valid in the exception frame: * - * Exception-time FLAGS. * - * Exception-time espr, sfip, snip, sxip. * - * Exception number (EF_VECTOR). * - * Dmt0 * - * Other data pipeline control registers, if appropriate. * - * FPU control registers, if appropriate. * - * Exception SR3, if appropriate. * - * Held temporarly in the exception frame: * - * Return address to the calling excption handler. * - *************************************************** * - * immediate goal: * - * Do an RTE to restart the fpu and jump to "fpu_enable" * - * Another exception (or exceptions) may be raised in * - * this, which is why FLAG_ENABLING_FPU is set in SR1. * - \***************************************************************/ - - RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */ - + set FLAGS, FLAGS, 1 + xcr FLAGS, FLAGS, SR1 + st r1, r31, REG_OFF(EF_RET) /* save the return address */ + ld r1, r31, GENREG_OFF(1) /* get original r1 */ + + xcr TMP, r31, SR3 /* TMP now restored. R31 now saved in SR3 */ + ld r31, r31, GENREG_OFF(31) /* get original r31 */ + + /* + * SR0: current thread + * SR1: CPU flags + * SR2: free + * SR3: pointer to our exception frame (our stack pointer) + * r1 through r31: original exception-time values + * + * Valid in the exception frame: + * Exception-time FLAGS. + * Exception-time espr, sfip, snip, sxip. + * Exception number (EF_VECTOR). + * Dmt0 + * Other data pipeline control registers, if appropriate. + * FPU control registers, if appropriate. + * Exception SR3, if appropriate. + * Held temporarly in the exception frame: + * Return address to the calling excption handler. + * + * immediate goal: + * Do an RTE to restart the fpu and jump to "fpu_enable" + * Another exception (or exceptions) may be raised in + * this, which is why FLAG_ENABLING_FPU is set in SR1. + */ + + RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */ + ASGLOBAL(fpu_enable) FLUSH_PIPELINE - xcr TMP, TMP, SR3 /* get E.F. pointer */ - st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */ - or r31, TMP, r0 /* transfer E.F. pointer to r31 */ - ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3; maybe important*/ - + xcr TMP, TMP, SR3 /* get E.F. pointer */ + st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */ + or r31, TMP, r0 /* transfer E.F. pointer to r31 */ + ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3 */ + /* make sure that the FLAG_ENABLING_FPU bit is off */ - xcr FLAGS,FLAGS,SR1 - clr FLAGS,FLAGS,1 - xcr FLAGS,FLAGS,SR1 - - xcr TMP, TMP, SR3 /* replace TMP, SR3 */ - + xcr FLAGS,FLAGS,SR1 + clr FLAGS,FLAGS,1 + xcr FLAGS,FLAGS,SR1 + + xcr TMP, TMP, SR3 /* replace TMP, SR3 */ + /* now save all regs to the exception frame. */ - st.d r0 , r31, GENREG_OFF(0) - st.d r2 , r31, GENREG_OFF(2) - st.d r4 , r31, GENREG_OFF(4) - st.d r6 , r31, GENREG_OFF(6) - st.d r8 , r31, GENREG_OFF(8) - st.d r10, r31, GENREG_OFF(10) - st.d r12, r31, GENREG_OFF(12) - st.d r14, r31, GENREG_OFF(14) - st.d r16, r31, GENREG_OFF(16) - st.d r18, r31, GENREG_OFF(18) - st.d r20, r31, GENREG_OFF(20) - st.d r22, r31, GENREG_OFF(22) - st.d r24, r31, GENREG_OFF(24) - st.d r26, r31, GENREG_OFF(26) - st.d r28, r31, GENREG_OFF(28) + st.d r0 , r31, GENREG_OFF(0) + st.d r2 , r31, GENREG_OFF(2) + st.d r4 , r31, GENREG_OFF(4) + st.d r6 , r31, GENREG_OFF(6) + st.d r8 , r31, GENREG_OFF(8) + st.d r10, r31, GENREG_OFF(10) + st.d r12, r31, GENREG_OFF(12) + st.d r14, r31, GENREG_OFF(14) + st.d r16, r31, GENREG_OFF(16) + st.d r18, r31, GENREG_OFF(18) + st.d r20, r31, GENREG_OFF(20) + st.d r22, r31, GENREG_OFF(22) + st.d r24, r31, GENREG_OFF(24) + st.d r26, r31, GENREG_OFF(26) + st.d r28, r31, GENREG_OFF(28) #ifdef JEFF_DEBUG /* mark beginning of frame with notable value */ - or.u r20, r0, hi16(0x12345678) - or r20, r20, lo16(0x12345678) - st r20, r31, GENREG_OFF(0) + or.u r20, r0, hi16(0x12345678) + or r20, r20, lo16(0x12345678) + st r20, r31, GENREG_OFF(0) #endif /* get and save IPL */ bsr _C_LABEL(getipl) st r2, r31, REG_OFF(EF_MASK) - - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread * - * SR1: free * - * SR2: free * - * SR3: previous exception-time SR3 * - * r1: return address to the calling exception handler * - * r2 through r30: free * - * r31: our exception frame * - * * - * Valid in the exception frame: * - * Exception-time r0 through r31. * - * Exception-time FLAGS. * - * Exception-time espr, sfip, snip, sxip. * - * Exception number (EF_VECTOR). * - * Dmt0 * - * Other data pipeline control registers, if appropriate. * - * FPU control registers, if appropriate. * - * Exception SR3, if appropriate. * - *************************************************** * - * immediate goal: * - * Pick up a stack if we came in from user mode. Put * - * A copy of the exception frame pointer into r30 * - * bump the stack a doubleword and write the exception * - * frame pointer. * - * if not an interrupt exception, * - * Turn on interrupts and service any outstanding * - * data access exceptions. * - * Return to calling exception handler to * - * service the exception. * - \***************************************************************/ - + + /* + * SR0: current thread + * SR1: free + * SR2: free + * SR3: previous exception-time SR3 + * r1: return address to the calling exception handler + * r2 through r30: free + * r31: our exception frame + * + * Valid in the exception frame: + * Exception-time r0 through r31. + * Exception-time FLAGS. + * Exception-time espr, sfip, snip, sxip. + * Exception number (EF_VECTOR). + * Dmt0 + * Other data pipeline control registers, if appropriate. + * FPU control registers, if appropriate. + * Exception SR3, if appropriate. + * + * immediate goal: + * Pick up a stack if we came in from user mode. + * Put a copy of the exception frame pointer into r30 + * Bump the stack a doubleword and write the exception frame pointer. + * If not an interrupt exception, turn on interrupts and service any + * outstanding data access exceptions. + * Return to calling exception handler to service the exception. + */ + /* * If it's not the interrupt exception, enable interrupts and * take care of any data access exceptions...... */ -#if INTSTACK +#ifdef INTSTACK /* * If interrupt exception, switch to interrupt stack if not * already there. Else, switch to kernel stack. */ #endif - or r30, r0, r31 /* get a copy of the e.f. pointer */ - ld r2, r31, REG_OFF(EF_EPSR) - bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* If in kernel mode */ - -#if INTSTACK - ld r3, r31, REG_OFF(EF_VECTOR) - cmp r3, r3, 1 /* is interrupt ? */ - bb0 eq, r3, 2f - or.u r31, r0, hi16(_intstack_end) /* swith to int stack */ - or r31, r31, lo16(_intstack_end) - br 3f + or r30, r0, r31 /* get a copy of the e.f. pointer */ + ld r2, r31, REG_OFF(EF_EPSR) + bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* if in kernel mode */ + +#ifdef INTSTACK + ld r3, r31, REG_OFF(EF_VECTOR) + cmp r3, r3, 1 /* is interrupt ? */ + bb0 eq, r3, 2f + or.u r31, r0, hi16(_intstack_end) /* switch to int stack */ + or r31, r31, lo16(_intstack_end) + br 3f 2: #endif - or.u r31, r0, hi16(_kstack) - ld r31, r31, lo16(_kstack) - addu r31, r31, USIZE /* point at proper end */ - br 3f + or.u r31, r0, hi16(_kstack) + ld r31, r31, lo16(_kstack) + addu r31, r31, USIZE /* point at proper end */ + br 3f 1: -#if INTSTACK - ld r3, r31, REG_OFF(EF_VECTOR) - cmp r3, r3, 1 /* is interrupt ? */ - bb0 eq, r3, 3f /* no, we will stay on kern stack */ - or.u r31, r0, hi16(_intstack_end) /* swith to int stack */ - or r31, r31, lo16(_intstack_end) -#endif /* INTSTACK */ +#ifdef INTSTACK + ld r3, r31, REG_OFF(EF_VECTOR) + cmp r3, r3, 1 /* is interrupt ? */ + bb0 eq, r3, 3f /* no, we will stay on kern stack */ + or.u r31, r0, hi16(_intstack_end) /* switch to int stack */ + or r31, r31, lo16(_intstack_end) +#endif /* This label is here for debugging */ -exception_handler_has_ksp: global exception_handler_has_ksp +exception_handler_has_ksp: +global exception_handler_has_ksp 3: /* * here - r30 holds a pointer to the exception frame. * r31 is a pointer to the kernel stack/interrupt stack. - */ - subu r31, r31, 8 /* make some breathing space */ - st r30, r31, 0 /* store frame pointer on the stack */ -#if DDB - st r30, r31, 4 /* store it again for the debugger to recognize */ + */ + subu r31, r31, 8 /* make some breathing space */ + st r30, r31, 0 /* store frame pointer on the stack */ +#ifdef DDB + st r30, r31, 4 /* store it for the debugger to recognize */ #endif /* DDB */ - ld r2, r30, REG_OFF(EF_VECTOR) - bcnd.n eq0, r2, return_to_calling_exception_handler /* is error */ - ld r14, r30, REG_OFF(EF_RET) - cmp r3, r2, 1 /* interrupt is exception #1 ;Is an interrupt? */ - bb1.n eq, r3, return_to_calling_exception_handler /* skip if so */ - -#if DDB - cmp r3, r2, 130 /* DDB break exception */ - bb1.n eq, r3, return_to_calling_exception_handler - cmp r3, r2, 132 /* DDB entry exception */ - bb1.n eq, r3, return_to_calling_exception_handler + ld r2, r30, REG_OFF(EF_VECTOR) + bcnd.n eq0, r2, return_to_calling_exception_handler /* is error */ + ld r14, r30, REG_OFF(EF_RET) + cmp r3, r2, 1 /* is an interrupt? */ + bb1.n eq, r3, return_to_calling_exception_handler /* skip if so */ + +#ifdef DDB + cmp r3, r2, 130 /* DDB break exception */ + bb1.n eq, r3, return_to_calling_exception_handler + cmp r3, r2, 132 /* DDB entry exception */ + bb1.n eq, r3, return_to_calling_exception_handler #endif - ldcr r2, PSR - clr r2, r2, 1 /* enable interrupts */ - stcr r2, PSR -#if DDB + /* enable interrupts */ + ldcr r2, PSR + clr r2, r2, 1 + stcr r2, PSR +#ifdef DDB FLUSH_PIPELINE #endif /* service any outstanding data pipeline stuff - - check dmt0 anything outstanding?*/ + - check dmt0 anything outstanding? */ - ld r3, r30, REG_OFF(EF_DMT0) - bb0 DMT_VALID_BIT, r3, return_to_calling_exception_handler + ld r3, r30, REG_OFF(EF_DMT0) + bb0 DMT_VALID_BIT, r3, return_to_calling_exception_handler /* - r30 can be clobbered by calls. So stuff its value into a - preserved register, say r15. R14 is in use (see return_to_... below). + * r30 can be clobbered by calls. So stuff its value into a preserved + * register, say r15. R14 is in use (see return_to_... below). */ - or r15, r0, r30 + or r15, r0, r30 CALL(_C_LABEL(m88100_trap), T_DATAFLT, r15) CALL(_data_access_emulation, r15, r0) - /* restore it... */ - or r30, r0, r15 + /* restore it... */ + or r30, r0, r15 /* clear the dmt0 word in the E.F */ - st r0, r30, REG_OFF(EF_DMT0) + st r0, r30, REG_OFF(EF_DMT0) ASGLOBAL(return_to_calling_exception_handler) - jmp r14 /* loaded above */ -#endif /* m88100 */ - + jmp r14 /* loaded above */ +#endif /* M88100 */ /* * proc_trampoline. @@ -1962,16 +1930,16 @@ ENTRY(proc_trampoline) ld r1,r31,0 /* load func */ ld r2,r31,4 /* load proc pointer */ jsr.n r1 - subu r31,r31,40 /* create stack space for function */ + subu r31,r31,40 /* create stack space for function */ addu r31,r31,48 /* stack space above + ksigframe */ ld r1, r31,0 /* load pc */ - ld r2, r31,4 /* & proc pointer from switch frame */ + ld r2, r31,4 /* & proc pointer from switch frame */ jsr.n r1 - addu r31,r31,8 + addu r31,r31,8 bsr _C_LABEL(panic) /* - * proc_do_uret + * proc_do_uret * this is called as proc_do_uret(proc) from proc_trampoline(). This function * loads r31 with a pointer to the trap frame for the given proc and calls * return_from_exception_handler which loads all the registers and does an @@ -2001,33 +1969,33 @@ ASGLOBAL(return_from_exception_handler) * and thread_bootstrap in luna88k/locore.c. * */ -#ifdef M88110 +#ifdef M88110 or.u r2, r0, hi16(_C_LABEL(cputyp)) ld r3, r2, lo16(_C_LABEL(cputyp)) cmp r2, r3, CPU_88110 - bb1 eq, r2, m88110_return_code -#endif + bb1 eq, r2, m88110_return_code +#endif #ifdef M88100 -#define FPTR r14 - ld FPTR, r31, 0 /* grab exception frame pointer */ +#define FPTR r14 + ld FPTR, r31, 0 /* grab exception frame pointer */ ld r3, FPTR, REG_OFF(EF_DMT0) - bb0 DMT_VALID_BIT, r3, check_ast /*[Oh well, nothing to do here] */ + bb0 DMT_VALID_BIT, r3, check_ast #if 1 /* * This might happen for non-interrupts If the user sets DMT0 - * in an exception handler......... + * in an exception handler... */ ld r2, FPTR, REG_OFF(EF_VECTOR) - cmp r2, r2, 1 /* interrupt is exception #1 ; Is an interrupt? */ + cmp r2, r2, 1 /* is an interrupt? */ bb1 eq, r2, 1f or.u r4, r0, hi16(2f) or r4, r4, lo16(2f) -#if DDB +#ifdef DDB CALL(_C_LABEL(db_printf), r4, r0) tb0 0, r0, 132 #endif - br 1f + br 1f data 2: string "OOPS: DMT0 not zero and not interrupt.\n\000" align 8 @@ -2038,42 +2006,42 @@ ASGLOBAL(return_from_exception_handler) * If it's the interrupt exception, enable interrupt. * Take care of any data access exception...... 90/8/15 add by yama */ - + /* * Is it ever possible to have interrupt exception while EPSR has * it disabled? I don't think so.. XXX nivas */ - ld r2, FPTR, REG_OFF(EF_VECTOR) - cmp r2, r2, 1 /* interrupt is exception #1 ; Is an interrupt? */ - bb1 ne, r2, 1f /* If not so, skip */ + ld r2, FPTR, REG_OFF(EF_VECTOR) + cmp r2, r2, 1 /* is an interrupt? */ + bb1 ne, r2, 1f /* If not so, skip */ /* if EPSR has interrupts disabled, skip also */ - ld r2, FPTR, REG_OFF(EF_EPSR) - bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if disabled */ - ldcr r2, PSR - clr r2, r2, 1 /* enable interrupts */ + ld r2, FPTR, REG_OFF(EF_EPSR) + bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if disabled */ + ldcr r2, PSR + clr r2, r2, 1 /* enable interrupts */ FLUSH_PIPELINE - stcr r2, PSR + stcr r2, PSR 1: - ld r2, FPTR, REG_OFF(EF_DMT0) - bb0 DMT_VALID_BIT, r2, 2f + ld r2, FPTR, REG_OFF(EF_DMT0) + bb0 DMT_VALID_BIT, r2, 2f /* * if there happens to be a data fault that hasn't been serviced yet, * go off and service that... */ CALL(_C_LABEL(m88100_trap), T_DATAFLT, r30) - CALL(_C_LABEL(data_access_emulation), r30, r0) /* really only 2 args */ + CALL(_C_LABEL(data_access_emulation), r30, r0) /* really only 2 args */ /* clear the dmt0 word in the E.F. */ - st r0 , FPTR, REG_OFF(EF_DMT0) + st r0 , FPTR, REG_OFF(EF_DMT0) 2: - br check_ast -#endif /* m88100 */ + br check_ast +#endif /* M88100 */ #ifdef M88110 ASLOCAL(m88110_return_code) -#define FPTR r14 - ld FPTR, r31, 0 /* grab exception frame pointer */ +#define FPTR r14 + ld FPTR, r31, 0 /* grab exception frame pointer */ /* * If it's the interrupt exception, enable interrupt. @@ -2083,25 +2051,25 @@ ASLOCAL(m88110_return_code) /* * Is it ever possible to have interrupt exception while EPSR has * it disabled? I don't think so.. XXX nivas - * + * * On mc88110, you can. The NMI interrupt. aka ABORT. XXX smurph */ ld r2, FPTR, REG_OFF(EF_VECTOR) - cmp r2, r2, 1 /* Is it an interrupt? */ - bb1 ne, r2, 1f /* If not, skip */ + cmp r2, r2, 1 /* Is it an interrupt? */ + bb1 ne, r2, 1f /* If not, skip */ /* if EPSR has interrupts disabled, skip also */ ld r2, FPTR, REG_OFF(EF_EPSR) - bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if disabled */ + bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if disabled */ ldcr r2, PSR - clr r2, r2, 1 /* enable interrupts */ + clr r2, r2, 1 /* enable interrupts */ FLUSH_PIPELINE stcr r2, PSR 1: - br 2f /* temp XXX smurph */ + br 2f /* temp XXX smurph */ ld r2, FPTR, REG_OFF(EF_VECTOR) - cmp r2, r2, 3 /* Is it a data access exception? */ - bb1 ne, r2, 2f /* If not, skip */ + cmp r2, r2, 3 /* Is it a data access exception? */ + bb1 ne, r2, 2f /* If not, skip */ /* * if there happens to be a data fault that hasn't been serviced yet, @@ -2122,37 +2090,36 @@ ASLOCAL(m88110_return_code) * If returning to user land, look for ASTs */ ASLOCAL(check_ast) + ld r2, FPTR, REG_OFF(EF_EPSR) /* get pre-exception PSR */ + bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if ints off */ + ld r2, FPTR, REG_OFF(EF_MASK) /* get pre-exception ipl */ + bcnd ne0, r2, 1f /* can't do softint's */ - ld r2, FPTR, REG_OFF(EF_EPSR) /* get pre-exception PSR */ - bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if ints off */ - ld r2, FPTR, REG_OFF(EF_MASK) /* get pre-exception ipl */ - bcnd ne0, r2, 1f /* can't do softint's */ - subu r31, r31, 32 - bsr.n _C_LABEL(setipl) - or r2,r0,1 - /* at ipl 1 now */ + bsr.n _C_LABEL(setipl) + or r2,r0,1 + /* at ipl 1 now */ addu r31, r31, 32 - bsr _C_LABEL(dosoftint) + bsr _C_LABEL(dosoftint) /* is this needed? we are going to restore the ipl below XXX nivas */ subu r31, r31, 32 - bsr.n _C_LABEL(setipl) - or r2,r0,0 /* ints are enabled */ + bsr.n _C_LABEL(setipl) + or r2,r0,0 /* ints are enabled */ addu r31, r31, 32 /* at ipl 0 now */ 1: - ld r2, FPTR, REG_OFF(EF_EPSR) /* get pre-exception PSR */ - bb1 PSR_SUPERVISOR_MODE_BIT, r2, no_ast /*skip if in system mode */ - - /* should assert here - not in user mode with ints off XXX nivas */ - /* get and check want_ast */ - or.u r2, r0, hi16(_C_LABEL(want_ast)) - ld r3, r2, lo16(_C_LABEL(want_ast)) - bcnd eq0, r3, no_ast - - /* - * trap(AST,...) will service ast's. - */ + ld r2, FPTR, REG_OFF(EF_EPSR) /* get pre-exception PSR */ + bb1 PSR_SUPERVISOR_MODE_BIT, r2, no_ast /*skip if system mode */ + + /* should assert here - not in user mode with ints off XXX nivas */ + /* get and check want_ast */ + or.u r2, r0, hi16(_C_LABEL(want_ast)) + ld r3, r2, lo16(_C_LABEL(want_ast)) + bcnd eq0, r3, no_ast + + /* + * trap(AST,...) will service ast's. + */ #if defined(M88110) && defined(M88100) or.u r2, r0, hi16(_C_LABEL(cputyp)) ld r3, r2, lo16(_C_LABEL(cputyp)) @@ -2160,105 +2127,103 @@ ASLOCAL(check_ast) bb0 eq, r2, 2f #endif #if defined(M88110) - CALL(_C_LABEL(m88110_trap), T_ASTFLT, FPTR) + CALL(_C_LABEL(m88110_trap), T_ASTFLT, FPTR) #endif #if defined(M88110) && defined(M88100) br no_ast 2: #endif #ifdef M88100 - CALL(_C_LABEL(m88100_trap), T_ASTFLT, FPTR) + CALL(_C_LABEL(m88100_trap), T_ASTFLT, FPTR) #endif ASLOCAL(no_ast) + /* disable interrupts */ + ldcr r1, PSR + set r1, r1, 1 + FLUSH_PIPELINE + stcr r1, PSR - /* disable interrupts */ - ldcr r1, PSR - set r1, r1, 1 - FLUSH_PIPELINE - stcr r1, PSR - - /* now ready to return....*/ + /* now ready to return....*/ subu r31, r31, 40 - bsr.n _C_LABEL(setipl) - ld r2, FPTR, REG_OFF(EF_MASK) /* get pre-exception ipl */ + bsr.n _C_LABEL(setipl) + ld r2, FPTR, REG_OFF(EF_MASK) /* get pre-exception ipl */ addu r31, r31, 40 - - /* - * Transfer the frame pointer to r31, since we no longer need a stack. - * No page faults here, and interrupts are disabled. - */ - or r31, r0, FPTR - /* restore r1 later */ - ld.d r2 , r31, GENREG_OFF(2) - ld.d r4 , r31, GENREG_OFF(4) - ld.d r6 , r31, GENREG_OFF(6) - ld.d r8 , r31, GENREG_OFF(8) - ld.d r10, r31, GENREG_OFF(10) - ld.d r12, r31, GENREG_OFF(12) - ld.d r14, r31, GENREG_OFF(14) - ld.d r16, r31, GENREG_OFF(16) - ld.d r18, r31, GENREG_OFF(18) - ld.d r20, r31, GENREG_OFF(20) - ld.d r22, r31, GENREG_OFF(22) - ld.d r24, r31, GENREG_OFF(24) - ld.d r26, r31, GENREG_OFF(26) - ld.d r28, r31, GENREG_OFF(28) - /* restore r1, r30, r31 later */ - - /* disable shadowing */ - ldcr r1, PSR - set r1, r1, 1 - FLUSH_PIPELINE - stcr r1, PSR + + /* + * Transfer the frame pointer to r31, since we no longer need a stack. + * No page faults here, and interrupts are disabled. + */ + or r31, r0, FPTR + /* restore r1 later */ + ld.d r2 , r31, GENREG_OFF(2) + ld.d r4 , r31, GENREG_OFF(4) + ld.d r6 , r31, GENREG_OFF(6) + ld.d r8 , r31, GENREG_OFF(8) + ld.d r10, r31, GENREG_OFF(10) + ld.d r12, r31, GENREG_OFF(12) + ld.d r14, r31, GENREG_OFF(14) + ld.d r16, r31, GENREG_OFF(16) + ld.d r18, r31, GENREG_OFF(18) + ld.d r20, r31, GENREG_OFF(20) + ld.d r22, r31, GENREG_OFF(22) + ld.d r24, r31, GENREG_OFF(24) + ld.d r26, r31, GENREG_OFF(26) + ld.d r28, r31, GENREG_OFF(28) + /* restore r1, r30, r31 later */ + + /* disable shadowing */ + ldcr r1, PSR + set r1, r1, 1 + FLUSH_PIPELINE + stcr r1, PSR /* reload the control regs*/ #ifdef M88110 - or.u r1, r0, hi16(_C_LABEL(cputyp)) + or.u r1, r0, hi16(_C_LABEL(cputyp)) ld r30, r1, lo16(_C_LABEL(cputyp)) cmp r1, r30, CPU_88110 bb1 ne, r1, 1f - /* mc88110 needs the EXIP */ - ld r30, r31, REG_OFF(EF_ENIP) - ld r1, r31, REG_OFF(EF_EXIP) - stcr r30, ENIP - stcr r1, EXIP - br 2f + /* mc88110 needs the EXIP */ + ld r30, r31, REG_OFF(EF_ENIP) + ld r1, r31, REG_OFF(EF_EXIP) + stcr r30, ENIP + stcr r1, EXIP + br 2f 1: -#endif - st r0, r31, REG_OFF(EF_IPFSR) - st r0, r31, REG_OFF(EF_DPFSR) - - /* - * Note: no need to restore the SXIP. - * When the "rte" causes execution to continue - * first with the instruction pointed to by the NIP - * and then the FIP. - * - * See MC88100 Risc Processor User's Manual, 2nd Edition, - * section 6.4.3.1.2-4 - */ - ld r30, r31, REG_OFF(EF_SNIP) - ld r1, r31, REG_OFF(EF_SFIP) - stcr r0, SSBR - stcr r30, SNIP - stcr r1, SFIP - -2: - ld r30, r31, REG_OFF(EF_EPSR) - ld r1, r31, REG_OFF(EF_MODE) - stcr r30, EPSR - - /* Now restore r1, r30, and r31 */ - ld r1, r31, GENREG_OFF(1) - ld.d r30, r31, GENREG_OFF(30) - - RTE - -#ifdef M88110 -/*#########################################################################*/ -/*#### THE ACTUAL EXCEPTION HANDLER ENTRY POINTS - MVME197 ################*/ -/*#########################################################################*/ +#endif + st r0, r31, REG_OFF(EF_IPFSR) + st r0, r31, REG_OFF(EF_DPFSR) + + /* + * Note: no need to restore the SXIP. + * When the "rte" causes execution to continue + * first with the instruction pointed to by the NIP + * and then the FIP. + * + * See MC88100 Risc Processor User's Manual, 2nd Edition, + * section 6.4.3.1.2-4 + */ + ld r30, r31, REG_OFF(EF_SNIP) + ld r1, r31, REG_OFF(EF_SFIP) + stcr r0, SSBR + stcr r30, SNIP + stcr r1, SFIP +2: + ld r30, r31, REG_OFF(EF_EPSR) + ld r1, r31, REG_OFF(EF_MODE) + stcr r30, EPSR + + /* Now restore r1, r30, and r31 */ + ld r1, r31, GENREG_OFF(1) + ld.d r30, r31, GENREG_OFF(30) + + RTE + +#ifdef M88110 +/* + * MVME197 exception handlers + */ /* unknown exception handler */ GLOBAL(m88110_unknown_handler) @@ -2300,7 +2265,7 @@ GLOBAL(m88110_unimplemented_handler) /* privilege exception handler */ GLOBAL(m88110_privilege_handler) - PREP2("privilege", 6, DEBUG_PRIVILEGE_BIT, No_SSBR_Stuff, No_Precheck) + PREP2("privilege", 6, DEBUG_PRIVILEGE_BIT, No_SSBR_Stuff, No_Precheck) CALL(_C_LABEL(m88110_trap), T_PRIVINFLT, r30) DONE(DEBUG_PRIVILEGE_BIT) @@ -2328,7 +2293,7 @@ GLOBAL(m88110_overflow_handler) /* Floating-point precise handler */ GLOBAL(m88110_fp_precise_handler) PREP2("FPU precise", 114, DEBUG_FPp_BIT, No_SSBR_Stuff, No_Precheck) - CALL(_m88110_Xfp_precise, r0, r30) /* call fp_precise(??, exception_frame)*/ + CALL(_m88110_Xfp_precise, r0, r30) DONE(DEBUG_FPp_BIT) /* MVME197 non-maskable interrupt handler (ABORT button) */ @@ -2358,15 +2323,15 @@ GLOBAL(m88110_inst_atc_miss) /* All standard system calls. */ GLOBAL(m88110_syscall_handler) PREP2("syscall", 128, DEBUG_SYSCALL_BIT, No_SSBR_Stuff, No_Precheck) - ld r13, r30, GENREG_OFF(13) - CALL(_m88110_syscall, r13, r30) /* system call no. is in r13 */ + ld r13, r30, GENREG_OFF(13) + CALL(_m88110_syscall, r13, r30) /* system call no. is in r13 */ DONE(DEBUG_SYSCALL_BIT) /* trap 496 comes here */ GLOBAL(m88110_bugtrap) PREP2("bugsyscall", 496, DEBUG_BUGCALL_BIT, No_SSBR_Stuff, No_Precheck) - ld r9, r30, GENREG_OFF(9) - CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */ + ld r9, r30, GENREG_OFF(9) + CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */ DONE(DEBUG_BUGCALL_BIT) GLOBAL(m88110_sigsys) @@ -2389,7 +2354,7 @@ GLOBAL(m88110_userbpt) CALL(_C_LABEL(m88110_trap), T_USERBPT, r30) DONE(DEBUG_SIGTRAP_BIT) -#if DDB +#ifdef DDB GLOBAL(m88110_break) PREP2("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck) CALL(_C_LABEL(m88110_trap), T_KDB_BREAK, r30) @@ -2404,7 +2369,7 @@ GLOBAL(m88110_entry) PREP2("kdb", 132, DEBUG_KDB_BIT, No_SSBR_Stuff, No_Precheck) CALL(_C_LABEL(m88110_trap), T_KDB_ENTRY, r30) DONE(DEBUG_KDB_BIT) -#else /* else not DDB */ +#else GLOBAL(m88110_break) PREP2("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck) CALL(_C_LABEL(m88110_trap), T_UNKNOWNFLT, r30) @@ -2419,10 +2384,8 @@ GLOBAL(m88110_entry) PREP2("unknown", 132, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck) CALL(_C_LABEL(m88110_trap), T_UNKNOWNFLT, r30) DONE(DEBUG_KDB_BIT) -#endif /* DDB */ - +#endif -/*--------------------------------------------------------------------------*/ /* * The error exception handler. * The error exception is raised when any other non-trap exception is raised @@ -2435,22 +2398,22 @@ GLOBAL(m88110_entry) * since they aren't generally used. */ GLOBAL(m88110_error_handler) - xcr r2, r2, SRX + xcr r2, r2, SRX or r2, r0, 10 - stcr r2, SR0 + stcr r2, SR0 br.n _C_LABEL(m88110_fatal) - xcr r2, r2, SRX + xcr r2, r2, SRX /* * The reset exception handler. - * The reset exception is raised when the RST signal is asserted (machine - * is reset), the value of VBR is changed after exceptions are enabled, + * The reset exception is raised when the RST signal is asserted (machine + * is reset), the value of VBR is changed after exceptions are enabled, * or when a jmp, br/bsr to addr 0 (accidents do happen :-) * - * Upon a real reset, VBR is set to zero (0), so code must be at addr 0 - * to handle it!!! + * Upon a real reset, VBR is set to zero (0), so code must be at addr 0 + * to handle it!!! * - * This is totaly different than _error_handler. Shadowing might or + * This is totaly different than _error_handler. Shadowing might or * might not be on. * R1-R31 could tell u alot about what happend, so we'll save them. * @@ -2458,11 +2421,11 @@ GLOBAL(m88110_error_handler) * since they aren't generally used. */ GLOBAL(m88110_reset_handler) - stcr r0, SR0 - /* FALL THROUGH */ + stcr r0, SR0 + /* FALLTHROUGH */ GLOBAL(m88110_fatal) - /* pick up the slavestack */ - or r26, r0, r31 /* save old stack */ + /* pick up the slavestack */ + or r26, r0, r31 /* save old stack */ or.u r31, r0, hi16(_intstack_end) or r31, r31, lo16(_intstack_end) @@ -2470,43 +2433,43 @@ GLOBAL(m88110_fatal) or.u r27, r0, hi16(_intstack) or r27, r27, lo16(_intstack) 1: cmp r28, r27, r31 - bb1 ge, r28, 2f /* branch if at the end of the stack */ + bb1 ge, r28, 2f /* branch if at the end of the stack */ st r0, r0, r27 br.n 1b - addu r27, r27, 4 /* bump up */ + addu r27, r27, 4 /* bump up */ 2: /* stack has been cleared */ /* ensure that stack is 8-byte aligned */ - clr r31, r31, 3<0> /* round down to 8-byte boundary */ + clr r31, r31, 3<0> /* round down to 8-byte boundary */ /* create exception frame on stack */ - subu r31, r31, SIZEOF_EF /* r31 now our E.F. */ + subu r31, r31, SIZEOF_EF /* r31 now our E.F. */ /* save old R31 and other R registers */ - st.d r0 , r31, GENREG_OFF(0) - st.d r2 , r31, GENREG_OFF(2) - st.d r4 , r31, GENREG_OFF(4) - st.d r6 , r31, GENREG_OFF(6) - st.d r8 , r31, GENREG_OFF(8) - st.d r10, r31, GENREG_OFF(10) - st.d r12, r31, GENREG_OFF(12) - st.d r14, r31, GENREG_OFF(14) - st.d r16, r31, GENREG_OFF(16) - st.d r18, r31, GENREG_OFF(18) - st.d r20, r31, GENREG_OFF(20) - st.d r22, r31, GENREG_OFF(22) - st.d r24, r31, GENREG_OFF(24) - st r30, r31, GENREG_OFF(30) + st.d r0 , r31, GENREG_OFF(0) + st.d r2 , r31, GENREG_OFF(2) + st.d r4 , r31, GENREG_OFF(4) + st.d r6 , r31, GENREG_OFF(6) + st.d r8 , r31, GENREG_OFF(8) + st.d r10, r31, GENREG_OFF(10) + st.d r12, r31, GENREG_OFF(12) + st.d r14, r31, GENREG_OFF(14) + st.d r16, r31, GENREG_OFF(16) + st.d r18, r31, GENREG_OFF(18) + st.d r20, r31, GENREG_OFF(20) + st.d r22, r31, GENREG_OFF(22) + st.d r24, r31, GENREG_OFF(24) + st r30, r31, GENREG_OFF(30) st r26, r31, GENREG_OFF(31) /* vector is put in SRO (either 0 or 10 at this point) */ ldcr r10, SR0 - st r10, r31, REG_OFF(EF_VECTOR) - cmp r10, r10, 0 /* Is it the reset exception? */ - bb1.n ne, r10, 1f /* If not, skip. */ - + st r10, r31, REG_OFF(EF_VECTOR) + cmp r10, r10, 0 /* is it the reset exception? */ + bb1.n ne, r10, 1f /* if not, skip */ + /* save shadow registers (are OLD if error_handler, though) */ - ldcr r10, EPSR + ldcr r10, EPSR st r10, r31, REG_OFF(EF_EPSR) ldcr r10, EXIP st r10, r31, REG_OFF(EF_EXIP) @@ -2526,9 +2489,9 @@ GLOBAL(m88110_fatal) st r10, r31, REG_OFF(EF_IPAR) ldcr r10, SR1 br.n 2f - st r10, r31, REG_OFF(EF_MODE) + st r10, r31, REG_OFF(EF_MODE) -1: +1: /* retrieve saved shadow registers for error_handler, though) */ or.u r30, r0, hi16(_save_frame) or r30, r30, lo16(_save_frame) @@ -2567,502 +2530,490 @@ GLOBAL(m88110_fatal) ldcr r10, SR3 st r10, r31, REG_OFF(EF_FPHS2) - /* * Cheap way to enable FPU and start shadowing again. */ - ldcr r10, PSR - clr r10, r10, 1 /* enable the FPU */ - clr r10, r10, 1 /* also enable shadowing */ - - stcr r10, PSR /* bang */ + ldcr r10, PSR + clr r10, r10, 1 /* enable the FPU */ + clr r10, r10, 1 /* and shadowing */ + stcr r10, PSR FLUSH_PIPELINE /* put pointer to regs into r30... r31 will become a simple stack */ or r30, r31, r0 - subu r31, r31, 0x10 /* make some breathing space */ - st r30, r31, 0x0c /* store frame pointer on the st */ - st r30, r31, 0x08 /* store again for the debugger to recognize */ + subu r31, r31, 0x10 /* make some breathing space */ + st r30, r31, 0x0c /* store frame pointer on the st */ + st r30, r31, 0x08 /* store again for the debugger to recognize */ or.u r20, r0, hi16(0x87654321) or r20, r20, lo16(0x87654321) st r20, r31, 0x04 st r20, r31, 0x00 - + CALL(_error_fatal, r30, r30) - /* TURN INTERUPTS back on */ - ldcr r1, PSR - clr r1, r1, 1 - stcr r1, PSR - FLUSH_PIPELINE + /* turn interupts back on */ + ldcr r1, PSR + clr r1, r1, 1 + stcr r1, PSR + FLUSH_PIPELINE ASGLOBAL(m88110_error_loop) - bsr m88110_error_loop - /* never returns*/ + bsr m88110_error_loop + /* never returns*/ ASGLOBAL(m88110_setup_phase_one) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread (if any, null if not) * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: saved copy of exception-time r1 * - * SR3: must be preserved .. may be the exception-time stack * - * r1: return address to calling exception handler * - * FLAGS: CPU status flags * - *************************************************** * - * immediate goal: * - * Decide where we're going to put the exception frame. * - * Might be at the end of R31, SR3, or the thread's * - * pcb. * - \***************************************************************/ - + /* + * SR0: current thread (if any, null if not) + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: saved copy of exception-time r1 + * SR3: must be preserved .. may be the exception-time stack + * r1: return address to calling exception handler + * FLAGS: CPU status flags + * + * immediate goal: + * Decide where we're going to put the exception frame. + * Might be at the end of R31, SR3, or the thread's pcb. + */ + /* Check if we are coming in from a FPU restart exception. If so, the pcb will be in SR3 */ NOP - xcr r1, r1, SR2 + xcr r1, r1, SR2 NOP NOP NOP - - bb1 FLAG_ENABLING_FPU, FLAGS, m88110_use_SR3_pcb + + bb1 FLAG_ENABLING_FPU, FLAGS, m88110_use_SR3_pcb /* are we coming in from user mode? If so, pick up process pcb */ - bb0 FLAG_FROM_KERNEL, FLAGS, m88110_pickup_stack - + bb0 FLAG_FROM_KERNEL, FLAGS, m88110_pickup_stack + /* Interrupt in kernel mode, not FPU restart */ ASGLOBAL(m88110_already_on_kernel_stack) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread (if any, null if not) * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: return address to the calling exception handler * - * SR3: must be preserved; may be important for other exceptions * - * FLAGS: CPU status flags * - *************************************************** * - * immediate goal: * - * We're already on the kernel stack, but not having * - * needed to use SR3. We can just make room on the * - * stack (r31) for our exception frame. * - \***************************************************************/ - subu r31, r31, SIZEOF_EF /* r31 now our E.F. */ - st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */ - st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/ - - ldcr r1, SR3 /* save previous SR3 */ - st r1, r31, REG_OFF(EF_SR3) - - addu r1, r31, SIZEOF_EF /* save previous r31 */ - br.n m88110_have_pcb - st r1, r31, GENREG_OFF(31) - - + /* + * SR0: current thread (if any, null if not) + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: return address to the calling exception handler + * SR3: must be preserved; may be important for other exceptions + * FLAGS: CPU status flags + * + * immediate goal: + * We're already on the kernel stack, but not having + * needed to use SR3. We can just make room on the + * stack (r31) for our exception frame. + */ + subu r31, r31, SIZEOF_EF /* r31 now our E.F. */ + st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */ + st r1, r31, GENREG_OFF(1) /* save prev. r1 (now free) */ + + ldcr r1, SR3 /* save previous SR3 */ + st r1, r31, REG_OFF(EF_SR3) + + addu r1, r31, SIZEOF_EF /* save previous r31 */ + br.n m88110_have_pcb + st r1, r31, GENREG_OFF(31) + ASGLOBAL(m88110_use_SR3_pcb) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread (if any, null if not) * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: return address to the calling exception handler * - * SR3: must be preserved; exception-time stack pointer * - * FLAGS: CPU status flags * - *************************************************** * - * immediate goal: * - * An exception occured while enabling the FPU. Since r31 * - * is the user's r31 while enabling the FPU, we had put * - * our pcb pointer into SR3, so make room from * - * there for our stack pointer. * - * We need to check if SR3 is the old stack pointer or the * - * pointer off to the user pcb. If it pointing to the user * - * pcb, we need to pick up the kernel stack. Otherwise * - * we need to allocate a frame upon it. * - * We look at the EPSR to see if it was from user mode * - * Unfortunately, we have no registers free at the moment * - * But we know register 0 in the pcb frame will always be * - * zero, so we can use it as scratch storage. * - * * - * * - \***************************************************************/ - xcr r2, r2, SRX + /* + * SR0: current thread (if any, null if not) + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: return address to the calling exception handler + * SR3: must be preserved; exception-time stack pointer + * FLAGS: CPU status flags + * + * immediate goal: + * An exception occured while enabling the FPU. Since r31 is the + * user's r31 while enabling the FPU, we had put our pcb pointer + * into SR3, so make room from there for our stack pointer. + * We need to check if SR3 is the old stack pointer or the pointer + * off to the user pcb. If it pointing to the user pcb, we need to + * pick up the kernel stack. Otherwise we need to allocate a frame + * upon it. + * We look at the EPSR to see if it was from user mode + * Unfortunately, we have no registers free at the moment, but we + * know register 0 in the pcb frame will always be zero, so we can + * use it as scratch storage. + */ + xcr r2, r2, SRX or r2, r0, 10 - stcr r2, SR0 + stcr r2, SR0 br.n _C_LABEL(m88110_fatal) - xcr r2, r2, SRX + xcr r2, r2, SRX /* Testing!!! */ - xcr r30, r30, SR3 /* r30 = old exception frame */ - st r1, r30, GENREG_OFF(0) /* free up r1 */ - ld r1, r30, REG_OFF(EF_EPSR) /* get back the epsr */ - bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f /* if user mode */ - ld r1, r30, GENREG_OFF(0) /* restore r1 */ + xcr r30, r30, SR3 /* r30 = old exception frame */ + st r1, r30, GENREG_OFF(0) /* free up r1 */ + ld r1, r30, REG_OFF(EF_EPSR) /* get back the epsr */ + bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f /* if user mode */ + ld r1, r30, GENREG_OFF(0) /* restore r1 */ /* we were in kernel mode - dump frame upon the stack */ - st r0, r30, GENREG_OFF(0) /* repair old frame */ - subu r30, r30, SIZEOF_EF /* r30 now our E.F. */ - st FLAGS,r30, REG_OFF(EF_FLAGS) /* save flags */ - st r1, r30, GENREG_OFF(1) /* save prev. r1 (now r1 free) */ - - st r31, r30, GENREG_OFF(31) /* save previous r31 */ - or r31, r0, r30 /* make r31 our pointer. */ - addu r30, r30, SIZEOF_EF /* r30 now has previous SR3 */ - st r30, r31, REG_OFF(EF_SR3) /* save previous SR3 */ - br.n m88110_have_pcb - xcr r30, r30, SR3 /* restore r30 */ + st r0, r30, GENREG_OFF(0) /* repair old frame */ + subu r30, r30, SIZEOF_EF /* r30 now our E.F. */ + st FLAGS,r30, REG_OFF(EF_FLAGS) /* save flags */ + st r1, r30, GENREG_OFF(1) /* save prev. r1 (now free) */ + + st r31, r30, GENREG_OFF(31) /* save previous r31 */ + or r31, r0, r30 /* make r31 our pointer. */ + addu r30, r30, SIZEOF_EF /* r30 now has previous SR3 */ + st r30, r31, REG_OFF(EF_SR3) /* save previous SR3 */ + br.n m88110_have_pcb + xcr r30, r30, SR3 /* restore r30 */ 1: - /* we took an exception while restarting the FPU from user space. + /* + * We took an exception while restarting the FPU from user space. * Consequently, we never picked up a stack. Do so now. * R1 is currently free (saved in the exception frame pointed at by - * r30) */ - or.u r1, r0, hi16(_kstack) - ld r1, r1, lo16(_kstack) - addu r1, r1, USIZE-SIZEOF_EF - st FLAGS,r1, REG_OFF(EF_FLAGS) /* store flags */ - st r31, r1, GENREG_OFF(31) /* store r31 - now free */ - st r30, r1, REG_OFF(EF_SR3) /* store old SR3 (pcb) */ - or r31, r1, r0 /* make r31 our exception frame pointer */ - ld r1, r30, GENREG_OFF(0) /* restore old r1 */ - st r0, r30, GENREG_OFF(0) /* repair that frame */ - st r1, r31, GENREG_OFF(1) /* store r1 in its proper place */ - br.n m88110_have_pcb - xcr r30, r30, SR3 /* restore r30 */ - + * r30) + */ + or.u r1, r0, hi16(_kstack) + ld r1, r1, lo16(_kstack) + addu r1, r1, USIZE-SIZEOF_EF + st FLAGS,r1, REG_OFF(EF_FLAGS) /* store flags */ + st r31, r1, GENREG_OFF(31) /* store r31 - now free */ + st r30, r1, REG_OFF(EF_SR3) /* store old SR3 (pcb) */ + or r31, r1, r0 /* make r31 our exception fp */ + ld r1, r30, GENREG_OFF(0) /* restore old r1 */ + st r0, r30, GENREG_OFF(0) /* repair that frame */ + st r1, r31, GENREG_OFF(1) /* store r1 */ + br.n m88110_have_pcb + xcr r30, r30, SR3 /* restore r30 */ + ASGLOBAL(m88110_pickup_stack) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: return address to the calling exception handler * - * SR3: free * - * FLAGS: CPU status flags * - *************************************************** * - * immediate goal: * - * Since we're servicing an exception from user mode, we * - * know that SR3 is free. We use it to free up a temp. * - * register to be used in getting the thread's pcb * - \***************************************************************/ - stcr r31, SR3 /* save previous r31 */ - + /* + * SR0: current thread + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: return address to the calling exception handler + * SR3: free + * FLAGS: CPU status flags + * + * immediate goal: + * Since we're servicing an exception from user mode, we + * know that SR3 is free. We use it to free up a temporary + * register to be used in getting the thread's pcb. + */ + stcr r31, SR3 /* save previous r31 */ + /* switch to the thread's kernel stack. */ - or.u r31, r0, hi16(_curpcb) - ld r31, r31, lo16(_curpcb) - addu r31, r31, PCB_USER_STATE /* point to user save area */ - st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */ - st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/ - ldcr r1, SR3 /* save previous r31 */ - st r1, r31, GENREG_OFF(31) - /*FALLTHROUGH */ - + or.u r31, r0, hi16(_curpcb) + ld r31, r31, lo16(_curpcb) + addu r31, r31, PCB_USER_STATE /* point to user save area */ + st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */ + st r1, r31, GENREG_OFF(1) /* save prev. r1 (now free)*/ + ldcr r1, SR3 /* save previous r31 */ + st r1, r31, GENREG_OFF(31) + /* FALLTHROUGH */ + ASGLOBAL(m88110_have_pcb) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: return address to the calling exception handler * - * SR3: free * - * r1: free * - * FLAGS: CPU status flags * - * r31: our exception frame * - * Valid in the exception frame: * - * Exception-time r1, r31, FLAGS. * - * Exception SR3, if appropriate. * - *************************************************** * - * immediate goal: * - * Save the shadow registers that need to be saved to * - * the exception frame. * - \***************************************************************/ - stcr TMP, SR3 /* free up TMP, TMP2, TMP3 */ + /* + * SR0: current thread + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: return address to the calling exception handler + * SR3: free + * r1: free + * FLAGS: CPU status flags + * r31: our exception frame + * Valid in the exception frame: + * Exception-time r1, r31, FLAGS. + * Exception SR3, if appropriate. + * + * immediate goal: + * Save the shadow registers that need to be saved to + * the exception frame. + */ + stcr TMP, SR3 /* free up TMP, TMP2, TMP3 */ SAVE_TMP2 SAVE_TMP3 - + /* save some exception-time registers to the exception frame */ - ldcr TMP, EPSR - st TMP, r31, REG_OFF(EF_EPSR) - ldcr TMP2, EXIP - st TMP2, r31, REG_OFF(EF_EXIP) - bb0.n 0, TMP2, 1f + ldcr TMP, EPSR + st TMP, r31, REG_OFF(EF_EPSR) + ldcr TMP2, EXIP + st TMP2, r31, REG_OFF(EF_EXIP) + bb0.n 0, TMP2, 1f /* The instruction was NOT in the delay slot, zero ENIP. */ - st r0, r31, REG_OFF(EF_ENIP) + st r0, r31, REG_OFF(EF_ENIP) /* The instruction was in the delay slot, save ENIP. */ - ldcr TMP3, ENIP - st TMP3, r31, REG_OFF(EF_ENIP) + ldcr TMP3, ENIP + st TMP3, r31, REG_OFF(EF_ENIP) 1: /* NO SFIP on mc88110, zero it */ - st r0, r31, REG_OFF(EF_SFIP) - - /* get and store the cpu number */ - extu TMP, FLAGS, FLAG_CPU_FIELD_WIDTH<0> /* TMP = cpu# */ - st TMP, r31, REG_OFF(EF_CPU) - + st r0, r31, REG_OFF(EF_SFIP) + + /* get and store the cpu number */ + extu TMP, FLAGS, FLAG_CPU_FIELD_WIDTH<0> /* TMP = cpu# */ + st TMP, r31, REG_OFF(EF_CPU) + /* * Save Pbus fault status register from data and inst CMMU. */ - ldcr TMP, ISR - ldcr TMP2, ILAR - ldcr TMP3, IPAR - st TMP, r31, REG_OFF(EF_ISR) - st TMP2, r31, REG_OFF(EF_ILAR) - st TMP3, r31, REG_OFF(EF_IPAR) - ldcr TMP, ISAP - ldcr TMP2, IUAP - st TMP, r31, REG_OFF(EF_ISAP) - st TMP2, r31, REG_OFF(EF_IUAP) - ldcr TMP, DSR - ldcr TMP2, DLAR - ldcr TMP3, DPAR - st TMP, r31, REG_OFF(EF_DSR) - st TMP2, r31, REG_OFF(EF_DLAR) - st TMP3, r31, REG_OFF(EF_DPAR) - ldcr TMP, DSAP - ldcr TMP2, DUAP - st TMP, r31, REG_OFF(EF_DSAP) - st TMP2, r31, REG_OFF(EF_DUAP) - - ldcr r1, SR2 - jmp r1 /* return */ - -/************************************************************************/ -/************************************************************************/ + ldcr TMP, ISR + ldcr TMP2, ILAR + ldcr TMP3, IPAR + st TMP, r31, REG_OFF(EF_ISR) + st TMP2, r31, REG_OFF(EF_ILAR) + st TMP3, r31, REG_OFF(EF_IPAR) + ldcr TMP, ISAP + ldcr TMP2, IUAP + st TMP, r31, REG_OFF(EF_ISAP) + st TMP2, r31, REG_OFF(EF_IUAP) + ldcr TMP, DSR + ldcr TMP2, DLAR + ldcr TMP3, DPAR + st TMP, r31, REG_OFF(EF_DSR) + st TMP2, r31, REG_OFF(EF_DLAR) + st TMP3, r31, REG_OFF(EF_DPAR) + ldcr TMP, DSAP + ldcr TMP2, DUAP + st TMP, r31, REG_OFF(EF_DSAP) + st TMP2, r31, REG_OFF(EF_DUAP) + + ldcr r1, SR2 + jmp r1 ASGLOBAL(m88110_setup_phase_two) - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: saved return address to calling exception handler * - * SR1: saved copy of exception-time register now holding FLAGS * - * SR2: free * - * SR3: saved TMP * - * r1: return address to calling exception handler * - * TMP: possibly revised SSBR * - * TMP2: free * - * TMP3: free * - * FLAGS: CPU status flags * - * r31: our exception frame * - * Valid in the exception frame: * - * Exception-time r1, r31, FLAGS. * - * Exception-time TMP2, TMP3. * - * Exception-time espr, enip, exip. * - * Exception number (EF_VECTOR). * - * Dmt0 * - * Other data pipeline control registers, if appropriate. * - * FPU control registers, if appropriate. * - * Exception SR3, if appropriate. * - *************************************************** * - * immediate goal: * - * restore the system to the exception-time state (except * - * SR3 will be OUR stack pointer) so that we may resart the FPU. * - \***************************************************************/ - /*stcr r1, SR0*/ /* save return address */ - - RESTORE_TMP2 /* done with extra temp regs */ - RESTORE_TMP3 /* done with extra temp regs */ - - ldcr TMP, PSR - clr TMP, TMP, 1 /* enable the FPU */ - clr TMP, TMP, 1 /* also enable shadowing */ - stcr TMP, EPSR - - or.u TMP, r0, hi16(m88110_fpu_enable) - or TMP, TMP, lo16(m88110_fpu_enable) - stcr TMP, EXIP /* jump to here fpu_enable */ - addu TMP, TMP, 4 - stcr TMP, ENIP /* and then continue after that */ - - set FLAGS, FLAGS, 1 /* note what we're doing.*/ - xcr FLAGS, FLAGS, SR1 - st r1, r31, REG_OFF(EF_RET) /* save the return address */ - ld r1, r31, GENREG_OFF(1) /* get original r1 */ - - ldcr TMP, SR3 - stcr r31, SR3 /* TMP now restored. R31 now saved in SR3 */ - ld r31, r31, GENREG_OFF(31) /* get original r31 */ - - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread * - * SR1: CPU flags * - * SR2: free * - * SR3: pointer to our exception frame (our stack pointer) * - * r1 through r31: original exception-time values * - * * - * Valid in the exception frame: * - * Exception-time FLAGS. * - * Exception-time espr, sfip, enip, exip. * - * Exception number (EF_VECTOR). * - * Dmt0 * - * Other data pipeline control registers, if appropriate. * - * FPU control registers, if appropriate. * - * Exception SR3, if appropriate. * - * Held temporarly in the exception frame: * - * Return address to the calling excption handler. * - *************************************************** * - * immediate goal: * - * Do an RTE to restart the fpu and jump to "fpu_enable" * - * Another exception (or exceptions) may be raised in * - * this, which is why FLAG_ENABLING_FPU is set in SR1. * - \***************************************************************/ + /* + * SR0: saved return address to calling exception handler + * SR1: saved copy of exception-time register now holding FLAGS + * SR2: free + * SR3: saved TMP + * r1: return address to calling exception handler + * TMP: possibly revised SSBR + * TMP2: free + * TMP3: free + * FLAGS: CPU status flags + * r31: our exception frame + * Valid in the exception frame: + * Exception-time r1, r31, FLAGS. + * Exception-time TMP2, TMP3. + * Exception-time espr, enip, exip. + * Exception number (EF_VECTOR). + * Dmt0 + * Other data pipeline control registers, if appropriate. + * FPU control registers, if appropriate. + * Exception SR3, if appropriate. + * + * immediate goal: + * restore the system to the exception-time state (except SR3 will + * be OUR stack pointer) so that we may resart the FPU. + */ + /*stcr r1, SR0*/ /* save return address */ + + RESTORE_TMP2 /* done with extra temp regs */ + RESTORE_TMP3 /* done with extra temp regs */ + + ldcr TMP, PSR + clr TMP, TMP, 1 /* enable the FPU */ + clr TMP, TMP, 1 /* and shadowing */ + stcr TMP, EPSR + + or.u TMP, r0, hi16(m88110_fpu_enable) + or TMP, TMP, lo16(m88110_fpu_enable) + stcr TMP, EXIP /* jump to here fpu_enable */ + addu TMP, TMP, 4 + stcr TMP, ENIP /* and then continue after that */ + + set FLAGS, FLAGS, 1 + xcr FLAGS, FLAGS, SR1 + st r1, r31, REG_OFF(EF_RET) /* save the return address */ + ld r1, r31, GENREG_OFF(1) /* get original r1 */ + + ldcr TMP, SR3 + stcr r31, SR3 /* TMP now restored. R31 now saved in SR3 */ + ld r31, r31, GENREG_OFF(31) /* get original r31 */ + + /* + * SR0: current thread + * SR1: CPU flags + * SR2: free + * SR3: pointer to our exception frame (our stack pointer) + * r1 through r31: original exception-time values + * + * Valid in the exception frame: + * Exception-time FLAGS. + * Exception-time espr, sfip, enip, exip. + * Exception number (EF_VECTOR). + * Dmt0 + * Other data pipeline control registers, if appropriate. + * FPU control registers, if appropriate. + * Exception SR3, if appropriate. + * Held temporarly in the exception frame: + * Return address to the calling excption handler. + * + * immediate goal: + * Do an RTE to restart the fpu and jump to "fpu_enable" + * Another exception (or exceptions) may be raised in + * this, which is why FLAG_ENABLING_FPU is set in SR1. + */ NOP - RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */ - + RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */ + ASGLOBAL(m88110_fpu_enable) FLUSH_PIPELINE /* Now we can handle another exception!!! */ /* Now that EFZE is cleared, we can clear these */ - stcr r0, ISR /* Clear ISR */ - stcr r0, ILAR /* Clear ILAR */ - stcr r0, IPAR /* Clear IPAR */ - stcr r0, DSR /* Clear DSR */ - stcr r0, DLAR /* Clear DLAR */ - stcr r0, DPAR /* Clear DPAR */ - xcr TMP, TMP, SR3 /* get E.F. pointer */ - st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */ - or r31, TMP, r0 /* transfer E.F. pointer to r31 */ - ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3; maybe important*/ + stcr r0, ISR /* Clear ISR */ + stcr r0, ILAR /* Clear ILAR */ + stcr r0, IPAR /* Clear IPAR */ + stcr r0, DSR /* Clear DSR */ + stcr r0, DLAR /* Clear DLAR */ + stcr r0, DPAR /* Clear DPAR */ + xcr TMP, TMP, SR3 /* get E.F. pointer */ + st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */ + or r31, TMP, r0 /* transfer E.F. pointer */ + ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3 */ /* make sure that the FLAG_ENABLING_FPU bit is off */ - xcr FLAGS,FLAGS,SR1 - clr FLAGS,FLAGS,1 - xcr FLAGS,FLAGS,SR1 + xcr FLAGS,FLAGS,SR1 + clr FLAGS,FLAGS,1 + xcr FLAGS,FLAGS,SR1 - xcr TMP, TMP, SR3 /* replace TMP, SR3 */ + xcr TMP, TMP, SR3 /* replace TMP, SR3 */ /* now save all regs to the exception frame. */ - st.d r0 , r31, GENREG_OFF(0) - st.d r2 , r31, GENREG_OFF(2) - st.d r4 , r31, GENREG_OFF(4) - st.d r6 , r31, GENREG_OFF(6) - st.d r8 , r31, GENREG_OFF(8) - st.d r10, r31, GENREG_OFF(10) - st.d r12, r31, GENREG_OFF(12) - st.d r14, r31, GENREG_OFF(14) - st.d r16, r31, GENREG_OFF(16) - st.d r18, r31, GENREG_OFF(18) - st.d r20, r31, GENREG_OFF(20) - st.d r22, r31, GENREG_OFF(22) - st.d r24, r31, GENREG_OFF(24) - st.d r26, r31, GENREG_OFF(26) - st.d r28, r31, GENREG_OFF(28) + st.d r0 , r31, GENREG_OFF(0) + st.d r2 , r31, GENREG_OFF(2) + st.d r4 , r31, GENREG_OFF(4) + st.d r6 , r31, GENREG_OFF(6) + st.d r8 , r31, GENREG_OFF(8) + st.d r10, r31, GENREG_OFF(10) + st.d r12, r31, GENREG_OFF(12) + st.d r14, r31, GENREG_OFF(14) + st.d r16, r31, GENREG_OFF(16) + st.d r18, r31, GENREG_OFF(18) + st.d r20, r31, GENREG_OFF(20) + st.d r22, r31, GENREG_OFF(22) + st.d r24, r31, GENREG_OFF(24) + st.d r26, r31, GENREG_OFF(26) + st.d r28, r31, GENREG_OFF(28) #ifdef JEFF_DEBUG /* mark beginning of frame with notable value */ - or.u r20, r0, hi16(0x12345678) - or r20, r20, lo16(0x12345678) - st r20, r31, GENREG_OFF(0) + or.u r20, r0, hi16(0x12345678) + or r20, r20, lo16(0x12345678) + st r20, r31, GENREG_OFF(0) #endif - - /***************** REGISTER STATUS BLOCK ***********************\ - * SR0: current thread * - * SR1: free * - * SR2: free * - * SR3: previous exception-time SR3 * - * r1: return address to the calling exception handler * - * r2 through r30: free * - * r31: our exception frame * - * * - * Valid in the exception frame: * - * Exception-time r0 through r31. * - * Exception-time FLAGS. * - * Exception-time espr, enip, exip. * - * Exception number (EF_VECTOR). * - * DSR * - * Other data pipeline control registers, if appropriate. * - * FPU control registers, if appropriate. * - * Exception SR3, if appropriate. * - *************************************************** * - * immediate goal: * - * Pick up a stack if we came in from user mode. Put * - * A copy of the exception frame pointer into r30 * - * bump the stack a doubleword and write the exception * - * frame pointer. * - * if not an interrupt exception, * - * Turn on interrupts and service any outstanding * - * data access exceptions. * - * Return to calling exception handler to * - * service the exception. * - \***************************************************************/ - + + /* + * SR0: current thread + * SR1: free + * SR2: free + * SR3: previous exception-time SR3 + * r1: return address to the calling exception handler + * r2 through r30: free + * r31: our exception frame + * + * Valid in the exception frame: + * Exception-time r0 through r31. + * Exception-time FLAGS. + * Exception-time espr, enip, exip. + * Exception number (EF_VECTOR). + * DSR + * Other data pipeline control registers, if appropriate. + * FPU control registers, if appropriate. + * Exception SR3, if appropriate. + * + * immediate goal: + * Pick up a stack if we came in from user mode. + * Put a copy of the exception frame pointer into r30 + * Bump the stack a doubleword and write the exception frame pointer. + * If not an interrupt exception, turn on interrupts and service any + * outstanding data access exceptions. + * Return to calling exception handler to service the exception. + */ + /* * If it's not the interrupt exception, enable interrupts and * take care of any data access exceptions...... */ - or r30, r0, r31 /* get a copy of the e.f. pointer */ - ld r2, r31, REG_OFF(EF_EPSR) - bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* If in kernel mode */ + or r30, r0, r31 /* get a copy of the e.f. pointer */ + ld r2, r31, REG_OFF(EF_EPSR) + bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* if in kernel mode */ -#if INTSTACK +#ifdef INTSTACK /* * If interrupt exception, switch to interrupt stack if not * already there. Else, switch to kernel stack. */ - ld r3, r31, REG_OFF(EF_VECTOR) - cmp r3, r3, 1 /* is interrupt ? */ - bb0 eq, r3, 2f - or.u r31, r0, hi16(_intstack_end) /* swith to int stack */ - or r31, r31, lo16(_intstack_end) - br 3f + ld r3, r31, REG_OFF(EF_VECTOR) + cmp r3, r3, 1 /* is interrupt ? */ + bb0 eq, r3, 2f + or.u r31, r0, hi16(_intstack_end) /* switch to int stack */ + or r31, r31, lo16(_intstack_end) + br 3f 2: #endif - or.u r31, r0, hi16(_kstack) - ld r31, r31, lo16(_kstack) - addu r31, r31, USIZE /* point at proper end */ - br 3f + or.u r31, r0, hi16(_kstack) + ld r31, r31, lo16(_kstack) + addu r31, r31, USIZE /* point at proper end */ + br 3f 1: -#if INTSTACK - ld r3, r31, REG_OFF(EF_VECTOR) - cmp r3, r3, 1 /* is interrupt ? */ - bb0 eq, r3, 3f /* no, we will stay on kern stack */ - or.u r31, r0, hi16(_intstack_end) /* swith to int stack */ - or r31, r31, lo16(_intstack_end) -#endif /* INTSTACK */ +#ifdef INTSTACK + ld r3, r31, REG_OFF(EF_VECTOR) + cmp r3, r3, 1 /* is interrupt ? */ + bb0 eq, r3, 3f /* no, we will stay on kern stack */ + or.u r31, r0, hi16(_intstack_end) /* switch to int stack */ + or r31, r31, lo16(_intstack_end) +#endif /* This label is here for debugging */ -m88110_exception_handler_has_ksp: global m88110_exception_handler_has_ksp +m88110_exception_handler_has_ksp: +global m88110_exception_handler_has_ksp 3: /* * here - r30 holds a pointer to the exception frame. * r31 is a pointer to the kernel stack/interrupt stack. */ - subu r31, r31, 8 /* make some breathing space */ - st r30, r31, 0 /* store frame pointer on the stack */ -#if DDB - st r30, r31, 4 /* store it again for the debugger to recognize */ + subu r31, r31, 8 /* make some breathing space */ + st r30, r31, 0 /* store frame pointer on the stack */ +#ifdef DDB + st r30, r31, 4 /* store it again for the debugger */ #endif /* DDB */ - ld r2, r30, REG_OFF(EF_VECTOR) - bcnd.n eq0, r2, m88110_return_to_calling_exception_handler /* is error */ - ld r14, r30, REG_OFF(EF_RET) /* load return value XXX!!! */ - cmp r3, r2, 1 /* interrupt is exception #1 ;Is an interrupt? */ - bb1.n eq, r3, m88110_return_to_calling_exception_handler /* skip if so */ + ld r2, r30, REG_OFF(EF_VECTOR) + bcnd.n eq0, r2, m88110_return_to_calling_exception_handler + ld r14, r30, REG_OFF(EF_RET) /* load return value XXX!!! */ + cmp r3, r2, 1 /* is an interrupt? */ + bb1.n eq, r3, m88110_return_to_calling_exception_handler -#if DDB - cmp r3, r2, 130 /* DDB break exception */ - bb1.n eq, r3, m88110_return_to_calling_exception_handler +#ifdef DDB + cmp r3, r2, 130 /* DDB break exception */ + bb1.n eq, r3, m88110_return_to_calling_exception_handler - cmp r3, r2, 132 /* DDB entry exception */ - bb1.n eq, r3, m88110_return_to_calling_exception_handler + cmp r3, r2, 132 /* DDB entry exception */ + bb1.n eq, r3, m88110_return_to_calling_exception_handler #endif - ldcr r2, PSR - clr r2, r2, 1 /* enable interrupts */ - stcr r2, PSR -#if DDB + /* enable interrupts */ + ldcr r2, PSR + clr r2, r2, 1 + stcr r2, PSR +#ifdef DDB FLUSH_PIPELINE #endif #if 1 /* test */ - br m88110_return_to_calling_exception_handler + br m88110_return_to_calling_exception_handler #endif /* service any outstanding data pipeline stuff - - check dsr... anything outstanding?*/ + - check dsr... anything outstanding? */ - ld r3, r30, REG_OFF(EF_DSR) - cmp r3, r3, 0 - bb1 eq, r3, m88110_return_to_calling_exception_handler + ld r3, r30, REG_OFF(EF_DSR) + cmp r3, r3, 0 + bb1 eq, r3, m88110_return_to_calling_exception_handler /* * r30 can be clobbered by calls. So stuff its value into a * preserved register, say r15. R14 is in use (see return_to_... below). */ - or r15, r0, r30 -#if 0 - CALL(_C_LABEL(test_trap), r15, r0) -#endif + or r15, r0, r30 CALL(_C_LABEL(m88110_trap), T_DATAFLT, r15) - /* restore it... */ - or r30, r0, r15 + /* restore it... */ + or r30, r0, r15 /* clear the dsr word in the E.F */ - st r0, r30, REG_OFF(EF_DSR) + st r0, r30, REG_OFF(EF_DSR) ASGLOBAL(m88110_return_to_calling_exception_handler) - jmp r14 /* loaded above */ - + jmp r14 /* loaded above */ + data .align 8 GLOBAL(save_frame) - space SIZEOF_EF -#endif + space SIZEOF_EF +#endif /* M88110 */ diff --git a/sys/arch/mvme88k/mvme88k/locore.S b/sys/arch/mvme88k/mvme88k/locore.S index 8ed665786b2..de7e92d55e4 100644 --- a/sys/arch/mvme88k/mvme88k/locore.S +++ b/sys/arch/mvme88k/mvme88k/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.26 2003/01/14 03:20:16 miod Exp $ */ +/* $OpenBSD: locore.S,v 1.27 2003/08/03 23:34:09 miod Exp $ */ /* * Copyright (c) 1998 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -65,18 +65,15 @@ #include #include #include -#include /* INTSTACK_SIZE */ - -/***********************************************************************/ +#include /* INTSTACK_SIZE */ /* * The memory looks like: - * 0x00000 - 0x01000 : trap vectors - * 0x01000 - 0x10000 : first 64k used by BUG - * 0x10000 == start : Boot loader jumps here. (for now, this can - * handle only NMAGIC - screwy linker) - * - ***********************************************************************/ + * 0x00000 - 0x01000 trap vectors + * 0x01000 - 0x10000 first 64k used by BUG + * 0x10000 == start Boot loader jumps here. (for now, this can + * handle only NMAGIC - screwy linker) + */ text GLOBAL(kernelstart) @@ -90,7 +87,7 @@ ASGLOBAL(start) GLOBAL(doboot) /* - * Try hitting the SRST bit in VMEchip2 to reset the system. + * Try hitting the SRST bit in VMEchip2 to reset the system. */ #ifdef MVME188 /* check if it's a mvme188 */ @@ -101,20 +98,20 @@ GLOBAL(doboot) bsr _C_LABEL(m188_reset) br m188_doboot_fail #endif /* MVME188 */ -1: +1: or.u r3,r0, 0xfff4 ld r4,r3, 0x0060 /* read offset (LCSR +0x60) */ - set r4,r4,1<23> /* set SYSRST bit - bit 23 */ + set r4,r4,1<23> /* set SYSRST bit - bit 23 */ st r4,r3, 0x0060 /* and store it back */ /* - * We will be here if the reset above failed. In this case, - * we will try to return to bug. + * We will be here if the reset above failed. In this case, + * we will try to return to bug. * - * Switch to interrupt stack and call _doboot to take care - * going to BUG. Need to do this since _doboot turns off the - * the MMU and we need to be on a 1-to-1 mapped stack so that - * further calls don't get data access exceptions. + * Switch to interrupt stack and call _doboot to take care + * going to BUG. Need to do this since _doboot turns off the + * the MMU and we need to be on a 1-to-1 mapped stack so that + * further calls don't get data access exceptions. */ /* Should we use idle_u instead? XXX nivas */ @@ -126,8 +123,8 @@ m188_doboot_fail: bsr _C_LABEL(_doboot) /*NOTREACHED*/ -/**************************************************************************/ -GLOBAL(start_text) /* This is the *real* start upon poweron or reset */ + /* This is the *real* start upon poweron or reset */ +GLOBAL(start_text) /* * Args passed by boot loader * r2 howto @@ -139,9 +136,9 @@ GLOBAL(start_text) /* This is the *real* start upon poweron or reset */ * r8 cpu type (0x187, 0x188, 0x197) */ /* - * (*entry)(flag, bugargs.ctrl_addr, cp, kernel.smini, - * kernel.emini, bootdev, brdtyp); - */ + * (*entry)(flag, bugargs.ctrl_addr, cp, kernel.smini,kernel.emini, + * bootdev, brdtyp); + */ or.u r13, r0, hi16(_boothowto) st r2, r13, lo16(_boothowto) or.u r13, r0, hi16(_bootaddr) @@ -156,20 +153,20 @@ GLOBAL(start_text) /* This is the *real* start upon poweron or reset */ st r7, r13, lo16(_bootdev) or.u r13, r0, hi16(_brdtyp) st r8, r13, lo16(_brdtyp) - + /* set _cputyp */ - cmp r2, r8, BRD_197 /* r8 contains brdtyp */ - bb1 ne, r2, 1f /* if it's a '197, CPU is 88110 */ - or.u r13, r0, hi16(CPU_88110) - or r8, r13, lo16(CPU_88110)/* r8 contains 0x110 */ + cmp r2, r8, BRD_197 /* r8 contains brdtyp */ + bb1 ne, r2, 1f /* if it's a '197, CPU is 88110 */ + or.u r13, r0, hi16(CPU_88110) + or r8, r13, lo16(CPU_88110) /* r8 contains 0x110 */ br 2f -1: - or.u r13, r0, hi16(CPU_88100) - or r8, r13, lo16(CPU_88100)/* r8 contains 0x100 */ -2: +1: + or.u r13, r0, hi16(CPU_88100) + or r8, r13, lo16(CPU_88100) /* r8 contains 0x100 */ +2: or.u r13, r0, hi16(_cputyp) - st r8, r13, lo16(_cputyp) /* r8 contains cputyp */ - + st r8, r13, lo16(_cputyp) /* r8 contains cputyp */ + /* * CPU Initialization * @@ -204,25 +201,25 @@ GLOBAL(start_text) /* This is the *real* start upon poweron or reset */ * * jfriedl@omron.co.jp */ - - cmp r2, r8, CPU_88110 /* r8 contains cputyp */ - bb1 eq, r2, 1f /* if it's a 'mc88110, skip SSBR */ + + cmp r2, r8, CPU_88110 /* r8 contains cputyp */ + bb1 eq, r2, 1f /* if it's a 'mc88110, skip SSBR */ stcr r0, SSBR /* clear this for later */ 1: stcr r0, SR0 /* clear "current thread" */ stcr r0, SR1 /* clear the CPU flags */ - + set r11, r0, 1 set r11, r11, 1 set r11, r11, 1 /* set r11, r11, 1 */ set r11, r11, 1 stcr r11, PSR - stcr r0, VBR /* set Vector Base Register to 0, ALWAYS! */ + stcr r0, VBR /* set Vector Base Register to 0, ALWAYS! */ FLUSH_PIPELINE - cmp r2, r8, CPU_88110 /* r8 contains cputyp */ - bb1 eq, r2, master_start /* if it's a '197, skip to master_start */ - + cmp r2, r8, CPU_88110 /* r8 contains cputyp */ + bb1 eq, r2, master_start /* if it's a '197, skip */ + #if 0 /* clear BSS. Boot loader might have already done this... */ or.u r2, r0, hi16(_edata) @@ -230,7 +227,7 @@ GLOBAL(start_text) /* This is the *real* start upon poweron or reset */ or.u r4, r0, hi16(_end) or r4, r4, lo16(_end) bsr.n _bzero /* bzero(edata, end-edata) */ - subu r3, r4, r2 + subu r3, r4, r2 #endif /* * First time to count how many CPUs to attach @@ -240,8 +237,8 @@ GLOBAL(start_text) /* This is the *real* start upon poweron or reset */ ASGLOBAL(check_init_lock) FLUSH_PIPELINE or r22, r0, 1 - xmem r22, r11, r0 /* If r22 gets 0, we have the lock.. */ - bcnd eq0, r22, have_init_lock/* ..but if not, we must wait */ + xmem r22, r11, r0 /* If r22 gets 0, we have the lock.. */ + bcnd eq0, r22, have_init_lock /* ..but if not, we must wait */ ASGLOBAL(wait_for_init_lock) /* just watch the lock until it looks clear */ @@ -259,8 +256,8 @@ ASGLOBAL(have_init_lock) or.u r11, r0, hi16(initialized_cpu_lock) st r0, r11, lo16(initialized_cpu_lock) /* - * Now we vie with any other processors to see who's the master. - * We first try to obtain a lock to see who's allowed + * Now we view with any other processors to see who's the master. + * We first try to obtain a lock to see who's allowed * to check/set the master lock. */ or.u r11, r0, hi16(_inter_processor_lock) @@ -268,19 +265,19 @@ ASGLOBAL(have_init_lock) ASGLOBAL(check_ip_lock) FLUSH_PIPELINE or r22, r0, 1 - xmem r22, r11, r0 /* If r22 gets 0, we have the lock.. */ - bcnd eq0, r22, have_ip_lock /* ..but if not, we must wait */ + xmem r22, r11, r0 /* If r22 gets 0, we have the lock.. */ + bcnd eq0, r22, have_ip_lock /* ..but if not, we must wait */ ASGLOBAL(wait_for_ip_lock) /* just watch the lock until it looks clear */ ld r22, r11, r0 bcnd ne0, r22, wait_for_ip_lock - /* since we can be here with caches off, add a few nops to - keep the bus from getting overloaded */ + /* since we can be here with caches off, add a few nops to + keep the bus from getting overloaded */ or r2, r0, lo16(1000) ASGLOBAL(ip_loop) subu r2, r2, 1 bcnd eq0, r2, ip_loop - br check_ip_lock /* looks clear -- try to grab */ + br check_ip_lock /* looks clear -- try to grab */ ASGLOBAL(have_ip_lock) /* now try to grab the master_processor_chosen prize */ @@ -313,11 +310,11 @@ ASGLOBAL(master_start) #ifdef M88110 cmp r2, r8, CPU_88110 /* r8 contains cputyp */ - bb1 ne, r2, 1f /* if it's a 'mc88110, use different vectors */ + bb1 ne, r2, 1f /* if it's a 'mc88110, use different vectors */ or.u r3, r0, hi16(_m88110_vector_list) or r3, r3, lo16(_m88110_vector_list) bsr.n _vector_init - ldcr r2, VBR + ldcr r2, VBR br 2f #endif /* M88110 */ 1: @@ -329,22 +326,23 @@ ASGLOBAL(master_start) or.u r3, r0, hi16(_vector_list) or r3, r3, lo16(_vector_list) bsr.n _vector_init - ldcr r2, VBR + ldcr r2, VBR #endif /* M88100 */ -2: +2: /* still on int stack */ bsr.n _mvme_bootstrap - subu r31, r31, 40 + subu r31, r31, 40 addu r31, r31, 40 - - /* we now know our cpu number, so we + + /* + * we now know our cpu number, so we * can set interrupt_stack[cpu_number()] = _intstack */ - ldcr r10, SR1 - extu r10, r10, FLAG_CPU_FIELD_WIDTH<0> /* r10 <-- CPU# */ - + ldcr r10, SR1 + extu r10, r10, FLAG_CPU_FIELD_WIDTH<0> /* r10 <-- CPU# */ + /* figure interrupt_stack[cpu_number()] */ - or.u r11, r0, hi16(_interrupt_stack) + or.u r11, r0, hi16(_interrupt_stack) or r11, r11, lo16(_interrupt_stack) or.u r12, r0, hi16(_intstack) or r12, r12, lo16(_intstack) @@ -364,15 +362,16 @@ ASGLOBAL(master_start) addu r31, r31, 40 bsr _panic -/*********************************************************************** +/* * slave CPUs starts here */ ASGLOBAL(slave_start) - /* while holding the inter_processor_lock, the slave cpu - can find use the slavestack to call slave_pre_main and - determine its cpu number. After that, however, it should - switch over to the interrupt stack associated with its - cpu */ + /* + * While holding the inter_processor_lock, the slave cpu can use + * the slavestack to call slave_pre_main and determine its cpu number. + * After that, however, it should switch over to the interrupt stack + * associated with its cpu. + */ /* r31 <-- slavestack */ or.u r31, r0, hi16(_slavestack_end) @@ -380,61 +379,63 @@ ASGLOBAL(slave_start) clr r31, r31, 3<0> /* round down to 8-byte boundary */ bsr.n _slave_pre_main /* set cpu number */ - subu r31, r31, 48 /* allocate frame */ + subu r31, r31, 48 /* allocate frame */ bsr _get_slave_stack addu r31, r2, INTSTACK_SIZE + 4096 - /* SR1 now contains our cpu number. We can now release - the inter_processor_lock, as we are done with the - slavestack. We also have an interrupt stack */ + /* + * SR1 now contains our cpu number. We can now release the + * inter_processor_lock, as we are done with the slavestack. + * We also have an interrupt stack + */ or.u r10, r0, hi16(_inter_processor_lock) - st r0, r10, lo16(_inter_processor_lock) + st r0, r10, lo16(_inter_processor_lock) br.n _slave_main /* does not return */ - subu r31, r31, 40 /* allocate frame */ - + subu r31, r31, 40 /* allocate frame */ + GLOBAL(spin_cpu) - or.u r3, r0, hi16(_start_text) + or.u r3, r0, hi16(_start_text) or r3, r3, lo16(_start_text) or r9, r0, 0x100 /* .FORKMPU */ tb0 0, r0, 0x200-16 /* call 188Bug */ - jmp r1 - + jmp r1 + /*****************************************************************************/ data - .align 4096 /* SDT (segment descriptor table */ + .align 4096 /* SDT (segment descriptor table */ global _kernel_sdt -_kernel_sdt: - space (0x2000) /* 8K - 4K phys, 4K virt*/ +_kernel_sdt: + space (0x2000) /* 8K - 4K phys, 4K virt*/ global _ret_addr _ret_addr: word 0 global _msgsw _msgsw: - word 0 /* Bits here turn on/off debugging somewhere */ + word 0 /* Bits here turn on/off debugging somewhere */ ASGLOBAL(initialized_cpu_lock) - /* XMEM spin lock -- to count CPUs */ + /* XMEM spin lock -- to count CPUs */ word 0 GLOBAL(initialized_cpus) - /* CPU counter to initialize */ + /* CPU counter to initialize */ word 0 ASGLOBAL(master_processor_chosen) - /* The first processor that XMEMs this becomes the master */ + /* The first processor that XMEMs this becomes the master */ word 0 GLOBAL(inter_processor_lock) - /* XMEM spin lock -- controls access to master_processor_chosen */ + /* XMEM spin lock -- controls access to master_processor_chosen */ word 0 - + .align 4096 global _intstack, _intstack_end, _slavestack, _slavestack_end _intstack: space (4 * NBPG) /* 16K, just to be safe */ _intstack_end: _slavestack: - space (NBPG) /* 4K, small, interim stack */ + space (NBPG) /* 4K, small, interim stack */ _slavestack_end: /* @@ -502,14 +503,13 @@ _curpcb: word _u0 /* curpcb = &u0 */ * user stack in exec. */ global _sigcode -_sigcode: - /* r31 points to sigframe */ +_sigcode: /* r31 points to sigframe */ ld r2, r31, 0 /* signo */ ld r3, r31, 4 /* siginfo_t* */ ld r4, r31, 8 /* sigcontext* */ ld r5, r31, 12 /* handler */ jsr.n r5 - subu r31, r31, 40 /* give some stack space */ + subu r31, r31, 40 /* give some stack space */ addu r31, r31, 40 /* restore old sp value */ ld r2, r31, 8 /* sigcontext* */ or r13, r0, SYS_sigreturn @@ -544,5 +544,3 @@ _eintrnames: _intrcnt: word 0,0,0,0,0,0,0,0,0,0,0,0 _eintrcnt: - - diff --git a/sys/arch/mvme88k/mvme88k/locore_asm_routines.S b/sys/arch/mvme88k/mvme88k/locore_asm_routines.S index 7838389e6cb..a96c50db5a9 100644 --- a/sys/arch/mvme88k/mvme88k/locore_asm_routines.S +++ b/sys/arch/mvme88k/mvme88k/locore_asm_routines.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore_asm_routines.S,v 1.21 2003/01/09 22:27:09 miod Exp $ */ +/* $OpenBSD: locore_asm_routines.S,v 1.22 2003/08/03 23:34:09 miod Exp $ */ /* * Mach Operating System * Copyright (c) 1993-1992 Carnegie Mellon University @@ -169,12 +169,12 @@ ENTRY(do_xmem_byte) /* do_xmem_byte(address, data, supervisor) */ 1: xmem.bu r3,r2,r0 2: jmp r1 -#if DDB +#ifdef DDB ENTRY(db_are_interrupts_disabled) - ldcr r2, PSR /* get the processor status word */ - set r3, r0, 1 /* set mask */ - jmp.n r1 /* delayed return */ - and r2, r2, r3 /* r2 = r3 & r2 */ + ldcr r2, PSR + set r3, r0, 1 + jmp.n r1 + and r2, r2, r3 #endif /* DDB */ GLOBAL(FAULT_ERROR) @@ -190,23 +190,25 @@ GLOBAL(FAULT_ERROR) * (r1=return addr) */ -#define SRC r2 -#define DEST r3 -#define LEN r4 +#define SRC r2 +#define DEST r3 +#define LEN r4 ENTRY(copyin) /* set up fault handler */ - or.u r5, r0, hi16(_curpcb) + or.u r5, r0, hi16(_curpcb) ld r6, r5, lo16(_curpcb) or.u r5, r0, hi16(.Lciflt) or r5, r5, lo16(.Lciflt) st r5, r6, PCB_ONFAULT /* pcb_onfault = .Lciflt */ - - /*bcnd ne0, LEN, 1f ; XXX optimize len = 0 case */ - /*;or r2, r0, 0 */ - /*;br .Lcidone */ - /*;1: ;bcnd lt0, LEN, .Lciflt ; EFAULT if len < 0 */ - + +#if 0 + bcnd ne0, LEN, 1f /* XXX optimize len = 0 case */ + or r2, r0, 0 + br .Lcidone +1: bcnd lt0, LEN, .Lciflt /* EFAULT if len < 0 */ +#endif + /* If it's a small length (less than 8), then do byte-by-byte */ cmp r9, LEN, 8 bb1 lt, r9, copyin_byte_only @@ -233,93 +235,93 @@ copyin_right_aligned_to_word: /* At this point, both SRC and DEST are aligned to a word */ /* boundry, and LEN is an even multiple of 4. */ bb1.n 2, LEN, copyin_right_align_to_doubleword - or r7, r0, 4 + or r7, r0, 4 copyin_right_aligned_to_doubleword: #ifdef ERRATA__XXX_USR NOP - ld.usr r5, SRC, r0 + ld.usr r5, SRC, r0 NOP NOP NOP - ld.usr r6, SRC, r7 + ld.usr r6, SRC, r7 NOP NOP NOP #else - ld.usr r5, SRC, r0 - ld.usr r6, SRC, r7 + ld.usr r5, SRC, r0 + ld.usr r6, SRC, r7 #endif subu LEN, LEN, 8 st r5, DEST, r0 addu SRC, SRC, 8 st r6, DEST, r7 bcnd.n ne0, LEN, copyin_right_aligned_to_doubleword - addu DEST, DEST, 8 - or r2, r0, r0 /* successful return */ + addu DEST, DEST, 8 + or r2, r0, r0 /* successful return */ br .Lcidone - /***************************************************/ + /***************************************************/ copyin_left_align_to_halfword: #ifdef ERRATA__XXX_USR NOP - ld.b.usr r5, SRC, r0 + ld.b.usr r5, SRC, r0 NOP NOP NOP #else - ld.b.usr r5, SRC, r0 + ld.b.usr r5, SRC, r0 #endif subu LEN, LEN, 1 st.b r5, DEST, r0 addu SRC, SRC, 1 br.n copyin_left_aligned_to_halfword - addu DEST, DEST, 1 + addu DEST, DEST, 1 copyin_left_align_to_word: #ifdef ERRATA__XXX_USR NOP - ld.h.usr r5, SRC, r0 + ld.h.usr r5, SRC, r0 NOP NOP NOP #else - ld.h.usr r5, SRC, r0 + ld.h.usr r5, SRC, r0 #endif - subu LEN, LEN, 2 + subu LEN, LEN, 2 st.h r5, DEST, r0 addu SRC, SRC, 2 br.n copyin_left_aligned_to_word - addu DEST, DEST, 2 + addu DEST, DEST, 2 copyin_right_align_to_halfword: subu LEN, LEN, 1 #ifdef ERRATA__XXX_USR NOP - ld.b.usr r5, SRC, LEN + ld.b.usr r5, SRC, LEN NOP NOP NOP #else - ld.b.usr r5, SRC, LEN + ld.b.usr r5, SRC, LEN #endif br.n copyin_right_aligned_to_halfword - st.b r5, DEST, LEN + st.b r5, DEST, LEN copyin_right_align_to_word: subu LEN, LEN, 2 #ifdef ERRATA__XXX_USR NOP - ld.h.usr r5, SRC, LEN + ld.h.usr r5, SRC, LEN NOP NOP NOP #else - ld.h.usr r5, SRC, LEN + ld.h.usr r5, SRC, LEN #endif br.n copyin_right_aligned_to_word - st.h r5, DEST, LEN + st.h r5, DEST, LEN copyin_right_align_to_doubleword: subu LEN, LEN, 4 @@ -333,26 +335,26 @@ copyin_right_align_to_doubleword: ld.usr r5, SRC, LEN #endif bcnd.n ne0, LEN, copyin_right_aligned_to_doubleword - st r5, DEST, LEN + st r5, DEST, LEN or r2, r0, r0 /* successful return */ br .Lcidone copyin_byte_only: bcnd eq0, LEN, 2f - 1: +1: subu LEN, LEN, 1 #ifdef ERRATA__XXX_USR NOP - ld.b.usr r5, SRC, LEN + ld.b.usr r5, SRC, LEN NOP NOP NOP #else - ld.b.usr r5, SRC, LEN + ld.b.usr r5, SRC, LEN #endif bcnd.n ne0, LEN, 1b - st.b r5, DEST, LEN - 2: or r2, r0, r0 /* successful return */ + st.b r5, DEST, LEN +2: or r2, r0, r0 /* successful return */ br .Lcidone .Lcidone: or.u r5,r0,hi16(_curpcb) @@ -363,13 +365,13 @@ copyin_byte_only: or r2, r0, EFAULT /* return fault */ br .Lcidone -#undef SRC -#undef DEST -#undef LEN +#undef SRC +#undef DEST +#undef LEN /*######################################################################*/ /*######################################################################*/ -/* +/* * Copy a null terminated string from the user space to the kernel * address space. * @@ -380,15 +382,15 @@ copyin_byte_only: * r5 == len actually transferred (includes the terminating NULL!!!) * r6 & r7 - used as temporaries */ -#define SRC r2 -#define DEST r3 -#define CNT r4 -#define LEN r5 +#define SRC r2 +#define DEST r3 +#define CNT r4 +#define LEN r5 -ENTRY(copyinstr) +ENTRY(copyinstr) /* setup fault handler */ - or.u r6, r0, hi16(_curpcb) + or.u r6, r0, hi16(_curpcb) ld r7, r6, lo16(_curpcb) or.u r6, r0, hi16(.Lcisflt) or r6, r6, lo16(.Lcisflt) @@ -399,7 +401,7 @@ ENTRY(copyinstr) 1: #ifdef ERRATA__XXX_USR NOP - ld.bu.usr r7, SRC, r6 + ld.bu.usr r7, SRC, r6 NOP NOP NOP @@ -408,7 +410,7 @@ ENTRY(copyinstr) #endif st.b r7, DEST, r6 bcnd.n eq0, r7, 2f /* all done */ - addu r6, r6, 1 + addu r6, r6, 1 cmp r7, r6, CNT bb1 lt, r7, 1b @@ -421,12 +423,12 @@ ENTRY(copyinstr) subu r6, r6, 1 st.b r0, DEST, r6 /* clear last byte */ br.n .Lcisdone - addu r6, r6, 1 + addu r6, r6, 1 2: /* all done */ or r2, r0, 0 .Lcisdone: - bcnd eq0, LEN, 3f + bcnd eq0, LEN, 3f st r6, r0, LEN 3: or.u r5,r0,hi16(_curpcb) @@ -437,10 +439,10 @@ ENTRY(copyinstr) or r2, r0, EFAULT /* return fault */ br .Lcisnull -#undef SRC -#undef DEST -#undef CNT -#undef LEN +#undef SRC +#undef DEST +#undef CNT +#undef LEN /* * Copy specified amount of data from kernel to the user space @@ -450,31 +452,35 @@ ENTRY(copyinstr) * r4 == length */ -#define SRC r2 -#define DEST r3 -#define LEN r4 +#define SRC r2 +#define DEST r3 +#define LEN r4 ENTRY(copyout) /* setup fault handler */ -/* tb0 0, r0, 132 entry trap */ -/* SET_PCB_ONFAULT(r5, r6, .Lcoflt)*/ - or.u r5, r0, hi16(_curpcb) +#if 0 + tb0 0, r0, 132 /* entry trap */ + SET_PCB_ONFAULT(r5, r6, .Lcoflt) +#endif + or.u r5, r0, hi16(_curpcb) ld r6, r5, lo16(_curpcb) or.u r5, r0, hi16(.Lcoflt) or r5, r5, lo16(.Lcoflt) st r5, r6, PCB_ONFAULT /* pcb_onfault = .Lcoflt */ -/* ;bcnd ne0, LEN, 1f ; XXX optimize len = 0 case */ -/* ;or r2, r0, 0 */ -/* ;br .Lcodone */ - /*;1: ;bcnd lt0, LEN, .Lcoflt ; EFAULT if len < 0 */ +#if 0 + bcnd ne0, LEN, 1f /* XXX optimize len = 0 case */ + or r2, r0, 0 + br .Lcodone +1: bcnd lt0, LEN, .Lcoflt /* EFAULT if len < 0 */ +#endif /* If it's a small length (less than 8), then do byte-by-byte */ - cmp r9, LEN, 8 - bb1 lt, r9, copyout_byte_only + cmp r9, LEN, 8 + bb1 lt, r9, copyout_byte_only /* If they're not aligned similiarly, use byte only... */ - xor r9, SRC, DEST - mask r8, r9, 0x3 - bcnd ne0, r8, copyout_byte_only + xor r9, SRC, DEST + mask r8, r9, 0x3 + bcnd ne0, r8, copyout_byte_only /* * At this point, we don't know if they're word aligned or not, @@ -495,7 +501,7 @@ copyout_right_aligned_to_word: * boundry, and LEN is an even multiple of 4. */ bb1.n 2, LEN, copyout_right_align_to_doubleword - or r7, r0, 4 + or r7, r0, 4 copyout_right_aligned_to_doubleword: ld r5, SRC, r0 @@ -521,71 +527,71 @@ copyout_right_aligned_to_doubleword: st.usr r6, DEST, r7 #endif bcnd.n ne0, LEN, copyout_right_aligned_to_doubleword - addu DEST, DEST, 8 - or r2, r0, r0 /* successful return */ + addu DEST, DEST, 8 + or r2, r0, r0 /* successful return */ br .Lcodone /***************************************************/ copyout_left_align_to_halfword: - ld.b r5, SRC, r0 + ld.b r5, SRC, r0 subu LEN, LEN, 1 #ifdef ERRATA__XXX_USR NOP - st.b.usr r5, DEST, r0 + st.b.usr r5, DEST, r0 NOP NOP NOP #else - st.b.usr r5, DEST, r0 + st.b.usr r5, DEST, r0 #endif addu SRC, SRC, 1 br.n copyout_left_aligned_to_halfword - addu DEST, DEST, 1 + addu DEST, DEST, 1 copyout_left_align_to_word: - ld.h r5, SRC, r0 - subu LEN, LEN, 2 + ld.h r5, SRC, r0 + subu LEN, LEN, 2 #ifdef ERRATA__XXX_USR NOP - st.h.usr r5, DEST, r0 + st.h.usr r5, DEST, r0 NOP NOP NOP #else - st.h.usr r5, DEST, r0 + st.h.usr r5, DEST, r0 #endif addu SRC, SRC, 2 br.n copyout_left_aligned_to_word - addu DEST, DEST, 2 + addu DEST, DEST, 2 copyout_right_align_to_halfword: subu LEN, LEN, 1 - ld.b r5, SRC, LEN + ld.b r5, SRC, LEN #ifdef ERRATA__XXX_USR - NOP - st.b.usr r5, DEST, LEN + NOP + st.b.usr r5, DEST, LEN NOP NOP NOP br copyout_right_aligned_to_halfword #else br.n copyout_right_aligned_to_halfword - st.b.usr r5, DEST, LEN + st.b.usr r5, DEST, LEN #endif copyout_right_align_to_word: subu LEN, LEN, 2 - ld.h r5, SRC, LEN + ld.h r5, SRC, LEN #ifdef ERRATA__XXX_USR - NOP - st.h.usr r5, DEST, LEN + NOP + st.h.usr r5, DEST, LEN NOP NOP NOP br copyout_right_aligned_to_word -#else +#else br.n copyout_right_aligned_to_word - st.h.usr r5, DEST, LEN + st.h.usr r5, DEST, LEN #endif copyout_right_align_to_doubleword: @@ -600,29 +606,29 @@ copyout_right_align_to_doubleword: bcnd ne0, LEN, copyout_right_aligned_to_doubleword #else bcnd.n ne0, LEN, copyout_right_aligned_to_doubleword - st.usr r5, DEST, LEN + st.usr r5, DEST, LEN #endif - or r2, r0, r0 /* successful return */ + or r2, r0, r0 /* successful return */ br .Lcodone ASGLOBAL(copyout_byte_only) bcnd eq0, LEN, 2f - 1: +1: subu LEN, LEN, 1 - ld.b r5, SRC, LEN + ld.b r5, SRC, LEN #ifdef ERRATA__XXX_USR NOP - st.b.usr r5, DEST, LEN + st.b.usr r5, DEST, LEN NOP NOP NOP bcnd ne0, LEN, 1b #else bcnd.n ne0, LEN, 1b - st.b.usr r5, DEST, LEN + st.b.usr r5, DEST, LEN #endif - 2: or r2, r0, r0 /* successful return */ +2: or r2, r0, r0 /* successful return */ br .Lcodone .Lcodone: @@ -634,11 +640,11 @@ ASGLOBAL(copyout_byte_only) or r2, r0, EFAULT /* return fault */ br .Lcodone -#undef SRC -#undef DEST -#undef LEN +#undef SRC +#undef DEST +#undef LEN -/* +/* * Copy a null terminated string from the kernel space to the user * address space. * @@ -649,14 +655,14 @@ ASGLOBAL(copyout_byte_only) * r5 == len actually copied (including the terminating NULL!!!) */ -#define SRC r2 -#define DEST r3 -#define CNT r4 -#define LEN r5 +#define SRC r2 +#define DEST r3 +#define CNT r4 +#define LEN r5 ENTRY(copyoutstr) /* setup fault handler */ - or.u r6, r0, hi16(_curpcb) + or.u r6, r0, hi16(_curpcb) ld r7, r6, lo16(_curpcb) or.u r6, r0, hi16(.Lcosflt) or r6, r6, lo16(.Lcosflt) @@ -664,24 +670,24 @@ ENTRY(copyoutstr) bcnd lt0, CNT, .Lcosflt bcnd eq0, CNT, .Lcosdone or r6, r0, 0 - 1: +1: ld.bu r7, SRC, r6 #ifdef ERRATA__XXX_USR NOP - st.b.usr r7, DEST, r6 + st.b.usr r7, DEST, r6 NOP NOP NOP #else - st.b.usr r7, DEST, r6 + st.b.usr r7, DEST, r6 #endif bcnd.n eq0, r7, 2f /* all done */ - addu r6, r6, 1 + addu r6, r6, 1 cmp r7, r6, CNT bb1 lt, r7, 1b or r2, r0, ENAMETOOLONG /* over flow */ br .Lcosdone - 2: /* all done */ +2: /* all done */ or r2, r0, 0 br .Lcosdone @@ -690,17 +696,17 @@ ENTRY(copyoutstr) br .Lcosdone .Lcosdone: - bcnd eq0, LEN, 3f + bcnd eq0, LEN, 3f st r6, r0, LEN - 3: or.u r5,r0,hi16(_curpcb) +3: or.u r5,r0,hi16(_curpcb) ld r6,r5,lo16(_curpcb) st r0,r6,PCB_ONFAULT /* clear the handler */ jmp r1 -#undef SRC -#undef DEST -#undef CNT -#undef LEN +#undef SRC +#undef DEST +#undef CNT +#undef LEN /*######################################################################*/ @@ -710,23 +716,23 @@ ENTRY(copyoutstr) * Copy len bytes from src to dst, aborting if we encounter a page fault. */ ENTRY(kcopy) - or.u r5, r0, hi16(_curpcb) + or.u r5, r0, hi16(_curpcb) ld r6, r5, lo16(_curpcb) or.u r5, r0, hi16(kcopy_fault) or r5, r5, lo16(kcopy_fault) st r5, r6, PCB_ONFAULT /* pcb_onfault = kcopy_fault */ - bcnd le0,r4,kcopy_out /* nothing to do if count <= 0 */ + bcnd le0,r4,kcopy_out /* nothing to do if count <= 0 */ /* * check position of source and destination data */ cmp r9,r2,r3 /* compare source address to destination */ - bb1 eq,r9,kcopy_out /* nothing to do if addresses are equal */ - bb1 lo,r9,kcopy_reverse /* copy in reverse if src < destination */ + bb1 eq,r9,kcopy_out /* nothing to do if addresses are equal */ + bb1 lo,r9,kcopy_reverse /* copy in reverse if src < dest */ /* - * source address is greater than destination address, copy forward + * source address is greater than destination address, copy forward */ cmp r9,r4,16 /* see if we have at least 16 bytes */ - bb1 lt,r9,kf_byte_copy /* copy bytes for small data length */ + bb1 lt,r9,kf_byte_copy /* copy bytes for small data length */ /* * determine copy strategy based on alignment of source and destination */ @@ -734,8 +740,8 @@ ENTRY(kcopy) mask r7,r3,3 /* get 2 low order bits of destintation addr */ mak r6,r6,0<4> /* convert source bits to table offset */ mak r7,r7,0<2> /* convert destination bits to table offset */ - or.u r12,r0,hi16(kf_strat) /* forward strategy table address (high) */ - or r12,r12,lo16(kf_strat) /* forward strategy table address (low) */ + or.u r12,r0,hi16(kf_strat) /* forward strategy table address (high) */ + or r12,r12,lo16(kf_strat) /* forward strategy table address (low) */ addu r6,r6,r7 /* compute final table offset for strategy */ ld r12,r12,r6 /* load the strategy routine */ jmp r12 /* branch to strategy routine */ @@ -753,7 +759,7 @@ ASGLOBAL(kf_3byte_word_copy) addu r2,r2,3 /* increment source pointer */ addu r3,r3,3 /* increment destination pointer */ br.n kf_word_copy /* copy full words */ - subu r4,r4,3 /* decrement length */ + subu r4,r4,3 /* decrement length */ /* * Copy 1 halfword from src to destination then copy words @@ -764,9 +770,9 @@ ASGLOBAL(kf_1half_word_copy) addu r2,r2,2 /* increment source pointer */ addu r3,r3,2 /* increment destination pointer */ br.n kf_word_copy /* copy full words */ - subu r4,r4,2 /* decrement remaining length */ + subu r4,r4,2 /* decrement remaining length */ -/* +/* * Copy 1 byte from src to destination then copy words */ ASGLOBAL(kf_1byte_word_copy) @@ -778,9 +784,9 @@ ASGLOBAL(kf_1byte_word_copy) /* fall through to word copy */ /* * Copy as many full words as possible, 4 words per loop - */ + */ ASGLOBAL(kf_word_copy) - cmp r10,r4,16 /* see if we have 16 bytes remaining */ + cmp r10,r4,16 /* see if we have 16 bytes remaining */ bb1 lo,r10,kf_byte_copy /* not enough left, copy bytes */ ld r6,r2,0 /* load first word */ ld r7,r2,4 /* load second word */ @@ -793,8 +799,8 @@ ASGLOBAL(kf_word_copy) addu r2,r2,16 /* increment source pointer */ addu r3,r3,16 /* increment destination pointer */ br.n kf_word_copy /* branch to copy another block */ - subu r4,r4,16 /* decrement remaining length */ - + subu r4,r4,16 /* decrement remaining length */ + ASGLOBAL(kf_1byte_half_copy) ld.bu r6,r2,0 /* load 1 byte from source */ st.b r6,r3,0 /* store 1 byte to destination */ @@ -804,8 +810,8 @@ ASGLOBAL(kf_1byte_half_copy) /* fall through to half copy */ ASGLOBAL(kf_half_copy) - cmp r10,r4,16 /* see if we have 16 bytes remaining */ - bb1 lo,r10,kf_byte_copy /* not enough left, copy bytes */ + cmp r10,r4,16 /* see if we have 16 bytes remaining */ + bb1 lo,r10,kf_byte_copy /* not enough left, copy bytes */ ld.hu r6,r2,0 /* load first half-word */ ld.hu r7,r2,2 /* load second half-word */ ld.hu r8,r2,4 /* load third half-word */ @@ -825,23 +831,23 @@ ASGLOBAL(kf_half_copy) addu r2,r2,16 /* increment source pointer */ addu r3,r3,16 /* increment destination pointer */ br.n kf_half_copy /* branch to copy another block */ - subu r4,r4,16 /* decrement remaining length */ - + subu r4,r4,16 /* decrement remaining length */ + ASGLOBAL(kf_byte_copy) - bcnd eq0,r4,kcopy_out /* branch if nothing left to copy */ + bcnd eq0,r4,kcopy_out /* branch if nothing left to copy */ ld.bu r6,r2,0 /* load byte from source */ st.b r6,r3,0 /* store byte in destination */ addu r2,r2,1 /* increment source pointer */ addu r3,r3,1 /* increment destination pointer */ - br.n kf_byte_copy /* branch for next byte */ - subu r4,r4,1 /* decrement remaining length */ + br.n kf_byte_copy /* branch for next byte */ + subu r4,r4,1 /* decrement remaining length */ /* * source address is less than destination address, copy in reverse */ ASGLOBAL(kcopy_reverse) /* - * start copy pointers at end of data + * start copy pointers at end of data */ addu r2,r2,r4 /* start source at end of data */ addu r3,r3,r4 /* start destination at end of data */ @@ -849,7 +855,7 @@ ASGLOBAL(kcopy_reverse) * check for short data */ cmp r9,r4,16 /* see if we have at least 16 bytes */ - bb1 lt,r9,kr_byte_copy /* copy bytes for small data length */ + bb1 lt,r9,kr_byte_copy /* copy bytes for small data length */ /* * determine copy strategy based on alignment of source and destination */ @@ -857,8 +863,8 @@ ASGLOBAL(kcopy_reverse) mask r7,r3,3 /* get 2 low order bits of destintation addr */ mak r6,r6,0<4> /* convert source bits to table offset */ mak r7,r7,0<2> /* convert destination bits to table offset */ - or.u r12,r0,hi16(kr_strat) /* reverse strategy table address (high) */ - or r12,r12,lo16(kr_strat) /* reverse strategy table address (low) */ + or.u r12,r0,hi16(kr_strat) /* reverse strategy table address (high) */ + or r12,r12,lo16(kr_strat) /* reverse strategy table address (low) */ addu r6,r6,r7 /* compute final table offset for strategy */ ld r12,r12,r6 /* load the strategy routine */ jmp r12 /* branch to strategy routine */ @@ -876,7 +882,7 @@ ASGLOBAL(kr_3byte_word_copy) st.b r7,r3,1 /* store byte to destination */ st.b r8,r3,2 /* store byte to destination */ br.n kr_word_copy /* copy full words */ - subu r4,r4,3 /* decrement length */ + subu r4,r4,3 /* decrement length */ /* * Copy 1 halfword from src to destination then copy words @@ -887,9 +893,9 @@ ASGLOBAL(kr_1half_word_copy) ld.hu r6,r2,0 /* load half-word from source */ st.h r6,r3,0 /* store half-word to destination */ br.n kr_word_copy /* copy full words */ - subu r4,r4,2 /* decrement remaining length */ + subu r4,r4,2 /* decrement remaining length */ -/* +/* * Copy 1 byte from src to destination then copy words */ ASGLOBAL(kr_1byte_word_copy) @@ -901,10 +907,10 @@ ASGLOBAL(kr_1byte_word_copy) /* fall through to word copy */ /* * Copy as many full words as possible, 4 words per loop - */ + */ ASGLOBAL(kr_word_copy) - cmp r10,r4,16 /* see if we have 16 bytes remaining */ - bb1 lo,r10,kr_byte_copy /* not enough left, copy bytes */ + cmp r10,r4,16 /* see if we have 16 bytes remaining */ + bb1 lo,r10,kr_byte_copy /* not enough left, copy bytes */ subu r2,r2,16 /* decrement source pointer */ subu r3,r3,16 /* decrement destination pointer */ ld r6,r2,0 /* load first word */ @@ -916,8 +922,8 @@ ASGLOBAL(kr_word_copy) st r8,r3,8 /* store third word */ st r9,r3,12 /* store fourth word */ br.n kr_word_copy /* branch to copy another block */ - subu r4,r4,16 /* decrement remaining length */ - + subu r4,r4,16 /* decrement remaining length */ + ASGLOBAL(kr_1byte_half_copy) subu r2,r2,1 /* decrement source pointer */ subu r3,r3,1 /* decrement destination pointer */ @@ -927,8 +933,8 @@ ASGLOBAL(kr_1byte_half_copy) /* fall through to half copy */ ASGLOBAL(kr_half_copy) - cmp r10,r4,16 /* see if we have 16 bytes remaining */ - bb1 lo,r10,kr_byte_copy /* not enough left, copy bytes */ + cmp r10,r4,16 /* see if we have 16 bytes remaining */ + bb1 lo,r10,kr_byte_copy /* not enough left, copy bytes */ subu r2,r2,16 /* decrement source pointer */ subu r3,r3,16 /* decrement destination pointer */ ld.hu r6,r2,0 /* load first half-word */ @@ -948,20 +954,20 @@ ASGLOBAL(kr_half_copy) st.h r12,r3,12 /* store seventh half-word */ st.h r13,r3,14 /* store eighth half-word */ br.n kr_half_copy /* branch to copy another block */ - subu r4,r4,16 /* decrement remaining length */ - + subu r4,r4,16 /* decrement remaining length */ + ASGLOBAL(kr_byte_copy) - bcnd eq0,r4,kcopy_out /* branch if nothing left to copy */ + bcnd eq0,r4,kcopy_out /* branch if nothing left to copy */ subu r2,r2,1 /* decrement source pointer */ subu r3,r3,1 /* decrement destination pointer */ ld.bu r6,r2,0 /* load byte from source */ st.b r6,r3,0 /* store byte in destination */ - br.n kr_byte_copy /* branch for next byte */ - subu r4,r4,1 /* decrement remaining length */ + br.n kr_byte_copy /* branch for next byte */ + subu r4,r4,1 /* decrement remaining length */ ASGLOBAL(kcopy_out) or r2, r0, 0 /* return success */ -ASGLOBAL(kcopy_out_fault) +ASGLOBAL(kcopy_out_fault) or.u r5,r0,hi16(_curpcb) ld r6,r5,lo16(_curpcb) st r0,r6,PCB_ONFAULT /* clear the handler */ @@ -969,8 +975,8 @@ ASGLOBAL(kcopy_out_fault) ASGLOBAL(kcopy_fault) or r2, r0, EFAULT /* return fault */ - br kcopy_out_fault - + br kcopy_out_fault + data align 4 ASGLOBAL(kf_strat) @@ -1012,13 +1018,13 @@ ASGLOBAL(kr_strat) text #ifdef notyet /* This give a stack problem. For now, use the above */ ENTRY(kcopy) - or.u r5, r0, hi16(_curpcb) + or.u r5, r0, hi16(_curpcb) ld r6, r5, lo16(_curpcb) or.u r5, r0, hi16(kcfault) or r5, r5, lo16(kcfault) st r5, r6, PCB_ONFAULT /* pcb_onfault = kcfault */ subu r31, r31, 40 - bsr _ovbcopy /* call ovbcopy */ + bsr _ovbcopy /* call ovbcopy */ addu r31, r31, 40 or r2, r0, 0 /* return success */ kcdone: @@ -1032,20 +1038,20 @@ kcfault: #endif /* 0 */ /* - * Gcc 2 generates calls to memcpy for bcopies of unknown size. memcpy - * can simply be implemented as ovbcopy but the src (r2, r3) and dst args need to - * be switched. + * Gcc 2 generates calls to memcpy for bcopies of unknown size. memcpy can + * simply be implemented as ovbcopy but the src (r2, r3) and dst args need to + * be switched. */ /* * void memcpy(dest, source, count) * */ ENTRY(memcpy) - or r5, r0, r2 /* dst -> tmp */ - or r2, r0, r3 /* src -> 1st arg */ - br.n _ovbcopy /* call ovbcopy */ - or r3, r0, r5 /* dst -> 2nd arg */ - + or r5, r0, r2 /* dst -> tmp */ + or r2, r0, r3 /* src -> 1st arg */ + br.n _ovbcopy /* call ovbcopy */ + or r3, r0, r5 /* dst -> 2nd arg */ + /* * void bcopy(source, destination, count) * @@ -1056,18 +1062,18 @@ ENTRY(memcpy) ENTRY(bcopy) ENTRY(ovbcopy) - bcnd le0,r4,bcopy_out /* nothing to do if count <= 0 */ + bcnd le0,r4,bcopy_out /* nothing to do if count <= 0 */ /* * check position of source and destination data */ cmp r9,r2,r3 /* compare source address to destination */ - bb1 eq,r9,bcopy_out /* nothing to do if addresses are equal */ - bb1 lo,r9,bcopy_reverse /* copy in reverse if src < destination */ + bb1 eq,r9,bcopy_out /* nothing to do if addresses are equal */ + bb1 lo,r9,bcopy_reverse /* copy in reverse if src < dest */ /* - * source address is greater than destination address, copy forward + * source address is greater than destination address, copy forward */ cmp r9,r4,16 /* see if we have at least 16 bytes */ - bb1 lt,r9,f_byte_copy /* copy bytes for small data length */ + bb1 lt,r9,f_byte_copy /* copy bytes for small data length */ /* * determine copy strategy based on alignment of source and destination */ @@ -1075,8 +1081,8 @@ ENTRY(ovbcopy) mask r7,r3,3 /* get 2 low order bits of destintation addr */ mak r6,r6,0<4> /* convert source bits to table offset */ mak r7,r7,0<2> /* convert destination bits to table offset */ - or.u r12,r0,hi16(f_strat) /* forward strategy table address (high) */ - or r12,r12,lo16(f_strat) /* forward strategy table address (low) */ + or.u r12,r0,hi16(f_strat) /* forward strategy table address (high) */ + or r12,r12,lo16(f_strat) /* forward strategy table address (low) */ addu r6,r6,r7 /* compute final table offset for strategy */ ld r12,r12,r6 /* load the strategy routine */ jmp r12 /* branch to strategy routine */ @@ -1095,7 +1101,7 @@ ASGLOBAL(f_3byte_word_copy) addu r2,r2,3 /* increment source pointer */ addu r3,r3,3 /* increment destination pointer */ br.n f_word_copy /* copy full words */ - subu r4,r4,3 /* decrement length */ + subu r4,r4,3 /* decrement length */ /* * Copy 1 halfword from src to destination then copy words @@ -1106,9 +1112,9 @@ ASGLOBAL(f_1half_word_copy) addu r2,r2,2 /* increment source pointer */ addu r3,r3,2 /* increment destination pointer */ br.n f_word_copy /* copy full words */ - subu r4,r4,2 /* decrement remaining length */ + subu r4,r4,2 /* decrement remaining length */ -/* +/* * Copy 1 byte from src to destination then copy words */ ASGLOBAL(f_1byte_word_copy) @@ -1120,10 +1126,10 @@ ASGLOBAL(f_1byte_word_copy) /* fall through to word copy */ /* * Copy as many full words as possible, 4 words per loop - */ + */ ASGLOBAL(f_word_copy) - cmp r10,r4,16 /* see if we have 16 bytes remaining */ - bb1 lo,r10,f_byte_copy /* not enough left, copy bytes */ + cmp r10,r4,16 /* see if we have 16 bytes remaining */ + bb1 lo,r10,f_byte_copy /* not enough left, copy bytes */ ld r6,r2,0 /* load first word */ ld r7,r2,4 /* load second word */ ld r8,r2,8 /* load third word */ @@ -1135,8 +1141,8 @@ ASGLOBAL(f_word_copy) addu r2,r2,16 /* increment source pointer */ addu r3,r3,16 /* increment destination pointer */ br.n f_word_copy /* branch to copy another block */ - subu r4,r4,16 /* decrement remaining length */ - + subu r4,r4,16 /* decrement remaining length */ + ASGLOBAL(f_1byte_half_copy) ld.bu r6,r2,0 /* load 1 byte from source */ st.b r6,r3,0 /* store 1 byte to destination */ @@ -1146,8 +1152,8 @@ ASGLOBAL(f_1byte_half_copy) /* fall through to half copy */ ASGLOBAL(f_half_copy) - cmp r10,r4,16 /* see if we have 16 bytes remaining */ - bb1 lo,r10,f_byte_copy /* not enough left, copy bytes */ + cmp r10,r4,16 /* see if we have 16 bytes remaining */ + bb1 lo,r10,f_byte_copy /* not enough left, copy bytes */ ld.hu r6,r2,0 /* load first half-word */ ld.hu r7,r2,2 /* load second half-word */ ld.hu r8,r2,4 /* load third half-word */ @@ -1167,23 +1173,23 @@ ASGLOBAL(f_half_copy) addu r2,r2,16 /* increment source pointer */ addu r3,r3,16 /* increment destination pointer */ br.n f_half_copy /* branch to copy another block */ - subu r4,r4,16 /* decrement remaining length */ - + subu r4,r4,16 /* decrement remaining length */ + ASGLOBAL(f_byte_copy) - bcnd eq0,r4,bcopy_out /* branch if nothing left to copy */ + bcnd eq0,r4,bcopy_out /* branch if nothing left to copy */ ld.bu r6,r2,0 /* load byte from source */ st.b r6,r3,0 /* store byte in destination */ addu r2,r2,1 /* increment source pointer */ addu r3,r3,1 /* increment destination pointer */ - br.n f_byte_copy /* branch for next byte */ - subu r4,r4,1 /* decrement remaining length */ + br.n f_byte_copy /* branch for next byte */ + subu r4,r4,1 /* decrement remaining length */ /* * source address is less than destination address, copy in reverse */ ASGLOBAL(bcopy_reverse) /* - * start copy pointers at end of data + * start copy pointers at end of data */ addu r2,r2,r4 /* start source at end of data */ addu r3,r3,r4 /* start destination at end of data */ @@ -1191,7 +1197,7 @@ ASGLOBAL(bcopy_reverse) * check for short data */ cmp r9,r4,16 /* see if we have at least 16 bytes */ - bb1 lt,r9,r_byte_copy /* copy bytes for small data length */ + bb1 lt,r9,r_byte_copy /* copy bytes for small data length */ /* * determine copy strategy based on alignment of source and destination */ @@ -1199,8 +1205,8 @@ ASGLOBAL(bcopy_reverse) mask r7,r3,3 /* get 2 low order bits of destintation addr */ mak r6,r6,0<4> /* convert source bits to table offset */ mak r7,r7,0<2> /* convert destination bits to table offset */ - or.u r12,r0,hi16(r_strat) /* reverse strategy table address (high) */ - or r12,r12,lo16(r_strat) /* reverse strategy table address (low) */ + or.u r12,r0,hi16(r_strat) /* reverse strategy table address (high) */ + or r12,r12,lo16(r_strat) /* reverse strategy table address (low) */ addu r6,r6,r7 /* compute final table offset for strategy */ ld r12,r12,r6 /* load the strategy routine */ jmp r12 /* branch to strategy routine */ @@ -1218,7 +1224,7 @@ ASGLOBAL(r_3byte_word_copy) st.b r7,r3,1 /* store byte to destination */ st.b r8,r3,2 /* store byte to destination */ br.n r_word_copy /* copy full words */ - subu r4,r4,3 /* decrement length */ + subu r4,r4,3 /* decrement length */ /* * Copy 1 halfword from src to destination then copy words @@ -1229,9 +1235,9 @@ ASGLOBAL(r_1half_word_copy) ld.hu r6,r2,0 /* load half-word from source */ st.h r6,r3,0 /* store half-word to destination */ br.n r_word_copy /* copy full words */ - subu r4,r4,2 /* decrement remaining length */ + subu r4,r4,2 /* decrement remaining length */ -/* +/* * Copy 1 byte from src to destination then copy words */ ASGLOBAL(r_1byte_word_copy) @@ -1243,10 +1249,10 @@ ASGLOBAL(r_1byte_word_copy) /* fall through to word copy */ /* * Copy as many full words as possible, 4 words per loop - */ + */ ASGLOBAL(r_word_copy) - cmp r10,r4,16 /* see if we have 16 bytes remaining */ - bb1 lo,r10,r_byte_copy /* not enough left, copy bytes */ + cmp r10,r4,16 /* see if we have 16 bytes remaining */ + bb1 lo,r10,r_byte_copy /* not enough left, copy bytes */ subu r2,r2,16 /* decrement source pointer */ subu r3,r3,16 /* decrement destination pointer */ ld r6,r2,0 /* load first word */ @@ -1258,8 +1264,8 @@ ASGLOBAL(r_word_copy) st r8,r3,8 /* store third word */ st r9,r3,12 /* store fourth word */ br.n r_word_copy /* branch to copy another block */ - subu r4,r4,16 /* decrement remaining length */ - + subu r4,r4,16 /* decrement remaining length */ + ASGLOBAL(r_1byte_half_copy) subu r2,r2,1 /* decrement source pointer */ subu r3,r3,1 /* decrement destination pointer */ @@ -1269,8 +1275,8 @@ ASGLOBAL(r_1byte_half_copy) /* fall through to half copy */ ASGLOBAL(r_half_copy) - cmp r10,r4,16 /* see if we have 16 bytes remaining */ - bb1 lo,r10,r_byte_copy /* not enough left, copy bytes */ + cmp r10,r4,16 /* see if we have 16 bytes remaining */ + bb1 lo,r10,r_byte_copy /* not enough left, copy bytes */ subu r2,r2,16 /* decrement source pointer */ subu r3,r3,16 /* decrement destination pointer */ ld.hu r6,r2,0 /* load first half-word */ @@ -1290,20 +1296,20 @@ ASGLOBAL(r_half_copy) st.h r12,r3,12 /* store seventh half-word */ st.h r13,r3,14 /* store eighth half-word */ br.n r_half_copy /* branch to copy another block */ - subu r4,r4,16 /* decrement remaining length */ - + subu r4,r4,16 /* decrement remaining length */ + ASGLOBAL(r_byte_copy) - bcnd eq0,r4,bcopy_out /* branch if nothing left to copy */ + bcnd eq0,r4,bcopy_out /* branch if nothing left to copy */ subu r2,r2,1 /* decrement source pointer */ subu r3,r3,1 /* decrement destination pointer */ ld.bu r6,r2,0 /* load byte from source */ st.b r6,r3,0 /* store byte in destination */ - br.n r_byte_copy /* branch for next byte */ - subu r4,r4,1 /* decrement remaining length */ + br.n r_byte_copy /* branch for next byte */ + subu r4,r4,1 /* decrement remaining length */ ASGLOBAL(bcopy_out) jmp r1 /* all done, return to caller */ - + data align 4 ASGLOBAL(f_strat) @@ -1345,7 +1351,6 @@ ASGLOBAL(r_strat) text /*######################################################################*/ -/*######################################################################*/ /* * April 1990, Omron Corporation @@ -1387,13 +1392,13 @@ ENTRY(bzero) */ or.u R_mark_address, r0, hi16(mark) or R_mark_address, R_mark_address, lo16(mark) - + top_of_main_loop: #define MAX_AT_ONE_TIME 128 /* * Now we find out how many words we can zero-fill in a row. * We do this by doing something like: - * + * * bytes &= 0xfffffffc; * if (bytes > MAX_AT_ONE_TIME) * bytes = MAX_AT_ONE_TIME; @@ -1425,8 +1430,8 @@ ENTRY(bzero) * so if you change things here, WATCH OUT. */ br.n do_max - or R_bytes, r0, MAX_AT_ONE_TIME - + or R_bytes, r0, MAX_AT_ONE_TIME + 1: /* @@ -1441,7 +1446,7 @@ ENTRY(bzero) /* and go there (after adjusting the length via ".n") */ jmp.n R_addr -do_max: subu R_len, R_len, R_bytes /* NOTE: this is in the delay slot! */ +do_max: subu R_len, R_len, R_bytes /* NOTE: this is in the delay slot! */ st r0, R_dest, 0x7c /* 128 */ st r0, R_dest, 0x78 /* 124 */ @@ -1476,25 +1481,23 @@ do_max: subu R_len, R_len, R_bytes /* NOTE: this is in the delay slot! */ st r0, R_dest, 0x04 /* 4 */ st r0, R_dest, 0x00 /* 0 */ - mark: +mark: br.n top_of_main_loop - addu R_dest, R_dest, R_bytes /* bump up the dest address */ + addu R_dest, R_dest, R_bytes /* bump up the dest address */ - - - done_doing_words: +done_doing_words: bcnd ne0, R_len, finish_up_last_bytes - jmp r1 /* RETURN */ + jmp r1 - finish_up_last_bytes: +finish_up_last_bytes: subu R_len, R_len, 1 bcnd.n ne0, R_len, finish_up_last_bytes - st.b r0, R_dest, R_len + st.b r0, R_dest, R_len + +leave: + jmp r1 - leave: - jmp r1 /* RETURN */ - - not_initially_word_aligned: +not_initially_word_aligned: /* * Bzero to word-align the address (at least if the length allows it). */ @@ -1503,20 +1506,16 @@ do_max: subu R_len, R_len, R_bytes /* NOTE: this is in the delay slot! */ addu R_dest, R_dest, 1 mask R_temp, R_dest, 0x3 bcnd.n eq0, R_temp, now_word_aligned - subu R_len, R_len, 1 + subu R_len, R_len, 1 br not_initially_word_aligned -#undef R_dest -#undef R_len -#undef R_bytes -#undef R_mark_address -#undef R_addr -#undef R_temp -#undef MAX_AT_ONE_TIME - -/**********************************************************************/ -/**********************************************************************/ -/**********************************************************************/ +#undef R_dest +#undef R_len +#undef R_bytes +#undef R_mark_address +#undef R_addr +#undef R_temp +#undef MAX_AT_ONE_TIME /* * non-local goto @@ -1545,7 +1544,7 @@ _setjmp: st r30,r2,17*4 st r31,r2,18*4 jmp.n r1 - or r2,r0,r0 + or r2,r0,r0 global _longjmp _longjmp: @@ -1569,7 +1568,7 @@ _longjmp: ld r30,r2,17*4 ld r31,r2,18*4 jmp.n r1 - or r2,r0,1 + or r2,r0,1 ENTRY(longjmp_int_enable) ld r1,r2,0 @@ -1609,21 +1608,21 @@ ENTRY(getsp) * that pte. It also returns the pte found in the table. */ ENTRY(invalidate_pte) - or r3,r0,r0 - xmem r3,r2,r0 - tb1 0,r0,0 - jmp.n r1 - or r2,r3,r0 + or r3,r0,r0 + xmem r3,r2,r0 + tb1 0,r0,0 + jmp.n r1 + or r2,r3,r0 -#if DDB +#ifdef DDB ENTRY(db_flush_pipeline) - FLUSH_PIPELINE + FLUSH_PIPELINE jmp r1 -#endif /* DDB */ +#endif /* DDB */ ENTRY(read_processor_identification_register) - jmp.n r1 - ldcr r2, PID + jmp.n r1 + ldcr r2, PID ENTRY(safe_byte_access) ld.b r9,r0,r2 @@ -1661,32 +1660,27 @@ ENTRY(guarded_access_start) ENTRY(guarded_access_bad) jmp.n r1 - or r2,r0,14 + or r2,r0,14 @L142: ENTRY(guarded_access_end) jmp.n r1 - or r2,r0,0 - -/************************************************************************* - ************************************************************************* - ** - ** void set_cpu_number(unsigned number); - ** - ** Sets the kernel cpu number for this cpu to the given value. - ** - ** Input: - ** r1 return address - ** r2 the number (should be 0, 1, 2, or 3). - ** - ** Other registers used: - ** r3 temp - ** r4 original PSR - ** r5 temporary new PSR - ** - ** Output: - ** none - **/ + or r2,r0,0 + +/* + * void set_cpu_number(unsigned number); + * + * Sets the kernel cpu number for this cpu to the given value. + * + * Input: + * r1 return address + * r2 the number (should be 0, 1, 2, or 3). + * + * Other registers used: + * r3 temp + * r4 original PSR + * r5 temporary new PSR + */ ENTRY(set_cpu_number) /* make sure the CPU number is valid */ clr r3, r2, FLAG_CPU_FIELD_WIDTH<0> @@ -1703,16 +1697,15 @@ ENTRY(set_cpu_number) clr r3, r3, FLAG_CPU_FIELD_WIDTH<0> /* clean the slate */ or r3, r3, r2 /* add the cpu number */ stcr r3, SR1 /* put back */ - + /* put back the PSR to what it was before and return */ stcr r4, PSR jmp r1 -1: /* bad cpu number*/ +1: /* bad cpu number*/ or.u r2, r0, hi16(1f) bsr.n _panic - or r2, r2, lo16(1f) + or r2, r2, lo16(1f) 1: string "set_cpu_number: bad CPU number\0" align 4 /* will not return */ - diff --git a/sys/arch/mvme88k/mvme88k/process.S b/sys/arch/mvme88k/mvme88k/process.S index 46600092ba0..beec7ec39ed 100644 --- a/sys/arch/mvme88k/mvme88k/process.S +++ b/sys/arch/mvme88k/mvme88k/process.S @@ -1,4 +1,4 @@ -/* $OpenBSD: process.S,v 1.15 2001/12/22 09:49:39 smurph Exp $ */ +/* $OpenBSD: process.S,v 1.16 2003/08/03 23:34:09 miod Exp $ */ /* * Copyright (c) 1996 Nivas Madhur * All rights reserved. @@ -36,26 +36,26 @@ #include data - align 4 + align 4 swchanpanic: - string "switch wchan %x" - align 4 + string "switch wchan %x" + align 4 swsrunpanic: string "switch SRUN %x" text - align 8 + align 8 Lswchanpanic: - or.u r2, r0, hi16(swchanpanic) - or r2, r2, lo16(swchanpanic) - or r3, r0, r9 - bsr _panic + or.u r2, r0, hi16(swchanpanic) + or r2, r2, lo16(swchanpanic) + or r3, r0, r9 + bsr _panic Lswsrunpanic: - or.u r2, r0, hi16(swsrunpanic) - or r2, r2, lo16(swsrunpanic) - or r3, r0, r9 - bsr _panic + or.u r2, r0, hi16(swsrunpanic) + or r2, r2, lo16(swsrunpanic) + or r3, r0, r9 + bsr _panic /* * At exit of a process, do a cpu_switch for the last time. * The mapping of the pcb at p->p_addr has already been deleted, @@ -76,7 +76,7 @@ ENTRY(switch_exit) st r30, r10,lo16(_curpcb) /* curpcb = &idle_u */ or.u r10, r0, hi16(_curproc) st r0, r10, lo16(_curproc) /* curproc = NULL */ - + /* Schedule the vmspace and stack to be freed. */ bsr.n _exit2 /* call exit2(p); */ subu r31, r31, 48 /* allocate stack */ @@ -98,7 +98,7 @@ ASGLOBAL(idle) /* spin reading whichqs until != 0 */ 1: or.u r10, r0, hi16(_whichqs) - ld r11, r10,lo16(_whichqs) + ld r11, r10,lo16(_whichqs) bcnd eq0, r11, 1b bsr.n _setipl or r2, r0, IPL_HIGH /* block all ints */ @@ -154,7 +154,7 @@ Lidleloop: bcnd ne0, r7, Ldoneloop Lloopchk: /* if whichqs is zero, keep checking */ - bsr.n _setipl /* enable all ints */ + bsr.n _setipl /* enable all ints */ or r2, r0, 0 br Lidleloop @@ -170,14 +170,14 @@ Ldoneloop: bcnd eq0, r7, Lloopchk /* keep spinning for whichqs to be !=0*/ xor r6, r6, r6 /* set r6 to 0 */ - 1: bb1 0, r7, 2f /* if rightmost bit set, done */ +1: bb1 0, r7, 2f /* if rightmost bit set, done */ extu r7, r7, 0<1> /* else, right shift whichqs, */ br.n 1b /* increment r6, and repeat */ addu r6, r6, 1 - 2: +2: or.u r7, r0, hi16(_qs) or r7, r7, lo16(_qs) - + /* * Need to make * p->p_forw->p_back = p->p_back and @@ -190,21 +190,21 @@ Ldoneloop: ld r9, r8, P_FORW /* r8 is q, r9 is p */ ld r12, r9, P_FORW /* r12 = p->p_forw */ - st r8, r12, P_BACK /* p->p_forw->p_back = q (p->p_back) */ - st r12, r8, P_FORW /* q->p_forw = p->p_forw */ + st r8, r12, P_BACK /* p->p_forw->p_back = q (p->p_back) */ + st r12, r8, P_FORW /* q->p_forw = p->p_forw */ lda.d r8, r7[r6] /* reload r8 with qs[ff1(whichqs)] */ - ld r12, r8, P_FORW /* q->p_forw */ + ld r12, r8, P_FORW /* q->p_forw */ cmp r12, r12, r8 /* q == q->p_forw; anyone left on queue? */ bb1 ne, r12, Lsw2 /* yes, skip clearing bit in whichqs */ or r12, r0, 1 /* r12 is 1 now */ - 1:bcnd eq0, r6, 2f +1: bcnd eq0, r6, 2f mak r12, r12, 0<1> /* shift left by 1 */ br.n 1b subu r6, r6, 1 /* keep doing this while r6 != 0 */ - 2: +2: /* - * NOTE: we could have just used "mak r12, r12, r6" instead of the + * NOTE: we could have just used "mak r12, r12, r6" instead of the * loop above. But that will break if NQS is made > 32. I can use * preprocessor to do the right thing, but that means I have to * include sys/proc.h in this file. XXX nivas @@ -221,11 +221,11 @@ Lsw2: bb1 ne, r2, Lswsrunpanic or.u r11, r0, hi16(_want_resched) - st r0, r11, lo16(_want_resched) /* clear want_resched */ + st r0, r11, lo16(_want_resched) /* clear want_resched */ or.u r11, r0, hi16(_curproc) st r9, r11,lo16(_curproc) /* curproc = p */ - + /* huh??? */ or.u r10, r0, hi16(_curpcb) ld r10,r10, lo16(_curpcb) @@ -240,7 +240,7 @@ Lsw2: ld r3, r9, P_ADDR or.u r10, r0, hi16(_curpcb) st r3, r10, lo16(_curpcb) /* curpcb = p->p_addr */ - + /* see if pmap_activate needs to be called */ /* _pmap_activate() now has proc * as parameter 01-11-2000 smurph */ /* No more VM_PMAP to contend with!!! */ @@ -248,7 +248,7 @@ Lsw2: or r14, r0, r9 /* save p in r14 */ subu r31, r31,48 /* r2 = pmap, r3 = pcb, r4 = cpu number */ - bsr _pmap_activate /* _pmap_activate(proc *p)*/ + bsr _pmap_activate /* _pmap_activate(proc *p)*/ addu r31, r31,48 or r9, r0, r14 /* restore p saved in r14 */ @@ -256,11 +256,11 @@ Lswnochg: or.u r31, r0, hi16(_intstack_end) or r31,r31, lo16(_intstack_end)/* now goto a tmp stack for NMI */ subu r31, r31,48 - bsr.n _load_u_area /* load_u_area(p) */ + bsr.n _load_u_area or r2, r0, r9 addu r31, r31,48 - /* flush tlb of any user addresses */ - or r2, r0, 0 /* 0 = user space */ + /* flush tlb of any user addresses */ + or r2, r0, 0 /* 0 = user space */ or r3, r0, 0 /* start at addr 0 */ subu r31, r31,48 /* r2 = 1 : kernel ? user, r3 = address, r4 = size */ @@ -275,7 +275,7 @@ Lswnochg: st r10, r14, P_ADDR /* p->p_addr = curpcb; restore p_addr */ /* restore from the current context */ - ld r1,r10, PCB_PC + ld r1,r10, PCB_PC ld.d r14,r10, PCB_R14 ld.d r16,r10, PCB_R16 ld.d r18,r10, PCB_R18 -- cgit v1.2.3