From e8531b715d75b75521217c682ee07e1b52ec66f8 Mon Sep 17 00:00:00 2001 From: Jonathan Gray Date: Mon, 16 May 2016 13:18:52 +0000 Subject: Implement membar(9) for armv5. As there are no barrier instructions in armv5 this is just a "memory" clobber hint to the compiler. ok kettenis@ --- sys/arch/arm/include/atomic.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'sys/arch/arm') diff --git a/sys/arch/arm/include/atomic.h b/sys/arch/arm/include/atomic.h index b50a12e9c12..27dddf96e60 100644 --- a/sys/arch/arm/include/atomic.h +++ b/sys/arch/arm/include/atomic.h @@ -1,4 +1,4 @@ -/* $OpenBSD: atomic.h,v 1.14 2016/04/25 08:00:43 patrick Exp $ */ +/* $OpenBSD: atomic.h,v 1.15 2016/05/16 13:18:51 jsg Exp $ */ /* Public Domain */ @@ -465,6 +465,19 @@ atomic_clearbits_int(volatile unsigned int *p, unsigned int v) : "memory", "cc" ); } +#endif /* CPU_ARMv7 */ + +#if !defined(CPU_ARMv7) + +#define __membar() do { __asm __volatile("" ::: "memory"); } while (0) + +#define membar_enter() __membar() +#define membar_exit() __membar() +#define membar_producer() __membar() +#define membar_consumer() __membar() +#define membar_sync() __membar() + +#else /* !CPU_ARMv7 */ #define __membar(_f) do { __asm __volatile(_f ::: "memory"); } while (0) -- cgit v1.2.3