From e45e51059ce9ca535b377adfc9a87566382d8f1e Mon Sep 17 00:00:00 2001 From: Dale Rahn <drahn@cvs.openbsd.org> Date: Mon, 5 Nov 2001 22:26:58 +0000 Subject: Workaround to prevent Altivec Unavilable problem. Why did Motorola put this exception misaligned with respect to all other exceptions? Altivec is not supported. This will cause any process executing altivec instructions to recieve an illegal instruction signal. --- sys/arch/powerpc/powerpc/trap.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'sys/arch/powerpc') diff --git a/sys/arch/powerpc/powerpc/trap.c b/sys/arch/powerpc/powerpc/trap.c index 5cad508fb23..d5778172955 100644 --- a/sys/arch/powerpc/powerpc/trap.c +++ b/sys/arch/powerpc/powerpc/trap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: trap.c,v 1.33 2001/09/20 13:46:04 drahn Exp $ */ +/* $OpenBSD: trap.c,v 1.34 2001/11/05 22:26:57 drahn Exp $ */ /* $NetBSD: trap.c,v 1.3 1996/10/13 03:31:37 christos Exp $ */ /* @@ -413,6 +413,14 @@ for (i = 0; i < errnum; i++) { break; } + /* This is not really a perf exception, but is an ALTIVEC unavail + * which we do not handle, kill the process with illegal instruction. + */ + case EXC_PERF|EXC_USER: + sv.sival_int = frame->srr0; + trapsignal(p, SIGILL, 0, ILL_ILLOPC, sv); + break; + case EXC_AST|EXC_USER: /* This is just here that we trap */ break; -- cgit v1.2.3