From e43558c65c4e1ada177750e34935adadeb7a8adb Mon Sep 17 00:00:00 2001 From: Miod Vallat Date: Mon, 26 Oct 2009 18:00:07 +0000 Subject: Better crime/mace interrupt handling; interrupt information is no longer specified in the kernel configuration file, but is provided by macebus(4) as part of the child device attachment args, and provide both crime and mace interrupt bitmasks; this allows us to only really enable interrupt sources we care about, and to avoid invoking interrupt handler we don't need to for the few mace interrupts multiplexed at the crime level. --- sys/arch/sgi/conf/GENERIC-IP32 | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'sys/arch/sgi/conf/GENERIC-IP32') diff --git a/sys/arch/sgi/conf/GENERIC-IP32 b/sys/arch/sgi/conf/GENERIC-IP32 index 62798a2984e..a7c821e1d83 100644 --- a/sys/arch/sgi/conf/GENERIC-IP32 +++ b/sys/arch/sgi/conf/GENERIC-IP32 @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC-IP32,v 1.9 2009/07/16 21:02:54 miod Exp $ +# $OpenBSD: GENERIC-IP32,v 1.10 2009/10/26 18:00:04 miod Exp $ # # THIS KERNEL IS FOR O2 (IP32) SYSTEMS ONLY. # @@ -46,13 +46,13 @@ macebus0 at mainbus0 # MACE controller localbus. gbe0 at mainbus0 # Localbus devices -mec0 at macebus0 base 0x00280000 irq 4 -mavb0 at macebus0 base 0x00300000 irq 7 -mkbc0 at macebus0 base 0x00320000 irq 6 -com0 at macebus0 base 0x00390000 irq 5 -com1 at macebus0 base 0x00398000 irq 5 +mec0 at macebus0 +mavb0 at macebus0 +mkbc0 at macebus0 +com0 at macebus0 base 0x00390000 +com1 at macebus0 base 0x00398000 dsrtc0 at macebus0 -power0 at macebus0 irq 6 +power0 at macebus0 #### PCI Bus macepcibr0 at macebus0 # MACE controller PCI Bus bridge. -- cgit v1.2.3