From 0f1999f25862af2d5386986298b529f677f12159 Mon Sep 17 00:00:00 2001 From: Jason Wright Date: Sat, 18 Aug 2001 20:56:42 +0000 Subject: enough to get sbus.o from NetBSD --- sys/arch/sparc64/dev/sbusreg.h | 192 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 192 insertions(+) create mode 100644 sys/arch/sparc64/dev/sbusreg.h (limited to 'sys/arch/sparc64/dev/sbusreg.h') diff --git a/sys/arch/sparc64/dev/sbusreg.h b/sys/arch/sparc64/dev/sbusreg.h new file mode 100644 index 00000000000..a53429f8f62 --- /dev/null +++ b/sys/arch/sparc64/dev/sbusreg.h @@ -0,0 +1,192 @@ +/* $NetBSD: sbusreg.h,v 1.7 1999/06/07 05:28:03 eeh Exp $ */ + +/* + * Copyright (c) 1996-1999 Eduardo Horvath + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + + +/* + * Sbus device addresses are obtained from the FORTH PROMs. They come + * in `absolute' and `relative' address flavors, so we have to handle both. + * Relative addresses do *not* include the slot number. + */ +#define SBUS_BASE 0xf8000000 +#define SBUS_ADDR(slot, off) (SBUS_BASE + ((slot) << 25) + (off)) +#define SBUS_ABS(a) ((unsigned)(a) >= SBUS_BASE) +#define SBUS_ABS_TO_SLOT(a) (((a) - SBUS_BASE) >> 25) +#define SBUS_ABS_TO_OFFSET(a) (((a) - SBUS_BASE) & 0x1ffffff) + +/* + * Sun4u S-bus definitions. Here's where we deal w/the machine + * dependencies of sysio. + * + * SYSIO implements or is the interface to several things: + * + * o The SBUS interface itself + * o The IOMMU + * o The DVMA units + * o The interrupt controller + * o The counter/timers + * + * Since it has registers to control lots of different things + * as well as several on-board SBUS devices and external SBUS + * slots scattered throughout its address space, it's a pain. + * + * One good point, however, is that all registers are 64-bit. + */ + +struct sysioreg { + struct upareg { + u_int64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */ + u_int64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */ + } sys_upa; + + u_int64_t sys_csr; /* SYSIO control/status register */ /* 1fe.0000.0010 */ + u_int64_t pad0; + u_int64_t sys_ecccr; /* ECC control register */ /* 1fe.0000.0020 */ + u_int64_t reserved; /* 1fe.0000.0028 */ + u_int64_t sys_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */ + u_int64_t sys_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */ + u_int64_t sys_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */ + u_int64_t sys_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */ + + u_int64_t pad1[22]; + + struct perfmon { + u_int64_t pm_cr; /* Performance monitor control reg */ /* 1fe.0000.0100 */ + u_int64_t pm_count; /* Performance monitor counter reg */ /* 1fe.0000.0108 */ + } sys_pm; + + u_int64_t pad2[990]; + + struct sbusreg { + u_int64_t sbus_cr; /* SBUS Control Register */ /* 1fe.0000.2000 */ + u_int64_t reserved; /* 1fe.0000.2008 */ + u_int64_t sbus_afsr; /* SBUS AFSR */ /* 1fe.0000.2010 */ + u_int64_t sbus_afar; /* SBUS AFAR */ /* 1fe.0000.2018 */ + u_int64_t sbus_config0; /* SBUS Slot 0 config register */ /* 1fe.0000.2020 */ + u_int64_t sbus_config1; /* SBUS Slot 1 config register */ /* 1fe.0000.2028 */ + u_int64_t sbus_config2; /* SBUS Slot 2 config register */ /* 1fe.0000.2030 */ + u_int64_t sbus_config3; /* SBUS Slot 3 config register */ /* 1fe.0000.2038 */ + u_int64_t sbus_config13; /* Slot 13 config register