From 5a0b6e0de393e7052b6894ae2aaa6163d61f1ab3 Mon Sep 17 00:00:00 2001
From: Michael Shalayeff <mickey@cvs.openbsd.org>
Date: Wed, 4 Aug 2004 14:47:31 +0000
Subject: interrupt mitigation bits

---
 sys/dev/ic/dcreg.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'sys/dev/ic/dcreg.h')

diff --git a/sys/dev/ic/dcreg.h b/sys/dev/ic/dcreg.h
index 463131cc26a..96a76cf2265 100644
--- a/sys/dev/ic/dcreg.h
+++ b/sys/dev/ic/dcreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: dcreg.h,v 1.34 2004/05/19 11:36:59 brad Exp $ */
+/*	$OpenBSD: dcreg.h,v 1.35 2004/08/04 14:47:30 mickey Exp $ */
 
 /*
  * Copyright (c) 1997, 1998, 1999
@@ -297,9 +297,15 @@
 
 /*
  * General purpose timer register
+ * (upper 15 bits exist on rev 0x41 chips only)
  */
-#define DC_TIMER_VALUE		0x0000FFFF
+#define DC_TIMER_CLKDIV		0x80000000	/* clock/16 */
+#define DC_TIMER_TXTIMER	0x78000000	/* TX intr delay timer */
+#define DC_TIMER_TXCOUNT	0x07000000	/* TX intr delay counter */
+#define DC_TIMER_RXTIMER	0x00F00000	/* RX intr delay timer */
+#define DC_TIMER_RXCOUNT	0x000E0000	/* RX intr delay counter */
 #define DC_TIMER_CONTINUOUS	0x00010000
+#define DC_TIMER_VALUE		0x0000FFFF	/* 81.92us */
 
 /*
  * 10baseT status register
-- 
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