From f4ca37f42e6888b337fcaea7e9b787c6462226ec Mon Sep 17 00:00:00 2001
From: Jonathan Gray <jsg@cvs.openbsd.org>
Date: Tue, 28 Feb 2006 08:13:48 +0000
Subject: We need to special case ciphy to ask for RGMII interface at 2.5V for
 nfe. This makes Cicada/Vitesse PHYs attached to nfe work. Many thanks to Bill
 Paul for diagnosing the problem and suggesting a solution.

Tested by otto@, ok deraadt@
---
 sys/dev/mii/ciphy.c    |  9 ++++++++-
 sys/dev/mii/ciphyreg.h | 12 +++++++++++-
 2 files changed, 19 insertions(+), 2 deletions(-)

(limited to 'sys/dev/mii')

diff --git a/sys/dev/mii/ciphy.c b/sys/dev/mii/ciphy.c
index f95f041fa6d..642ad41cd05 100644
--- a/sys/dev/mii/ciphy.c
+++ b/sys/dev/mii/ciphy.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ciphy.c,v 1.9 2005/10/07 03:45:11 brad Exp $	*/
+/*	$OpenBSD: ciphy.c,v 1.10 2006/02/28 08:13:47 jsg Exp $	*/
 /*	$FreeBSD: ciphy.c,v 1.1 2004/09/10 20:57:45 wpaul Exp $	*/
 /*
  * Copyright (c) 2004
@@ -337,6 +337,13 @@ ciphy_fixup(struct mii_softc *sc)
 	status = PHY_READ(sc, CIPHY_MII_AUXCSR);
 	speed = status & CIPHY_AUXCSR_SPEED;
 
+	if (strcmp(sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name, "nfe") == 0) {
+		printf("ciphy nfe fixup called!\n");
+		/* need to set for 2.5V RGMII for NVIDIA adapters */
+		PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_INTSEL_RGMII);
+		PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_IOVOL_2500MV);
+	}
+
 	switch (model) {
 	case MII_MODEL_CICADA_CS8201:
 
diff --git a/sys/dev/mii/ciphyreg.h b/sys/dev/mii/ciphyreg.h
index 3b8bb8fc909..0b7175664a3 100644
--- a/sys/dev/mii/ciphyreg.h
+++ b/sys/dev/mii/ciphyreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ciphyreg.h,v 1.1 2004/12/01 00:24:38 pvalchev Exp $	*/
+/*	$OpenBSD: ciphyreg.h,v 1.2 2006/02/28 08:13:47 jsg Exp $	*/
 /*	$FreeBSD: ciphyreg.h,v 1.1 2004/09/10 20:57:45 wpaul Exp $	*/
 /*
  * Copyright (c) 2004
@@ -251,6 +251,16 @@
 /* Extended PHY control register #1 */
 #define CIPHY_MII_ECTL1		0x17
 #define CIPHY_ECTL1_ACTIPHY	0x0020	/* Enable ActiPHY power saving */
+#define CIPHY_ECTL1_IOVOL	0x0e00	/* MAC interface and I/O voltage select */
+#define CIPHY_ECTL1_INTSEL	0xf000	/* select MAC interface */
+
+#define CIPHY_IOVOL_3300MV	0x0000	/* 3.3V for I/O pins */
+#define CIPHY_IOVOL_2500MV	0x0200	/* 2.5V for I/O pins */
+
+#define CIPHY_INTSEL_GMII	0x0000	/* GMII/MII */
+#define CIPHY_INTSEL_RGMII	0x1000
+#define CIPHY_INTSEL_TBI	0x2000
+#define CIPHY_INTSEL_RTBI	0x3000
 
 /* Extended PHY control register #2 */
 #define CIPHY_MII_ECTL2		0x18
-- 
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