From 59ff7701bdc9ab4ab613b5b3ca8241cc883ad8c6 Mon Sep 17 00:00:00 2001 From: David Gwynne Date: Sun, 29 Apr 2007 11:58:13 +0000 Subject: Nadav Shemer of Tehuti Networks is magical. not leaving the gap in the txt fifo when uploading the firmware was the cause of my fifo write bug in tht_start. because i was filling the whole fifo, i was writing the wptr back to its original position. because of this i dont think the firmware thought i had written anything. only the last short chunk would have been noticed, which strikes me as possibly confusing to the chip. this diff removes the delay at the top of tht_fifo_post. one less XXX :) --- sys/dev/pci/if_tht.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'sys/dev') diff --git a/sys/dev/pci/if_tht.c b/sys/dev/pci/if_tht.c index 4d604b76077..ccd6cb1f7f9 100644 --- a/sys/dev/pci/if_tht.c +++ b/sys/dev/pci/if_tht.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_tht.c,v 1.84 2007/04/29 11:39:15 dlg Exp $ */ +/* $OpenBSD: if_tht.c,v 1.85 2007/04/29 11:58:12 dlg Exp $ */ /* * Copyright (c) 2007 David Gwynne @@ -1491,8 +1491,6 @@ tht_fifo_write_pad(struct tht_softc *sc, struct tht_fifo *tf, int bc) void tht_fifo_post(struct tht_softc *sc, struct tht_fifo *tf) { - delay(100); /* XXX this is dumb */ - bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem), 0, tf->tf_len, THT_FIFO_PRE_SYNC(tf->tf_desc)); if (tf->tf_desc->tfd_write) -- cgit v1.2.3