From b899f9fc60c1688213f09711b7d77a6db1cc7ee4 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Fri, 6 May 2016 08:11:59 +0000 Subject: Round the requested clock frequency down to a support value instead of insisting on an exact match. Add support for a 50 MHz clock. ok stsp@ --- sys/dev/ic/rtsx.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'sys/dev') diff --git a/sys/dev/ic/rtsx.c b/sys/dev/ic/rtsx.c index bdb5d50154c..f5142b3af36 100644 --- a/sys/dev/ic/rtsx.c +++ b/sys/dev/ic/rtsx.c @@ -1,4 +1,4 @@ -/* $OpenBSD: rtsx.c,v 1.15 2016/05/06 08:09:20 kettenis Exp $ */ +/* $OpenBSD: rtsx.c,v 1.16 2016/05/06 08:11:58 kettenis Exp $ */ /* * Copyright (c) 2006 Uwe Stuehler @@ -630,6 +630,14 @@ rtsx_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) goto ret; } + /* Round down to a supported frequency. */ + if (freq >= SDMMC_SDCLK_50MHZ) + freq = SDMMC_SDCLK_50MHZ; + else if (freq >= SDMMC_SDCLK_25MHZ) + freq = SDMMC_SDCLK_25MHZ; + else + freq = SDMMC_SDCLK_400KHZ; + /* * Configure the clock frequency. */ @@ -646,6 +654,12 @@ rtsx_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) mcu = 7; RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); break; + case SDMMC_SDCLK_50MHZ: + n = 100; + div = RTSX_CLK_DIV_2; + mcu = 7; + RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); + break; default: error = EINVAL; goto ret; -- cgit v1.2.3