From 0e30b534b58a2a1036179cf82c18f411934d36d2 Mon Sep 17 00:00:00 2001
From: Claudio Jeker <claudio@cvs.openbsd.org>
Date: Wed, 25 Jan 2006 11:02:55 +0000
Subject: Reset and initialize part of the device early. Makes reading the ROM
 more reliable because correct bus timings were set later.

---
 sys/dev/pci/musycc.c      |  8 +-------
 sys/dev/pci/musycc_obsd.c | 24 +++++++++++++++++++++++-
 2 files changed, 24 insertions(+), 8 deletions(-)

(limited to 'sys')

diff --git a/sys/dev/pci/musycc.c b/sys/dev/pci/musycc.c
index b8751fbea91..7087b66e3bd 100644
--- a/sys/dev/pci/musycc.c
+++ b/sys/dev/pci/musycc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: musycc.c,v 1.10 2005/12/19 15:49:10 claudio Exp $ */
+/*	$OpenBSD: musycc.c,v 1.11 2006/01/25 11:02:53 claudio Exp $ */
 
 /*
  * Copyright (c) 2004,2005  Internet Business Solutions AG, Zurich, Switzerland
@@ -94,12 +94,6 @@ musycc_attach_common(struct musycc_softc *sc, u_int32_t portmap, u_int32_t mode)
 	struct musycc_group	*mg;
 	int			 i, j;
 
-	/* soft reset device */
-	bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_SERREQ(0),
-	    MUSYCC_SREQ_SET(1));
-	bus_space_barrier(sc->mc_st, sc->mc_sh, MUSYCC_SERREQ(0),
-	    sizeof(u_int32_t), BUS_SPACE_BARRIER_WRITE);
-
 	if (musycc_alloc_groupdesc(sc) == -1) {
 		printf(": couldn't alloc group descriptors\n");
 		return (-1);
diff --git a/sys/dev/pci/musycc_obsd.c b/sys/dev/pci/musycc_obsd.c
index becebe270ab..b7df54ad8d1 100644
--- a/sys/dev/pci/musycc_obsd.c
+++ b/sys/dev/pci/musycc_obsd.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: musycc_obsd.c,v 1.8 2005/08/27 13:32:01 claudio Exp $ */
+/*	$OpenBSD: musycc_obsd.c,v 1.9 2006/01/25 11:02:54 claudio Exp $ */
 
 /*
  * Copyright (c) 2004,2005  Internet Business Solutions AG, Zurich, Switzerland
@@ -135,6 +135,28 @@ musycc_softc_attach(struct device *parent, struct device *self, void *aux)
 	}
 
 	printf(": %s\n", intrstr);
+
+	/* soft reset device */
+	bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_SERREQ(0),
+	    MUSYCC_SREQ_SET(1));
+	bus_space_barrier(sc->mc_st, sc->mc_sh, MUSYCC_SERREQ(0),
+	    sizeof(u_int32_t), BUS_SPACE_BARRIER_WRITE);
+
+	/*
+	 * preload global configuration: set EBUS to sane defaults
+	 * so that the ROM access will work.
+	 * intel mode, elapse = 3, blapse = 3, alapse = 3, disable INTB
+	 */
+	sc->mc_global_conf = MUSYCC_CONF_MPUSEL | MUSYCC_CONF_ECKEN |
+	    MUSYCC_CONF_ELAPSE_SET(3) | MUSYCC_CONF_ALAPSE_SET(3) |
+	    MUSYCC_CONF_BLAPSE_SET(3) | MUSYCC_CONF_INTB;
+
+	/* Dual Address Cycle Base Pointer */
+	bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_DACB_PTR, 0);
+	/* Global Configuration Descriptor */
+	bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_GLOBALCONF,
+	    sc->mc_global_conf);
+
 	return;
 }
 
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