From bdbb32946e48a5aabf464be454a89244d082504b Mon Sep 17 00:00:00 2001 From: Miod Vallat Date: Sat, 22 Dec 2007 17:14:40 +0000 Subject: Move initial PSR initialization to a separate routine, instead of duplicating it five times. --- sys/arch/aviion/aviion/locore.S | 84 ++------------------------------------- sys/arch/luna88k/luna88k/locore.S | 50 ++--------------------- sys/arch/m88k/m88k/genassym.cf | 7 +++- sys/arch/m88k/m88k/subr.S | 55 +++++++++++++++++++++++-- sys/arch/mvme88k/mvme88k/locore.S | 63 ++--------------------------- 5 files changed, 67 insertions(+), 192 deletions(-) (limited to 'sys') diff --git a/sys/arch/aviion/aviion/locore.S b/sys/arch/aviion/aviion/locore.S index 560d2c43758..9001a588e66 100644 --- a/sys/arch/aviion/aviion/locore.S +++ b/sys/arch/aviion/aviion/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.10 2007/12/20 21:14:06 miod Exp $ */ +/* $OpenBSD: locore.S,v 1.11 2007/12/22 17:14:36 miod Exp $ */ /* * Copyright (c) 2005, Miodrag Vallat. * Copyright (c) 1998 Steve Murphree, Jr. @@ -122,65 +122,12 @@ ASLOCAL(main_start) or.u r13, r0, hi16(_C_LABEL(cputyp)) st r8, r13, lo16(_C_LABEL(cputyp)) - /* - * CPU Initialization - * - * I use r11 and r22 here because they're easy to not - * get mixed up -- r10, for example, looks too similar - * to r0 when not being careful.... - * - * Ensure that the PSR is as we like: - * supervisor mode - * big-endian byte ordering - * concurrent operation allowed - * carry bit clear (I don't think we really care about this) - * FPU enabled - * misaligned access raises an exception - * interrupts disabled - * shadow registers frozen - * - * The manual says not to disable interrupts and freeze shadowing - * at the same time because interrupts are not actually disabled - * until after the next instruction. Well, if an interrupt - * occurs now, we're in deep trouble anyway, so I'm going to do - * the two together. - * - * Upon a reset (or poweron, I guess), the PSR indicates: - * supervisor mode - * interrupts, shadowing, FPU, misaligned exception: all disabled - * - * We'll just construct our own turning on what we want. - * - * jfriedl@omron.co.jp - */ - - cmp r2, r8, CPU_88110 /* r8 contains cputyp */ - bb1 eq, r2, 1f /* if it's a 'mc88110, skip SSBR */ - stcr r0, SSBR /* clear this for later */ -1: - stcr r0, SR1 /* clear the CPU flags */ - - set r11, r0, 1 - set r11, r11, 1 - set r11, r11, 1 - /* - * XXX On 88110 processors, force serial instruction execution for now. - * Situation where OoO would break will be hopefully taken care of in - * the near future -- miod - */ -#if 0 - clr r11, r11, 1 -#else - set r11, r11, 1 -#endif - set r11, r11, 1 - stcr r11, PSR - FLUSH_PIPELINE + bsr _ASM_LABEL(setup_psr) /* save PROM vbr */ ldcr r12, VBR or.u r13, r0, hi16(_C_LABEL(prom_vbr)) - st r12, r13, lo16(_C_LABEL(prom_vbr)) + st r12, r13, lo16(_C_LABEL(prom_vbr)) stcr r0, VBR #ifdef MULTIPROCESSOR @@ -261,31 +208,8 @@ GLOBAL(secondary_start) or.u r31, r0, hi16(_ASM_LABEL(slavestack_end)) or r31, r31, lo16(_ASM_LABEL(slavestack_end)) - or.u r13, r0, hi16(_C_LABEL(cputyp)) - ld r8, r13, lo16(_C_LABEL(cputyp)) - - cmp r2, r8, CPU_88110 - bb1 eq, r2, 1f - stcr r0, SSBR -1: - stcr r0, SR1 + bsr _ASM_LABEL(setup_psr) - set r11, r0, 1 - set r11, r11, 1 - set r11, r11, 1 - /* - * XXX On 88110 processors, force serial instruction execution for now. - * Situation where OoO would break will be hopefully taken care of in - * the near future -- miod - */ -#if 0 - clr r11, r11, 1 -#else - set r11, r11, 1 -#endif - set r11, r11, 1 - stcr r11, PSR - FLUSH_PIPELINE stcr r0, VBR /* set Vector Base Register to 0, ALWAYS! */ FLUSH_PIPELINE diff --git a/sys/arch/luna88k/luna88k/locore.S b/sys/arch/luna88k/luna88k/locore.S index f09b18f2834..d0291c72734 100644 --- a/sys/arch/luna88k/luna88k/locore.S +++ b/sys/arch/luna88k/luna88k/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.19 2007/12/20 21:14:07 miod Exp $ */ +/* $OpenBSD: locore.S,v 1.20 2007/12/22 17:14:39 miod Exp $ */ /* * Copyright (c) 1998 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -91,50 +91,8 @@ ASGLOBAL(start) * Startup code common to all processors. */ ASLOCAL(main_start) - /* - * CPU Initialization - * - * Every CPU starts from here.. - * (well, from 'start' above, which just jumps here). - * - * I use r11 and r22 here 'cause they're easy to not - * get mixed up -- r10, for example, looks too similar - * to r0 when not being careful.... - * - * Ensure that the PSR is as we like: - * supervisor mode - * big-endian byte ordering - * concurrent operation allowed - * carry bit clear (I don't think we really care about this) - * FPU enabled - * misaligned access raises an exception - * interrupts disabled - * shadow registers frozen - * - * The manual says not to disable interrupts and freeze shadowing - * at the same time because interrupts are not actually disabled - * until after the next instruction. Well, if an interrupt - * occurs now, we're in deep trouble anyway, so I'm going to do - * the two together. - * - * Upon a reset (or poweron, I guess), the PSR indicates: - * supervisor mode - * interrupts, shadowing, FPU, misaligned exception: all disabled - * - * We'll just construct our own turning on what we want. - * - * jfriedl@omron.co.jp - */ + bsr _ASM_LABEL(setup_psr) - stcr r0, SSBR /* clear this for later */ - stcr r0, SR1 /* clear the CPU flags */ - - set r11, r0, 1 - set r11, r11, 1 - set r11, r11, 1 - - stcr r11, PSR - FLUSH_PIPELINE stcr r0, VBR /* set Vector Base Register to 0, ALWAYS! */ FLUSH_PIPELINE @@ -307,8 +265,8 @@ ASLOCAL(secondary_init) GLOBAL(delay) bcnd eq0, r2, 2f - or.u r3, r0, hi16(_C_LABEL(cpuseed)) - ld r3, r3, lo16(_C_LABEL(cpuseed)) + or.u r3, r0, hi16(_C_LABEL(cpuspeed)) + ld r3, r3, lo16(_C_LABEL(cpuspeed)) mul r4, r2, r3 subu r4, r4, 4 /* overhead of these instructions */ diff --git a/sys/arch/m88k/m88k/genassym.cf b/sys/arch/m88k/m88k/genassym.cf index 147153612c0..da3351166c0 100644 --- a/sys/arch/m88k/m88k/genassym.cf +++ b/sys/arch/m88k/m88k/genassym.cf @@ -1,4 +1,4 @@ -# $OpenBSD: genassym.cf,v 1.16 2007/12/21 23:56:54 miod Exp $ +# $OpenBSD: genassym.cf,v 1.17 2007/12/22 17:14:39 miod Exp $ # # Copyright (c) 1982, 1990 The Regents of the University of California. # All rights reserved. @@ -28,7 +28,7 @@ # SUCH DAMAGE. # # @(#)genassym.c 7.8 (Berkeley) 5/7/91 -# $Id: genassym.cf,v 1.16 2007/12/21 23:56:54 miod Exp $ +# $Id: genassym.cf,v 1.17 2007/12/22 17:14:39 miod Exp $ # include @@ -47,6 +47,9 @@ include include include +# initialization PSR value +define KERNEL_PSR PSR_MODE | PSR_SFD | PSR_SFD2 | PSR_IND + # proc fields and values struct proc member p_addr diff --git a/sys/arch/m88k/m88k/subr.S b/sys/arch/m88k/m88k/subr.S index f11dfd63d57..d03edba7c2e 100644 --- a/sys/arch/m88k/m88k/subr.S +++ b/sys/arch/m88k/m88k/subr.S @@ -1,4 +1,4 @@ -/* $OpenBSD: subr.S,v 1.15 2007/12/02 21:22:19 miod Exp $ */ +/* $OpenBSD: subr.S,v 1.16 2007/12/22 17:14:39 miod Exp $ */ /* * Mach Operating System * Copyright (c) 1993-1992 Carnegie Mellon University @@ -34,6 +34,7 @@ #include #include +#include #include #ifdef M88100 @@ -1076,7 +1077,7 @@ ENTRY(longjmp) * The kernel arranges for the handler to be invoked directly, and return * here. */ -GLOBAL(sigcode) /* r31 points to sigframe */ +ENTRY(sigcode) /* r31 points to sigframe */ ld r2, r31, 0 /* pick sigcontext* */ or r13, r0, SYS_sigreturn tb0 0, r0, 128 /* syscall trap, calling sigreturn */ @@ -1102,7 +1103,7 @@ GLOBAL(esigcode) * * This copies PAGE_SIZE bytes from src to dst in 32 byte chunks. */ -GLOBAL(copypage) +ENTRY(copypage) addu r12, r2, PAGE_SIZE 1: ld.d r4, r2, 0x00 @@ -1124,7 +1125,7 @@ GLOBAL(copypage) * * This zeroes PAGE_SIZE bytes from src to dst in 64 byte chunks. */ -GLOBAL(zeropage) +ENTRY(zeropage) addu r12, r2, PAGE_SIZE or r3, r1, r0 or r1, r0, r0 @@ -1141,3 +1142,49 @@ GLOBAL(zeropage) cmp r4, r2, r12 bb1 ne, r4, 1b jmp r3 + +/* + * PSR initialization code, invoked from locore on every processor startup. + */ +ASENTRY(setup_psr) + ldcr r2, PID + extu r3, r2, 8<8> + + /* + * Ensure that the PSR is as we like: + * supervisor mode + * big-endian byte ordering + * concurrent operation allowed + * carry bit clear (I don't think we really care about this) + * FPU enabled + * misaligned access raises an exception + * interrupts disabled + * shadow registers frozen + * + * The manual says not to disable interrupts and freeze shadowing + * at the same time because interrupts are not actually disabled + * until after the next instruction. Well, if an interrupt + * occurs now, we're in deep trouble anyway, so I'm going to do + * the two together. + * + * Upon a reset (or poweron, I guess), the PSR indicates: + * supervisor mode + * interrupts, shadowing, FPU, misaligned exception: all disabled + * + * We'll just construct our own turning on what we want. + * + * jfriedl@omron.co.jp + */ + + cmp r4, r3, CPU_88110 + bb1 eq, r4, 1f /* if it's a mc88110, skip SSBR */ + stcr r0, SSBR /* clear this for later */ +1: + stcr r0, SR1 /* clear the CPU flags */ + + or.u r2, r0, hi16(KERNEL_PSR) + or r2, r2, lo16(KERNEL_PSR) + stcr r2, PSR + FLUSH_PIPELINE + + jmp r1 diff --git a/sys/arch/mvme88k/mvme88k/locore.S b/sys/arch/mvme88k/mvme88k/locore.S index 6590cebec1c..53953cd7f98 100644 --- a/sys/arch/mvme88k/mvme88k/locore.S +++ b/sys/arch/mvme88k/mvme88k/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.60 2007/12/20 21:14:07 miod Exp $ */ +/* $OpenBSD: locore.S,v 1.61 2007/12/22 17:14:39 miod Exp $ */ /* * Copyright (c) 2005, Miodrag Vallat. * Copyright (c) 1998 Steve Murphree, Jr. @@ -128,51 +128,8 @@ ASLOCAL(main_start) or.u r13, r0, hi16(_C_LABEL(cputyp)) st r8, r13, lo16(_C_LABEL(cputyp)) - /* - * CPU Initialization - * - * I use r11 and r22 here because they're easy to not - * get mixed up -- r10, for example, looks too similar - * to r0 when not being careful.... - * - * Ensure that the PSR is as we like: - * supervisor mode - * big-endian byte ordering - * concurrent operation allowed - * carry bit clear (I don't think we really care about this) - * FPU enabled - * misaligned access raises an exception - * interrupts disabled - * shadow registers frozen - * - * The manual says not to disable interrupts and freeze shadowing - * at the same time because interrupts are not actually disabled - * until after the next instruction. Well, if an interrupt - * occurs now, we're in deep trouble anyway, so I'm going to do - * the two together. - * - * Upon a reset (or poweron, I guess), the PSR indicates: - * supervisor mode - * interrupts, shadowing, FPU, misaligned exception: all disabled - * - * We'll just construct our own turning on what we want. - * - * jfriedl@omron.co.jp - */ + bsr _ASM_LABEL(setup_psr) - cmp r2, r8, CPU_88110 - bb1 eq, r2, 1f /* if it's a 'mc88110, skip SSBR */ - stcr r0, SSBR /* clear this for later */ -1: - stcr r0, SR1 /* clear the CPU flags */ - - set r11, r0, 1 - set r11, r11, 1 - set r11, r11, 1 - clr r11, r11, 1 - set r11, r11, 1 - stcr r11, PSR - FLUSH_PIPELINE stcr r0, VBR /* set Vector Base Register to 0, ALWAYS! */ FLUSH_PIPELINE @@ -243,22 +200,8 @@ GLOBAL(secondary_start) or.u r31, r0, hi16(_ASM_LABEL(slavestack_end)) or r31, r31, lo16(_ASM_LABEL(slavestack_end)) - ldcr r1, PID - extu r8, r1, 8<8> + bsr _ASM_LABEL(setup_psr) - cmp r2, r8, CPU_88110 - bb1 eq, r2, 1f - stcr r0, SSBR -1: - stcr r0, SR1 - - set r11, r0, 1 - set r11, r11, 1 - set r11, r11, 1 - clr r11, r11, 1 - set r11, r11, 1 - stcr r11, PSR - FLUSH_PIPELINE stcr r0, VBR /* set Vector Base Register to 0, ALWAYS! */ FLUSH_PIPELINE -- cgit v1.2.3