.\" $OpenBSD: cpu.4tbl,v 1.25 2010/09/19 12:41:23 jmc Exp $
.\"
.\" Copyright (c) 2002 Michael Shalayeff
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.Dd $Mdocdate: September 19 2010 $
.Dt CPU 4 hppa
.Os
.Sh NAME
.Nm cpu
.Nd HP PA-RISC CPU
.Sh SYNOPSIS
.Cd "cpu*       at mainbus0 irq 31"
.Sh DESCRIPTION
The following table lists the
.Tn PA-RISC
CPU types and their characteristics, such as TLB, maximum
cache sizes (where * character means on-chip) and
.Tn HP 9000/700
machines they were used in (see also
.Xr intro 4
for the reverse list).
.Pp
.in +\n(dIu
.TS
tab (:) ;
l l l l l l l
l l l l l l l
_ _ _ _ _ _ _
l l l l l l l .
CPU:PA:Clock  :Caches:TLB:BAT:Models
   :  :MHz max:KB max:   :   :
7000:1.1a:66 : 256 L1I:96I:4I:705,710,720
    :    :   : 256 L1D:96D:4D:730,750
7100:1.1b:100:1024 L1I:120:16:715/33/50/75
    :    :   :2048 L1D:   :  :725/50/75
    :    :   :        :   :  :{735,755}/100
    :    :   :        :   :  :742i, 745i, 747i
7150:1.1b:125:1024 L1I:120:16:{735,755}/125
    :    :   :2048 L1D:   :  :
7100LC:1.1c:100:   1 L1I*:64:8:712/60/80/100
      :    :   :1024 L2I:  : :715/64/80/100
      :    :   :1024 L2D:  : :715/100XC
      :    :   :        :  : :725/64/100
      :    :   :        :  : :743i, 748i
      :    :   :        :  : :SAIC
7200:1.1d:140:   2 L1*:120:16:C100,C110
    :    :   :1024 L2I:   :  :J200,J210
    :    :   :1024 L2D:   :  :
7300LC:1.1e:180:  64 L1I*:96:8:A180,A180C
       :    :  :  64 L1D*:  : :B132,B160,B180
       :    :  :8192 L2:  : :C132L,C160L
       :    :  :       :  : :744, 745, 748
       :    :  :       :  : :RDI PrecisionBook
8000:2.0:180:1024 L1I:96:  :C160, C180
    :   :   :1024 L1D:  :  :J280, J282
8200:2.0:300:2048 L1I:120:  :C200, C240
    :   :   :2048 L1D:   :  :J2240
8500:2.0:440: 512 L1I*:160:  :A400,A500,C360
    :   :   :1024 L1D*:   :  :B1000,B2000,C3000
    :   :   :         :   :  :J5000,J7000
8600:2.0:550: 512 L1I*:160:  :A400,A500,C3600
    :   :   :1024 L1D*:   :  :B2000,B2600
    :   :   :         :   :  :J5600,J6000,J7600
8700:2.0:875: 768 L1I*:240:  :A400,A500,J6700
    :   :   :1536 L1D*:   :  :C3650,C3700,C3750
.TE
.in -\n(dIu
.Sh FLOATING-POINT COPROCESSOR
The following table summarizes available floating-point coprocessor
models for the 32-bit
.Tn PA-RISC
processors.
.Pp
.in +\n(dIu
.TS
tab (:) nokeep ;
l l
_ _
l l .
FPU:Model
Indigo:
Sterling I MIU (TYCO):
Sterling I MIU (ROC w/Weitek):
FPC (w/Weitek):
FPC (w/Bit):
Timex-II:
Rolex:725/50, 745i
HARP-I:
Tornado:J2x0,C1x0
PA-50 (Hitachi):
PCXL:712/60/80/100
.TE
.in -\n(dIu
.Sh SUPERSCALAR EXECUTION
The following table summarizes the superscalar execution capabilities
of 32-bit
.Tn PA-RISC
processors.
.Pp
.in +\n(dIu
.TS
tab (:) nokeep ;
l l l
_ _ _
l l l .
CPU:Units:Bundles
7100:1 integer ALU:load-store/fp
    :1 FP         :int/fp
    :             :branch/*
7100LC:2 integer ALU:load-store/int
      :1 FP	    :load-store/fp
      :             :int/fp
      :             :branch/*
7200:2 integer ALU:load-store/int
    :1 FP         :load-store/fp
    :        :int/int
    :        :int/fp
    :        :branch/*
7300LC:2 integer ALU:load-store/int
      :1 FP         :load-store/fp
      :        :int/fp
      :        :branch/*
8x00:2 integer ALU:4-way superscalar
    :2 shift/merge:
    :2 load/store:
    :2 FPU mul/add:
    :2 FPU div/sqrt:
.TE
.in -\n(dIu
.Pp
In conclusion, all of the above CPUs are dual-issue, or 2-way superscalar,
with the exception that on CPUs with two integer ALUs only one of these
units is capable of doing shift, load/store and test operations.
Additionally, there are several kinds of restrictions placed upon the
superscalar execution:
.Pp
For the purpose of showing which instructions are allowed to proceed
together through the pipeline, they are divided into classes:
.Pp
.in +\n(dIu
.TS
tab (:) ;
l l
_ _
l l .
Class:Description
flop:floating point operation
ldst:loads and stores
flex:integer ALU
mm:shifts, extracts and deposits
nul:might nullify successor
bv:BV, BE
br:other branches
fsys:FTEST and FP status/exception
sys:system control instructions
.TE
.in -\n(dIu
.Pp
For CPUs with two integer ALUs (7100LC, 7200, 7300LC), the following
table lists the instructions which are allowed to be executed
concurrently:
.Pp
.in +\n(dIu
.TS
tab (:) ;
l l
_ _
l l .
First:Second instruction
flop: + ldst/flex/mm/nul/bv/br
ldst: + flop/flex/mm/nul/br
flex: + flop/ldst/flex/mm/nul/br/fsys
mm: + flop/ldst/flex/fsys
nul: + flop
sys: never bundled
.TE
.in -\n(dIu
.Pp
ldst + ldst is also possible under certain circumstances, which is then
called "double word load/store".
.Pp
The following restrictions are placed upon the superscalar execution:
.Pp
.Bl -bullet -compact
.It
An instruction that modifies a register will not be bundled with another
instruction that takes this register as operand.
Exception: a flop can be bundled with an FP store of the flop's result register.
.It
An FP load to one word of a doubleword register will not be bundled with
a flop that uses the other doubleword of this register.
.It
A flop will not be bundled with an FP load if both instructions have the
same target register.
.It
An instruction that could set the carry/borrow bits will not be bundled
with an instruction that uses
carry/borrow bits.
.It
An instruction which is in the delay slot of a branch is never bundled
with other instructions.
.It
An instruction which is at an odd word address and executed as a target
of a taken branch is never bundled.
.It
An instruction which might nullify its successor is never bundled with
this successor.
Only if the successor is a flop instruction is this bundle allowed.
.El
.Sh PERFORMANCE MONITOR COPROCESSOR
The performance monitor coprocessor is an optional,
implementation-dependent coprocessor which provides a minimal common
software interface to implementation-dependent performance monitor hardware.
.Sh DEBUG SPECIAL UNIT
The debug special function unit is an optional,
architected SFU which provides hardware assistance for software debugging
using breakpoints.
The debug SFU is currently defined only for Level 0 processors.
.Sh SEE ALSO
.Xr asp 4 ,
.Xr intro 4 ,
.Xr lasi 4 ,
.Xr mem 4 ,
.Xr pdc 4 ,
.Xr wax 4
.Rs
.%T PA-RISC 1.1 Architecture and Instruction Set Reference Manual
.%A Hewlett-Packard
.%D May 15, 1996
.Re
.Rs
.%T PA7100LC ERS
.%A Hewlett-Packard
.%D March 30 1999
.%N Public version 1.0
.Re
.Rs
.%T Design of the PA7200 CPU
.%A Hewlett-Packard Journal
.%D February 1996
.Re
.Rs
.%T PA7300LC ERS
.%A Hewlett-Packard
.%D March 18 1996
.%N Version 1.0
.Re
.Sh HISTORY
The
.Nm
driver was written by
.An Michael Shalayeff Aq mickey@openbsd.org
for the HPPA
port for
.Ox 2.5 .