/* $OpenBSD: mvme188.h,v 1.7 2001/08/26 14:31:07 miod Exp $ */ /* * Copyright (c) 1999 Steve Murphree, Jr. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Nivas Madhur. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* * Mach Operating System * Copyright (c) 1991 Carnegie Mellon University * Copyright (c) 1991 OMRON Corporation * All Rights Reserved. * * Permission to use, copy, modify and distribute this software and its * documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. * */ #ifndef __MACHINE_MVME188_H__ #define __MACHINE_MVME188_H__ /* * Something to put append a 'U' to a long constant if it's C so that * it'll be unsigned in both ANSI and traditional. */ #ifndef UDEFINED #if defined(_LOCORE) #define U(num) num #else #if defined(__STDC__) #define U(num) num ## U #else #define U(num) num/**/U #endif #endif #endif #define MVME188_EPROM U(0xFFC00000) #define MVME188_EPROM_SIZE U(0x00080000) #define MVME188_SRAM U(0xFFE00000) #define MVME188_SRAM_SIZE U(0x00020000) #define MVME188_UTILITY U(0xFF000000) #define MVME188_UTILITY_SIZE U(0x01000000) #define UTIL_START U(0xFFC00000) /* start of MVME188 utility space */ #define UTIL_SIZE U(0x003FFFFF) /* size of MVME188 utility space */ /* * MVME188 declarations for hardware level device registers and such. */ /* base address for the interrupt control registers */ #define INTR_CONTROL_BASE U(0xfff84000) #define VMEA24SPACE U(0xEEC00000) /* VMEA24 master addr space (4 Meg) */ /* per-processor interrupt enable registers */ #define MVME188_IEN0 U(0xFFF84004) /* interrupt enable CPU 0 */ #define MVME188_IEN1 U(0xFFF84008) /* interrupt enable CPU 1 */ #define MVME188_IEN2 U(0xFFF84010) /* interrupt enable CPU 2 */ #define MVME188_IEN3 U(0xFFF84020) /* interrupt enable CPU 3 */ /* same as above */ #define IEN0_REG U(0xfff84004) #define IEN1_REG U(0xfff84008) #define IEN2_REG U(0xfff84010) #define IEN3_REG U(0xfff84020) #define IENALL_REG U(0xfff8403c) #define MVME188_IST U(0xFFF84040) /* interrupt status register */ #define IST_REG U(0xfff84040) /* same as above */ #define MVME188_SETSWI U(0xFFF84080) /* generate soft interrupt */ #define MVME188_CLRSWI U(0xFFF84084) /* reset soft interrupt */ #define MVME188_ISTATE U(0xFFF84088) /* HW interrupt status */ #define MVME188_CLRINT U(0xFFF8408C) /* reset HW interrupt */ /* same as above */ #define SETSWI_REG U(0xfff84080) /* SETSWI register addr */ #define CLRSWI_REG U(0xfff84084) /* CLRSWI register addr */ #define ISTATE_REG U(0xfff84088) #define CLRINT_REG U(0xfff8408C) #define MVME188_GCSR U(0xFFF86000) /* 188 global control and status reg */ #define MVME188_UCSR U(0xFFF87000) /* 188 utility control and status reg */ #define MVME188_BASAD U(0xFFF87004) /* 188 base address reg */ #define MVME188_GLBRES U(0xFFF8700C) /* 188 global reset reg */ #define GCSR_BASE U(0xfff86000) #define GLOBAL0 GCSR_BASE + 0x01 #define GLOBAL1 GCSR_BASE + 0x03 #define GLOBAL2 GCSR_BASE + 0x05 #define GLOBAL3 GCSR_BASE + 0x07 #define GLB0 U(0xfff86001) #define GLB1 U(0xfff86003) #define GLB2 U(0xfff86005) #define GLB3 U(0xfff86007) #define M188_SYSCON U(0x00000040) #define UCSR_REG U(0xfff87000) #define GLBRES_REG U(0xfff8700C) #define MVME188_CCSR U(0xFFF88000) /* 188 CPU board control status reg */ #define MVME188_ERROR U(0xFFF88004) /* 188 Mbus fault reg */ #define MVME188_PCNFA U(0xFFF88008) /* 188 Pbus A decoder reg */ #define MVME188_PCNFB U(0xFFF8800C) /* 188 Pbus B decoder reg */ #define MVME188_EXTAD U(0xFFF88010) /* 188 A24 master A24-A31 addr reg */ #define MVME188_WHOAMI U(0xFFF88018) /* 188 whoami reg */ #define MVME188_WMAD U(0xFFF88020) /* 188 write mbus addr decoder reg */ #define MVME188_RMAD U(0xFFF88024) /* 188 read mbus addr decoder reg */ #define MVME188_WVAD U(0xFFF88028) /* 188 write vmebus addr decoder reg */ #define MVME188_RVAD U(0xFFF8802C) /* 188 read vmebus adds decoder reg */ /* duplicates of above */ #define CCSR_REG U(0xfff88000) #define ERROR_REG U(0xfff88004) /* ERROR register addr */ #define PCNFA_REG U(0xfff88008) #define PCNFB_REG U(0xfff8800c) #define EXTAD_REG U(0xfff88010) #define EXTAM_REG U(0xfff88014) #define WHOAMI_REG U(0xfff88018) /* WHOAMI register addr */ #define WMAD_REG U(0xfff88020) #define RMAD_REG U(0xfff88024) #define WVAD_REG U(0xfff88028) #define RVAD_REG U(0xfff8802c) #define MAD_MDS 0x07 /* 188 MAD Device Select bits */ #define VMEA24 0x5 /* Mbus addess decode select for VMEA24 */ #define VADV 0x1 /* vmeaddres decode enable */ #define VBDSELBIT 0 /* bit to enable vme slave response low true */ #define VBDISABLE 0x1 /* VME BUS Disable */ #define VSDBIT 1 /* bit number to enable snooping low true */ #define VSDISABLE 0x2 /* VME Snoop Disable */ #define VASPBIT 21 /* addr space 0 = A32, 1 = A24 bit */ #define VASP 0x00200000 /* A24 VME address space */ #define VPN 0x00400000 /* Page Number LSB */ #define PAGECNT 0x400 /* number of (4 meg) pages to map */ #define UCSR_PWRUPBIT 0x4000 /* 188 UCSR powerup indicator */ #define UCSR_DRVSFBIT 0x2000 /* 188 UCSR Board system fail */ #define UCSR_BRIRQBIT 0x1000 /* 188 UCSR drives VME IRQ1 broadcast int */ #define UCSR_ROBINBIT 0x800 /* 188 UCSR sel round robin VME arbiter mode */ #define UCSR_BRLVBITS 0x600 /* 188 UCSR VME bus request level 0-3 */ #define UCSR_RNEVERBIT 0x100 /* 188 UCSR VME bus never release once req'd */ #define UCSR_RONRBIT 0x80 /* 188 UCSR VME bus req release on no request */ #define UCSR_RWDBIT 0x40 /* 188 UCSR VME bus request release when done */ #define UCSR_EARBTOBIT 0x20 /* 188 UCSR enable VME arbiter bus timeout */ /* MVME188 VMEbus data transfer timeout select */ #define VTOSELBITS 0x18 /* 188 UCSR VMEbus timeout select bits */ #define VTO32US 0x00 /* VMEbus timeout length - 32 MicroSec */ #define VTO64US 0x01 /* VMEbus timeout length - 64 MicroSec */ #define VTO128US 0x10 /* VMEbus timeout length - 128 MicroSec */ #define VTODISABLE 0x18 /* VMEbus timeout length - disabled */ /* * processor dependend code section * main goal is to concentrate HW dependencies into a few lines */ #define ISR_LOW_SOFTINT_MASK(cpu) (1<