/* * THIS FILE IS AUTOMATICALLY GENERATED * DONT EDIT THIS FILE */ /* $OpenBSD: cn30xxfpareg.h,v 1.3 2022/12/28 01:39:21 yasuoka Exp $ */ /* * Copyright (c) 2007 Internet Initiative Japan, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Cavium Networks OCTEON CN30XX Hardware Reference Manual * CN30XX-HM-1.0 * 6.2 FPA Registers */ #ifndef _CN30XXFPAREG_H_ #define _CN30XXFPAREG_H_ /* ---- register offsets */ #define FPA_INT_SUM 0x0001180028000040ULL #define FPA_INT_ENB 0x0001180028000048ULL #define FPA_CTL_STATUS 0x0001180028000050ULL #define FPA_QUE0_AVAILABLE 0x0001180028000098ULL #define FPA_QUE1_AVAILABLE 0x00011800280000a0ULL #define FPA_QUE2_AVAILABLE 0x00011800280000a8ULL #define FPA_QUE3_AVAILABLE 0x00011800280000b0ULL #define FPA_QUE4_AVAILABLE 0x00011800280000b8ULL #define FPA_QUE5_AVAILABLE 0x00011800280000c0ULL #define FPA_QUE6_AVAILABLE 0x00011800280000c8ULL #define FPA_QUE7_AVAILABLE 0x00011800280000d0ULL #define FPA_WART_CTL 0x00011800280000d8ULL #define FPA_WART_STATUS 0x00011800280000e0ULL #define FPA_BIST_STATUS 0x00011800280000e8ULL #define FPA_QUE0_PAGE_INDEX 0x00011800280000f0ULL #define FPA_QUE1_PAGE_INDEX 0x00011800280000f8ULL #define FPA_QUE2_PAGE_INDEX 0x0001180028000100ULL #define FPA_QUE3_PAGE_INDEX 0x0001180028000108ULL #define FPA_QUE4_PAGE_INDEX 0x0001180028000110ULL #define FPA_QUE5_PAGE_INDEX 0x0001180028000118ULL #define FPA_QUE6_PAGE_INDEX 0x0001180028000120ULL #define FPA_QUE7_PAGE_INDEX 0x0001180028000128ULL #define FPA_QUE_EXP 0x0001180028000130ULL #define FPA_QUE_ACT 0x0001180028000138ULL /* ---- register bit definitions */ #define FPA_INT_SUM_XXX_63_28 0xfffffffff0000000ULL #define FPA_INT_SUM_Q7_PERR 0x0000000008000000ULL #define FPA_INT_SUM_Q7_COFF 0x0000000004000000ULL #define FPA_INT_SUM_Q7_UND 0x0000000002000000ULL #define FPA_INT_SUM_Q6_PERR 0x0000000001000000ULL #define FPA_INT_SUM_Q6_COFF 0x0000000000800000ULL #define FPA_INT_SUM_Q6_UND 0x0000000000400000ULL #define FPA_INT_SUM_Q5_PERR 0x0000000000200000ULL #define FPA_INT_SUM_Q5_COFF 0x0000000000100000ULL #define FPA_INT_SUM_Q5_UND 0x0000000000080000ULL #define FPA_INT_SUM_Q4_PERR 0x0000000000040000ULL #define FPA_INT_SUM_Q4_COFF 0x0000000000020000ULL #define FPA_INT_SUM_Q4_UND 0x0000000000010000ULL #define FPA_INT_SUM_Q3_PERR 0x0000000000008000ULL #define FPA_INT_SUM_Q3_COFF 0x0000000000004000ULL #define FPA_INT_SUM_Q3_UND 0x0000000000002000ULL #define FPA_INT_SUM_Q2_PERR 0x0000000000001000ULL #define FPA_INT_SUM_Q2_COFF 0x0000000000000800ULL #define FPA_INT_SUM_Q2_UND 0x0000000000000400ULL #define FPA_INT_SUM_Q1_PERR 0x0000000000000200ULL #define FPA_INT_SUM_Q1_COFF 0x0000000000000100ULL #define FPA_INT_SUM_Q1_UND 0x0000000000000080ULL #define FPA_INT_SUM_Q0_PERR 0x0000000000000040ULL #define FPA_INT_SUM_Q0_COFF 0x0000000000000020ULL #define FPA_INT_SUM_Q0_UND 0x0000000000000010ULL #define FPA_INT_SUM_FED1_DBE 0x0000000000000008ULL #define FPA_INT_SUM_FED1_SBE 0x0000000000000004ULL #define FPA_INT_SUM_FED0_DBE 0x0000000000000002ULL #define FPA_INT_SUM_FED0_SBE 0x0000000000000001ULL #define FPA_INT_ENB_XXX_63_28 0xfffffffff0000000ULL #define FPA_INT_ENB_Q7_PERR 0x0000000008000000ULL #define FPA_INT_ENB_Q7_COFF 0x0000000004000000ULL #define FPA_INT_ENB_Q7_UND 0x0000000002000000ULL #define FPA_INT_ENB_Q6_PERR 0x0000000001000000ULL #define FPA_INT_ENB_Q6_COFF 0x0000000000800000ULL #define FPA_INT_ENB_Q6_UND 0x0000000000400000ULL #define FPA_INT_ENB_Q5_PERR 0x0000000000200000ULL #define FPA_INT_ENB_Q5_COFF 0x0000000000100000ULL #define FPA_INT_ENB_Q5_UND 0x0000000000080000ULL #define FPA_INT_ENB_Q4_PERR 0x0000000000040000ULL #define FPA_INT_ENB_Q4_COFF 0x0000000000020000ULL #define FPA_INT_ENB_Q4_UND 0x0000000000010000ULL #define FPA_INT_ENB_Q3_PERR 0x0000000000008000ULL #define FPA_INT_ENB_Q3_COFF 0x0000000000004000ULL #define FPA_INT_ENB_Q3_UND 0x0000000000002000ULL #define FPA_INT_ENB_Q2_PERR 0x0000000000001000ULL #define FPA_INT_ENB_Q2_COFF 0x0000000000000800ULL #define FPA_INT_ENB_Q2_UND 0x0000000000000400ULL #define FPA_INT_ENB_Q1_PERR 0x0000000000000200ULL #define FPA_INT_ENB_Q1_COFF 0x0000000000000100ULL #define FPA_INT_ENB_Q1_UND 0x0000000000000080ULL #define FPA_INT_ENB_Q0_PERR 0x0000000000000040ULL #define FPA_INT_ENB_Q0_COFF 0x0000000000000020ULL #define FPA_INT_ENB_Q0_UND 0x0000000000000010ULL #define FPA_INT_ENB_FED1_DBE 0x0000000000000008ULL #define FPA_INT_ENB_FED1_SBE 0x0000000000000004ULL #define FPA_INT_ENB_FED0_DBE 0x0000000000000002ULL #define FPA_INT_ENB_FED0_SBE 0x0000000000000001ULL #define FPA_CTL_STATUS_XXX_63_18 0xfffffffffffc0000ULL #define FPA_CTL_STATUS_RESET 0x0000000000020000ULL #define FPA_CTL_STATUS_USE_LDT 0x0000000000010000ULL #define FPA_CTL_STATUS_USE_STT 0x0000000000008000ULL #define FPA_CTL_STATUS_ENB 0x0000000000004000ULL #define FPA_CTL_STATUS_MEM1_ERR 0x0000000000003f80ULL #define FPA_CTL_STATUS_MEM0_ERR 0x000000000000007fULL #define FPA_QUEX_AVAILABLE_XXX_63_29 0xffffffffe0000000ULL #define FPA_QUEX_AVAILABLE_QUE_SIZ 0x000000001fffffffULL #define FPA_WART_CTL_XXX_63_16 0xffffffffffff0000ULL #define FPA_WART_CTL_CTL 0x000000000000ffffULL #define FPA_WART_STATUS_XXX_63_32 0xffffffff00000000ULL #define FPA_WART_STATUS_STATUS 0x00000000ffffffffULL #define FPA_BIST_STATUS_XXX_63_5 0xffffffffffffffe0ULL #define FPA_BIST_STATUS_FRD 0x0000000000000010ULL #define FPA_BIST_STATUS_FPF0 0x0000000000000008ULL #define FPA_BIST_STATUS_FPF1 0x0000000000000004ULL #define FPA_BIST_STATUS_FFR 0x0000000000000002ULL #define FPA_BIST_STATUS_FDR 0x0000000000000001ULL #define FPA_QUEX_PAGE_INDEX_XXX_63_25 0xfffffffffe000000ULL #define FPA_QUEX_PAGE_INDEX_PG_NUM 0x0000000001ffffffULL #define FPA_QUE_EXP_XXX_63_32 0xffffffff00000000ULL #define FPA_QUE_EXP_XXX_31_29 0x00000000e0000000ULL #define FPA_QUE_EXP_EXP_QUE 0x000000001c000000ULL #define FPA_QUE_EXP_EXP_INDX 0x0000000003ffffffULL #define FPA_QUE_ACT_XXX_63_32 0xffffffff00000000ULL #define FPA_QUE_ACT_XXX_31_29 0x00000000e0000000ULL #define FPA_QUE_ACT_ACT_QUE 0x000000001c000000ULL #define FPA_QUE_ACT_ACT_INDX 0x0000000003ffffffULL /* ---- operations */ /* * 6.1 Free Pool Unit Operations */ #define FPA_MAJORDID 0x5 /* 0b00101 */ #define FPA_OPS_MAJORDID 0x0000f80000000000ULL #define FPA_OPS_MAJORDID_SHIFT 43 #define FPA_OPS_SUBDID 0x0000070000000000ULL #define FPA_OPS_SUBDID_SHIFT 40 #define FPA_OPS_XXX_39_0 0x000000ffffffffffULL /* 6.1.1 Load Operations */ #define FPA_OPS_LOAD_1 0x0001000000000000ULL #define FPA_OPS_LOAD_MAJORDID 0x0000f80000000000ULL #define FPA_OPS_LOAD_SUBDID 0x0000070000000000ULL #define FPA_OPS_LOAD_XXX_39_0 0x000000ffffffffffULL /* 6.1.2 IOBDMA Operations */ #define FPA_OPS_IOBDMA_SRCADDR 0xff00000000000000ULL #define FPA_OPS_IOBDMA_LEN 0x00ff000000000000ULL #define FPA_OPS_IOBDMA_LEN_SHIFT 48 #define FPA_OPS_IOBDMA_MAJORDID 0x0000f80000000000ULL #define FPA_OPS_IOBDMA_SUBDIR 0x0000070000000000ULL #define FPA_OPS_IOBDMA_XXX_39_0 0x000000ffffffffffULL /* 6.1.3 Store Operations */ #define FPA_OPS_STORE_1 0x0001000000000000ULL #define FPA_OPS_STORE_MAJORDID 0x0000f80000000000ULL #define FPA_OPS_STORE_SUBDID 0x0000070000000000ULL #define FPA_OPS_STORE_XXX_39_0 0x000000ffffffffffULL #define FPA_OPS_STORE_DATA_XXX_63_9 0xfffffffffffffe00ULL #define FPA_OPS_STORE_DATA_DWBCOUNT 0x00000000000001ffULL /* ---- bus_space(9) */ #define FPA_BASE 0x0001180028000000ULL #define FPA_SIZE 0x0200 #define FPA_INT_SUM_OFFSET 0x0040 #define FPA_INT_ENB_OFFSET 0x0048 #define FPA_CTL_STATUS_OFFSET 0x0050 #define FPA_QUE0_AVAILABLE_OFFSET 0x0098 #define FPA_QUE1_AVAILABLE_OFFSET 0x00a0 #define FPA_QUE2_AVAILABLE_OFFSET 0x00a8 #define FPA_QUE3_AVAILABLE_OFFSET 0x00b0 #define FPA_QUE4_AVAILABLE_OFFSET 0x00b8 #define FPA_QUE5_AVAILABLE_OFFSET 0x00c0 #define FPA_QUE6_AVAILABLE_OFFSET 0x00c8 #define FPA_QUE7_AVAILABLE_OFFSET 0x00d0 #define FPA_WART_CTL_OFFSET 0x00d8 #define FPA_WART_STATUS_OFFSET 0x00e0 #define FPA_BIST_STATUS_OFFSET 0x00e8 #define FPA_QUE0_PAGE_INDEX_OFFSET 0x00f0 #define FPA_QUE1_PAGE_INDEX_OFFSET 0x00f8 #define FPA_QUE2_PAGE_INDEX_OFFSET 0x0100 #define FPA_QUE3_PAGE_INDEX_OFFSET 0x0108 #define FPA_QUE4_PAGE_INDEX_OFFSET 0x0110 #define FPA_QUE5_PAGE_INDEX_OFFSET 0x0118 #define FPA_QUE6_PAGE_INDEX_OFFSET 0x0120 #define FPA_QUE7_PAGE_INDEX_OFFSET 0x0128 #define FPA_QUE_EXP_OFFSET 0x0130 #define FPA_QUE_ACT_OFFSET 0x0138 /* XXXX not use bit field */ /** * cvmx_fpa_ctl_status * * FPA_CTL_STATUS = FPA's Control/Status Register * * The FPA's interrupt enable register. */ #if 0 #ifndef MIPS_SPACE #define MIPS_SPACE typedef enum { MIPS_SPACE_XKSEG = 3LL, MIPS_SPACE_XKPHYS = 2LL, MIPS_SPACE_XSSEG = 1LL, MIPS_SPACE_XUSEG = 0LL } mips_space_t; #endif typedef enum { MIPS_XKSEG_SPACE_KSEG0 = 0LL, MIPS_XKSEG_SPACE_KSEG1 = 1LL, MIPS_XKSEG_SPACE_SSEG = 2LL, MIPS_XKSEG_SPACE_KSEG3 = 3LL } mips_xkseg_space_t; // decodes <14:13> of a kseg3 window address typedef enum { OCTEON_ADD_WIN_SCR = 0L, OCTEON_ADD_WIN_DMA = 1L, // see cvmx_add_win_dma_dec_t for further decode OCTEON_ADD_WIN_UNUSED = 2L, OCTEON_ADD_WIN_UNUSED2 = 3L } octeon_add_win_dec_t; // decode within DMA space typedef enum { OCTEON_ADD_WIN_DMA_ADD = 0L, // add store data to the write buffer entry, allocating it if necessary OCTEON_ADD_WIN_DMA_SENDMEM = 1L, // send out the write buffer entry to DRAM // store data must be normal DRAM memory space address in this case OCTEON_ADD_WIN_DMA_SENDDMA = 2L, // send out the write buffer entry as an IOBDMA command // see CVMX_ADD_WIN_DMA_SEND_DEC for data contents OCTEON_ADD_WIN_DMA_SENDIO = 3L, // send out the write buffer entry as an IO write // store data must be normal IO space address in this case OCTEON_ADD_WIN_DMA_SENDSINGLE = 4L, // send out a single-tick command on the NCB bus // no write buffer data needed/used } octeon_add_win_dma_dec_t; typedef union { uint64_t u64; struct { mips_space_t R : 2; uint64_t offset :62; } sva; // mapped or unmapped virtual address struct { uint64_t zeroes :33; uint64_t offset :31; } suseg; // mapped USEG virtual addresses (typically) struct { uint64_t ones :33; mips_xkseg_space_t sp : 2; uint64_t offset :29; } sxkseg; // mapped or unmapped virtual address struct { mips_space_t R : 2; // CVMX_MIPS_SPACE_XKPHYS in this case uint64_t cca : 3; // ignored by octeon uint64_t mbz :10; uint64_t pa :49; // physical address } sxkphys; // physical address accessed through xkphys unmapped virtual address struct { uint64_t mbz :15; uint64_t is_io : 1; // if set, the address is uncached and resides on MCB bus uint64_t did : 8; // the hardware ignores this field when is_io==0, else device ID uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I uint64_t offset :36; } sphys; // physical address struct { uint64_t zeroes :24; // techically, <47:40> are dont-cares uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I uint64_t offset :36; } smem; // physical mem address struct { uint64_t mem_region :2; uint64_t mbz :13; uint64_t is_io : 1; // 1 in this case uint64_t did : 8; // the hardware ignores this field when is_io==0, else device ID uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I uint64_t offset :36; } sio; // physical IO address struct { uint64_t ones : 49; octeon_add_win_dec_t csrdec : 2; // CVMX_ADD_WIN_SCR (0) in this case uint64_t addr : 13; } sscr; // scratchpad virtual address - accessed through a window at the end of kseg3 // there should only be stores to IOBDMA space, no loads struct { uint64_t ones : 49; octeon_add_win_dec_t csrdec : 2; // CVMX_ADD_WIN_DMA (1) in this case uint64_t unused2: 3; octeon_add_win_dma_dec_t type : 3; uint64_t addr : 7; } sdma; // IOBDMA virtual address - accessed through a window at the end of kseg3 struct { uint64_t didspace : 24; uint64_t unused : 40; } sfilldidspace; } cn30xxfpa_addr_t; #endif #endif /* _CN30XXFPAREG_H_ */