/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */ #include #include "radeon.h" #include #include "radeon_asic.h" void drm_fb_helper_restore(void); /* can't include radeon_drv.h due to duplicated defines in radeon_reg.h */ #define DRIVER_NAME "radeon" #define DRIVER_DESC "ATI Radeon" #define DRIVER_DATE "20080613" #define KMS_DRIVER_MAJOR 2 #define KMS_DRIVER_MINOR 29 #define KMS_DRIVER_PATCHLEVEL 0 int radeon_driver_irq_handler_kms(void *); void radeon_driver_irq_preinstall_kms(struct drm_device *); int radeon_driver_irq_postinstall_kms(struct drm_device *); void radeon_driver_irq_uninstall_kms(struct drm_device *d); int radeon_gem_object_init(struct drm_obj *); void radeon_gem_object_free(struct drm_obj *); int radeon_gem_object_open(struct drm_obj *, struct drm_file *); void radeon_gem_object_close(struct drm_obj *, struct drm_file *); int radeon_driver_unload_kms(struct drm_device *); int radeon_driver_load_kms(struct drm_device *, unsigned long); int radeon_info_ioctl(struct drm_device *, void *, struct drm_file *); int radeon_driver_firstopen_kms(struct drm_device *); void radeon_driver_lastclose_kms(struct drm_device *); int radeon_driver_open_kms(struct drm_device *, struct drm_file *); void radeon_driver_postclose_kms(struct drm_device *, struct drm_file *); void radeon_driver_preclose_kms(struct drm_device *, struct drm_file *); u32 radeon_get_vblank_counter_kms(struct drm_device *, int); int radeon_enable_vblank_kms(struct drm_device *, int); void radeon_disable_vblank_kms(struct drm_device *, int); int radeon_get_vblank_timestamp_kms(struct drm_device *, int, int *, struct timeval *, unsigned); void radeon_set_filp_rights(struct drm_device *, struct drm_file **, struct drm_file *, uint32_t *); int radeondrm_ioctl_kms(struct drm_device *, u_long, caddr_t, struct drm_file *); int radeon_ioctl_kms(struct drm_device *, u_long, caddr_t, struct drm_file *); int radeon_dma_ioctl_kms(struct drm_device *, struct drm_dma *, struct drm_file *); int radeon_cp_init_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_start_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_stop_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_reset_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_idle_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_resume_kms(struct drm_device *, void *, struct drm_file *); int radeon_engine_reset_kms(struct drm_device *, void *, struct drm_file *); int radeon_fullscreen_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_swap_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_clear_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_vertex_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_indices_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_texture_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_stipple_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_indirect_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_vertex2_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_cmdbuf_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_getparam_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_flip_kms(struct drm_device *, void *, struct drm_file *); int radeon_mem_alloc_kms(struct drm_device *, void *, struct drm_file *); int radeon_mem_free_kms(struct drm_device *, void *, struct drm_file *); int radeon_mem_init_heap_kms(struct drm_device *, void *, struct drm_file *); int radeon_irq_emit_kms(struct drm_device *, void *, struct drm_file *); int radeon_irq_wait_kms(struct drm_device *, void *, struct drm_file *); int radeon_cp_setparam_kms(struct drm_device *, void *, struct drm_file *); int radeon_surface_alloc_kms(struct drm_device *, void *, struct drm_file *); int radeon_surface_free_kms(struct drm_device *, void *, struct drm_file *); int radeondrm_probe(struct device *, void *, void *); void radeondrm_attach_kms(struct device *, struct device *, void *); int radeondrm_detach_kms(struct device *, int); int radeondrm_activate_kms(struct device *, int); void radeondrm_attachhook(void *); struct cfattach radeondrm_ca = { sizeof (struct radeon_device), radeondrm_probe, radeondrm_attach_kms, radeondrm_detach_kms, radeondrm_activate_kms }; struct cfdriver radeondrm_cd = { NULL, "radeondrm", DV_DULL }; /* Disable AGP writeback for scratch registers */ int radeon_no_wb; /* Disable/Enable modesetting */ int radeon_modeset = 1; /* Disable/Enable dynamic clocks */ int radeon_dynclks = -1; /* Enable ATOMBIOS modesetting for R4xx */ int radeon_r4xx_atom = 0; /* AGP Mode (-1 == PCI) */ int radeon_agpmode = 0; /* Restrict VRAM for testing */ int radeon_vram_limit = 0; /* Size of PCIE/IGP gart to setup in megabytes (32, 64, etc) */ int radeon_gart_size = 512; /* default gart size */ /* Run benchmark */ int radeon_benchmarking = 0; /* Run tests */ int radeon_testing = 0; /* Force connector table */ int radeon_connector_table = 0; /* TV enable (0 = disable) */ int radeon_tv = 1; /* Audio enable (1 = enable) */ int radeon_audio = 0; /* Display Priority (0 = auto, 1 = normal, 2 = high) */ int radeon_disp_priority = 0; /* hw i2c engine enable (0 = disable) */ int radeon_hw_i2c = 0; /* PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable) */ int radeon_pcie_gen2 = -1; /* MSI support (1 = enable, 0 = disable, -1 = auto) */ int radeon_msi = -1; /* GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable) */ int radeon_lockup_timeout = 10000; const struct drm_pcidev radeondrm_pciidlist[] = { {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_M241P, CHIP_RV380|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X300M24, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_M24GL, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X600_RV380, CHIP_RV380|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V3200, CHIP_RV380|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_IGP320, CHIP_RS100|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_IGP340, CHIP_RS200|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_9500PRO, CHIP_R300}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_AE9700PRO, CHIP_R300}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_AF9600TX, CHIP_R300}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_AGZ1, CHIP_R300}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_AH_9800SE, CHIP_R350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_AI_9800, CHIP_R350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_AJ_9800, CHIP_R350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_AKX2, CHIP_R350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_9600PRO, CHIP_RV350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_9600LE, CHIP_RV350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_9600XT, CHIP_RV350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_9550, CHIP_RV350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_ATT2, CHIP_RV350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_9650, CHIP_RV350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_AVT2, CHIP_RV350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_IGP_RS250, CHIP_RS200|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_R200_BB, CHIP_R200}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_R200_BC, CHIP_R200}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_IGP320M, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_M6, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_MIGP_RS250, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV250, CHIP_RV250}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_IG9000, CHIP_RV250}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_JHX800, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800PRO, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800SE, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800XT, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_X3256, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_M18, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_JOX800SE, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800XTPE, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_AIW_X800VE, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X850XT, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X850SE, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X850PRO, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X850XTPE, CHIP_R420|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_M7LW, CHIP_RV200|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_M7, CHIP_RV200|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_M6LY, CHIP_RV100|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_M6LZ, CHIP_RV100|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_M9LD, CHIP_RV250|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_M9Lf, CHIP_RV250}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_M9Lg, CHIP_RV250|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_R300, CHIP_R300}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON9500_PRO, CHIP_R300}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON9600TX, CHIP_R300}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_X1, CHIP_R300}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_R350, CHIP_R350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON9800, CHIP_R350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_9800XT, CHIP_R350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_X2, CHIP_R350}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV350, CHIP_RV350|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV350NQ, CHIP_RV350|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV350NR, CHIP_RV350|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV350NS, CHIP_RV350|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV350_WS, CHIP_RV350|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_9550, CHIP_RV350|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_AIW, CHIP_R100|RADEON_SINGLE_CRTC}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_QE, CHIP_R100|RADEON_SINGLE_CRTC}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_QF, CHIP_R100|RADEON_SINGLE_CRTC}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_QG, CHIP_R100|RADEON_SINGLE_CRTC}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_QH, CHIP_R200}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_R200_QL, CHIP_R200}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_R200_QM, CHIP_R200}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV200_QW, CHIP_RV200}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV200_QX, CHIP_RV200}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_QY, CHIP_RV100}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_QZ, CHIP_RV100}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_ES1000_1, CHIP_RV100}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_M300_M22, CHIP_RV380|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X600_M24C, CHIP_RV380|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_M44, CHIP_RV380|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800_RV423, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800PRORV423, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800XT_RV423, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800SE_RV423, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800XTPRV430, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800XL_RV430, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800SE_RV430, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800_RV430, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V7100_RV423, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V5100_RV423, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_UR_RV423, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_UT_RV423, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V5000_M26, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V5000_M26b, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X700XL_M26, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X700_M26_1, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X700_M26_2, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X550XTX, CHIP_RV410|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_IGP9100_IGP, CHIP_RS300|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_IGP9100, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, #if 0 {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RS480, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_IGPGART}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RS480_B, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RS482, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RS482_B, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, #endif {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RV280_PRO, CHIP_RV280}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RV280, CHIP_RV280}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RV280_B, CHIP_RV280}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RV280_SE_S, CHIP_RV280}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREMV_2200, CHIP_RV280}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_ES1000, CHIP_RV100}, #if 0 {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RS400, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RS400_B, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RC410, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RC410_B, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, #endif {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X300, CHIP_RV380|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X600_RV370, CHIP_RV380|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X550, CHIP_RV380|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_RV370, CHIP_RV380|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREMV_2200_5B65, CHIP_RV380|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RV280_M, CHIP_RV280|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_M9PLUS, CHIP_RV280|RADEON_IS_MOBILITY}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800XT_M28, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V5100_M28, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X800_M28, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X850_R480, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X850XTPER480, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X850SE_R480, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800_GTO, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_R480, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X850XT_R480, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X800XT_R423, CHIP_R423|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V5000_R410, CHIP_RV410|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X700XT_R410, CHIP_RV410|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X700PRO_R410, CHIP_RV410|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X700SE_R410, CHIP_RV410|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X700_PCIE, CHIP_RV410|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X700SE_PCIE, CHIP_RV410|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1800A, CHIP_R520|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1800XT, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X1800, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_M_V7200, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_M_V7200, CHIP_R520|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V5300, CHIP_R520|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_M_V7100, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1800B, CHIP_R520|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1800C, CHIP_R520|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1800D, CHIP_R520|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1800E, CHIP_R520|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1800F, CHIP_R520|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V7300, CHIP_R520|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V7350, CHIP_R520|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1600, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV505_1, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1300_X1550, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1550, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_M54_GL, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1400, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1550_X1300, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1550_64, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1300_M52, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X1300_4A, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X1300_4B, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X1300_4C, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1300_4D, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1300_4E, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV505_2, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV505_3, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V3300, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V3350, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1300_5E, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1550_64_2, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1300X1550, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1600_81, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1300PRO, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1450, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1300, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X2300, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X2300_2, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X1350, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X1350_2, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X1450, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1300_8F, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1550_2, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X1350_3, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREMV_2250, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1550_64_3, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1600_C0, CHIP_RV530|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1650, CHIP_RV530|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1600_PRO, CHIP_RV530|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1600_C3, CHIP_RV530|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V5200, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1600_M, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1650_PRO, CHIP_RV530|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1650_PRO2, CHIP_RV530|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1600_CD, CHIP_RV530|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1300_XT, CHIP_RV530|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V3400, CHIP_RV530|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV530_M56, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1700, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1700XT, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V5200_1, CHIP_RV530|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X1700, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X2300HD, CHIP_RV515|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X2300HD, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X2300HD_1, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1950_40, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1900_43, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1950_44, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1900_45, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1900_46, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1900_47, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1900_48, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1900_49, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1900_4A, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1900_4B, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1900_4C, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1900_4D, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_STREAM_PROCESSOR, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1900_4F, CHIP_R580|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1950_PRO, CHIP_RV570|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV560, CHIP_RV560|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV560_1, CHIP_RV560|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_X1900, CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV560_2, CHIP_RV560|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1950GT, CHIP_RV570|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV570, CHIP_RV570|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV570_2, CHIP_RV570|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V7400, CHIP_RV570|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV560_3, CHIP_RV560|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RX1650_XT, CHIP_RV560|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1650_1, CHIP_RV560|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RV560_4, CHIP_RV560|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_9000IGP, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_RS350IGP, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, #if 0 {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1250_1, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1250_2, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_X1250IGP, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, #endif {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V4000, CHIP_RV610|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREMV_2260, CHIP_RV610|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_E2400, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2350, CHIP_RV610|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2400_PRO, CHIP_RV610|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2400PROAGP, CHIP_RV610|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2400_XT, CHIP_RV610|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2400_M72, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2400_XT_M, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2400PROPCI, CHIP_RV610|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREMV_2450, CHIP_RV620|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREMV_2260_1, CHIP_RV620|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREMV_2260_2, CHIP_RV620|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V3700, CHIP_RV620|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3400_M82, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3430, CHIP_RV620|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3430_M, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3450, CHIP_RV620|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3450_AGP, CHIP_RV620|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3450_PCI, CHIP_RV620|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3470, CHIP_RV620|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V5600, CHIP_RV630|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V3600, CHIP_RV630|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2600_PRO, CHIP_RV630|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2600_XT, CHIP_RV630|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2600_M76, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2600_XT_M, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2600XTAGP, CHIP_RV630|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD2600PROAGP, CHIP_RV630|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V5700_M, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V5725_M, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3600, CHIP_RV635|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3650_AGP, CHIP_RV635|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3650_M, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3650, CHIP_RV635|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3670_M, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREGL_V7700, CHIP_RV670|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIRESTREAM_9170, CHIP_RV670|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3690, CHIP_RV670|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3850, CHIP_RV670|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3850_AGP, CHIP_RV670|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3850_M, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3850_X2_M, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3870, CHIP_RV670|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3870_X2, CHIP_RV670|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3870_M, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3870_X2_M, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3000, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3200_1, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3200_2, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD3300, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_RG220, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4350, CHIP_RV710|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4300_M, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4330_M, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4500_M, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4500_M_2, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4550, CHIP_RV710|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_E4600, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V3750, CHIP_RV730|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V5700, CHIP_RV730|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V7750, CHIP_RV730|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4600, CHIP_RV730|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4650, CHIP_RV730|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4650_M, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4670, CHIP_RV730|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4670_M, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4670_M_2, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_M5750, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4700, CHIP_RV740|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4770, CHIP_RV740|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4830_M, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4850_M_2, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_M7740, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_M7750, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_RV770, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V7760, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V8700, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V8750, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIRESTREAM_9250, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIRESTREAM_9270, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4800, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4800_2, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4850, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4850_M, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4850_X2_M, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4850_X2, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4870, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4870_X2, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4870_M, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4870_M98, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4890, CHIP_RV770|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4100, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4200, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4250, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4100_M, CHIP_RS880|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4200_M, CHIP_RS880|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD4290, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_HD5470, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_HD5430, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6370M, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6330M, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CEDAR, CHIP_CEDAR|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_CEDAR, CHIP_CEDAR|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_2460, CHIP_CEDAR|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_2270, CHIP_CEDAR|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7300, CHIP_CEDAR|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5450, CHIP_CEDAR|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7350, CHIP_CEDAR|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CEDAR_LE, CHIP_CEDAR|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_HD5730, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_HD5650, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_HD5570, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V4800, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V3800, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5670, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5570, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5550, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_REDWOOD, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_HD5870, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_HD5850, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6850M, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V5800, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_HD5800, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5770, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5670_640SP, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6770, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5750, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6750, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CYPRESS, CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V8800, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V7800, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V9800, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIRESTREAM_9370, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIRESTREAM_9350, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5870, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5850, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6800, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5830, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5970, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD5900, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6310_1, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6310_2, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6250_1, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6250_2, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6320, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6290, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7340, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7310, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7290, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6550D, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6620G, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6520G, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6480G_1, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6480G_2, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6530D, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SUMO_1, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SUMO_2, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SUMO_3, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SUMO_4, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6370D, CHIP_SUMO2|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6380G, CHIP_SUMO2|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6410D_1, CHIP_SUMO2|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6410D_2, CHIP_SUMO2|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6970M, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_HD6000_1, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_BARTS_1, CHIP_BARTS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_BARTS_2, CHIP_BARTS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MOBILITY_HD6000_2, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6900M, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_BARTS_3, CHIP_BARTS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_BARTS_4, CHIP_BARTS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_BARTS_5, CHIP_BARTS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_BARTS_6, CHIP_BARTS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6870, CHIP_BARTS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6850, CHIP_BARTS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6790, CHIP_BARTS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6730M, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6600M, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6610M, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_E6760, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TURKS_1, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TURKS_2, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TURKS_3, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TURKS_4, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TURKS_5, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V4900, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V3900, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6650A, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7670A, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6670, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6570, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TURKS_6, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7570, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6510, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7670M_1, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7550M, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7000M, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7670M_2, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7400, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TURKS_7, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TURKS_8, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TURKS_9, CHIP_TURKS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6400M, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6430M, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAICOS_1, CHIP_CAICOS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_E6460, CHIP_CAICOS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6400M_1, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6400M_2, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAICOS_2, CHIP_CAICOS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAICOS_3, CHIP_CAICOS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAICOS_4, CHIP_CAICOS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6450A, CHIP_CAICOS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8490, CHIP_CAICOS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7450A, CHIP_CAICOS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7470, CHIP_CAICOS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6450, CHIP_CAICOS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7450, CHIP_CAICOS|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAYMAN_1, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAYMAN_2, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAYMAN_3, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAYMAN_4, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V7900, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAYMAN_5, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAYMAN_6, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V5900, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAYMAN_7, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_CAYMAN_8, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6970, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6950, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6990_1, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6990_2, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD6930, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_ARUBA_1, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7660D, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7640G_1, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7560D, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_A300_1, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_A300_2, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7620G_1, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7600G_1, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7500G_1, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7500G_2, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8650G, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8670D, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8550G, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8570D, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8610G, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7660G, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7640G_2, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7620G_2, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7600G_2, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7500G, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7520G_1, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7540D, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7420G_1, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7480D, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7400G_1, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8450G, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8470D, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8350G, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8370D, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8510G, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8410G, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8310G, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_ARUBA_2, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_ARUBA_3, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7520G_2, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7420G_2, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7400G_2, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_W9000, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V_1, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_V_2, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TAHITI_1, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TAHITI_2, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TAHITI_3, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TAHITI_4, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7970, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7900, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7950, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7990, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7870XT, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_TAHITI_5, CHIP_TAHITI|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7970M, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8970M, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_PITCAIRN_1, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_PITCAIRN_2, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_W7000, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_W5000, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_PITCAIRN_3, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_PITCAIRN_4, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_PITCAIRN_5, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_PITCAIRN_6, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7870, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7850, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_PITCAIRN_7, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8800M_1, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8800M_2, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_VERDE_4, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8800M_3, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7700M_1, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7870M, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7700M_2, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7850M, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_W600, CHIP_VERDE|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_VERDE_1, CHIP_VERDE|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_VERDE_5, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8800M, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_FIREPRO_M4000, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7730M, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7800M, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7700M, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_VERDE_6, CHIP_VERDE|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7730, CHIP_VERDE|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_VERDE_2, CHIP_VERDE|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_VERDE_3, CHIP_VERDE|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7700, CHIP_VERDE|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7770, CHIP_VERDE|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD7750, CHIP_VERDE|RADEON_NEW_MEMMAP}, #if 0 {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8670A, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8730M, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_OLAND_1, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_OLAND_2, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8790M, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8530M, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8600, CHIP_OLAND|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8570, CHIP_OLAND|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8500, CHIP_OLAND|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_OLAND_3, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_OLAND_4, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_OLAND_5, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_OLAND_6, CHIP_OLAND|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8670M, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8500M_1, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_HAINAN_1, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_HAINAN_2, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_HAINAN_3, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, {PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_HD8500M_2, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, #endif {0, 0, 0} }; static struct drm_driver_info kms_driver = { .flags = DRIVER_AGP | DRIVER_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_IRQ | DRIVER_DMA | DRIVER_GEM | DRIVER_MODESET, .buf_priv_size = 0, .ioctl = radeondrm_ioctl_kms, .firstopen = radeon_driver_firstopen_kms, .open = radeon_driver_open_kms, .mmap = radeon_mmap, #ifdef notyet .preclose = radeon_driver_preclose_kms, .postclose = radeon_driver_postclose_kms, #endif .lastclose = radeon_driver_lastclose_kms, #ifdef notyet .suspend = radeon_suspend_kms, .resume = radeon_resume_kms, #endif .get_vblank_counter = radeon_get_vblank_counter_kms, .enable_vblank = radeon_enable_vblank_kms, .disable_vblank = radeon_disable_vblank_kms, .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, .get_scanout_position = radeon_get_crtc_scanoutpos, #if defined(CONFIG_DEBUG_FS) .debugfs_init = radeon_debugfs_init, .debugfs_cleanup = radeon_debugfs_cleanup, #endif .irq_preinstall = radeon_driver_irq_preinstall_kms, .irq_postinstall = radeon_driver_irq_postinstall_kms, .irq_uninstall = radeon_driver_irq_uninstall_kms, .irq_handler = radeon_driver_irq_handler_kms, .gem_init_object = radeon_gem_object_init, .gem_free_object = radeon_gem_object_free, #ifdef notyet .gem_open_object = radeon_gem_object_open, .gem_close_object = radeon_gem_object_close, #endif .gem_size = sizeof(struct radeon_bo), .dma_ioctl = radeon_dma_ioctl_kms, .dumb_create = radeon_mode_dumb_create, .dumb_map_offset = radeon_mode_dumb_mmap, .dumb_destroy = radeon_mode_dumb_destroy, #ifdef notyet .fops = &radeon_driver_kms_fops, .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_export = radeon_gem_prime_export, .gem_prime_import = radeon_gem_prime_import, #endif .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, .major = KMS_DRIVER_MAJOR, .minor = KMS_DRIVER_MINOR, .patchlevel = KMS_DRIVER_PATCHLEVEL, }; int radeondrm_probe(struct device *parent, void *match, void *aux) { return drm_pciprobe((struct pci_attach_args *)aux, radeondrm_pciidlist); } /** * radeon_driver_unload_kms - Main unload function for KMS. * * @dev: drm dev pointer * * This is the main unload function for KMS (all asics). * It calls radeon_modeset_fini() to tear down the * displays, and radeon_device_fini() to tear down * the rest of the device (CP, writeback, etc.). * Returns 0 on success. */ int radeondrm_detach_kms(struct device *self, int flags) { struct radeon_device *rdev = (struct radeon_device *)self; if (rdev == NULL) return 0; radeon_acpi_fini(rdev); radeon_modeset_fini(rdev); radeon_device_fini(rdev); if (rdev->ddev != NULL) { config_detach((struct device *)rdev->ddev, flags); rdev->ddev = NULL; } pci_intr_disestablish(rdev->pc, rdev->irqh); if (rdev->rmmio_size > 0) bus_space_unmap(rdev->memt, rdev->rmmio, rdev->rmmio_size); return 0; } int radeondrm_wsioctl(void *, u_long, caddr_t, int, struct proc *); paddr_t radeondrm_wsmmap(void *, off_t, int); int radeondrm_alloc_screen(void *, const struct wsscreen_descr *, void **, int *, int *, long *); void radeondrm_free_screen(void *, void *); int radeondrm_show_screen(void *, void *, int, void (*)(void *, int, int), void *); void radeondrm_doswitch(void *, void *); int radeondrm_getchar(void *, int, int, struct wsdisplay_charcell *); struct wsscreen_descr radeondrm_stdscreen = { "std", 0, 0, 0, 0, 0, WSSCREEN_UNDERLINE | WSSCREEN_HILIT | WSSCREEN_REVERSE | WSSCREEN_WSCOLORS }; const struct wsscreen_descr *radeondrm_scrlist[] = { &radeondrm_stdscreen, }; struct wsscreen_list radeondrm_screenlist = { nitems(radeondrm_scrlist), radeondrm_scrlist }; struct wsdisplay_accessops radeondrm_accessops = { radeondrm_wsioctl, radeondrm_wsmmap, radeondrm_alloc_screen, radeondrm_free_screen, radeondrm_show_screen, NULL, NULL, radeondrm_getchar, radeondrm_burner }; int radeondrm_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) { return (-1); } paddr_t radeondrm_wsmmap(void *v, off_t off, int prot) { return (-1); } int radeondrm_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, int *curxp, int *curyp, long *attrp) { struct radeon_device *rdev = v; struct rasops_info *ri = &rdev->ro; return rasops_alloc_screen(ri, cookiep, curxp, curyp, attrp); } void radeondrm_free_screen(void *v, void *cookie) { struct radeon_device *rdev = v; struct rasops_info *ri = &rdev->ro; return rasops_free_screen(ri, cookie); } int radeondrm_show_screen(void *v, void *cookie, int waitok, void (*cb)(void *, int, int), void *cbarg) { struct radeon_device *rdev = v; struct rasops_info *ri = &rdev->ro; if (cookie == ri->ri_active) return (0); rdev->switchcb = cb; rdev->switchcbarg = cbarg; if (cb) { workq_queue_task(NULL, &rdev->switchwqt, 0, radeondrm_doswitch, v, cookie); return (EAGAIN); } radeondrm_doswitch(v, cookie); return (0); } void radeondrm_doswitch(void *v, void *cookie) { struct radeon_device *rdev = v; struct rasops_info *ri = &rdev->ro; rasops_show_screen(ri, cookie, 0, NULL, NULL); drm_fb_helper_restore(); if (rdev->switchcb) (rdev->switchcb)(rdev->switchcbarg, 0, 0); } int radeondrm_getchar(void *v, int row, int col, struct wsdisplay_charcell *cell) { struct radeon_device *rdev = v; struct rasops_info *ri = &rdev->ro; return rasops_getchar(ri, row, col, cell); } /** * radeon_driver_load_kms - Main load function for KMS. * * @dev: drm dev pointer * @flags: device flags * * This is the main load function for KMS (all asics). * It calls radeon_device_init() to set up the non-display * parts of the chip (asic init, CP, writeback, etc.), and * radeon_modeset_init() to set up the display parts * (crtcs, encoders, hotplug detect, etc.). * Returns 0 on success, error on failure. */ void radeondrm_attach_kms(struct device *parent, struct device *self, void *aux) { struct radeon_device *rdev = (struct radeon_device *)self; struct drm_device *dev; struct pci_attach_args *pa = aux; const struct drm_pcidev *id_entry; #ifndef __sparc64__ struct vga_pci_softc *vga_sc = (struct vga_pci_softc *)parent; #endif int is_agp; pcireg_t type; id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id), radeondrm_pciidlist); rdev->flags = id_entry->driver_private; rdev->pc = pa->pa_pc; rdev->pa_tag = pa->pa_tag; rdev->iot = pa->pa_iot; rdev->memt = pa->pa_memt; rdev->dmat = pa->pa_dmat; #define RADEON_PCI_MEM 0x10 #define RADEON_PCI_IO 0x14 #define RADEON_PCI_MMIO 0x18 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM); if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || pci_mapreg_info(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, type, &rdev->fb_aper_offset, &rdev->fb_aper_size, NULL)) { printf(": can't get frambuffer info\n"); return; } if (PCI_MAPREG_MEM_TYPE(type) != PCI_MAPREG_MEM_TYPE_64BIT) { if (pci_mapreg_map(pa, RADEON_PCI_IO, PCI_MAPREG_TYPE_IO, 0, NULL, &rdev->rio_mem, NULL, &rdev->rio_mem_size, 0)) { printf(": can't map IO space\n"); return; } } type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RADEON_PCI_MMIO); if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || pci_mapreg_map(pa, RADEON_PCI_MMIO, type, 0, NULL, &rdev->rmmio, &rdev->rmmio_base, &rdev->rmmio_size, 0)) { printf(": can't map mmio space\n"); return; } if (pci_intr_map(pa, &rdev->intrh) != 0) { printf(": couldn't map interrupt\n"); return; } printf(": %s\n", pci_intr_string(pa->pa_pc, rdev->intrh)); #ifdef notyet mtx_init(&rdev->swi_lock, IPL_TTY); #endif /* update BUS flag */ if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, NULL, NULL)) { rdev->flags |= RADEON_IS_AGP; } else if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, NULL, NULL)) { rdev->flags |= RADEON_IS_PCIE; } else { rdev->flags |= RADEON_IS_PCI; } DRM_DEBUG("%s card detected\n", ((rdev->flags & RADEON_IS_AGP) ? "AGP" : (((rdev->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); is_agp = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, NULL, NULL); dev = (struct drm_device *)drm_attach_pci(&kms_driver, pa, is_agp, self); rdev->ddev = dev; rdev->irqh = pci_intr_establish(pa->pa_pc, rdev->intrh, IPL_TTY, radeon_driver_irq_handler_kms, rdev->ddev, rdev->dev.dv_xname); if (rdev->irqh == NULL) { printf("%s: couldn't establish interrupt\n", rdev->dev.dv_xname); return; } #ifndef __sparc64__ vga_sc->sc_type = -1; #endif if (rootvp == NULL) mountroothook_establish(radeondrm_attachhook, rdev); else radeondrm_attachhook(rdev); } void radeondrm_attachhook(void *xsc) { struct radeon_device *rdev = xsc; int r, acpi_status; int console = 0; /* radeon_device_init should report only fatal error * like memory allocation failure or iomapping failure, * or memory manager initialization failure, it must * properly initialize the GPU MC controller and permit * VRAM allocation */ r = radeon_device_init(rdev, rdev->ddev); if (r) { printf(": Fatal error during GPU init\n"); return; } /* Again modeset_init should fail only on fatal error * otherwise it should provide enough functionalities * for shadowfb to run */ r = radeon_modeset_init(rdev); if (r) printf("Fatal error during modeset init\n"); /* Call ACPI methods: require modeset init * but failure is not fatal */ if (!r) { acpi_status = radeon_acpi_init(rdev); if (acpi_status) DRM_DEBUG("Error during ACPI methods call\n"); } { #ifdef __sparc64__ extern int fbnode; #else extern int wsdisplay_console_initted; #endif struct wsemuldisplaydev_attach_args aa; struct rasops_info *ri = &rdev->ro; if (ri->ri_bits == NULL) return; drm_fb_helper_restore(); ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY; #ifdef __sparc64__ ri->ri_flg |= RI_BSWAP; #endif rasops_init(ri, 160, 160); ri->ri_hw = rdev; radeondrm_stdscreen.capabilities = ri->ri_caps; radeondrm_stdscreen.nrows = ri->ri_rows; radeondrm_stdscreen.ncols = ri->ri_cols; radeondrm_stdscreen.textops = &ri->ri_ops; radeondrm_stdscreen.fontwidth = ri->ri_font->fontwidth; radeondrm_stdscreen.fontheight = ri->ri_font->fontheight; #ifdef __sparc64__ if (fbnode == PCITAG_NODE(rdev->pa_tag)) console = 1; #else console = wsdisplay_console_initted; #endif aa.console = console; aa.scrdata = &radeondrm_screenlist; aa.accessops = &radeondrm_accessops; aa.accesscookie = rdev; aa.defaultscreens = 0; if (console) { long defattr; ri->ri_ops.alloc_attr(ri->ri_active, 0, 0, 0, &defattr); wsdisplay_cnattach(&radeondrm_stdscreen, ri->ri_active, 0, 0, defattr); aa.console = 1; } printf("%s: %dx%d\n", rdev->dev.dv_xname, ri->ri_width, ri->ri_height); config_found_sm(&rdev->dev, &aa, wsemuldisplaydevprint, wsemuldisplaydevsubmatch); } } int radeondrm_activate_kms(struct device *arg, int act) { struct radeon_device *rdev = (struct radeon_device *)arg; switch (act) { case DVACT_SUSPEND: radeon_suspend_kms(rdev->ddev); break; case DVACT_RESUME: radeon_resume_kms(rdev->ddev); break; } return (0); } /** * radeon_set_filp_rights - Set filp right. * * @dev: drm dev pointer * @owner: drm file * @applier: drm file * @value: value * * Sets the filp rights for the device (all asics). */ void radeon_set_filp_rights(struct drm_device *dev, struct drm_file **owner, struct drm_file *applier, uint32_t *value) { DRM_LOCK(); if (*value == 1) { /* wants rights */ if (!*owner) *owner = applier; } else if (*value == 0) { /* revokes rights */ if (*owner == applier) *owner = NULL; } *value = *owner == applier ? 1 : 0; DRM_UNLOCK(); } /* * Userspace get information ioctl */ /** * radeon_info_ioctl - answer a device specific request. * * @rdev: radeon device pointer * @data: request object * @filp: drm filp * * This function is used to pass device specific parameters to the userspace * drivers. Examples include: pci device id, pipeline parms, tiling params, * etc. (all asics). * Returns 0 on success, -EINVAL on failure. */ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct radeon_device *rdev = dev->dev_private; struct drm_radeon_info *info = data; struct radeon_mode_info *minfo = &rdev->mode_info; uint32_t value, *value_ptr; uint64_t value64, *value_ptr64; struct drm_crtc *crtc; int i, found; /* TIMESTAMP is a 64-bit value, needs special handling. */ if (info->request == RADEON_INFO_TIMESTAMP) { if (rdev->family >= CHIP_R600) { value_ptr64 = (uint64_t*)((unsigned long)info->value); if (rdev->family >= CHIP_TAHITI) { value64 = si_get_gpu_clock(rdev); } else { value64 = r600_get_gpu_clock(rdev); } if (DRM_COPY_TO_USER(value_ptr64, &value64, sizeof(value64))) { DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); return -EFAULT; } return 0; } else { DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); return -EINVAL; } } value_ptr = (uint32_t *)((unsigned long)info->value); if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) { DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); return -EFAULT; } switch (info->request) { case RADEON_INFO_DEVICE_ID: value = dev->pci_device; break; case RADEON_INFO_NUM_GB_PIPES: value = rdev->num_gb_pipes; break; case RADEON_INFO_NUM_Z_PIPES: value = rdev->num_z_pipes; break; case RADEON_INFO_ACCEL_WORKING: /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) value = false; else value = rdev->accel_working; break; case RADEON_INFO_CRTC_FROM_ID: for (i = 0, found = 0; i < rdev->num_crtc; i++) { crtc = (struct drm_crtc *)minfo->crtcs[i]; if (crtc && crtc->base.id == value) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); value = radeon_crtc->crtc_id; found = 1; break; } } if (!found) { DRM_DEBUG_KMS("unknown crtc id %d\n", value); return -EINVAL; } break; case RADEON_INFO_ACCEL_WORKING2: value = rdev->accel_working; break; case RADEON_INFO_TILING_CONFIG: if (rdev->family >= CHIP_TAHITI) value = rdev->config.si.tile_config; else if (rdev->family >= CHIP_CAYMAN) value = rdev->config.cayman.tile_config; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.tile_config; else if (rdev->family >= CHIP_RV770) value = rdev->config.rv770.tile_config; else if (rdev->family >= CHIP_R600) value = rdev->config.r600.tile_config; else { DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); return -EINVAL; } break; case RADEON_INFO_WANT_HYPERZ: /* The "value" here is both an input and output parameter. * If the input value is 1, filp requests hyper-z access. * If the input value is 0, filp revokes its hyper-z access. * * When returning, the value is 1 if filp owns hyper-z access, * 0 otherwise. */ if (value >= 2) { DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value); return -EINVAL; } radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value); break; case RADEON_INFO_WANT_CMASK: /* The same logic as Hyper-Z. */ if (value >= 2) { DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value); return -EINVAL; } radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value); break; case RADEON_INFO_CLOCK_CRYSTAL_FREQ: /* return clock value in KHz */ value = rdev->clock.spll.reference_freq * 10; break; case RADEON_INFO_NUM_BACKENDS: if (rdev->family >= CHIP_TAHITI) value = rdev->config.si.max_backends_per_se * rdev->config.si.max_shader_engines; else if (rdev->family >= CHIP_CAYMAN) value = rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.max_backends; else if (rdev->family >= CHIP_RV770) value = rdev->config.rv770.max_backends; else if (rdev->family >= CHIP_R600) value = rdev->config.r600.max_backends; else { return -EINVAL; } break; case RADEON_INFO_NUM_TILE_PIPES: if (rdev->family >= CHIP_TAHITI) value = rdev->config.si.max_tile_pipes; else if (rdev->family >= CHIP_CAYMAN) value = rdev->config.cayman.max_tile_pipes; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.max_tile_pipes; else if (rdev->family >= CHIP_RV770) value = rdev->config.rv770.max_tile_pipes; else if (rdev->family >= CHIP_R600) value = rdev->config.r600.max_tile_pipes; else { return -EINVAL; } break; case RADEON_INFO_FUSION_GART_WORKING: value = 1; break; case RADEON_INFO_BACKEND_MAP: if (rdev->family >= CHIP_TAHITI) value = rdev->config.si.backend_map; else if (rdev->family >= CHIP_CAYMAN) value = rdev->config.cayman.backend_map; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.backend_map; else if (rdev->family >= CHIP_RV770) value = rdev->config.rv770.backend_map; else if (rdev->family >= CHIP_R600) value = rdev->config.r600.backend_map; else { return -EINVAL; } break; case RADEON_INFO_VA_START: /* this is where we report if vm is supported or not */ return -EINVAL; #ifdef notyet if (rdev->family < CHIP_CAYMAN) return -EINVAL; value = RADEON_VA_RESERVED_SIZE; break; #endif case RADEON_INFO_IB_VM_MAX_SIZE: /* this is where we report if vm is supported or not */ return -EINVAL; #ifdef notyet if (rdev->family < CHIP_CAYMAN) return -EINVAL; value = RADEON_IB_VM_MAX_SIZE; break; #endif case RADEON_INFO_MAX_PIPES: if (rdev->family >= CHIP_TAHITI) value = rdev->config.si.max_cu_per_sh; else if (rdev->family >= CHIP_CAYMAN) value = rdev->config.cayman.max_pipes_per_simd; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.max_pipes; else if (rdev->family >= CHIP_RV770) value = rdev->config.rv770.max_pipes; else if (rdev->family >= CHIP_R600) value = rdev->config.r600.max_pipes; else { return -EINVAL; } break; case RADEON_INFO_MAX_SE: if (rdev->family >= CHIP_TAHITI) value = rdev->config.si.max_shader_engines; else if (rdev->family >= CHIP_CAYMAN) value = rdev->config.cayman.max_shader_engines; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.num_ses; else value = 1; break; case RADEON_INFO_MAX_SH_PER_SE: if (rdev->family >= CHIP_TAHITI) value = rdev->config.si.max_sh_per_se; else return -EINVAL; break; default: DRM_DEBUG_KMS("Invalid request %d\n", info->request); return -EINVAL; } if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); return -EFAULT; } return 0; } /* * Outdated mess for old drm with Xorg being in charge (void function now). */ /** * radeon_driver_firstopen_kms - drm callback for first open * * @dev: drm dev pointer * * Nothing to be done for KMS (all asics). * Returns 0 on success. */ int radeon_driver_firstopen_kms(struct drm_device *dev) { return 0; } /** * radeon_driver_firstopen_kms - drm callback for last close * * @dev: drm dev pointer * * Switch vga switcheroo state after last close (all asics). */ void radeon_driver_lastclose_kms(struct drm_device *dev) { #ifdef notyet vga_switcheroo_process_delayed_switch(); #endif } /** * radeon_driver_open_kms - drm callback for open * * @dev: drm dev pointer * @file_priv: drm file * * On device open, init vm on cayman+ (all asics). * Returns 0 on success, error on failure. */ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) { struct radeon_device *rdev = dev->dev_private; file_priv->driver_priv = NULL; /* new gpu have virtual address space support */ if (rdev->family >= CHIP_CAYMAN) { struct radeon_fpriv *fpriv; struct radeon_bo_va *bo_va; int r; fpriv = malloc(sizeof(*fpriv), M_DRM, M_WAITOK | M_ZERO); if (unlikely(!fpriv)) { return -ENOMEM; } radeon_vm_init(rdev, &fpriv->vm); /* map the ib pool buffer read only into * virtual address space */ bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, rdev->ring_tmp_bo.bo); r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, RADEON_VM_PAGE_READABLE | RADEON_VM_PAGE_SNOOPED); if (r) { radeon_vm_fini(rdev, &fpriv->vm); free(fpriv, M_DRM); return r; } file_priv->driver_priv = fpriv; } return 0; } /** * radeon_driver_postclose_kms - drm callback for post close * * @dev: drm dev pointer * @file_priv: drm file * * On device post close, tear down vm on cayman+ (all asics). */ void radeon_driver_postclose_kms(struct drm_device *dev, struct drm_file *file_priv) { struct radeon_device *rdev = dev->dev_private; /* new gpu have virtual address space support */ if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { struct radeon_fpriv *fpriv = file_priv->driver_priv; struct radeon_bo_va *bo_va; int r; r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); if (!r) { bo_va = radeon_vm_bo_find(&fpriv->vm, rdev->ring_tmp_bo.bo); if (bo_va) radeon_vm_bo_rmv(rdev, bo_va); radeon_bo_unreserve(rdev->ring_tmp_bo.bo); } radeon_vm_fini(rdev, &fpriv->vm); free(fpriv, M_DRM); file_priv->driver_priv = NULL; } } /** * radeon_driver_preclose_kms - drm callback for pre close * * @dev: drm dev pointer * @file_priv: drm file * * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx * (all asics). */ void radeon_driver_preclose_kms(struct drm_device *dev, struct drm_file *file_priv) { struct radeon_device *rdev = dev->dev_private; if (rdev->hyperz_filp == file_priv) rdev->hyperz_filp = NULL; if (rdev->cmask_filp == file_priv) rdev->cmask_filp = NULL; } /* * VBlank related functions. */ /** * radeon_get_vblank_counter_kms - get frame count * * @dev: drm dev pointer * @crtc: crtc to get the frame count from * * Gets the frame count on the requested crtc (all asics). * Returns frame count on success, -EINVAL on failure. */ u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) { struct radeon_device *rdev = dev->dev_private; if (crtc < 0 || crtc >= rdev->num_crtc) { DRM_ERROR("Invalid crtc %d\n", crtc); return -EINVAL; } return radeon_get_vblank_counter(rdev, crtc); } /** * radeon_enable_vblank_kms - enable vblank interrupt * * @dev: drm dev pointer * @crtc: crtc to enable vblank interrupt for * * Enable the interrupt on the requested crtc (all asics). * Returns 0 on success, -EINVAL on failure. */ int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) { struct radeon_device *rdev = dev->dev_private; int r; if (crtc < 0 || crtc >= rdev->num_crtc) { DRM_ERROR("Invalid crtc %d\n", crtc); return -EINVAL; } mtx_enter(&rdev->irq.lock); rdev->irq.crtc_vblank_int[crtc] = true; r = radeon_irq_set(rdev); mtx_leave(&rdev->irq.lock); return r; } /** * radeon_disable_vblank_kms - disable vblank interrupt * * @dev: drm dev pointer * @crtc: crtc to disable vblank interrupt for * * Disable the interrupt on the requested crtc (all asics). */ void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) { struct radeon_device *rdev = dev->dev_private; if (crtc < 0 || crtc >= rdev->num_crtc) { DRM_ERROR("Invalid crtc %d\n", crtc); return; } mtx_enter(&rdev->irq.lock); rdev->irq.crtc_vblank_int[crtc] = false; radeon_irq_set(rdev); mtx_leave(&rdev->irq.lock); } /** * radeon_get_vblank_timestamp_kms - get vblank timestamp * * @dev: drm dev pointer * @crtc: crtc to get the timestamp for * @max_error: max error * @vblank_time: time value * @flags: flags passed to the driver * * Gets the timestamp on the requested crtc based on the * scanout position. (all asics). * Returns postive status flags on success, negative error on failure. */ int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, int *max_error, struct timeval *vblank_time, unsigned flags) { struct drm_crtc *drmcrtc; struct radeon_device *rdev = dev->dev_private; if (crtc < 0 || crtc >= dev->num_crtcs) { DRM_ERROR("Invalid crtc %d\n", crtc); return -EINVAL; } /* Get associated drm_crtc: */ drmcrtc = &rdev->mode_info.crtcs[crtc]->base; /* Helper routine in DRM core does all the work: */ return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, vblank_time, flags, drmcrtc); } /* * IOCTL. */ int radeon_dma_ioctl_kms(struct drm_device *dev, struct drm_dma *d, struct drm_file *file_priv) { /* Not valid in KMS. */ return -EINVAL; } #define KMS_INVALID_IOCTL(name) \ int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\ { \ DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ return -EINVAL; \ } /* * All these ioctls are invalid in kms world. */ KMS_INVALID_IOCTL(radeon_cp_init_kms) KMS_INVALID_IOCTL(radeon_cp_start_kms) KMS_INVALID_IOCTL(radeon_cp_stop_kms) KMS_INVALID_IOCTL(radeon_cp_reset_kms) KMS_INVALID_IOCTL(radeon_cp_idle_kms) KMS_INVALID_IOCTL(radeon_cp_resume_kms) KMS_INVALID_IOCTL(radeon_engine_reset_kms) KMS_INVALID_IOCTL(radeon_fullscreen_kms) KMS_INVALID_IOCTL(radeon_cp_swap_kms) KMS_INVALID_IOCTL(radeon_cp_clear_kms) KMS_INVALID_IOCTL(radeon_cp_vertex_kms) KMS_INVALID_IOCTL(radeon_cp_indices_kms) KMS_INVALID_IOCTL(radeon_cp_texture_kms) KMS_INVALID_IOCTL(radeon_cp_stipple_kms) KMS_INVALID_IOCTL(radeon_cp_indirect_kms) KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) KMS_INVALID_IOCTL(radeon_cp_getparam_kms) KMS_INVALID_IOCTL(radeon_cp_flip_kms) KMS_INVALID_IOCTL(radeon_mem_alloc_kms) KMS_INVALID_IOCTL(radeon_mem_free_kms) KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) KMS_INVALID_IOCTL(radeon_irq_emit_kms) KMS_INVALID_IOCTL(radeon_irq_wait_kms) KMS_INVALID_IOCTL(radeon_cp_setparam_kms) KMS_INVALID_IOCTL(radeon_surface_alloc_kms) KMS_INVALID_IOCTL(radeon_surface_free_kms) int radeondrm_ioctl_kms(struct drm_device *dev, u_long cmd, caddr_t data, struct drm_file *file_priv) { return -(radeon_ioctl_kms(dev, cmd, data, file_priv)); } int radeon_ioctl_kms(struct drm_device *dev, u_long cmd, caddr_t data, struct drm_file *file_priv) { if (file_priv->authenticated == 1) { switch (cmd) { case DRM_IOCTL_RADEON_CP_IDLE: return (radeon_cp_idle_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_CP_RESUME: return (radeon_cp_resume_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_RESET: return (radeon_engine_reset_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_FULLSCREEN: return (radeon_fullscreen_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_SWAP: return (radeon_cp_swap_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_CLEAR: return (radeon_cp_clear_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_VERTEX: return (radeon_cp_vertex_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_INDICES: return (radeon_cp_indices_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_TEXTURE: return (radeon_cp_texture_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_STIPPLE: return (radeon_cp_stipple_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_VERTEX2: return (radeon_cp_vertex2_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_CMDBUF: return (radeon_cp_cmdbuf_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_GETPARAM: return (radeon_cp_getparam_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_FLIP: return (radeon_cp_flip_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_ALLOC: return (radeon_mem_alloc_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_FREE: return (radeon_mem_free_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_IRQ_EMIT: return (radeon_irq_emit_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_IRQ_WAIT: return (radeon_irq_wait_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_SETPARAM: return (radeon_cp_setparam_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_SURF_ALLOC: return (radeon_surface_alloc_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_SURF_FREE: return (radeon_surface_free_kms(dev, data, file_priv)); /* KMS */ case DRM_IOCTL_RADEON_GEM_INFO: return (radeon_gem_info_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_GEM_CREATE: return (radeon_gem_create_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_GEM_MMAP: return (radeon_gem_mmap_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_GEM_SET_DOMAIN: return (radeon_gem_set_domain_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_GEM_PREAD: return (radeon_gem_pread_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_GEM_PWRITE: return (radeon_gem_pwrite_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_GEM_WAIT_IDLE: return (radeon_gem_wait_idle_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_CS: return (radeon_cs_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_INFO: return (radeon_info_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_GEM_SET_TILING: return (radeon_gem_set_tiling_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_GEM_GET_TILING: return (radeon_gem_get_tiling_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_GEM_BUSY: return (radeon_gem_busy_ioctl(dev, data, file_priv)); case DRM_IOCTL_RADEON_GEM_VA: return (radeon_gem_va_ioctl(dev, data, file_priv)); } } if (file_priv->master == 1) { switch (cmd) { case DRM_IOCTL_RADEON_CP_INIT: return (radeon_cp_init_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_CP_START: return (radeon_cp_start_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_CP_STOP: return (radeon_cp_stop_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_CP_RESET: return (radeon_cp_reset_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_INDIRECT: return (radeon_cp_indirect_kms(dev, data, file_priv)); case DRM_IOCTL_RADEON_INIT_HEAP: return (radeon_mem_init_heap_kms(dev, data, file_priv)); } } return -EINVAL; }