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.\" $OpenBSD: cpu.4tbl,v 1.4 2002/04/22 00:42:48 mickey Exp $
.\"
.\" Copyright (c) 2002 Michael Shalayeff
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Michael Shalayeff.
.\" 4. The name of the author may not be used to endorse or promote products
.\" derived from this software without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
.\" IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
.\" INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
.\" (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
.\" SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
.\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
.\" IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.Dd April 4, 2002
.Dt CPU 4 hppa
.Os
.Sh NAME
.Nm cpu
.Nd HP PA-RISC CPU
.Sh SYNOPSIS
.Cd "cpu* at mainbus0 irq 31
.Sh DESCRIPTION
.Pp
The following table lists the
.Tn PA-RISC
CPU types and their characteristics, such as TLB and maximum
cache sizes,
.Tn HP9000/700
machines they were used in (see also
.Xr intro 4
for the reverse list).
.Pp
.in +\n(dIu
.TS
tab (:) ;
l l l l l l l l
l l l l l l l l
_ _ _ _ _ _ _ _
l l l l l l l l .
CPU:PA:CLK:FPU:Caches:TLB:BTLB:Models
: :Mhz:y/n: KB : : :
7000:1.1a:66 :No : 256 L1I:96:4 I:705,710,720
: : : : 256 L1D: :4 D:730,750
7100:1.1b:100:Yes:1024 L1I:120:16:715/33/50/75
: : : :2048 L1D: : :725/50/75
: : : : : : :{735,755}/100
7150:1.1b:125:Yes:1024 L1I:120:16:{735,755}/125
: : : :2048 L1D: : :
7100LC:1.1c:100:Yes: 1 L1I:64:8:712/60/80/100
: : : :1024 L2I: : :715/64/80/100
: : : :1024 L2D: : :715/100XC
: : : : : : :725/64/100
7200:1.1d:140:Yes: 2 L1 :120:16:C100,C110
: : : :1024 L2I: : :J200,J210
: : : :1024 L2D: : :
7300LC:1.1e:180:Yes: 64 L1I:96:8:A180,A180C
: : : : 64 L1D: : :B132,B160,B180
: : : :8192 L2 : : :C132L,C160L
.TE
.in -\n(dIu
.Pp
.Sh FLOATING-POINT COPROCESSOR
The following table summarizes available floating-point coprocessor
models for the 32-bit
.Tn PA-RISC
processors.
.Pp
.in +\n(dIu
.TS
tab (:) ;
l l
_ _
l l .
FPU:Model
Indigo:
Sterling I MIU (TYCO):
Sterling I MIU (ROC w/Weitek):
FPC (w/Weitek):
FPC (w/Bit):
Timex-II:
Rolex:725/50
HARP-I:
Tornado:
PA-50 (Hitachi):
PCXL:712/60/80/100
.TE
.in -\n(dIu
.Pp
.Sh SUPERSCALAR EXECUTION
The following table summarizes the superscalar execution capabilities of 32-bit
.Tn PA-RISC
processors.
.Pp
.in +\n(dIu
.TS
tab (:) ;
l l l
_ _ _
l l l .
CPU:Units:Bundles
7100:1INT,1FP:load-store/fp
: :int/fp
: :branch/*
7100LC:2INT,1FP:load-store/int
: :load-store/fp
: :int/fp
: :branch/*
7200:2INT,1FP:load-store/int
: :load-store/fp
: :int/int
: :int/fp
: :branch/*
7300LC:2INT,1FP:load-store/int
: :load-store/fp
: :int/fp
: :branch/*
.TE
.in -\n(dIu
.Pp
Concluding, all of the above CPUs are dual-issue, or 2-way superscalar,
with the exception that on CPUs with two INT units only one of these units
is capable of doing shift, load/store and test operations.
Additionally there are several kinds of restrictions placed upon the superscalar
execution:
.Pp
.Bl -bullet -compact
.It
functional unit contention
.It
data dependency restrictions
.It
control flow restrictions
.It
special intruction restrictions
.El
.Pp
.Sh PERFORMANCE MONITOR COPROCESSOR
The performance monitor coprocessor is an optional,
implementation-dependent coprocessor which provides a minimal common
software interface to implementation-dependent performance monitor hardware.
.Pp
.Sh DEBUG SPECIAL UNIT
The debug special function unit is an optional,
architected SFU which provides hardware assistance for software debugging
using breakpoints.
The debug SFU is currently defined only for Level 0 processors.
.Pp
.Sh SEE ALSO
.Xr asp 4 ,
.Xr intro 4 ,
.Xr lasi 4 ,
.Xr wax 4
.Pp
.Rs
"PA-RISC 1.1 Architecture and Instruction Set Reference Manual"
.br
Hewlett-Packard, May 15, 1996
.Re
.Rs
"PA7100LC ERS"
.br
Hewlett-Packard, March 30 1999, Public version 1.0
.Re
.Rs
"Design of the PA7200 CPU"
.br
Hewlett-Packard Journal, February 1996
.Re
.Rs
"PA7300LC ERS"
.br
Hewlett-Packard, March 18 1996, Version 1.0
.Re
.Sh HISTORY
The
.Nm
driver was written by
.An Michael Shalayeff Aq mickey@openbsd.org
for HPPA
port for
.Ox 2.5 .
|
