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.\" $OpenBSD: gio.4,v 1.4 2012/03/28 20:44:23 miod Exp $
.\" $NetBSD: gio.4,v 1.20 2008/04/30 13:10:56 martin Exp $
.\"
.\" Copyright (c) 2002 The NetBSD Foundation, Inc.
.\" All rights reserved.
.\"
.\" This document is derived from work contributed to The NetBSD Foundation
.\" by Antti Kantee.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS BE
.\" LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
.\" POSSIBILITY OF SUCH DAMAGE.
.\"
.Dd $Mdocdate: March 28 2012 $
.Dt GIO 4 sgi
.Os
.Sh NAME
.Nd Graphics I/O GIO bus
.Sh SYNOPSIS
.Cd "gio0 at imc0"
.Sh DESCRIPTION
The
.Nm
bus is a bus for connecting high-speed peripherals to the main memory and
CPU.
The devices themselves are typically (but not necessarily) connected to the
.Xr hpc 4
peripheral controller, and memory and CPU are accessed through the
.Xr imc 4
system controller.
The
.Nm
bus is found on the Indigo, Indy, Challenge S,
Challenge M, and Indigo2 machines and exists in three incarnations:
GIO32, GIO32-bis, and GIO64.
.Sh SEE ALSO
.\" .Xr giopci 4 ,
.\" .Xr grtwo 4 ,
.Xr hpc 4 ,
.Xr imc 4 ,
.Xr intro 4
.\" .Xr light 4 ,
.\" .Xr newport 4
.Sh CAVEATS
Challenge S systems may use only one
.Nm
DMA-capable expansion card, despite having two slots.
Cards based on the
.Xr hpc 4
controller, such as the GIO32 scsi and E++ Ethernet adapters, must be
placed in slot 1 (closest to the side of the case).
All other cards must be placed in slot 0 (adjacent to the memory banks).
.Pp
Indigo2 and Challenge M systems contain either three or four GIO64 connectors,
depending on the model.
However, in both cases only two electrically distinct slots are present.
Therefore, distinct expansion cards may not share physical connectors
associated with the same slot.
On the other hand, this apparently redundant slot connectors allows
multiple board assemblies to draw more power from the bus, and also
helps mixing
.Nm
and EISA boards in the same chassis.
In all systems, the upper two GIO64 connectors are GIO slot 1, while
the lower connectors (either one or two of them) are GIO slot 0.
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