blob: caa638e604117107a4e9f434feef4b0a360cdc88 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
|
/* $OpenBSD: apecs_bus_mem.c,v 1.4 2001/02/16 08:23:38 jason Exp $ */
/* $NetBSD: apecs_bus_mem.c,v 1.1 1996/11/25 03:42:11 cgd Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/syslog.h>
#include <sys/device.h>
#include <vm/vm.h>
#include <machine/bus.h>
#include <alpha/pci/apecsreg.h>
#include <alpha/pci/apecsvar.h>
#define CHIP apecs
#define CHIP_EX_MALLOC_SAFE(v) (((struct apecs_config *)(v))->ac_mallocsafe)
#define CHIP_D_MEM_EXTENT(v) (((struct apecs_config *)(v))->ac_d_mem_ex)
#define CHIP_S_MEM_EXTENT(v) (((struct apecs_config *)(v))->ac_s_mem_ex)
/* Dense region 1 */
#define CHIP_D_MEM_W1_BUS_START(v) 0x00000000UL
#define CHIP_D_MEM_W1_BUS_END(v) 0xffffffffUL
#define CHIP_D_MEM_W1_SYS_START(v) APECS_PCI_DENSE
#define CHIP_D_MEM_W1_SYS_END(v) (APECS_PCI_DENSE + 0xffffffffUL)
/* Sparse region 1 */
#define CHIP_S_MEM_W1_BUS_START(v) 0x00000000UL
#define CHIP_S_MEM_W1_BUS_END(v) 0x00ffffffUL
#define CHIP_S_MEM_W1_SYS_START(v) APECS_PCI_SPARSE
#define CHIP_S_MEM_W1_SYS_END(v) \
(APECS_PCI_SPARSE + (0x01000000UL << 5) - 1)
/* Sparse region 2 */
#define CHIP_S_MEM_W2_BUS_START(v) \
((((struct apecs_config *)(v))->ac_haxr1 & EPIC_HAXR1_EADDR) + \
0x01000000UL)
#define CHIP_S_MEM_W2_BUS_END(v) \
((((struct apecs_config *)(v))->ac_haxr1 & EPIC_HAXR1_EADDR) + \
0x07ffffffUL)
#define CHIP_S_MEM_W2_SYS_START(v) \
(APECS_PCI_SPARSE + (0x01000000UL << 5))
#define CHIP_S_MEM_W2_SYS_END(v) \
(APECS_PCI_SPARSE + (0x08000000UL << 5) - 1)
#include "pci_swiz_bus_mem_chipdep.c"
|
