1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
|
/* $OpenBSD: intr.h,v 1.14 2008/12/06 04:31:24 tedu Exp $ */
/* $NetBSD: intr.h,v 1.2 2003/05/04 22:01:56 fvdl Exp $ */
/*-
* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum, and by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _X86_INTR_H_
#define _X86_INTR_H_
#include <machine/intrdefs.h>
#ifndef _LOCORE
#include <machine/cpu.h>
#include <sys/evcount.h>
/*
* Struct describing an interrupt source for a CPU. struct cpu_info
* has an array of MAX_INTR_SOURCES of these. The index in the array
* is equal to the stub number of the stubcode as present in vector.s
*
* The primary CPU's array of interrupt sources has its first 16
* entries reserved for legacy ISA irq handlers. This means that
* they have a 1:1 mapping for arrayindex:irq_num. This is not
* true for interrupts that come in through IO APICs, to find
* their source, go through ci->ci_isources[index].is_pic
*
* It's possible to always maintain a 1:1 mapping, but that means
* limiting the total number of interrupt sources to MAX_INTR_SOURCES
* (32), instead of 32 per CPU. It also would mean that having multiple
* IO APICs which deliver interrupts from an equal pin number would
* overlap if they were to be sent to the same CPU.
*/
struct intrstub {
void *ist_entry;
void *ist_recurse;
void *ist_resume;
};
struct intrsource {
int is_maxlevel; /* max. IPL for this source */
int is_pin; /* IRQ for legacy; pin for IO APIC */
struct intrhand *is_handlers; /* handler chain */
struct pic *is_pic; /* originating PIC */
void *is_recurse; /* entry for spllower */
void *is_resume; /* entry for doreti */
char is_evname[32]; /* event counter name */
int is_flags; /* see below */
int is_type; /* level, edge */
int is_idtvec;
int is_minlevel;
};
#define IS_LEGACY 0x0001 /* legacy ISA irq source */
#define IS_IPI 0x0002
#define IS_LOG 0x0004
/*
* Interrupt handler chains. *_intr_establish() insert a handler into
* the list. The handler is called with its (single) argument.
*/
struct intrhand {
int (*ih_fun)(void *);
void *ih_arg;
int (*ih_wrapped_fun)(void *);
void *ih_wrapped_arg;
int ih_level;
struct intrhand *ih_next;
int ih_pin;
int ih_slot;
struct cpu_info *ih_cpu;
int ih_irq;
struct evcount ih_count;
};
#define IMASK(ci,level) (ci)->ci_imask[(level)]
#define IUNMASK(ci,level) (ci)->ci_iunmask[(level)]
extern void Xspllower(int);
int splraise(int);
int spllower(int);
void softintr(int);
/*
* Convert spl level to local APIC level
*/
#define APIC_LEVEL(l) ((l) << 4)
/*
* compiler barrier: prevent reordering of instructions.
* XXX something similar will move to <sys/cdefs.h>
* or thereabouts.
* This prevents the compiler from reordering code around
* this "instruction", acting as a sequence point for code generation.
*/
#define __splbarrier() __asm __volatile("":::"memory")
/*
* Hardware interrupt masks
*/
#define splbio() splraise(IPL_BIO)
#define splnet() splraise(IPL_NET)
#define spltty() splraise(IPL_TTY)
#define splaudio() splraise(IPL_AUDIO)
#define splclock() splraise(IPL_CLOCK)
#define splstatclock() splclock()
#define splipi() splraise(IPL_IPI)
#define spllpt() spltty()
#define spllpt() spltty()
/*
* Software interrupt masks
*/
#define splsoftclock() splraise(IPL_SOFTCLOCK)
#define splsoftnet() splraise(IPL_SOFTNET)
#define splsofttty() splraise(IPL_SOFTTTY)
/*
* Miscellaneous
*/
#define splvm() splraise(IPL_VM)
#define splhigh() splraise(IPL_HIGH)
#define spl0() spllower(IPL_NONE)
#define splsched() splraise(IPL_SCHED)
#define spllock() splhigh()
#define splx(x) spllower(x)
/* SPL asserts */
#ifdef DIAGNOSTIC
/*
* Although this function is implemented in MI code, it must be in this MD
* header because we don't want this header to include MI includes.
*/
void splassert_fail(int, int, const char *);
extern int splassert_ctl;
void splassert_check(int, const char *);
#define splassert(__wantipl) do { \
if (splassert_ctl > 0) { \
splassert_check(__wantipl, __func__); \
} \
} while (0)
#else
#define splassert(wantipl) do { /* nada */ } while (0)
#endif
/*
* XXX
*/
#define setsoftnet() softintr(SIR_NET)
#define IPLSHIFT 4 /* The upper nibble of vectors is the IPL. */
#define IPL(level) ((level) >> IPLSHIFT) /* Extract the IPL. */
#include <machine/pic.h>
/*
* Stub declarations.
*/
extern void Xsoftclock(void);
extern void Xsoftnet(void);
extern void Xsofttty(void);
extern struct intrstub i8259_stubs[];
extern struct intrstub ioapic_edge_stubs[];
extern struct intrstub ioapic_level_stubs[];
struct cpu_info;
extern char idt_allocmap[];
void intr_default_setup(void);
int x86_nmi(void);
void intr_calculatemasks(struct cpu_info *);
int intr_allocate_slot_cpu(struct cpu_info *, struct pic *, int, int *);
int intr_allocate_slot(struct pic *, int, int, int, struct cpu_info **, int *,
int *);
#define INTR_ESTABLISH_MPSAFE 0x01
void *intr_establish(int, struct pic *, int, int, int, int (*)(void *),
void *, char *, int);
void intr_disestablish(struct intrhand *);
void cpu_intr_init(struct cpu_info *);
int intr_find_mpmapping(int bus, int pin, int *handle);
void intr_printconfig(void);
#ifdef MULTIPROCESSOR
int x86_send_ipi(struct cpu_info *, int);
int x86_fast_ipi(struct cpu_info *, int);
void x86_broadcast_ipi(int);
void x86_multicast_ipi(int, int);
void x86_ipi_handler(void);
void x86_softintlock(void);
void x86_softintunlock(void);
void x86_setperf_ipi(struct cpu_info *);
extern void (*ipifunc[X86_NIPI])(struct cpu_info *);
#endif
#endif /* !_LOCORE */
/*
* Generic software interrupt support.
*/
#define X86_SOFTINTR_SOFTCLOCK 0
#define X86_SOFTINTR_SOFTNET 1
#define X86_SOFTINTR_SOFTTTY 2
#define X86_NSOFTINTR 3
#ifndef _LOCORE
#include <sys/queue.h>
struct x86_soft_intrhand {
TAILQ_ENTRY(x86_soft_intrhand)
sih_q;
struct x86_soft_intr *sih_intrhead;
void (*sih_fn)(void *);
void *sih_arg;
int sih_pending;
};
struct x86_soft_intr {
TAILQ_HEAD(, x86_soft_intrhand)
softintr_q;
int softintr_ssir;
struct simplelock softintr_slock;
};
#define x86_softintr_lock(si, s) \
do { \
(s) = splhigh(); \
simple_lock(&si->softintr_slock); \
} while (/*CONSTCOND*/ 0)
#define x86_softintr_unlock(si, s) \
do { \
simple_unlock(&si->softintr_slock); \
splx((s)); \
} while (/*CONSTCOND*/ 0)
void *softintr_establish(int, void (*)(void *), void *);
void softintr_disestablish(void *);
void softintr_init(void);
void softintr_dispatch(int);
#define softintr_schedule(arg) \
do { \
struct x86_soft_intrhand *__sih = (arg); \
struct x86_soft_intr *__si = __sih->sih_intrhead; \
int __s; \
\
x86_softintr_lock(__si, __s); \
if (__sih->sih_pending == 0) { \
TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \
__sih->sih_pending = 1; \
softintr(__si->softintr_ssir); \
} \
x86_softintr_unlock(__si, __s); \
} while (/*CONSTCOND*/ 0)
#endif /* _LOCORE */
#endif /* !_X86_INTR_H_ */
|
