summaryrefslogtreecommitdiff
path: root/sys/arch/amiga/dev/scivar.h
blob: 622ee276d18e8ae276617dc8fdb87344f3dac154 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
/*	$NetBSD: scivar.h,v 1.8 1995/08/12 20:30:51 mycroft Exp $	*/

/*
 * Copyright (c) 1990 The Regents of the University of California.
 * All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * Van Jacobson of Lawrence Berkeley Laboratory.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Berkeley and its contributors.
 * 4. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)scivar.h	7.1 (Berkeley) 5/8/90
 */
#ifndef _SCIVAR_H_
#define _SCIVAR_H_

struct	sci_pending {
	TAILQ_ENTRY(sci_pending) link;
	struct scsi_xfer *xs;
};


struct	sci_softc {
	struct	device sc_dev;
	struct	isr sc_isr;
	struct	scsi_link sc_link;	/* proto for sub devices */
	TAILQ_HEAD(,sci_pending) sc_xslist;
	struct	sci_pending sc_xsstore[8][8];
	struct	scsi_xfer *sc_xs;	/* transfer from high level code */

	volatile u_char	*sci_data;	/* r: Current data */
	volatile u_char	*sci_odata;	/* w: Out data */
	volatile u_char	*sci_icmd;	/* rw: Initiator command */
	volatile u_char	*sci_mode;	/* rw: Mode */
	volatile u_char	*sci_tcmd;	/* rw: Target command */
	volatile u_char	*sci_bus_csr;	/* r: Bus Status */
	volatile u_char	*sci_sel_enb;	/* w: Select enable */
	volatile u_char	*sci_csr;	/* r: Status */
	volatile u_char	*sci_dma_send;	/* w: Start dma send data */
	volatile u_char	*sci_idata;	/* r: Input data */
	volatile u_char	*sci_trecv;	/* w: Start dma receive, target */
	volatile u_char	*sci_iack;	/* r: Interrupt Acknowledge */
	volatile u_char	*sci_irecv;	/* w: Start dma receive, initiator */

	int	(*dma_xfer_in)();	/* psuedo DMA transfer */
	int	(*dma_xfer_out)();	/* psuedo DMA transfer */
	int	(*dma_intr)();		/* board-specific interrupt */
	u_char	sc_flags;
	u_char	sc_lun;
	/* one for each target */
	struct syncpar {
	  u_char state;
	  u_char period, offset;
	} sc_sync[8];
	u_char	sc_slave;
	u_char	sc_scsi_addr;
	u_char	sc_stat[2];
	u_char	sc_msg[8];
};

/* sc_flags */
#define	SCI_IO		0x80	/* DMA I/O in progress */
#define	SCI_ALIVE	0x01	/* controller initialized */
#define SCI_SELECTED	0x04	/* bus is in selected state. Needed for
				   correct abort procedure. */

/* sync states */
#define SYNC_START	0	/* no sync handshake started */
#define SYNC_SENT	1	/* we sent sync request, no answer yet */
#define SYNC_DONE	2	/* target accepted our (or inferior) settings,
				   or it rejected the request and we stay async *

#define	PHASE		0x07		/* mask for psns/pctl phase */
#define	DATA_OUT_PHASE	0x00
#define	DATA_IN_PHASE	0x01
#define	CMD_PHASE	0x02
#define	STATUS_PHASE	0x03
#define	BUS_FREE_PHASE	0x04
#define	ARB_SEL_PHASE	0x05	/* Fuji chip combines arbitration with sel. */
#define	MESG_OUT_PHASE	0x06
#define	MESG_IN_PHASE	0x07

#define	MSG_CMD_COMPLETE	0x00
#define MSG_EXT_MESSAGE		0x01
#define	MSG_SAVE_DATA_PTR	0x02
#define	MSG_RESTORE_PTR		0x03
#define	MSG_DISCONNECT		0x04
#define	MSG_INIT_DETECT_ERROR	0x05
#define	MSG_ABORT		0x06
#define	MSG_REJECT		0x07
#define	MSG_NOOP		0x08
#define	MSG_PARITY_ERROR	0x09
#define	MSG_BUS_DEVICE_RESET	0x0C
#define	MSG_IDENTIFY		0x80
#define	MSG_IDENTIFY_DR		0xc0	/* (disconnect/reconnect allowed) */
#define	MSG_SYNC_REQ 		0x01


#define	STS_CHECKCOND	0x02	/* Check Condition (ie., read sense) */
#define	STS_CONDMET	0x04	/* Condition Met (ie., search worked) */
#define	STS_BUSY	0x08
#define	STS_INTERMED	0x10	/* Intermediate status sent */
#define	STS_EXT		0x80	/* Extended status valid */

/*
 * XXXX
 */
struct scsi_fmt_cdb {
	int len;		/* cdb length (in bytes) */
	u_char cdb[28];		/* cdb to use on next read/write */
};

struct buf;
struct scsi_xfer;

void sci_minphys __P((struct buf *bp));
int sci_scsicmd __P((struct scsi_xfer *));

#endif /* _SCIVAR_H_ */