1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
|
/* $OpenBSD: imxgpio.c,v 1.9 2016/07/11 14:51:31 kettenis Exp $ */
/*
* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
* Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/queue.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/evcount.h>
#include <arm/cpufunc.h>
#include <machine/bus.h>
#include <machine/fdt.h>
#include <machine/intr.h>
#include <armv7/armv7/armv7var.h>
#include <armv7/imx/imxgpiovar.h>
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_gpio.h>
/* iMX6 registers */
#define GPIO_DR 0x00
#define GPIO_GDIR 0x04
#define GPIO_PSR 0x08
#define GPIO_ICR1 0x0C
#define GPIO_ICR2 0x10
#define GPIO_IMR 0x14
#define GPIO_ISR 0x18
#define GPIO_EDGE_SEL 0x1C
#define GPIO_NUM_PINS 32
struct intrhand {
int (*ih_func)(void *); /* handler */
void *ih_arg; /* arg for handler */
int ih_ipl; /* IPL_* */
int ih_irq; /* IRQ number */
int ih_gpio; /* gpio pin */
struct evcount ih_count;
char *ih_name;
};
struct imxgpio_softc {
struct device sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
void *sc_ih_h;
void *sc_ih_l;
int sc_max_il;
int sc_min_il;
int sc_irq;
struct intrhand *sc_handlers[GPIO_NUM_PINS];
unsigned int (*sc_get_bit)(struct imxgpio_softc *sc,
unsigned int gpio);
void (*sc_set_bit)(struct imxgpio_softc *sc,
unsigned int gpio);
void (*sc_clear_bit)(struct imxgpio_softc *sc,
unsigned int gpio);
void (*sc_set_dir)(struct imxgpio_softc *sc,
unsigned int gpio, unsigned int dir);
struct gpio_controller sc_gc;
};
#define GPIO_PIN_TO_INST(x) ((x) >> 5)
#define GPIO_PIN_TO_OFFSET(x) ((x) & 0x1f)
int imxgpio_match(struct device *, void *, void *);
void imxgpio_attach(struct device *, struct device *, void *);
void imxgpio_config_pin(void *, uint32_t *, int);
int imxgpio_get_pin(void *, uint32_t *);
void imxgpio_set_pin(void *, uint32_t *, int);
unsigned int imxgpio_v6_get_bit(struct imxgpio_softc *, unsigned int);
void imxgpio_v6_set_bit(struct imxgpio_softc *, unsigned int);
void imxgpio_v6_clear_bit(struct imxgpio_softc *, unsigned int);
void imxgpio_v6_set_dir(struct imxgpio_softc *, unsigned int, unsigned int);
unsigned int imxgpio_v6_get_dir(struct imxgpio_softc *, unsigned int);
struct cfattach imxgpio_ca = {
sizeof (struct imxgpio_softc), imxgpio_match, imxgpio_attach
};
struct cfdriver imxgpio_cd = {
NULL, "imxgpio", DV_DULL
};
int
imxgpio_match(struct device *parent, void *match, void *aux)
{
struct fdt_attach_args *faa = aux;
return OF_is_compatible(faa->fa_node, "fsl,imx35-gpio");
}
void
imxgpio_attach(struct device *parent, struct device *self, void *aux)
{
struct imxgpio_softc *sc = (struct imxgpio_softc *)self;
struct fdt_attach_args *faa = aux;
if (faa->fa_nreg < 2)
return;
sc->sc_iot = faa->fa_iot;
if (bus_space_map(sc->sc_iot, faa->fa_reg[0],
faa->fa_reg[1], 0, &sc->sc_ioh))
panic("imxgpio_attach: bus_space_map failed!");
sc->sc_gc.gc_node = faa->fa_node;
sc->sc_gc.gc_cookie = sc;
sc->sc_gc.gc_config_pin = imxgpio_config_pin;
sc->sc_gc.gc_get_pin = imxgpio_get_pin;
sc->sc_gc.gc_set_pin = imxgpio_set_pin;
gpio_controller_register(&sc->sc_gc);
sc->sc_get_bit = imxgpio_v6_get_bit;
sc->sc_set_bit = imxgpio_v6_set_bit;
sc->sc_clear_bit = imxgpio_v6_clear_bit;
sc->sc_set_dir = imxgpio_v6_set_dir;
printf("\n");
/* XXX - IRQ */
/* XXX - SYSCONFIG */
/* XXX - CTRL */
/* XXX - DEBOUNCE */
}
void
imxgpio_config_pin(void *cookie, uint32_t *cells, int config)
{
struct imxgpio_softc *sc = cookie;
uint32_t pin = cells[0];
uint32_t val;
if (pin >= GPIO_NUM_PINS)
return;
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_GDIR);
if (config & GPIO_CONFIG_OUTPUT)
val |= 1 << pin;
else
val &= ~(1 << pin);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_GDIR, val);
}
int
imxgpio_get_pin(void *cookie, uint32_t *cells)
{
struct imxgpio_softc *sc = cookie;
uint32_t pin = cells[0];
uint32_t flags = cells[1];
uint32_t reg;
int val;
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_DR);
reg &= (1 << pin);
val = (reg >> pin) & 1;
if (flags & GPIO_ACTIVE_LOW)
val = !val;;
return val;
}
void
imxgpio_set_pin(void *cookie, uint32_t *cells, int val)
{
struct imxgpio_softc *sc = cookie;
uint32_t pin = cells[0];
uint32_t flags = cells[1];
uint32_t reg;
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_DR);
if (flags & GPIO_ACTIVE_LOW)
val = !val;
if (val)
reg |= (1 << pin);
else
reg &= ~(1 << pin);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_DR, reg);
}
unsigned int
imxgpio_get_bit(unsigned int gpio)
{
struct imxgpio_softc *sc = imxgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
return sc->sc_get_bit(sc, gpio);
}
void
imxgpio_set_bit(unsigned int gpio)
{
struct imxgpio_softc *sc = imxgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
sc->sc_set_bit(sc, gpio);
}
void
imxgpio_clear_bit(unsigned int gpio)
{
struct imxgpio_softc *sc = imxgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
sc->sc_clear_bit(sc, gpio);
}
void
imxgpio_set_dir(unsigned int gpio, unsigned int dir)
{
struct imxgpio_softc *sc = imxgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
sc->sc_set_dir(sc, gpio, dir);
}
unsigned int
imxgpio_v6_get_bit(struct imxgpio_softc *sc, unsigned int gpio)
{
u_int32_t val;
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_DR);
return (val >> GPIO_PIN_TO_OFFSET(gpio)) & 0x1;
}
void
imxgpio_v6_set_bit(struct imxgpio_softc *sc, unsigned int gpio)
{
u_int32_t val;
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_DR);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_DR,
val | (1 << GPIO_PIN_TO_OFFSET(gpio)));
}
void
imxgpio_v6_clear_bit(struct imxgpio_softc *sc, unsigned int gpio)
{
u_int32_t val;
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_DR);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_DR,
val & ~(1 << GPIO_PIN_TO_OFFSET(gpio)));
}
void
imxgpio_v6_set_dir(struct imxgpio_softc *sc, unsigned int gpio, unsigned int dir)
{
int s;
u_int32_t val;
s = splhigh();
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_GDIR);
if (dir == IMXGPIO_DIR_OUT)
val |= 1 << GPIO_PIN_TO_OFFSET(gpio);
else
val &= ~(1 << GPIO_PIN_TO_OFFSET(gpio));
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_GDIR, val);
splx(s);
}
unsigned int
imxgpio_v6_get_dir(struct imxgpio_softc *sc, unsigned int gpio)
{
int s;
u_int32_t val;
s = splhigh();
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_GDIR);
if (val & (1 << GPIO_PIN_TO_OFFSET(gpio)))
val = IMXGPIO_DIR_OUT;
else
val = IMXGPIO_DIR_IN;
splx(s);
return val;
}
|
