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/* $NetBSD: psl.h,v 1.11 1996/03/31 22:20:14 pk Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)psl.h 8.1 (Berkeley) 6/11/93
*/
#ifndef PSR_IMPL
#if !defined(_LOCORE) && !defined(__ASSEMBLER__)
#include <machine/asm.h>
#endif
#include <machine/asi.h>
#include <machine/sic.h>
/*
* SPARC Process Status Register (in psl.h for hysterical raisins).
*
* The picture in the Sun manuals looks like this:
* 1 1
* 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0
* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
* | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP |
* | | |n z v c| |C|F| | |S|T| |
* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
*/
#define PSR_IMPL 0xf0000000 /* implementation */
#define PSR_VER 0x0f000000 /* version */
#define PSR_ICC 0x00f00000 /* integer condition codes */
#define PSR_N 0x00800000 /* negative */
#define PSR_Z 0x00400000 /* zero */
#define PSR_O 0x00200000 /* overflow */
#define PSR_C 0x00100000 /* carry */
#define PSR_EC 0x00002000 /* coprocessor enable */
#define PSR_EF 0x00001000 /* FP enable */
#define PSR_PIL 0x00000f00 /* interrupt level */
#define PSR_S 0x00000080 /* supervisor (kernel) mode */
#define PSR_PS 0x00000040 /* previous supervisor mode (traps) */
#define PSR_ET 0x00000020 /* trap enable */
#define PSR_CWP 0x0000001f /* current window pointer */
#define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET"
#define SPL_SOFTCLOCK 128
#define SPL_NET 128
#define SPL_BIO 136
#define SPL_TTY 139
#define SPL_ZS SPL_TTY
#define SPL_CLOCK 141
#define SPL_VME 142
#define SPL_PROF 143
#define SPL_IMP 145
#define SPL_HIGH 255
#if defined(_KERNEL) && !defined(_LOCORE)
extern unsigned int ssir;
static __inline int getpsr __P((void));
static __inline void setpsr __P((int));
static __inline int setpil0 __P((void));
/*
* GCC pseudo-functions for manipulating PSR (primarily PIL field).
*/
static __inline int
getpsr ()
{
int psr;
__asm __volatile("rd %%psr,%0" : "=r" (psr));
return (psr);
}
static __inline void
setpsr (newpsr)
int newpsr;
{
__asm __volatile("wr %0,0,%%psr" : : "r" (newpsr));
__asm __volatile("nop");
__asm __volatile("nop");
__asm __volatile("nop");
}
static __inline int
setpil0 ()
{
int psr, oldipl;
/*
* wrpsr xors two values: we choose old psr and old ipl here,
* which gives us the same value as the old psr but with all
* the old PIL bits turned off.
*/
__asm __volatile("rd %%psr,%0" : "=r" (psr));
oldipl = psr & PSR_PIL;
__asm __volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl));
/*
* Three instructions must execute before we can depend
* on the bits to be changed.
*/
__asm __volatile("nop; nop; nop");
return (oldipl);
}
static __inline int setpil (int newpil)
{
int psr, oldipl;
psr = getpsr ();
oldipl = (psr & PSR_PIL) >> 8;
setpsr ((psr & ~PSR_PIL) | ((newpil << 8) & PSR_PIL));
return oldipl;
}
static __inline int
setpil15 (void)
{
int psr;
psr = getpsr ();
setpsr (psr | PSR_PIL);
return (psr & PSR_PIL) >> 8;
}
/*
* PIL 1 through 14 can use this macro.
* (spl0 and splhigh are special since they put all 0s or all 1s
* into the ipl field.)
*/
#define SPL(name, newspl) \
extern int name __P((void));
SPL(splsoftint, SPL_NET)
#define splsoftclock splsoftint
#define splsoftnet splsoftint
/* Block devices */
SPL(splbio, SPL_BIO)
/* network hardware interrupts are at level 6 */
SPL(splnet, SPL_NET)
/* tty input runs at software level 6 */
SPL(spltty, SPL_TTY)
/*
* Memory allocation (must be as high as highest network, tty, or disk device)
*/
SPL(splimp, SPL_IMP)
SPL(splclock, SPL_CLOCK)
SPL(splstatclock, SPL_CLOCK)
/* zs hardware interrupts are at level 12 */
SPL(splzs, SPL_ZS)
SPL(splhigh, SPL_HIGH)
SPL(spl0, 0)
extern int splx (int newspl);
#endif /* KERNEL && !_LOCORE */
#endif /* PSR_IMPL */
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