summaryrefslogtreecommitdiff
path: root/sys/arch/mips64/include/cpu.h
blob: f17c7ffa028e0988c8a1479ef69deb46d5518822 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
/*	$OpenBSD: cpu.h,v 1.46 2009/11/25 17:39:51 syuu Exp $	*/

/*-
 * Copyright (c) 1992, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * Ralph Campbell and Rick Macklem.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	Copyright (C) 1989 Digital Equipment Corporation.
 *	Permission to use, copy, modify, and distribute this software and
 *	its documentation for any purpose and without fee is hereby granted,
 *	provided that the above copyright notice appears in all copies.
 *	Digital Equipment Corporation makes no representations about the
 *	suitability of this software for any purpose.  It is provided "as is"
 *	without express or implied warranty.
 *
 *	from: @(#)cpu.h	8.4 (Berkeley) 1/4/94
 */

#ifndef _MIPS_CPU_H_
#define	_MIPS_CPU_H_

#ifndef _LOCORE

/*
 * MIPS32-style segment definitions.
 * They only cover the first 512MB of physical addresses.
 */
#define	CKSEG0_BASE		0xffffffff80000000UL
#define	CKSEG1_BASE		0xffffffffa0000000UL
#define	CKSSEG_BASE		0xffffffffc0000000UL
#define	CKSEG3_BASE		0xffffffffe0000000UL
#define	CKSEG_SIZE		0x0000000020000000UL

#define	CKSEG0_TO_PHYS(x)	((u_long)(x) & (CKSEG_SIZE - 1))
#define	CKSEG1_TO_PHYS(x)	((u_long)(x) & (CKSEG_SIZE - 1))
#define	PHYS_TO_CKSEG0(x)	((u_long)(x) | CKSEG0_BASE)
#define	PHYS_TO_CKSEG1(x)	((u_long)(x) | CKSEG1_BASE)

/*
 * MIPS64-style segment definitions.
 * These allow for 36 bits of addressable physical memory, thus 64GB.
 */

/*
 * Cache Coherency Attributes.
 */
/* r8k only */
#define	CCA_NC_COPROCESSOR	0UL	/* uncached, coprocessor ordered */
/* common to r4, r5k, r8k and r1xk */
#define	CCA_NC			2UL	/* uncached, write-around */
#define	CCA_NONCOHERENT		3UL	/* cached, non-coherent, write-back */
/* r8k, r1xk only */
#define	CCA_COHERENT_EXCL	4UL	/* cached, coherent, exclusive */
#define	CCA_COHERENT_EXCLWRITE	5UL	/* cached, coherent, exclusive write */
/* r1xk only */
#define	CCA_NC_ACCELERATED	7UL	/* uncached accelerated */
/* r4k only */
#define	CCA_COHERENT_UPDWRITE	6UL	/* cached, coherent, update on write */

#ifdef TGT_COHERENT
#define	CCA_CACHED		CCA_COHERENT_EXCLWRITE
#else
#define	CCA_CACHED		CCA_NONCOHERENT
#endif

/*
 * Uncached spaces.
 * R1x000 processors use bits 58:57 of uncached virtual addresses (CCA_NC)
 * to select different spaces. Unfortunately, other processors need these
 * bits to be zero, so uncached address have to be decided at runtime.
 */
#define	SP_HUB			0UL	/* Hub space */
#define	SP_IO			1UL	/* I/O space */
#define	SP_SPECIAL		2UL	/* Memory Special space */
#define	SP_NC			3UL	/* Memory Uncached space */

extern vaddr_t uncached_base;

#define	XKSSSEG_BASE		0x4000000000000000UL
#define	XKPHYS_BASE		0x8000000000000000UL
#define	XKSSEG_BASE		0xc000000000000000UL

#define	XKPHYS_TO_PHYS(x)	((paddr_t)(x) & 0x0000000fffffffffUL)
#define	PHYS_TO_XKPHYS(x,c)	((paddr_t)(x) | XKPHYS_BASE | ((c) << 59))
#define	PHYS_TO_XKPHYS_UNCACHED(x,s) \
	(PHYS_TO_XKPHYS(x, CCA_NC) | ((s) << 57))
#define	PHYS_TO_UNCACHED(x)	((paddr_t)(x) | uncached_base)
#define	IS_XKPHYS(va)		(((va) >> 62) == 2)
#define	XKPHYS_TO_CCA(x)	(((x) >> 59) & 0x07)
#define	XKPHYS_TO_SP(x)		(((x) >> 57) & 0x03)

#endif	/* _LOCORE */

#ifdef _KERNEL

/*
 * Status register.
 */
#define	SR_XX			0x80000000
#define	SR_COP_USABILITY	0x30000000	/* CP0 and CP1 only */
#define	SR_COP_0_BIT		0x10000000
#define	SR_COP_1_BIT		0x20000000
#define	SR_RP			0x08000000
#define	SR_FR_32		0x04000000
#define	SR_RE			0x02000000
#define	SR_DSD			0x01000000	/* Only on R12000 */
#define	SR_BOOT_EXC_VEC		0x00400000
#define	SR_TLB_SHUTDOWN		0x00200000
#define	SR_SOFT_RESET		0x00100000
#define	SR_DIAG_CH		0x00040000
#define	SR_DIAG_CE		0x00020000
#define	SR_DIAG_DE		0x00010000
#define	SR_KX			0x00000080
#define	SR_SX			0x00000040
#define	SR_UX			0x00000020
#define	SR_KSU_MASK		0x00000018
#define	SR_KSU_USER		0x00000010
#define	SR_KSU_SUPER		0x00000008
#define	SR_KSU_KERNEL		0x00000000
#define	SR_ERL			0x00000004
#define	SR_EXL			0x00000002
#define	SR_INT_ENAB		0x00000001

#define	SR_INT_MASK		0x0000ff00
#define	SOFT_INT_MASK_0		0x00000100
#define	SOFT_INT_MASK_1		0x00000200
#define	SR_INT_MASK_0		0x00000400
#define	SR_INT_MASK_1		0x00000800
#define	SR_INT_MASK_2		0x00001000
#define	SR_INT_MASK_3		0x00002000
#define	SR_INT_MASK_4		0x00004000
#define	SR_INT_MASK_5		0x00008000
/*
 * Interrupt control register in RM7000. Expansion of interrupts.
 */
#define	IC_INT_MASK		0x00003f00	/* Two msb reserved */
#define	IC_INT_MASK_6		0x00000100
#define	IC_INT_MASK_7		0x00000200
#define	IC_INT_MASK_8		0x00000400
#define	IC_INT_MASK_9		0x00000800
#define	IC_INT_TIMR		0x00001000	/* 12 Timer */
#define	IC_INT_PERF		0x00002000	/* 13 Performance counter */
#define	IC_INT_TE		0x00000080	/* Timer on INT11 */

#define	ALL_INT_MASK		((IC_INT_MASK << 8) | SR_INT_MASK)
#define	SOFT_INT_MASK		(SOFT_INT_MASK_0 | SOFT_INT_MASK_1)
#define	HW_INT_MASK		(ALL_INT_MASK & ~SOFT_INT_MASK)


/*
 * The bits in the cause register.
 *
 *	CR_BR_DELAY	Exception happened in branch delay slot.
 *	CR_COP_ERR	Coprocessor error.
 *	CR_IP		Interrupt pending bits defined below.
 *	CR_EXC_CODE	The exception type (see exception codes below).
 */
#define	CR_BR_DELAY		0x80000000
#define	CR_COP_ERR		0x30000000
#define	CR_EXC_CODE		0x0000007c
#define	CR_EXC_CODE_SHIFT	2
#define	CR_IPEND		0x003fff00
#define	CR_INT_SOFT0		0x00000100
#define	CR_INT_SOFT1		0x00000200
#define	CR_INT_0		0x00000400
#define	CR_INT_1		0x00000800
#define	CR_INT_2		0x00001000
#define	CR_INT_3		0x00002000
#define	CR_INT_4		0x00004000
#define	CR_INT_5		0x00008000
/* Following on RM7000 */
#define	CR_INT_6		0x00010000
#define	CR_INT_7		0x00020000
#define	CR_INT_8		0x00040000
#define	CR_INT_9		0x00080000
#define	CR_INT_HARD		0x000ffc00
#define	CR_INT_TIMR		0x00100000	/* 12 Timer */
#define	CR_INT_PERF		0x00200000	/* 13 Performance counter */

/*
 * The bits in the context register.
 */
#define	CNTXT_PTE_BASE		0xff800000
#define	CNTXT_BAD_VPN2		0x007ffff0

/*
 * Location of exception vectors.
 */
#define	RESET_EXC_VEC		(CKSEG0_BASE + 0x3fc00000)
#define	TLB_MISS_EXC_VEC	(CKSEG0_BASE + 0x00000000)
#define	XTLB_MISS_EXC_VEC	(CKSEG0_BASE + 0x00000080)
#define	CACHE_ERR_EXC_VEC	(CKSEG0_BASE + 0x00000100)
#define	GEN_EXC_VEC		(CKSEG0_BASE + 0x00000180)

/*
 * Coprocessor 0 registers:
 */
#define	COP_0_TLB_INDEX		$0
#define	COP_0_TLB_RANDOM	$1
#define	COP_0_TLB_LO0		$2
#define	COP_0_TLB_LO1		$3
#define	COP_0_TLB_CONTEXT	$4
#define	COP_0_TLB_PG_MASK	$5
#define	COP_0_TLB_WIRED		$6
#define	COP_0_BAD_VADDR		$8
#define	COP_0_COUNT		$9
#define	COP_0_TLB_HI		$10
#define	COP_0_COMPARE		$11
#define	COP_0_STATUS_REG	$12
#define	COP_0_CAUSE_REG		$13
#define	COP_0_EXC_PC		$14
#define	COP_0_PRID		$15
#define	COP_0_CONFIG		$16
#define	COP_0_LLADDR		$17
#define	COP_0_WATCH_LO		$18
#define	COP_0_WATCH_HI		$19
#define	COP_0_TLB_XCONTEXT	$20
#define	COP_0_TLB_FR_MASK	$21	/* R10000 onwards */
#define	COP_0_DIAG		$22	/* Loongson 2F */
#define	COP_0_ECC		$26
#define	COP_0_CACHE_ERR		$27
#define	COP_0_TAG_LO		$28
#define	COP_0_TAG_HI		$29
#define	COP_0_ERROR_PC		$30

/*
 * RM7000 specific
 */
#define	COP_0_WATCH_1		$18
#define	COP_0_WATCH_2		$19
#define	COP_0_WATCH_M		$24
#define	COP_0_PC_COUNT		$25
#define	COP_0_PC_CTRL		$22

#define	COP_0_ICR		$20	/* Use cfc0/ctc0 to access */

/*
 * Values for the code field in a break instruction.
 */
#define	BREAK_INSTR		0x0000000d
#define	BREAK_VAL_MASK		0x03ff0000
#define	BREAK_VAL_SHIFT		16
#define	BREAK_KDB_VAL		512
#define	BREAK_SSTEP_VAL		513
#define	BREAK_BRKPT_VAL		514
#define	BREAK_SOVER_VAL		515
#define	BREAK_DDB_VAL		516
#define	BREAK_KDB	(BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT))
#define	BREAK_SSTEP	(BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT))
#define	BREAK_BRKPT	(BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT))
#define	BREAK_SOVER	(BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT))
#define	BREAK_DDB	(BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT))

/*
 * The floating point version and status registers.
 */
#define	FPC_ID			$0
#define	FPC_CSR			$31

/*
 * The floating point coprocessor status register bits.
 */
#define	FPC_ROUNDING_BITS		0x00000003
#define	FPC_ROUND_RN			0x00000000
#define	FPC_ROUND_RZ			0x00000001
#define	FPC_ROUND_RP			0x00000002
#define	FPC_ROUND_RM			0x00000003
#define	FPC_STICKY_BITS			0x0000007c
#define	FPC_STICKY_INEXACT		0x00000004
#define	FPC_STICKY_UNDERFLOW		0x00000008
#define	FPC_STICKY_OVERFLOW		0x00000010
#define	FPC_STICKY_DIV0			0x00000020
#define	FPC_STICKY_INVALID		0x00000040
#define	FPC_ENABLE_BITS			0x00000f80
#define	FPC_ENABLE_INEXACT		0x00000080
#define	FPC_ENABLE_UNDERFLOW		0x00000100
#define	FPC_ENABLE_OVERFLOW		0x00000200
#define	FPC_ENABLE_DIV0			0x00000400
#define	FPC_ENABLE_INVALID		0x00000800
#define	FPC_EXCEPTION_BITS		0x0003f000
#define	FPC_EXCEPTION_INEXACT		0x00001000
#define	FPC_EXCEPTION_UNDERFLOW		0x00002000
#define	FPC_EXCEPTION_OVERFLOW		0x00004000
#define	FPC_EXCEPTION_DIV0		0x00008000
#define	FPC_EXCEPTION_INVALID		0x00010000
#define	FPC_EXCEPTION_UNIMPL		0x00020000
#define	FPC_COND_BIT			0x00800000
#define	FPC_FLUSH_BIT			0x01000000
#define	FPC_MBZ_BITS			0xfe7c0000

/*
 * Constants to determine if have a floating point instruction.
 */
#define	OPCODE_SHIFT		26
#define	OPCODE_C1		0x11

/*
 * The low part of the TLB entry.
 */
#define	VMTLB_PF_NUM		0x3fffffc0
#define	VMTLB_ATTR_MASK		0x00000038
#define	VMTLB_MOD_BIT		0x00000004
#define	VMTLB_VALID_BIT		0x00000002
#define	VMTLB_GLOBAL_BIT	0x00000001

#define	VMTLB_PHYS_PAGE_SHIFT	6

/*
 * The high part of the TLB entry.
 */
#define	VMTLB_VIRT_PAGE_NUM	0xffffe000
#define	VMTLB_PID		0x000000ff
#define	VMTLB_PID_SHIFT		0
#define	VMTLB_VIRT_PAGE_SHIFT	12

/*
 * The number of process id entries.
 */
#define	VMNUM_PIDS		256

/*
 * TLB probe return codes.
 */
#define	VMTLB_NOT_FOUND		0
#define	VMTLB_FOUND		1
#define	VMTLB_FOUND_WITH_PATCH	2
#define	VMTLB_PROBE_ERROR	3

/*
 * Exported definitions unique to mips cpu support.
 */

#ifndef _LOCORE

#include <sys/device.h>
#include <sys/lock.h>
#include <sys/sched.h>

#include <machine/intr.h>

struct cpu_info {
	struct device   *ci_dev;	/* our device */
	struct cpu_info *ci_self;	/* pointer to this structure */
	struct cpu_info *ci_next;	/* next cpu */
	struct proc	*ci_curproc;
	struct user *ci_curprocpaddr;

	struct schedstate_percpu
			 ci_schedstate;
	int		 ci_want_resched;	/* need_resched() invoked */
	cpuid_t          ci_cpuid;              /* our CPU ID */
	uint32_t	 ci_randseed;		/* per cpu random seed */
	int		 ci_ipl;		/* software IPL */
	uint32_t	 ci_softpending;	/* pending soft interrupts */
	int	         ci_clock_started;
	u_int32_t        ci_cpu_counter_last;
	u_int32_t        ci_cpu_counter_interval;
	u_int32_t        ci_pendingticks;
#ifdef MULTIPROCESSOR
	u_long           ci_flags;		/* flags; see below */
	struct intrhand  *ci_ipiih;
#endif
};

#define	CPUF_PRIMARY	0x01		/* CPU is primary CPU */
#define	CPUF_PRESENT	0x02		/* CPU is present */
#define	CPUF_RUNNING	0x04		/* CPU is running */

extern struct cpu_info cpu_info_primary;
extern struct cpu_info *cpu_info_list;
#define CPU_INFO_ITERATOR		int
#define	CPU_INFO_FOREACH(cii, ci)	for (cii = 0, ci = cpu_info_list; \
					    ci != NULL; ci = ci->ci_next)

#define CPU_INFO_UNIT(ci)               ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0)

#ifdef MULTIPROCESSOR
#define MAXCPUS				4
#define curcpu()			(cpu_info[cpu_number()])
#define	CPU_IS_PRIMARY(ci)		((ci)->ci_flags & CPUF_PRIMARY)
#define cpu_number()			hw_cpu_number()

extern struct cpuset cpus_running;
extern struct cpu_info *cpu_info[];
void cpu_unidle(struct cpu_info *);
void cpu_boot_secondary_processors(void);
#define cpu_boot_secondary(ci)          hw_cpu_boot_secondary(ci)
#define cpu_hatch(ci)                   hw_cpu_hatch(ci)

vaddr_t smp_malloc(size_t);

#define MIPS64_IPI_NOP		0x00000001
#define MIPS64_NIPIS		1	/* must not exceed 32 */

void    mips64_ipi_init(void);
void    mips64_send_ipi(unsigned int, unsigned int);
void    mips64_broadcast_ipi(unsigned int);
void    mips64_multicast_ipi(unsigned int, unsigned int);

#include <sys/mplock.h>
#else
#define MAXCPUS				1
#define curcpu()			(&cpu_info_primary)
#define	CPU_IS_PRIMARY(ci)		1
#define cpu_number()			0
#define cpu_unidle(ci)
#endif

void cpu_startclock(struct cpu_info *);

#include <machine/frame.h>

#endif	/* _LOCORE */

#ifndef _LOCORE

/*
 * Arguments to hardclock encapsulate the previous machine state in
 * an opaque clockframe.
 */
extern int int_nest_cntr;
#define	clockframe trap_frame	/* Use normal trap frame */

#define	CLKF_USERMODE(framep)	((framep)->sr & SR_KSU_USER)
#define	CLKF_PC(framep)		((framep)->pc)
#define	CLKF_INTR(framep)	(int_nest_cntr > 0)

/*
 * This is used during profiling to integrate system time.
 */
#define	PROC_PC(p)	((p)->p_md.md_regs->pc)

/*
 * Preempt the current process if in interrupt from user mode,
 * or after the current trap/syscall if in system mode.
 */
#define	need_resched(ci) \
	do { \
		(ci)->ci_want_resched = 1; \
		if ((ci)->ci_curproc != NULL) \
			aston((ci)->ci_curproc); \
	} while(0)
#define	clear_resched(ci) 	(ci)->ci_want_resched = 0

/*
 * Give a profiling tick to the current process when the user profiling
 * buffer pages are invalid.  On the PICA, request an ast to send us
 * through trap, marking the proc as needing a profiling tick.
 */
#define	need_proftick(p)	aston(p)

/*
 * Notify the current process (p) that it has a signal pending,
 * process as soon as possible.
 */
#define	signotify(p)		aston(p)

#define	aston(p)		p->p_md.md_astpending = 1

#endif /* !_LOCORE */
#endif /* _KERNEL */

/*
 * CTL_MACHDEP definitions.
 */
#define	CPU_ALLOWAPERTURE	1	/* allow mmap of /dev/xf86 */
#define	CPU_KBDRESET		2	/* keyboard reset */
#define	CPU_MAXID		3	/* number of valid machdep ids */

#define	CTL_MACHDEP_NAMES {			\
	{ 0, 0 },				\
	{ "allowaperture", CTLTYPE_INT },	\
	{ "kbdreset", CTLTYPE_INT },		\
}

/*
 * MIPS CPU types (cp_imp).
 */
#define	MIPS_R2000	0x01	/* MIPS R2000 CPU		ISA I   */
#define	MIPS_R3000	0x02	/* MIPS R3000 CPU		ISA I   */
#define	MIPS_R6000	0x03	/* MIPS R6000 CPU		ISA II	*/
#define	MIPS_R4000	0x04	/* MIPS R4000/4400 CPU		ISA III	*/
#define	MIPS_R3LSI	0x05	/* LSI Logic R3000 derivate	ISA I	*/
#define	MIPS_R6000A	0x06	/* MIPS R6000A CPU		ISA II	*/
#define	MIPS_R3IDT	0x07	/* IDT R3000 derivate		ISA I	*/
#define	MIPS_R10000	0x09	/* MIPS R10000/T5 CPU		ISA IV  */
#define	MIPS_R4200	0x0a	/* MIPS R4200 CPU (ICE)		ISA III */
#define	MIPS_R4300	0x0b	/* NEC VR4300 CPU		ISA III */
#define	MIPS_R4100	0x0c	/* NEC VR41xx CPU MIPS-16	ISA III */
#define	MIPS_R12000	0x0e	/* MIPS R12000			ISA IV  */
#define	MIPS_R14000	0x0f	/* MIPS R14000			ISA IV  */
#define	MIPS_R8000	0x10	/* MIPS R8000 Blackbird/TFP	ISA IV  */
#define	MIPS_R4600	0x20	/* PMCS R4600 Orion		ISA III */
#define	MIPS_R4700	0x21	/* PMCS R4700 Orion		ISA III */
#define	MIPS_R3TOSH	0x22	/* Toshiba R3000 based CPU	ISA I	*/
#define	MIPS_R5000	0x23	/* MIPS R5000 CPU		ISA IV  */
#define	MIPS_RM7000	0x27	/* PMCS RM7000 CPU		ISA IV  */
#define	MIPS_RM52X0	0x28	/* PMCS RM52X0 CPU		ISA IV  */
#define	MIPS_RM9000	0x34	/* PMCS RM9000 CPU		ISA IV  */
#define	MIPS_LOONGSON	0x42	/* STC LoongSon CPU		ISA III */
#define	MIPS_VR5400	0x54	/* NEC Vr5400 CPU		ISA IV+ */
#define	MIPS_LOONGSON2	0x63	/* STC LoongSon2 CPU		ISA III */

/*
 * MIPS FPU types. Only soft, rest is the same as cpu type.
 */
#define	MIPS_SOFT	0x00	/* Software emulation		ISA I   */


#if defined(_KERNEL) && !defined(_LOCORE)

extern u_int	CpuPrimaryInstCacheSize;
extern u_int	CpuPrimaryInstCacheLSize;
extern u_int	CpuPrimaryInstSetSize;
extern u_int	CpuPrimaryDataCacheSize;
extern u_int	CpuPrimaryDataCacheLSize;
extern u_int	CpuPrimaryDataSetSize;
extern u_int	CpuCacheAliasMask;
extern u_int	CpuSecondaryCacheSize;
extern u_int	CpuTertiaryCacheSize;
extern u_int	CpuNWayCache;
extern u_int	CpuCacheType;		/* R4K, R5K, RM7K */
extern u_int	CpuConfigRegister;
extern u_int	CpuStatusRegister;
extern u_int	CpuExternalCacheOn;	/* R5K, RM7K */
extern u_int	CpuOnboardCacheOn;	/* RM7K */

struct tlb_entry;
struct user;

void	tlb_set_wired(int);
void	tlb_set_pid(int);
u_int	cp0_get_prid(void);
u_int	cp1_get_prid(void);
u_int	cp0_get_count(void);
void	cp0_set_compare(u_int);

/*
 * Define soft selected cache functions.
 */
#define	Mips_SyncCache()	(*(sys_config._SyncCache))()
#define	Mips_InvalidateICache(a, l)	\
				(*(sys_config._InvalidateICache))((a), (l))
#define	Mips_SyncDCachePage(a)		\
				(*(sys_config._SyncDCachePage))((a))
#define	Mips_HitSyncDCache(a, l)	\
				(*(sys_config._HitSyncDCache))((a), (l))
#define	Mips_IOSyncDCache(a, l, h)	\
				(*(sys_config._IOSyncDCache))((a), (l), (h))
#define	Mips_HitInvalidateDCache(a, l)	\
				(*(sys_config._HitInvalidateDCache))((a), (l))

int	Loongson2_ConfigCache(void);
void	Loongson2_SyncCache(void);
void	Loongson2_InvalidateICache(vaddr_t, int);
void	Loongson2_SyncDCachePage(vaddr_t);
void	Loongson2_HitSyncDCache(vaddr_t, int);
void	Loongson2_IOSyncDCache(vaddr_t, int, int);
void	Loongson2_HitInvalidateDCache(vaddr_t, int);

int	Mips5k_ConfigCache(void);
void	Mips5k_SyncCache(void);
void	Mips5k_InvalidateICache(vaddr_t, int);
void	Mips5k_SyncDCachePage(vaddr_t);
void	Mips5k_HitSyncDCache(vaddr_t, int);
void	Mips5k_IOSyncDCache(vaddr_t, int, int);
void	Mips5k_HitInvalidateDCache(vaddr_t, int);

int	Mips10k_ConfigCache(void);
void	Mips10k_SyncCache(void);
void	Mips10k_InvalidateICache(vaddr_t, int);
void	Mips10k_SyncDCachePage(vaddr_t);
void	Mips10k_HitSyncDCache(vaddr_t, int);
void	Mips10k_IOSyncDCache(vaddr_t, int, int);
void	Mips10k_HitInvalidateDCache(vaddr_t, int);

void	tlb_flush(int);
void	tlb_flush_addr(vaddr_t);
void	tlb_write_indexed(int, struct tlb_entry *);
int	tlb_update(vaddr_t, unsigned);
void	tlb_read(int, struct tlb_entry *);

void	savectx(struct user *, int);
void	MipsSaveCurFPState(struct proc *);
void	MipsSaveCurFPState16(struct proc *);

int	guarded_read_4(paddr_t, uint32_t *);
int	guarded_write_4(paddr_t, uint32_t);

extern u_int32_t cpu_counter_interval;	/* Number of counter ticks/tick */
extern u_int32_t cpu_counter_last;	/* Last compare value loaded */

/*
 *  Low level access routines to CPU registers
 */

void	setsoftintr0(void);
void	clearsoftintr0(void);
void	setsoftintr1(void);
void	clearsoftintr1(void);
u_int32_t enableintr(void);
u_int32_t disableintr(void);
void	setsr(u_int32_t);
u_int32_t getsr(void);

#endif /* _KERNEL */
#endif /* !_MIPS_CPU_H_ */