1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
|
/* $OpenBSD: cp0access.S,v 1.23 2021/05/01 16:11:11 visa Exp $ */
/*
* Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
/*
* Low level code to manage processor specific registers.
*/
#include <sys/errno.h>
#include <sys/syscall.h>
#include <machine/param.h>
#include <machine/asm.h>
#include <machine/cpu.h>
#include <mips64/mips_cpu.h>
#include <machine/regnum.h>
#include "assym.h"
.set mips3
.set noreorder # Noreorder is default style!
/*
* Set/clear software interrupt.
*/
LEAF(setsoftintr0, 0)
MFC0 v0, COP_0_CAUSE_REG # read cause register
MFC0_HAZARD
NOP
or v0, v0, SOFT_INT_MASK_0 # set soft clock interrupt
MTC0 v0, COP_0_CAUSE_REG # save it
MTC0_HAZARD
j ra
NOP
END(setsoftintr0)
LEAF(clearsoftintr0, 0)
MFC0 v0, COP_0_CAUSE_REG # read cause register
MFC0_HAZARD
NOP
and v0, v0, ~SOFT_INT_MASK_0 # clear soft clock interrupt
MTC0 v0, COP_0_CAUSE_REG # save it
MTC0_HAZARD
j ra
NOP
END(clearsoftintr0)
LEAF(setsoftintr1, 0)
MFC0 v0, COP_0_CAUSE_REG # read cause register
MFC0_HAZARD
NOP
or v0, v0, SOFT_INT_MASK_1 # set soft net interrupt
MTC0 v0, COP_0_CAUSE_REG # save it
MTC0_HAZARD
j ra
NOP
END(setsoftintr1)
LEAF(clearsoftintr1, 0)
MFC0 v0, COP_0_CAUSE_REG # read cause register
MFC0_HAZARD
NOP
and v0, v0, ~SOFT_INT_MASK_1 # clear soft net interrupt
MTC0 v0, COP_0_CAUSE_REG # save it
MTC0_HAZARD
j ra
NOP
END(clearsoftintr1)
/*
* Set/change interrupt priority routines.
* These routines return the previous state.
*/
LEAF(enableintr, 0)
MFC0 v0, COP_0_STATUS_REG # read status register
MFC0_HAZARD
NOP
or v1, v0, SR_INT_ENAB
MTC0 v1, COP_0_STATUS_REG # enable all interrupts
MTC0_SR_IE_HAZARD
j ra
NOP
END(enableintr)
LEAF(disableintr, 0)
MFC0 v0, COP_0_STATUS_REG # read status register
MFC0_HAZARD
NOP
and v1, v0, ~SR_INT_ENAB
MTC0 v1, COP_0_STATUS_REG # disable all interrupts
MTC0_SR_IE_HAZARD
j ra
NOP
END(disableintr)
LEAF(updateimask, 0)
lw t0, idle_mask
not a0, a0 # 1 means masked so invert.
and a0, t0 # never upgrade to higher than max
MFC0 v0, COP_0_STATUS_REG
MFC0_HAZARD
LI v1, ~SR_INT_MASK
and v1, v0
and v0, a0, SR_INT_MASK
or v1, v0
MTC0 v1, COP_0_STATUS_REG
MTC0_SR_IE_HAZARD
ori v1, SR_INT_ENAB # enable interrupts
MTC0 v1, COP_0_STATUS_REG
MTC0_SR_IE_HAZARD
jr ra
move v0, v1
END(updateimask)
LEAF(setsr, 0)
MTC0 a0, COP_0_STATUS_REG
MTC0_SR_IE_HAZARD
jr ra
move v0, a0
END(setsr)
LEAF(getsr, 0)
MFC0 v0, COP_0_STATUS_REG
MFC0_HAZARD
j ra
NOP
END(getsr)
LEAF(cp0_get_config, 0)
MFC0 v0, COP_0_CONFIG
MFC0_HAZARD
j ra
NOP
END(cp0_get_config)
/* WARNING!
Needs to be invoked from uncached address if changing cache settings. */
LEAF(cp0_set_config, 0)
MTC0 a0, COP_0_CONFIG
MTC0_HAZARD
j ra
NOP
END(cp0_set_config)
LEAF(cp0_get_prid, 0)
MFC0 v0, COP_0_PRID
MFC0_HAZARD
j ra
NOP
END(cp0_get_prid)
LEAF(cp0_get_count, 0)
MFC0 v0, COP_0_COUNT
MFC0_HAZARD
j ra
NOP
END(cp0_get_count)
LEAF(cp0_set_compare, 0)
MTC0 a0, COP_0_COMPARE
MTC0_HAZARD
j ra
NOP
END(cp0_set_compare)
LEAF(cpu_rnd_messybits, 0)
MFC0 v0, COP_0_COUNT
MFC0_HAZARD
MFC0 v1, COP_0_BAD_VADDR
MFC0_HAZARD
xor v0, v1
j ra
NOP
END(cpu_rnd_messybits)
|
