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/* $Id: cpu.h,v 1.2 1995/11/07 08:49:47 deraadt Exp $ */
/*
* Copyright (c) 1995 Theo de Raadt
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed under OpenBSD by
* Theo de Raadt for Willowglen Singapore.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1982, 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Utah $Hdr: cpu.h 1.16 91/03/25$
*
* @(#)cpu.h 8.4 (Berkeley) 1/5/94
*/
/*
* Exported definitions unique to mvme68k/68k cpu support.
*/
/*
* definitions of cpu-dependent requirements
* referenced in generic code
*/
#define cpu_swapin(p) /* nothing */
#define cpu_wait(p) /* nothing */
#define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap
#define cpu_swapout(p) /* nothing */
/*
* Arguments to hardclock and gatherstats encapsulate the previous
* machine state in an opaque clockframe. One the m68k, we use
* what the hardware pushes on an interrupt (frame format 0).
*/
struct clockframe {
u_short sr; /* sr at time of interrupt */
u_long pc; /* pc at time of interrupt */
u_short vo; /* vector offset (4-word frame) */
};
#define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
#define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
#define CLKF_PC(framep) ((framep)->pc)
#if 0
/* We would like to do it this way... */
#define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0)
#else
/* but until we start using PSL_M, we have to do this instead */
#define CLKF_INTR(framep) (0) /* XXX */
#endif
/*
* Preempt the current process if in interrupt from user mode,
* or after the current trap/syscall if in system mode.
*/
#define need_resched() { want_resched++; aston(); }
/*
* Give a profiling tick to the current process when the user profiling
* buffer pages are invalid. On the m68k, request an ast to send us
* through trap, marking the proc as needing a profiling tick.
*/
#define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); }
/*
* Notify the current process (p) that it has a signal pending,
* process as soon as possible.
*/
#define signotify(p) aston()
#define aston() (astpending++)
int astpending; /* need to trap before returning to user mode */
int want_resched; /* resched() was called */
/*
* simulated software interrupt register
*/
extern unsigned char ssir;
#define SIR_NET 0x1
#define SIR_CLOCK 0x2
#define setsoftint(x) ssir |= (x)
#define setsoftnet() ssir |= SIR_NET
#define setsoftclock() ssir |= SIR_CLOCK
u_long allocate_sir __P((void (*proc)(), void *arg));
/*
* CTL_MACHDEP definitions.
*/
#define CPU_CONSDEV 1 /* dev_t: console terminal device */
#define CPU_MAXID 2 /* number of valid machdep ids */
#define CTL_MACHDEP_NAMES { \
{ 0, 0 }, \
{ "console_device", CTLTYPE_STRUCT }, \
}
/* values for mmutype (assigned for quick testing) */
#define MMU_68040 -2 /* 68040 on-chip MMU */
#define MMU_68030 -1 /* 68030 on-chip subset of 68851 */
#define MMU_68851 1 /* Motorola 68851 */
/* values for ectype */
#define EC_PHYS -1 /* external physical address cache */
#define EC_NONE 0 /* no external cache */
#define EC_VIRT 1 /* external virtual address cache */
#ifdef _KERNEL
extern int mmutype, ectype;
extern char *intiobase, *intiolimit;
extern char *iiomapbase;
extern int iiomapsize;
#endif
/* physical memory sections for mvme147 */
#define INTIOBASE_147 (0xfffe0000)
#define INTIOTOP_147 (0xfffe5000)
#define INTIOSIZE_147 ((INTIOTOP_147-INTIOBASE_147)/NBPG)
/* physical memory sections for mvme16x */
#define INTIOBASE_162 (0xfff00000)
#define INTIOTOP_162 (0xfffd0000) /* was 0xfff50000 */
#define INTIOSIZE_162 ((INTIOTOP_162-INTIOBASE_162)/NBPG)
/*
* Internal IO space (iiomapsize).
*
* Internal IO space is mapped in the kernel from ``intiobase'' to
* ``intiolimit'' (defined in locore.s). Since it is always mapped,
* conversion between physical and kernel virtual addresses is easy.
*/
#define ISIIOVA(va) \
((char *)(va) >= intiobase && (char *)(va) < intiolimit)
#define IIOV(pa) ((int)(pa)-(int)iiomapbase+(int)intiobase)
#define IIOP(va) ((int)(va)-(int)intiobase+(int)iiomapbase)
#define IIOPOFF(pa) ((int)(pa)-(int)iiomapbase)
/*
* 68851 and 68030 MMU
*/
#define PMMU_LVLMASK 0x0007
#define PMMU_INV 0x0400
#define PMMU_WP 0x0800
#define PMMU_ALV 0x1000
#define PMMU_SO 0x2000
#define PMMU_LV 0x4000
#define PMMU_BE 0x8000
#define PMMU_FAULT (PMMU_WP|PMMU_INV)
/*
* 68040 MMU
*/
#define MMU4_RES 0x001
#define MMU4_TTR 0x002
#define MMU4_WP 0x004
#define MMU4_MOD 0x010
#define MMU4_CMMASK 0x060
#define MMU4_SUP 0x080
#define MMU4_U0 0x100
#define MMU4_U1 0x200
#define MMU4_GLB 0x400
#define MMU4_BE 0x800
/* 680X0 function codes */
#define FC_USERD 1 /* user data space */
#define FC_USERP 2 /* user program space */
#define FC_SUPERD 5 /* supervisor data space */
#define FC_SUPERP 6 /* supervisor program space */
#define FC_CPU 7 /* CPU space */
/* fields in the 68020 cache control register */
#define IC_ENABLE 0x0001 /* enable instruction cache */
#define IC_FREEZE 0x0002 /* freeze instruction cache */
#define IC_CE 0x0004 /* clear instruction cache entry */
#define IC_CLR 0x0008 /* clear entire instruction cache */
/* additional fields in the 68030 cache control register */
#define IC_BE 0x0010 /* instruction burst enable */
#define DC_ENABLE 0x0100 /* data cache enable */
#define DC_FREEZE 0x0200 /* data cache freeze */
#define DC_CE 0x0400 /* clear data cache entry */
#define DC_CLR 0x0800 /* clear entire data cache */
#define DC_BE 0x1000 /* data burst enable */
#define DC_WA 0x2000 /* write allocate */
#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
#define CACHE_OFF (DC_CLR|IC_CLR)
#define CACHE_CLR (CACHE_ON)
#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
/* 68040 cache control register */
#define IC4_ENABLE 0x00008000 /* instruction cache enable bit */
#define DC4_ENABLE 0x80000000 /* data cache enable bit */
#define CACHE4_ON (IC4_ENABLE|DC4_ENABLE)
#define CACHE4_OFF (0)
extern int cputyp;
#define CPU_147 0x147
#define CPU_162 0x162
#define CPU_166 0x166
#define CPU_167 0x167
#define CPU_172 0x172
#define CPU_177 0x177
struct intrhand {
struct intrhand *ih_next;
int (*ih_fn)();
void *ih_arg;
int ih_ipl;
int ih_wantframe;
};
struct haltvec {
struct haltvec *hv_next;
void (*hv_fn) __P((void));
int hv_pri;
};
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