1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
|
/* $NetBSD: sii.c,v 1.8 1995/09/13 19:35:58 jonathan Exp $ */
/*-
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)sii.c 8.2 (Berkeley) 11/30/93
*
* from: Header: /sprite/src/kernel/dev/ds3100.md/RCS/devSII.c,
* v 9.2 89/09/14 13:37:41 jhh Exp $ SPRITE (DECWRL)";
*/
#include "sii.h"
#if NSII > 0
/*
* SCSI interface driver
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/dkstat.h>
#include <sys/buf.h>
#include <sys/conf.h>
#include <sys/errno.h>
#include <sys/device.h>
#ifdef notyet
#include <scsi/scsi_all.h>
#include <scsi/scsiconf.h>
#endif
#include <machine/autoconf.h>
#include <machine/machConst.h>
#include <pmax/dev/device.h>
#include <pmax/dev/scsi.h>
#include <pmax/dev/siireg.h>
#include <pmax/pmax/kn01.h>
typedef struct scsi_state {
int statusByte; /* status byte returned during STATUS_PHASE */
int dmaDataPhase; /* which data phase to expect */
int dmaCurPhase; /* SCSI phase if DMA is in progress */
int dmaPrevPhase; /* SCSI phase of DMA suspended by disconnect */
u_short *dmaAddr[2]; /* DMA buffer memory address */
int dmaBufIndex; /* which of the above is currently in use */
int dmalen; /* amount to transfer in this chunk */
int cmdlen; /* total remaining amount of cmd to transfer */
u_char *cmd; /* current pointer within scsicmd->cmd */
int buflen; /* total remaining amount of data to transfer */
char *buf; /* current pointer within scsicmd->buf */
u_short flags; /* see below */
u_short prevComm; /* command reg before disconnect */
u_short dmaCtrl; /* DMA control register if disconnect */
u_short dmaAddrL; /* DMA address register if disconnect */
u_short dmaAddrH; /* DMA address register if disconnect */
u_short dmaCnt; /* DMA count if disconnect */
u_short dmaByte; /* DMA byte if disconnect on odd boundary */
u_short dmaReqAck; /* DMA synchronous xfer offset or 0 if async */
} State;
/* state flags */
#define FIRST_DMA 0x01 /* true if no data DMA started yet */
#define PARITY_ERR 0x02 /* true if parity error seen */
#define SII_NCMD 7
struct siisoftc {
struct device sc_dev; /* us as a device */
SIIRegs *sc_regs; /* HW address of SII controller chip */
int sc_flags;
int sc_target; /* target SCSI ID if connected */
ScsiCmd *sc_cmd[SII_NCMD]; /* active command indexed by ID */
State sc_st[SII_NCMD]; /* state info for each active command */
#ifdef NEW_SCSI
struct scsi_link sc_link; /* scsi lint struct */
#endif
};
/*
* Device definition for autoconfiguration.
*
*/
int siimatch __P((struct device * parent, void *cfdata, void *aux));
void siiattach __P((struct device *parent, struct device *self, void *aux));
int siiprint(void*, char*);
int sii_doprobe __P((void *addr, int unit, int flags, int pri,
struct device *self));
int siiintr __P((void *sc));
extern struct cfdriver siicd;
struct cfdriver siicd = {
NULL, "sii", siimatch, siiattach, DV_DULL, sizeof(struct siisoftc)
};
#ifdef USE_NEW_SCSI
/* Glue to the machine-independent scsi */
struct scsi_adapter asc_switch = {
NULL, /* XXX - asc_scsi_cmd */
#if 0
/*XXX*/ minphys, /* no max transfer size; DMA engine deals */
#else
SII_MAX_DMA_XFER_LENGTH,
#endif
NULL,
NULL,
};
struct scsi_device sii_dev = {
/*XXX*/ NULL, /* Use default error handler */
/*XXX*/ NULL, /* have a queue, served by this */
/*XXX*/ NULL, /* have no async handler */
/*XXX*/ NULL, /* Use default 'done' routine */
};
#endif
/*
* Definition of the controller for the old auto-configuration program.
*/
void siistart();
struct pmax_driver siidriver = {
"sii", NULL, siistart, 0,
};
/*
* MACROS for timing out spin loops.
*
* Wait until expression is true.
*
* Control register bits can change at any time so when the CPU
* reads a register, the bits might change and
* invalidate the setup and hold times for the CPU.
* This macro reads the register twice to be sure the value is stable.
*
* args: var - variable to save control register contents
* reg - control register to read
* expr - expression to spin on
* spincount - maximum number of times through the loop
* cntr - variable for number of tries
*/
#define SII_WAIT_UNTIL(var, reg, expr, spincount, cntr) { \
register u_int tmp = reg; \
for (cntr = 0; cntr < spincount; cntr++) { \
while (tmp != (var = reg)) \
tmp = var; \
if (expr) \
break; \
if (cntr >= 100) \
DELAY(100); \
} \
}
#ifdef DEBUG
int sii_debug = 1;
int sii_debug_cmd;
int sii_debug_bn;
int sii_debug_sz;
#define NLOG 16
struct sii_log {
u_short cstat;
u_short dstat;
u_short comm;
u_short msg;
int rlen;
int dlen;
int target;
} sii_log[NLOG], *sii_logp = sii_log;
#endif
u_char sii_buf[256]; /* used for extended messages */
#define NORESET 0
#define RESET 1
#define NOWAIT 0
#define WAIT 1
/* define a safe address in the SCSI buffer for doing status & message DMA */
#define SII_BUF_ADDR (MACH_PHYS_TO_UNCACHED(KN01_SYS_SII_B_START) \
+ SII_MAX_DMA_XFER_LENGTH * 14)
static void sii_Reset();
static void sii_StartCmd();
static void sii_CmdDone();
static void sii_DoIntr();
static void sii_StateChg();
static void sii_DoSync();
static void sii_StartDMA();
static int sii_GetByte();
/*
* Match driver based on name
*/
int
siimatch(parent, match, aux)
struct device *parent;
void *match;
void *aux;
{
struct cfdata *cf = match;
struct confargs *ca = aux;
if (!BUS_MATCHNAME(ca, "sii") && !BUS_MATCHNAME(ca, "PMAZ-AA "))
return (0);
/* XXX check for bad address */
/* XXX kn01s have exactly one SII. Does any other machine use them? */
return (1);
}
void
siiattach(parent, self, aux)
struct device *parent;
struct device *self;
void *aux;
{
register struct confargs *ca = aux;
register struct siisoftc *sc = (struct siisoftc *) self;
register void *siiaddr;
register int i;
siiaddr = (void*)MACH_PHYS_TO_UNCACHED(BUS_CVTADDR(ca));
sc->sc_regs = (SIIRegs *)siiaddr;
sc->sc_flags = sc->sc_dev.dv_cfdata->cf_flags;
sc->sc_target = -1; /* no command active */
/*
* Give each target its own DMA buffer region.
* Make it big enough for 2 max transfers so we can ping pong buffers
* while we copy the data.
*/
for (i = 0; i < SII_NCMD; i++) {
sc->sc_st[i].dmaAddr[0] = (u_short *)
MACH_PHYS_TO_UNCACHED(KN01_SYS_SII_B_START) +
2 * SII_MAX_DMA_XFER_LENGTH * i;
sc->sc_st[i].dmaAddr[1] = sc->sc_st[i].dmaAddr[0] +
SII_MAX_DMA_XFER_LENGTH;
}
/* Hack for old-sytle SCSI-device probe */
(void) pmax_add_scsi(&siidriver, sc->sc_dev.dv_unit);
sii_Reset(sc, RESET);
/*priority = ca->ca_slot;*/
/* tie pseudo-slot to device */
BUS_INTR_ESTABLISH(ca, siiintr, sc);
printf("\n");
}
/*
* Start activity on a SCSI device.
* We maintain information on each device separately since devices can
* connect/disconnect during an operation.
*/
void
siistart(scsicmd)
register ScsiCmd *scsicmd; /* command to start */
{
register struct pmax_scsi_device *sdp = scsicmd->sd;
register struct siisoftc *sc = siicd.cd_devs[sdp->sd_ctlr];
int s;
s = splbio();
/*
* Check if another command is already in progress.
* We may have to change this if we allow SCSI devices with
* separate LUNs.
*/
if (sc->sc_cmd[sdp->sd_drive]) {
printf("%s: device %s busy at start\n", sc->sc_dev.dv_xname,
sdp->sd_driver->d_name);
(*sdp->sd_driver->d_done)(scsicmd->unit, EBUSY,
scsicmd->buflen, 0);
splx(s);
}
sc->sc_cmd[sdp->sd_drive] = scsicmd;
sii_StartCmd(sc, sdp->sd_drive);
splx(s);
}
/*
* Check to see if any SII chips have pending interrupts
* and process as appropriate.
*/
int
siiintr(xxxsc)
void *xxxsc;
{
register struct siisoftc *sc = xxxsc;
u_int dstat;
/*
* Find which controller caused the interrupt.
*/
dstat = sc->sc_regs->dstat;
if (dstat & (SII_CI | SII_DI))
sii_DoIntr(sc, dstat);
}
/*
* Reset the SII chip and do a SCSI reset if 'reset' is true.
* NOTE: if !cold && reset, should probably probe for devices
* since a SCSI bus reset will set UNIT_ATTENTION.
*/
static void
sii_Reset(sc, reset)
register struct siisoftc* sc;
int reset; /* TRUE => reset SCSI bus */
{
register SIIRegs *regs = sc->sc_regs;
#ifdef DEBUG
if (sii_debug > 1)
printf("sii: RESET\n");
#endif
/*
* Reset the SII chip.
*/
regs->comm = SII_CHRESET;
/*
* Set arbitrated bus mode.
*/
regs->csr = SII_HPM;
/*
* SII is always ID 7.
*/
regs->id = SII_ID_IO | 7;
/*
* Enable SII to drive the SCSI bus.
*/
regs->dictrl = SII_PRE;
regs->dmctrl = 0;
if (reset) {
register int i;
/*
* Assert SCSI bus reset for at least 25 Usec to clear the
* world. SII_DO_RST is self clearing.
* Delay 250 ms before doing any commands.
*/
regs->comm = SII_DO_RST;
MachEmptyWriteBuffer();
DELAY(250000);
/* rearbitrate synchronous offset */
for (i = 0; i < SII_NCMD; i++)
sc->sc_st[i].dmaReqAck = 0;
}
/*
* Clear any pending interrupts from the reset.
*/
regs->cstat = regs->cstat;
regs->dstat = regs->dstat;
/*
* Set up SII for arbitrated bus mode, SCSI parity checking,
* Reselect Enable, and Interrupt Enable.
*/
regs->csr = SII_HPM | SII_RSE | SII_PCE | SII_IE;
MachEmptyWriteBuffer();
}
/*
* Start a SCSI command by sending the cmd data
* to a SCSI controller via the SII.
* Call the device done proceedure if it can't be started.
* NOTE: we should be called with interrupts disabled.
*/
static void
sii_StartCmd(sc, target)
register struct siisoftc *sc; /* which SII to use */
register int target; /* which command to start */
{
register SIIRegs *regs;
register ScsiCmd *scsicmd;
register State *state;
register u_int status;
int error, retval;
/* if another command is currently in progress, just wait */
if (sc->sc_target >= 0)
return;
/* initialize state information for this command */
scsicmd = sc->sc_cmd[target];
state = &sc->sc_st[target];
state->flags = FIRST_DMA;
state->prevComm = 0;
state->dmalen = 0;
state->dmaCurPhase = -1;
state->dmaPrevPhase = -1;
state->dmaBufIndex = 0;
state->cmd = scsicmd->cmd;
state->cmdlen = scsicmd->cmdlen;
if ((state->buflen = scsicmd->buflen) == 0) {
state->dmaDataPhase = -1; /* illegal phase. shouldn't happen */
state->buf = (char *)0;
} else {
state->dmaDataPhase =
(scsicmd->flags & SCSICMD_DATA_TO_DEVICE) ?
SII_DATA_OUT_PHASE : SII_DATA_IN_PHASE;
state->buf = scsicmd->buf;
}
#ifdef DEBUG
if (sii_debug > 1) {
printf("sii_StartCmd: %s target %d cmd 0x%x addr %x size %d dma %d\n",
scsicmd->sd->sd_driver->d_name, target,
scsicmd->cmd[0], scsicmd->buf, scsicmd->buflen,
state->dmaDataPhase);
}
sii_debug_cmd = scsicmd->cmd[0];
if (scsicmd->cmd[0] == SCSI_READ_EXT ||
scsicmd->cmd[0] == SCSI_WRITE_EXT) {
sii_debug_bn = (scsicmd->cmd[2] << 24) |
(scsicmd->cmd[3] << 16) |
(scsicmd->cmd[4] << 8) |
scsicmd->cmd[5];
sii_debug_sz = (scsicmd->cmd[7] << 8) | scsicmd->cmd[8];
} else {
sii_debug_bn = 0;
sii_debug_sz = 0;
}
#endif
/* try to select the target */
regs = sc->sc_regs;
/*
* Another device may have selected us; in which case,
* this command will be restarted later.
*/
if ((status = regs->dstat) & (SII_CI | SII_DI)) {
sii_DoIntr(sc, status);
return;
}
sc->sc_target = target;
#if 0
/* seem to have problems with synchronous transfers */
if (scsicmd->flags & SCSICMD_USE_SYNC) {
printf("sii_StartCmd: doing extended msg\n"); /* XXX */
/*
* Setup to send both the identify message and the synchronous
* data transfer request.
*/
sii_buf[0] = SCSI_DIS_REC_IDENTIFY;
sii_buf[1] = SCSI_EXTENDED_MSG;
sii_buf[2] = 3; /* message length */
sii_buf[3] = SCSI_SYNCHRONOUS_XFER;
sii_buf[4] = 0;
sii_buf[5] = 3; /* maximum SII chip supports */
state->dmaCurPhase = SII_MSG_OUT_PHASE,
state->dmalen = 6;
CopyToBuffer((u_short *)sii_buf,
(volatile u_short *)SII_BUF_ADDR, 6);
regs->slcsr = target;
regs->dmctrl = state->dmaReqAck;
regs->dmaddrl = (u_short)(SII_BUF_ADDR >> 1);
regs->dmaddrh = (u_short)(SII_BUF_ADDR >> 17) & 03;
regs->dmlotc = 6;
regs->comm = SII_DMA | SII_INXFER | SII_SELECT | SII_ATN |
SII_CON | SII_MSG_OUT_PHASE;
} else
#endif
{
/* do a chained, select with ATN and programmed I/O command */
regs->data = SCSI_DIS_REC_IDENTIFY;
regs->slcsr = target;
regs->dmctrl = state->dmaReqAck;
regs->comm = SII_INXFER | SII_SELECT | SII_ATN | SII_CON |
SII_MSG_OUT_PHASE;
}
MachEmptyWriteBuffer();
/*
* Wait for something to happen
* (should happen soon or we would use interrupts).
*/
SII_WAIT_UNTIL(status, regs->cstat, status & (SII_CI | SII_DI),
SII_WAIT_COUNT/4, retval);
/* check to see if we are connected OK */
if ((status & (SII_RST | SII_SCH | SII_STATE_MSK)) ==
(SII_SCH | SII_CON)) {
regs->cstat = status;
MachEmptyWriteBuffer();
#ifdef DEBUG
sii_logp->target = target;
sii_logp->cstat = status;
sii_logp->dstat = 0;
sii_logp->comm = regs->comm;
sii_logp->msg = -1;
sii_logp->rlen = state->buflen;
sii_logp->dlen = state->dmalen;
if (++sii_logp >= &sii_log[NLOG])
sii_logp = sii_log;
#endif
/* wait a short time for command phase */
SII_WAIT_UNTIL(status, regs->dstat, status & SII_MIS,
SII_WAIT_COUNT, retval);
#ifdef DEBUG
if (sii_debug > 2)
printf("sii_StartCmd: ds %x cnt %d\n", status, retval);
#endif
if ((status & (SII_CI | SII_MIS | SII_PHASE_MSK)) !=
(SII_MIS | SII_CMD_PHASE)) {
printf("sii_StartCmd: timeout cs %x ds %x cnt %d\n",
regs->cstat, status, retval); /* XXX */
/* process interrupt or continue until it happens */
if (status & (SII_CI | SII_DI))
sii_DoIntr(sc, status);
return;
}
regs->dstat = SII_DNE; /* clear Msg Out DMA done */
/* send command data */
CopyToBuffer((u_short *)state->cmd,
(volatile u_short *)state->dmaAddr[0], state->cmdlen);
sii_StartDMA(regs, state->dmaCurPhase = SII_CMD_PHASE,
state->dmaAddr[0], state->dmalen = scsicmd->cmdlen);
/* wait a little while for DMA to finish */
SII_WAIT_UNTIL(status, regs->dstat, status & (SII_CI | SII_DI),
SII_WAIT_COUNT, retval);
#ifdef DEBUG
if (sii_debug > 2)
printf("sii_StartCmd: ds %x, cnt %d\n", status, retval);
#endif
if (status & (SII_CI | SII_DI))
sii_DoIntr(sc, status);
#ifdef DEBUG
if (sii_debug > 2)
printf("sii_StartCmd: DONE ds %x\n", regs->dstat);
#endif
return;
}
/*
* Another device may have selected us; in which case,
* this command will be restarted later.
*/
if (status & (SII_CI | SII_DI)) {
sii_DoIntr(sc, regs->dstat);
return;
}
/*
* Disconnect if selection command still in progress.
*/
if (status & SII_SIP) {
error = ENXIO; /* device didn't respond */
regs->comm = SII_DISCON;
MachEmptyWriteBuffer();
SII_WAIT_UNTIL(status, regs->cstat,
!(status & (SII_CON | SII_SIP)),
SII_WAIT_COUNT, retval);
} else
error = EBUSY; /* couldn't get the bus */
#ifdef DEBUG
if (sii_debug > 1)
printf("sii_StartCmd: Couldn't select target %d error %d\n",
target, error);
#endif
sc->sc_target = -1;
regs->cstat = 0xffff;
regs->dstat = 0xffff;
regs->comm = 0;
MachEmptyWriteBuffer();
sii_CmdDone(sc, target, error);
}
/*
* Process interrupt conditions.
*/
static void
sii_DoIntr(sc, dstat)
register struct siisoftc *sc;
register u_int dstat;
{
register SIIRegs *regs = sc->sc_regs;
register State *state;
register u_int cstat;
int i, msg;
u_int comm;
again:
comm = regs->comm;
#ifdef DEBUG
if (sii_debug > 3)
printf("sii_DoIntr: cs %x, ds %x cm %x ",
regs->cstat, dstat, comm);
sii_logp->target = sc->sc_target;
sii_logp->cstat = regs->cstat;
sii_logp->dstat = dstat;
sii_logp->comm = comm;
sii_logp->msg = -1;
if (sc->sc_target >= 0) {
sii_logp->rlen = sc->sc_st[sc->sc_target].buflen;
sii_logp->dlen = sc->sc_st[sc->sc_target].dmalen;
} else {
sii_logp->rlen = 0;
sii_logp->dlen = 0;
}
if (++sii_logp >= &sii_log[NLOG])
sii_logp = sii_log;
#endif
regs->dstat = dstat; /* acknowledge everything */
MachEmptyWriteBuffer();
if (dstat & SII_CI) {
/* deglitch cstat register */
msg = regs->cstat;
while (msg != (cstat = regs->cstat))
msg = cstat;
regs->cstat = cstat; /* acknowledge everything */
MachEmptyWriteBuffer();
#ifdef DEBUG
if (sii_logp > sii_log)
sii_logp[-1].cstat = cstat;
else
sii_log[NLOG - 1].cstat = cstat;
#endif
/* check for a BUS RESET */
if (cstat & SII_RST) {
printf("%s: SCSI bus reset!!\n", sc->sc_dev.dv_xname);
/* need to flush disconnected commands */
for (i = 0; i < SII_NCMD; i++) {
if (!sc->sc_cmd[i])
continue;
sii_CmdDone(sc, i, EIO);
}
/* rearbitrate synchronous offset */
for (i = 0; i < SII_NCMD; i++)
sc->sc_st[i].dmaReqAck = 0;
sc->sc_target = -1;
return;
}
#ifdef notdef
/*
* Check for a BUS ERROR.
* According to DEC, this feature doesn't really work
* and to just clear the bit if it's set.
*/
if (cstat & SII_BER) {
}
#endif
/* check for state change */
if (cstat & SII_SCH) {
sii_StateChg(sc, cstat);
comm = regs->comm;
}
}
/* check for DMA completion */
if (dstat & SII_DNE) {
u_short *dma;
char *buf;
/*
* There is a race condition with SII_SCH. There is a short
* window between the time a SII_SCH is seen after a disconnect
* and when the SII_SCH is cleared. A reselect can happen
* in this window and we will clear the SII_SCH without
* processing the reconnect.
*/
if (sc->sc_target < 0) {
cstat = regs->cstat;
printf("%s: target %d DNE?? dev %d,%d cs %x\n",
sc->sc_dev.dv_xname, sc->sc_target,
regs->slcsr, regs->destat,
cstat); /* XXX */
if (cstat & SII_DST) {
sc->sc_target = regs->destat;
state->prevComm = 0;
} else
panic("sc_target 1");
}
state = &sc->sc_st[sc->sc_target];
/* check for a PARITY ERROR */
if (dstat & SII_IPE) {
state->flags |= PARITY_ERR;
printf("%s: Parity error!!\n", sc->sc_dev.dv_xname);
goto abort;
}
/* dmalen = amount left to transfer, i = amount transfered */
i = state->dmalen;
state->dmalen = 0;
state->dmaCurPhase = -1;
#ifdef DEBUG
if (sii_debug > 4) {
printf("DNE: amt %d ", i);
if (!(dstat & SII_TCZ))
printf("no TCZ?? (%d) ", regs->dmlotc);
} else if (!(dstat & SII_TCZ)) {
printf("%s: device %d: no TCZ?? (%d)\n",
sc->sc_dev.dv_xname, sc->sc_target, regs->dmlotc);
sii_DumpLog(); /* XXX */
}
#endif
switch (comm & SII_PHASE_MSK) {
case SII_CMD_PHASE:
state->cmdlen -= i;
break;
case SII_DATA_IN_PHASE:
/* check for more data for the same phase */
dma = state->dmaAddr[state->dmaBufIndex];
buf = state->buf;
state->buf += i;
state->buflen -= i;
if (state->buflen > 0 && !(dstat & SII_MIS)) {
int len;
/* start reading next chunk */
len = state->buflen;
if (len > SII_MAX_DMA_XFER_LENGTH)
len = SII_MAX_DMA_XFER_LENGTH;
state->dmaBufIndex = !state->dmaBufIndex;
sii_StartDMA(regs,
state->dmaCurPhase = SII_DATA_IN_PHASE,
state->dmaAddr[state->dmaBufIndex],
state->dmalen = len);
dstat &= ~(SII_IBF | SII_TBE);
}
/* copy in the data */
CopyFromBuffer((volatile u_short *)dma, buf, i);
break;
case SII_DATA_OUT_PHASE:
state->dmaBufIndex = !state->dmaBufIndex;
state->buf += i;
state->buflen -= i;
/* check for more data for the same phase */
if (state->buflen <= 0 || (dstat & SII_MIS))
break;
/* start next chunk */
i = state->buflen;
if (i > SII_MAX_DMA_XFER_LENGTH) {
sii_StartDMA(regs, state->dmaCurPhase =
SII_DATA_OUT_PHASE,
state->dmaAddr[state->dmaBufIndex],
state->dmalen =
SII_MAX_DMA_XFER_LENGTH);
/* prepare for next chunk */
i -= SII_MAX_DMA_XFER_LENGTH;
if (i > SII_MAX_DMA_XFER_LENGTH)
i = SII_MAX_DMA_XFER_LENGTH;
CopyToBuffer((u_short *)(state->buf +
SII_MAX_DMA_XFER_LENGTH),
(volatile u_short *)
state->dmaAddr[!state->dmaBufIndex], i);
} else {
sii_StartDMA(regs, state->dmaCurPhase =
SII_DATA_OUT_PHASE,
state->dmaAddr[state->dmaBufIndex],
state->dmalen = i);
}
dstat &= ~(SII_IBF | SII_TBE);
}
}
/* check for phase change or another MsgIn/Out */
if (dstat & (SII_MIS | SII_IBF | SII_TBE)) {
/*
* There is a race condition with SII_SCH. There is a short
* window between the time a SII_SCH is seen after a disconnect
* and when the SII_SCH is cleared. A reselect can happen
* in this window and we will clear the SII_SCH without
* processing the reconnect.
*/
if (sc->sc_target < 0) {
cstat = regs->cstat;
printf("%s: target %d MIS?? dev %d,%d cs %x ds %x\n",
sc->sc_dev.dv_xname, sc->sc_target,
regs->slcsr, regs->destat,
cstat, dstat); /* XXX */
if (cstat & SII_DST) {
sc->sc_target = regs->destat;
state->prevComm = 0;
} else {
#ifdef DEBUG
sii_DumpLog();
#endif
panic("sc_target 2");
}
}
state = &sc->sc_st[sc->sc_target];
switch (dstat & SII_PHASE_MSK) {
case SII_CMD_PHASE:
if (state->dmaPrevPhase >= 0) {
/* restart DMA after disconnect/reconnect */
if (state->dmaPrevPhase != SII_CMD_PHASE) {
printf("%s: device %d: dma reselect phase doesn't match\n",
sc->sc_dev.dv_xname, sc->sc_target);
goto abort;
}
state->dmaCurPhase = SII_CMD_PHASE;
state->dmaPrevPhase = -1;
regs->dmaddrl = state->dmaAddrL;
regs->dmaddrh = state->dmaAddrH;
regs->dmlotc = state->dmaCnt;
if (state->dmaCnt & 1)
regs->dmabyte = state->dmaByte;
regs->comm = SII_DMA | SII_INXFER |
(comm & SII_STATE_MSK) | SII_CMD_PHASE;
MachEmptyWriteBuffer();
#ifdef DEBUG
if (sii_debug > 4)
printf("Cmd dcnt %d dadr %x ",
state->dmaCnt,
(state->dmaAddrH << 16) |
state->dmaAddrL);
#endif
} else {
/* send command data */
i = state->cmdlen;
if (i == 0) {
printf("%s: device %d: cmd count exceeded\n",
sc->sc_dev.dv_xname, sc->sc_target);
goto abort;
}
CopyToBuffer((u_short *)state->cmd,
(volatile u_short *)state->dmaAddr[0],
i);
sii_StartDMA(regs, state->dmaCurPhase =
SII_CMD_PHASE, state->dmaAddr[0],
state->dmalen = i);
}
/* wait a short time for XFER complete */
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & (SII_CI | SII_DI), SII_WAIT_COUNT, i);
if (dstat & (SII_CI | SII_DI)) {
#ifdef DEBUG
if (sii_debug > 4)
printf("cnt %d\n", i);
else if (sii_debug > 0)
printf("sii_DoIntr: cmd wait ds %x cnt %d\n",
dstat, i);
#endif
goto again;
}
break;
case SII_DATA_IN_PHASE:
case SII_DATA_OUT_PHASE:
if (state->cmdlen > 0) {
printf("%s: device %d: cmd %x: command data not all sent (%d) 1\n",
sc->sc_dev.dv_xname, sc->sc_target,
sc->sc_cmd[sc->sc_target]->cmd[0],
state->cmdlen);
state->cmdlen = 0;
#ifdef DEBUG
sii_DumpLog();
#endif
}
if (state->dmaPrevPhase >= 0) {
/* restart DMA after disconnect/reconnect */
if (state->dmaPrevPhase !=
(dstat & SII_PHASE_MSK)) {
printf("%s: device %d: dma reselect phase doesn't match\n",
sc->sc_dev.dv_xname, sc->sc_target);
goto abort;
}
state->dmaCurPhase = state->dmaPrevPhase;
state->dmaPrevPhase = -1;
regs->dmaddrl = state->dmaAddrL;
regs->dmaddrh = state->dmaAddrH;
regs->dmlotc = state->dmaCnt;
if (state->dmaCnt & 1)
regs->dmabyte = state->dmaByte;
regs->comm = SII_DMA | SII_INXFER |
(comm & SII_STATE_MSK) |
state->dmaCurPhase;
MachEmptyWriteBuffer();
#ifdef DEBUG
if (sii_debug > 4)
printf("Data %d dcnt %d dadr %x ",
state->dmaDataPhase,
state->dmaCnt,
(state->dmaAddrH << 16) |
state->dmaAddrL);
#endif
break;
}
if (state->dmaDataPhase != (dstat & SII_PHASE_MSK)) {
printf("%s: device %d: cmd %x: dma phase doesn't match\n",
sc->sc_dev.dv_xname, sc->sc_target,
sc->sc_cmd[sc->sc_target]->cmd[0]);
goto abort;
}
#ifdef DEBUG
if (sii_debug > 4) {
printf("Data %d ", state->dmaDataPhase);
if (sii_debug > 5)
printf("\n");
}
#endif
i = state->buflen;
if (i == 0) {
printf("%s: device %d: data count exceeded\n",
sc->sc_dev.dv_xname, sc->sc_target);
goto abort;
}
if (i > SII_MAX_DMA_XFER_LENGTH)
i = SII_MAX_DMA_XFER_LENGTH;
if ((dstat & SII_PHASE_MSK) == SII_DATA_IN_PHASE) {
sii_StartDMA(regs,
state->dmaCurPhase = SII_DATA_IN_PHASE,
state->dmaAddr[state->dmaBufIndex],
state->dmalen = i);
break;
}
/* start first chunk */
if (state->flags & FIRST_DMA) {
state->flags &= ~FIRST_DMA;
CopyToBuffer((u_short *)state->buf,
(volatile u_short *)
state->dmaAddr[state->dmaBufIndex], i);
}
sii_StartDMA(regs,
state->dmaCurPhase = SII_DATA_OUT_PHASE,
state->dmaAddr[state->dmaBufIndex],
state->dmalen = i);
i = state->buflen - SII_MAX_DMA_XFER_LENGTH;
if (i > 0) {
/* prepare for next chunk */
if (i > SII_MAX_DMA_XFER_LENGTH)
i = SII_MAX_DMA_XFER_LENGTH;
CopyToBuffer((u_short *)(state->buf +
SII_MAX_DMA_XFER_LENGTH),
(volatile u_short *)
state->dmaAddr[!state->dmaBufIndex], i);
}
break;
case SII_STATUS_PHASE:
if (state->cmdlen > 0) {
printf("%s: device %d: cmd %x: command data not all sent (%d) 2\n",
sc->sc_dev.dv_xname, sc->sc_target,
sc->sc_cmd[sc->sc_target]->cmd[0],
state->cmdlen);
state->cmdlen = 0;
#ifdef DEBUG
sii_DumpLog();
#endif
}
/* read amount transfered if DMA didn't finish */
if (state->dmalen > 0) {
i = state->dmalen - regs->dmlotc;
state->dmalen = 0;
state->dmaCurPhase = -1;
regs->dmlotc = 0;
regs->comm = comm &
(SII_STATE_MSK | SII_PHASE_MSK);
MachEmptyWriteBuffer();
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
#ifdef DEBUG
if (sii_debug > 4)
printf("DMA amt %d ", i);
#endif
switch (comm & SII_PHASE_MSK) {
case SII_DATA_IN_PHASE:
/* copy in the data */
CopyFromBuffer((volatile u_short *)
state->dmaAddr[state->dmaBufIndex],
state->buf, i);
case SII_CMD_PHASE:
case SII_DATA_OUT_PHASE:
state->buflen -= i;
}
}
/* read a one byte status message */
state->statusByte = msg =
sii_GetByte(regs, SII_STATUS_PHASE, 1);
if (msg < 0) {
dstat = regs->dstat;
goto again;
}
#ifdef DEBUG
if (sii_debug > 4)
printf("Status %x ", msg);
if (sii_logp > sii_log)
sii_logp[-1].msg = msg;
else
sii_log[NLOG - 1].msg = msg;
#endif
/* do a quick wait for COMMAND_COMPLETE */
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & (SII_CI | SII_DI), SII_WAIT_COUNT, i);
if (dstat & (SII_CI | SII_DI)) {
#ifdef DEBUG
if (sii_debug > 4)
printf("cnt2 %d\n", i);
#endif
goto again;
}
break;
case SII_MSG_IN_PHASE:
/*
* Save DMA state if DMA didn't finish.
* Be careful not to save state again after reconnect
* and see RESTORE_POINTER message.
* Note that the SII DMA address is not incremented
* as DMA proceeds.
*/
if (state->dmaCurPhase > 0) {
/* save dma registers */
state->dmaPrevPhase = state->dmaCurPhase;
state->dmaCurPhase = -1;
state->dmaCnt = i = regs->dmlotc;
if (dstat & SII_OBB)
state->dmaByte = regs->dmabyte;
if (i == 0)
i = SII_MAX_DMA_XFER_LENGTH;
i = state->dmalen - i;
/* note: no carry from dmaddrl to dmaddrh */
state->dmaAddrL = regs->dmaddrl + i;
state->dmaAddrH = regs->dmaddrh;
regs->comm = comm &
(SII_STATE_MSK | SII_PHASE_MSK);
MachEmptyWriteBuffer();
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
#ifdef DEBUG
if (sii_debug > 4) {
printf("SavP dcnt %d dadr %x ",
state->dmaCnt,
(state->dmaAddrH << 16) |
state->dmaAddrL);
if (((dstat & SII_OBB) != 0) ^
(state->dmaCnt & 1))
printf("OBB??? ");
} else if (sii_debug > 0) {
if (((dstat & SII_OBB) != 0) ^
(state->dmaCnt & 1)) {
printf("sii_DoIntr: OBB??? ds %x cnt %d\n",
dstat, state->dmaCnt);
sii_DumpLog();
}
}
#endif
}
/* read a one byte message */
msg = sii_GetByte(regs, SII_MSG_IN_PHASE, 0);
if (msg < 0) {
dstat = regs->dstat;
goto again;
}
#ifdef DEBUG
if (sii_debug > 4)
printf("MsgIn %x ", msg);
if (sii_logp > sii_log)
sii_logp[-1].msg = msg;
else
sii_log[NLOG - 1].msg = msg;
#endif
/* process message */
switch (msg) {
case SCSI_COMMAND_COMPLETE:
/* acknowledge last byte */
regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
(comm & SII_STATE_MSK);
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & SII_DNE, SII_WAIT_COUNT, i);
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
msg = sc->sc_target;
sc->sc_target = -1;
/*
* Wait a short time for disconnect.
* Don't be fooled if SII_BER happens first.
* Note: a reselect may happen here.
*/
SII_WAIT_UNTIL(cstat, regs->cstat,
cstat & (SII_RST | SII_SCH),
SII_WAIT_COUNT, i);
if ((cstat & (SII_RST | SII_SCH |
SII_STATE_MSK)) == SII_SCH) {
regs->cstat = SII_SCH | SII_BER;
regs->comm = 0;
MachEmptyWriteBuffer();
/*
* Double check that we didn't miss a
* state change between seeing it and
* clearing the SII_SCH bit.
*/
i = regs->cstat;
if (!(i & SII_SCH) &&
(i & SII_STATE_MSK) !=
(cstat & SII_STATE_MSK))
sii_StateChg(sc, i);
}
#ifdef DEBUG
if (sii_debug > 4)
printf("cs %x\n", cstat);
#endif
sii_CmdDone(sc, msg, 0);
break;
case SCSI_EXTENDED_MSG:
/* acknowledge last byte */
regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
(comm & SII_STATE_MSK);
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & SII_DNE, SII_WAIT_COUNT, i);
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
/* read the message length */
msg = sii_GetByte(regs, SII_MSG_IN_PHASE, 1);
if (msg < 0) {
dstat = regs->dstat;
goto again;
}
sii_buf[1] = msg; /* message length */
if (msg == 0)
msg = 256;
/*
* We read and acknowlege all the bytes
* except the last so we can assert ATN
* if needed before acknowledging the last.
*/
for (i = 0; i < msg; i++) {
dstat = sii_GetByte(regs,
SII_MSG_IN_PHASE, i < msg - 1);
if ((int)dstat < 0) {
dstat = regs->dstat;
goto again;
}
sii_buf[i + 2] = dstat;
}
switch (sii_buf[2]) {
case SCSI_MODIFY_DATA_PTR:
/* acknowledge last byte */
regs->comm = SII_INXFER |
SII_MSG_IN_PHASE |
(comm & SII_STATE_MSK);
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & SII_DNE,
SII_WAIT_COUNT, i);
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
i = (sii_buf[3] << 24) |
(sii_buf[4] << 16) |
(sii_buf[5] << 8) |
sii_buf[6];
if (state->dmaPrevPhase >= 0) {
state->dmaAddrL += i;
state->dmaCnt -= i;
}
break;
case SCSI_SYNCHRONOUS_XFER:
/*
* Acknowledge last byte and
* signal a request for MSG_OUT.
*/
regs->comm = SII_INXFER | SII_ATN |
SII_MSG_IN_PHASE |
(comm & SII_STATE_MSK);
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & SII_DNE,
SII_WAIT_COUNT, i);
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
sii_DoSync(regs, state);
break;
default:
reject:
/*
* Acknowledge last byte and
* signal a request for MSG_OUT.
*/
regs->comm = SII_INXFER | SII_ATN |
SII_MSG_IN_PHASE |
(comm & SII_STATE_MSK);
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & SII_DNE,
SII_WAIT_COUNT, i);
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
/* wait for MSG_OUT phase */
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & SII_TBE,
SII_WAIT_COUNT, i);
/* send a reject message */
regs->data = SCSI_MESSAGE_REJECT;
regs->comm = SII_INXFER |
(regs->cstat & SII_STATE_MSK) |
SII_MSG_OUT_PHASE;
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & SII_DNE,
SII_WAIT_COUNT, i);
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
}
break;
case SCSI_SAVE_DATA_POINTER:
case SCSI_RESTORE_POINTERS:
/* acknowledge last byte */
regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
(comm & SII_STATE_MSK);
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & SII_DNE, SII_WAIT_COUNT, i);
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
/* wait a short time for another msg */
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & (SII_CI | SII_DI),
SII_WAIT_COUNT, i);
if (dstat & (SII_CI | SII_DI)) {
#ifdef DEBUG
if (sii_debug > 4)
printf("cnt %d\n", i);
#endif
goto again;
}
break;
case SCSI_DISCONNECT:
/* acknowledge last byte */
regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
(comm & SII_STATE_MSK);
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & SII_DNE, SII_WAIT_COUNT, i);
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
state->prevComm = comm;
#ifdef DEBUG
if (sii_debug > 4)
printf("disconn %d ", sc->sc_target);
#endif
/*
* Wait a short time for disconnect.
* Don't be fooled if SII_BER happens first.
* Note: a reselect may happen here.
*/
SII_WAIT_UNTIL(cstat, regs->cstat,
cstat & (SII_RST | SII_SCH),
SII_WAIT_COUNT, i);
if ((cstat & (SII_RST | SII_SCH |
SII_STATE_MSK)) != SII_SCH) {
#ifdef DEBUG
if (sii_debug > 4)
printf("cnt %d\n", i);
#endif
dstat = regs->dstat;
goto again;
}
regs->cstat = SII_SCH | SII_BER;
regs->comm = 0;
MachEmptyWriteBuffer();
sc->sc_target = -1;
/*
* Double check that we didn't miss a state
* change between seeing it and clearing
* the SII_SCH bit.
*/
i = regs->cstat;
if (!(i & SII_SCH) && (i & SII_STATE_MSK) !=
(cstat & SII_STATE_MSK))
sii_StateChg(sc, i);
break;
case SCSI_MESSAGE_REJECT:
/* acknowledge last byte */
regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
(comm & SII_STATE_MSK);
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & SII_DNE, SII_WAIT_COUNT, i);
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
printf("%s: device %d: message reject.\n",
sc->sc_dev.dv_xname, sc->sc_target);
break;
default:
if (!(msg & SCSI_IDENTIFY)) {
printf("%s: device %d: couldn't handle message 0x%x... rejecting.\n",
sc->sc_dev.dv_xname, sc->sc_target,
msg);
#ifdef DEBUG
sii_DumpLog();
#endif
goto reject;
}
/* acknowledge last byte */
regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
(comm & SII_STATE_MSK);
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & SII_DNE, SII_WAIT_COUNT, i);
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
/* may want to check LUN some day */
/* wait a short time for another msg */
SII_WAIT_UNTIL(dstat, regs->dstat,
dstat & (SII_CI | SII_DI),
SII_WAIT_COUNT, i);
if (dstat & (SII_CI | SII_DI)) {
#ifdef DEBUG
if (sii_debug > 4)
printf("cnt %d\n", i);
#endif
goto again;
}
}
break;
case SII_MSG_OUT_PHASE:
#ifdef DEBUG
if (sii_debug > 4)
printf("MsgOut\n");
#endif
printf("MsgOut %x\n", state->flags); /* XXX */
/*
* Check for parity error.
* Hardware will automatically set ATN
* to request the device for a MSG_OUT phase.
*/
if (state->flags & PARITY_ERR) {
state->flags &= ~PARITY_ERR;
regs->data = SCSI_MESSAGE_PARITY_ERROR;
} else
regs->data = SCSI_NO_OP;
regs->comm = SII_INXFER | (comm & SII_STATE_MSK) |
SII_MSG_OUT_PHASE;
MachEmptyWriteBuffer();
/* wait a short time for XFER complete */
SII_WAIT_UNTIL(dstat, regs->dstat, dstat & SII_DNE,
SII_WAIT_COUNT, i);
#ifdef DEBUG
if (sii_debug > 4)
printf("ds %x i %d\n", dstat, i);
#endif
/* just clear the DNE bit and check errors later */
if (dstat & SII_DNE) {
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
}
break;
default:
printf("%s: Couldn't handle phase %d... ignoring.\n",
sc->sc_dev.dv_xname, dstat & SII_PHASE_MSK);
}
}
#ifdef DEBUG
if (sii_debug > 3)
printf("\n");
#endif
/*
* Check to make sure we won't be interrupted again.
* Deglitch dstat register.
*/
msg = regs->dstat;
while (msg != (dstat = regs->dstat))
msg = dstat;
if (dstat & (SII_CI | SII_DI))
goto again;
if (sc->sc_target < 0) {
/* look for another device that is ready */
for (i = 0; i < SII_NCMD; i++) {
/* don't restart a disconnected command */
if (!sc->sc_cmd[i] || sc->sc_st[i].prevComm)
continue;
sii_StartCmd(sc, i);
break;
}
}
return;
abort:
/* jump here to abort the current command */
printf("%s: device %d: current command terminated\n",
sc->sc_dev.dv_xname, sc->sc_target);
#ifdef DEBUG
sii_DumpLog();
#endif
if ((cstat = regs->cstat) & SII_CON) {
/* try to send an abort msg for awhile */
regs->dstat = SII_DNE;
regs->data = SCSI_ABORT;
regs->comm = SII_INXFER | SII_ATN | (cstat & SII_STATE_MSK) |
SII_MSG_OUT_PHASE;
MachEmptyWriteBuffer();
SII_WAIT_UNTIL(dstat, regs->dstat,
(dstat & (SII_DNE | SII_PHASE_MSK)) ==
(SII_DNE | SII_MSG_OUT_PHASE),
2 * SII_WAIT_COUNT, i);
#ifdef DEBUG
if (sii_debug > 0)
printf("Abort: cs %x ds %x i %d\n", cstat, dstat, i);
#endif
if (dstat & (SII_DNE | SII_PHASE_MSK) ==
(SII_DNE | SII_MSG_OUT_PHASE)) {
/* disconnect if command in progress */
regs->comm = SII_DISCON;
MachEmptyWriteBuffer();
SII_WAIT_UNTIL(cstat, regs->cstat,
!(cstat & SII_CON), SII_WAIT_COUNT, i);
}
} else {
#ifdef DEBUG
if (sii_debug > 0)
printf("Abort: cs %x\n", cstat);
#endif
}
regs->cstat = 0xffff;
regs->dstat = 0xffff;
regs->comm = 0;
MachEmptyWriteBuffer();
i = sc->sc_target;
sc->sc_target = -1;
sii_CmdDone(sc, i, EIO);
#ifdef DEBUG
if (sii_debug > 4)
printf("sii_DoIntr: after CmdDone target %d\n", sc->sc_target);
#endif
}
static void
sii_StateChg(sc, cstat)
register struct siisoftc *sc;
register u_int cstat;
{
register SIIRegs *regs = sc->sc_regs;
register State *state;
register int i;
#ifdef DEBUG
if (sii_debug > 4)
printf("SCH: ");
#endif
switch (cstat & SII_STATE_MSK) {
case 0:
/* disconnect */
i = sc->sc_target;
sc->sc_target = -1;
#ifdef DEBUG
if (sii_debug > 4)
printf("disconn %d ", i);
#endif
if (i >= 0 && !sc->sc_st[i].prevComm) {
printf("%s: device %d: spurrious disconnect (%d)\n",
sc->sc_dev.dv_xname, i, regs->slcsr);
sc->sc_st[i].prevComm = 0;
}
break;
case SII_CON:
/* connected as initiator */
i = regs->slcsr;
if (sc->sc_target == i)
break;
printf("%s: device %d: connect to device %d??\n",
sc->sc_dev.dv_xname, sc->sc_target, i);
sc->sc_target = i;
break;
case SII_DST:
/*
* Wait for CON to become valid,
* chip is slow sometimes.
*/
SII_WAIT_UNTIL(cstat, regs->cstat,
cstat & SII_CON, SII_WAIT_COUNT, i);
if (!(cstat & SII_CON))
panic("sii resel");
/* FALLTHROUGH */
case SII_CON | SII_DST:
/*
* Its a reselection. Save the ID and wait for
* interrupts to tell us what to do next
* (should be MSG_IN of IDENTIFY).
* NOTE: sc_target may be >= 0 if we were in
* the process of trying to start a command
* and were reselected before the select
* command finished.
*/
sc->sc_target = i = regs->destat;
state = &sc->sc_st[i];
regs->comm = SII_CON | SII_DST | SII_MSG_IN_PHASE;
regs->dmctrl = state->dmaReqAck;
MachEmptyWriteBuffer();
if (!state->prevComm) {
printf("%s: device %d: spurious reselection\n",
sc->sc_dev.dv_xname, i);
break;
}
state->prevComm = 0;
#ifdef DEBUG
if (sii_debug > 4)
printf("resel %d ", sc->sc_target);
#endif
break;
#ifdef notyet
case SII_DST | SII_TGT:
case SII_CON | SII_DST | SII_TGT:
/* connected as target */
printf("%s: Selected by device %d as target!!\n",
sc->sc_dev.dv_xname, regs->destat);
regs->comm = SII_DISCON;
MachEmptyWriteBuffer();
SII_WAIT_UNTIL(!(regs->cstat & SII_CON),
SII_WAIT_COUNT, i);
regs->cstat = 0xffff;
regs->dstat = 0xffff;
regs->comm = 0;
break;
#endif
default:
printf("%s: Unknown state change (cs %x)!!\n",
sc->sc_dev.dv_xname, cstat);
#ifdef DEBUG
sii_DumpLog();
#endif
}
}
/*
* Read one byte of data.
* If 'ack' is true, acknowledge the byte.
*/
static int
sii_GetByte(regs, phase, ack)
register SIIRegs *regs;
int phase, ack;
{
register u_int dstat;
register u_int state;
register int i;
register int data;
dstat = regs->dstat;
state = regs->cstat & SII_STATE_MSK;
if (!(dstat & SII_IBF) || (dstat & SII_MIS)) {
regs->comm = state | phase;
MachEmptyWriteBuffer();
/* wait a short time for IBF */
SII_WAIT_UNTIL(dstat, regs->dstat, dstat & SII_IBF,
SII_WAIT_COUNT, i);
#ifdef DEBUG
if (!(dstat & SII_IBF))
printf("status no IBF\n");
#endif
}
if (dstat & SII_DNE) { /* XXX */
printf("sii_GetByte: DNE set 5\n");
#ifdef DEBUG
sii_DumpLog();
#endif
regs->dstat = SII_DNE;
}
data = regs->data;
/* check for parity error */
if (dstat & SII_IPE) {
#ifdef DEBUG
if (sii_debug > 4)
printf("cnt0 %d\n", i);
#endif
printf("sii_GetByte: data %x ?? ds %x cm %x i %d\n",
data, dstat, regs->comm, i); /* XXX */
data = -1;
ack = 1;
}
if (ack) {
regs->comm = SII_INXFER | state | phase;
MachEmptyWriteBuffer();
/* wait a short time for XFER complete */
SII_WAIT_UNTIL(dstat, regs->dstat, dstat & SII_DNE,
SII_WAIT_COUNT, i);
/* clear the DNE */
if (dstat & SII_DNE) {
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
}
}
return (data);
}
/*
* Exchange messages to initiate synchronous data transfers.
*/
static void
sii_DoSync(regs, state)
register SIIRegs *regs;
register State *state;
{
register u_int dstat, comm;
register int i, j;
u_int len;
#ifdef DEBUG
if (sii_debug)
printf("sii_DoSync: len %d per %d req/ack %d\n",
sii_buf[1], sii_buf[3], sii_buf[4]);
#endif
/* SII chip can only handle a minimum transfer period of ??? */
if (sii_buf[3] < 64)
sii_buf[3] = 64;
/* SII chip can only handle a maximum REQ/ACK offset of 3 */
len = sii_buf[4];
if (len > 3)
len = 3;
sii_buf[0] = SCSI_EXTENDED_MSG;
sii_buf[1] = 3; /* message length */
sii_buf[2] = SCSI_SYNCHRONOUS_XFER;
sii_buf[4] = len;
#if 1
comm = SII_INXFER | SII_ATN | SII_MSG_OUT_PHASE |
(regs->cstat & SII_STATE_MSK);
regs->comm = comm & ~SII_INXFER;
for (j = 0; j < 5; j++) {
/* wait for target to request the next byte */
SII_WAIT_UNTIL(dstat, regs->dstat, dstat & SII_TBE,
SII_WAIT_COUNT, i);
if (!(dstat & SII_TBE) ||
(dstat & SII_PHASE_MSK) != SII_MSG_OUT_PHASE) {
printf("sii_DoSync: TBE? ds %x cm %x i %d\n",
dstat, comm, i); /* XXX */
return;
}
/* the last message byte should have ATN off */
if (j == 4)
comm &= ~SII_ATN;
regs->data = sii_buf[j];
regs->comm = comm;
MachEmptyWriteBuffer();
/* wait a short time for XFER complete */
SII_WAIT_UNTIL(dstat, regs->dstat, dstat & SII_DNE,
SII_WAIT_COUNT, i);
if (!(dstat & SII_DNE)) {
printf("sii_DoSync: DNE? ds %x cm %x i %d\n",
dstat, comm, i); /* XXX */
return;
}
/* clear the DNE, other errors handled later */
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
}
#else
CopyToBuffer((u_short *)sii_buf, (volatile u_short *)SII_BUF_ADDR, 5);
printf("sii_DoSync: %x %x %x ds %x\n",
((volatile u_short *)SII_BUF_ADDR)[0],
((volatile u_short *)SII_BUF_ADDR)[2],
((volatile u_short *)SII_BUF_ADDR)[4],
regs->dstat); /* XXX */
regs->dmaddrl = (u_short)(SII_BUF_ADDR >> 1);
regs->dmaddrh = (u_short)(SII_BUF_ADDR >> 17) & 03;
regs->dmlotc = 5;
regs->comm = SII_DMA | SII_INXFER | SII_ATN |
(regs->cstat & SII_STATE_MSK) | SII_MSG_OUT_PHASE;
MachEmptyWriteBuffer();
/* wait a short time for XFER complete */
SII_WAIT_UNTIL(dstat, regs->dstat,
(dstat & (SII_DNE | SII_TCZ)) == (SII_DNE | SII_TCZ),
SII_WAIT_COUNT, i);
if ((dstat & (SII_DNE | SII_TCZ)) != (SII_DNE | SII_TCZ)) {
printf("sii_DoSync: ds %x cm %x i %d lotc %d\n",
dstat, regs->comm, i, regs->dmlotc); /* XXX */
sii_DumpLog(); /* XXX */
return;
}
/* clear the DNE, other errors handled later */
regs->dstat = SII_DNE;
MachEmptyWriteBuffer();
#endif
#if 0
SII_WAIT_UNTIL(dstat, regs->dstat, dstat & (SII_CI | SII_DI),
SII_WAIT_COUNT, i);
printf("sii_DoSync: ds %x cm %x i %d lotc %d\n",
dstat, regs->comm, i, regs->dmlotc); /* XXX */
#endif
state->dmaReqAck = len;
}
/*
* Issue the sequence of commands to the controller to start DMA.
* NOTE: the data buffer should be word-aligned for DMA out.
*/
static void
sii_StartDMA(regs, phase, dmaAddr, size)
register SIIRegs *regs; /* which SII to use */
int phase; /* phase to send/receive data */
u_short *dmaAddr; /* DMA buffer address */
int size; /* # of bytes to transfer */
{
if (regs->dstat & SII_DNE) { /* XXX */
regs->dstat = SII_DNE;
printf("sii_StartDMA: DNE set\n");
#ifdef DEBUG
sii_DumpLog();
#endif
}
regs->dmaddrl = ((u_long)dmaAddr >> 1);
regs->dmaddrh = ((u_long)dmaAddr >> 17) & 03;
regs->dmlotc = size;
regs->comm = SII_DMA | SII_INXFER | (regs->cstat & SII_STATE_MSK) |
phase;
MachEmptyWriteBuffer();
#ifdef DEBUG
if (sii_debug > 5) {
printf("sii_StartDMA: cs 0x%x, ds 0x%x, cm 0x%x, size %d\n",
regs->cstat, regs->dstat, regs->comm, size);
}
#endif
}
/*
* Call the device driver's 'done' routine to let it know the command is done.
* The 'done' routine may try to start another command.
* To be fair, we should start pending commands for other devices
* before allowing the same device to start another command.
*/
static void
sii_CmdDone(sc, target, error)
register struct siisoftc *sc; /* which SII to use */
int target; /* which device is done */
int error; /* error code if any errors */
{
register ScsiCmd *scsicmd;
register int i;
scsicmd = sc->sc_cmd[target];
#ifdef DIAGNOSTIC
if (target < 0 || !scsicmd)
panic("sii_CmdDone");
#endif
sc->sc_cmd[target] = (ScsiCmd *)0;
#ifdef DEBUG
if (sii_debug > 1) {
printf("sii_CmdDone: %s target %d cmd %x err %d resid %d\n",
scsicmd->sd->sd_driver->d_name, target,
scsicmd->cmd[0], error, sc->sc_st[target].buflen);
}
#endif
/* look for another device that is ready */
for (i = 0; i < SII_NCMD; i++) {
/* don't restart a disconnected command */
if (!sc->sc_cmd[i] || sc->sc_st[i].prevComm)
continue;
sii_StartCmd(sc, i);
break;
}
(*scsicmd->sd->sd_driver->d_done)(scsicmd->unit, error,
sc->sc_st[target].buflen, sc->sc_st[target].statusByte);
}
#ifdef DEBUG
sii_DumpLog()
{
register struct sii_log *lp;
printf("sii: cmd %x bn %d cnt %d\n", sii_debug_cmd, sii_debug_bn,
sii_debug_sz);
lp = sii_logp;
do {
printf("target %d cs %x ds %x cm %x msg %x rlen %x dlen %x\n",
lp->target, lp->cstat, lp->dstat, lp->comm, lp->msg,
lp->rlen, lp->dlen);
if (++lp >= &sii_log[NLOG])
lp = sii_log;
} while (lp != sii_logp);
}
#endif
#endif
|