1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
|
/* $OpenBSD: wdc_obio.c,v 1.3 2000/03/20 07:26:51 rahnds Exp $ */
/* $NetBSD: wdc_obio.c,v 1.4 1999/06/14 08:53:06 tsubai Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum and by Onno van der Linden.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <vm/vm.h>
#include <machine/bus.h>
#include <machine/autoconf.h>
#include <dev/ata/atavar.h>
#include <dev/ic/wdcvar.h>
#include <powerpc/mac/dbdma.h>
#define WDC_REG_NPORTS 8
#define WDC_AUXREG_OFFSET 0x16
#define WDC_DEFAULT_PIO_IRQ 13 /* XXX */
#define WDC_DEFAULT_DMA_IRQ 2 /* XXX */
#define WDC_OPTIONS_DMA 0x01
/*
* XXX This code currently doesn't even try to allow 32-bit data port use.
*/
struct wdc_obio_softc {
struct wdc_softc sc_wdcdev;
struct channel_softc *wdc_chanptr;
struct channel_softc wdc_channel;
dbdma_regmap_t *sc_dmareg;
dbdma_command_t *sc_dmacmd;
};
u_int8_t wdc_obio_read_reg __P((struct channel_softc *, enum wdc_regs));
void wdc_obio_write_reg __P((struct channel_softc *, enum wdc_regs, u_int8_t));
void wdc_default_read_raw_multi_2 __P((struct channel_softc *,
void *, unsigned int));
void wdc_default_write_raw_multi_2 __P((struct channel_softc *,
void *, unsigned int));
void wdc_default_read_raw_multi_4 __P((struct channel_softc *,
void *, unsigned int));
void wdc_default_write_raw_multi_4 __P((struct channel_softc *,
void *, unsigned int));
struct channel_softc_vtbl wdc_obio_vtbl = {
wdc_obio_read_reg,
wdc_obio_write_reg,
wdc_default_read_raw_multi_2,
wdc_default_write_raw_multi_2,
wdc_default_read_raw_multi_4,
wdc_default_write_raw_multi_4
};
int wdc_obio_probe __P((struct device *, void *, void *));
void wdc_obio_attach __P((struct device *, struct device *, void *));
struct cfattach wdc_obio_ca = {
sizeof(struct wdc_obio_softc), wdc_obio_probe, wdc_obio_attach
};
#if 0
struct cfdriver wdc_cd = {
NULL, "wdc", DV_DULL
};
#endif
static int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int));
static void wdc_obio_dma_start __P((void *, int, int, int));
static int wdc_obio_dma_finish __P((void *, int, int, int));
int
wdc_obio_probe(parent, match, aux)
struct device *parent;
void *match;
void *aux;
{
struct confargs *ca = aux;
char compat[32];
/* XXX should not use name */
if (strcmp(ca->ca_name, "ATA") == 0 ||
strncmp(ca->ca_name, "ata", 3) == 0 ||
strcmp(ca->ca_name, "ide") == 0)
return 1;
bzero(compat, sizeof(compat));
OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat));
if (strcmp(compat, "heathrow-ata") == 0 ||
strcmp(compat, "keylargo-ata") == 0)
return 1;
return 0;
}
void
wdc_obio_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct wdc_obio_softc *sc = (void *)self;
struct confargs *ca = aux;
struct channel_softc *chp = &sc->wdc_channel;
int intr;
int use_dma = 0;
bus_addr_t cmdbase;
bus_size_t cmdsize;
bus_addr_t ctlbase;
bus_size_t ctlsize;
if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & WDC_OPTIONS_DMA) {
if (ca->ca_nreg >= 16 || ca->ca_nintr == -1)
use_dma = 1; /* XXX Don't work yet. */
}
if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) {
intr = ca->ca_intr[0];
printf(" irq %d", intr);
} else if (ca->ca_nintr == -1) {
intr = WDC_DEFAULT_PIO_IRQ;
printf(" irq property not found; using %d", intr);
} else {
printf(": couldn't get irq property\n");
return;
}
if (use_dma)
printf(": DMA transfer");
printf("\n");
chp->cmd_iot = chp->ctl_iot = ca->ca_iot;
chp->_vtbl = &wdc_obio_vtbl;
cmdbase = ca->ca_reg[0];
cmdsize = ca->ca_reg[1];
if (bus_space_map(chp->cmd_iot, cmdbase, cmdsize, 0, &chp->cmd_ioh) ||
bus_space_subregion(chp->cmd_iot, chp->cmd_ioh,
/* WDC_AUXREG_OFFSET<<4 */ 0x160, 1, &chp->ctl_ioh))
{
printf("%s: couldn't map registers\n",
sc->sc_wdcdev.sc_dev.dv_xname);
return;
}
printf ("wdc_obio cmd_ioh %x ctl_ioh %x\n", chp->cmd_ioh, chp->ctl_ioh);
chp->data32iot = chp->cmd_iot;
chp->data32ioh = chp->cmd_ioh;
mac_intr_establish(parent, intr, IST_LEVEL, IPL_BIO, wdcintr, chp,
"wdc_obio");
if (use_dma) {
sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20);
sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2],
ca->ca_reg[3]);
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA;
}
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16;
sc->sc_wdcdev.PIO_cap = 0;
sc->wdc_chanptr = chp;
sc->sc_wdcdev.channels = &sc->wdc_chanptr;
sc->sc_wdcdev.nchannels = 1;
sc->sc_wdcdev.dma_arg = sc;
sc->sc_wdcdev.dma_init = wdc_obio_dma_init;
sc->sc_wdcdev.dma_start = wdc_obio_dma_start;
sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish;
chp->channel = 0;
chp->wdc = &sc->sc_wdcdev;
chp->ch_queue = malloc(sizeof(struct channel_queue),
M_DEVBUF, M_NOWAIT);
if (chp->ch_queue == NULL) {
printf("%s: can't allocate memory for command queue",
sc->sc_wdcdev.sc_dev.dv_xname);
return;
}
wdcattach(chp);
}
static int
wdc_obio_dma_init(v, channel, drive, databuf, datalen, read)
void *v;
void *databuf;
size_t datalen;
int read;
{
struct wdc_obio_softc *sc = v;
vaddr_t va = (vaddr_t)databuf;
dbdma_command_t *cmdp;
u_int cmd, offset;
cmdp = sc->sc_dmacmd;
cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE;
offset = va & PGOFSET;
/* if va is not page-aligned, setup the first page */
if (offset != 0) {
int rest = NBPG - offset; /* the rest of the page */
if (datalen > rest) { /* if continues to next page */
DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va),
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER,
DBDMA_BRANCH_NEVER);
datalen -= rest;
va += rest;
cmdp++;
}
}
/* now va is page-aligned */
while (datalen > NBPG) {
DBDMA_BUILD(cmdp, cmd, 0, NBPG, vtophys(va),
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
datalen -= NBPG;
va += NBPG;
cmdp++;
}
/* the last page (datalen <= NBPG here) */
cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST;
DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va),
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
cmdp++;
DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0,
DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
return 0;
}
static void
wdc_obio_dma_start(v, channel, drive, read)
void *v;
int channel, drive;
{
struct wdc_obio_softc *sc = v;
dbdma_start(sc->sc_dmareg, sc->sc_dmacmd);
}
static int
wdc_obio_dma_finish(v, channel, drive, read)
void *v;
int channel, drive;
int read;
{
struct wdc_obio_softc *sc = v;
dbdma_stop(sc->sc_dmareg);
return 0;
}
/* read register code
* this allows the registers to be spaced by 0x10, instead of 0x1.
* mac hardware (obio) requires this.
*/
u_int8_t
wdc_obio_read_reg(chp, reg)
struct channel_softc *chp;
enum wdc_regs reg;
{
#ifdef DIAGNOSTIC
if (reg & _WDC_WRONLY) {
printf ("wdc_obio_read_reg: reading from a write-only register %d\n", reg);
}
#endif
if (reg & _WDC_AUX)
return (bus_space_read_1(chp->ctl_iot, chp->ctl_ioh,
(reg & _WDC_REGMASK) << 4));
else
return (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
(reg & _WDC_REGMASK) << 4));
}
void
wdc_obio_write_reg(chp, reg, val)
struct channel_softc *chp;
enum wdc_regs reg;
u_int8_t val;
{
#ifdef DIAGNOSTIC
if (reg & _WDC_RDONLY) {
printf ("wdc_obio_write_reg: writing to a read-only register %d\n", reg);
}
#endif
if (reg & _WDC_AUX)
bus_space_write_1(chp->ctl_iot, chp->ctl_ioh,
(reg & _WDC_REGMASK) << 4, val);
else
bus_space_write_1(chp->cmd_iot, chp->cmd_ioh,
(reg & _WDC_REGMASK) << 4, val);
}
|