1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
|
/* $OpenBSD: iocreg.h,v 1.8 2009/11/10 15:50:10 jsing Exp $ */
/*
* Copyright (c) 2008 Joel Sing.
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*
* Register definitions for SGI IOC3 ASIC.
*/
#define IOC_NDEVS 6
#define IOCDEV_SERIAL_A 0
#define IOCDEV_SERIAL_B 1
#define IOCDEV_LPT 2
#define IOCDEV_KBC 3
#define IOCDEV_RTC 4
#define IOCDEV_EF 5
/* SuperIO registers */
#define IOC3_SIO_IR 0x0000001c /* SIO interrupt register */
#define IOC3_SIO_IES 0x00000020 /* SIO interrupt enable */
#define IOC3_SIO_IEC 0x00000024 /* SIO interrupt disable */
#define IOC3_SIO_CR 0x00000028 /* SIO control register */
#define IOC3_MCR 0x00000030 /* MicroLan control register */
/* GPIO registers */
#define IOC3_GPCR_S 0x00000034 /* GPIO control bit set */
#define IOC3_GPCR_C 0x00000038 /* GPIO control bit clear */
#define IOC3_GPDR 0x0000003c /* GPIO data */
#define IOC3_GPPR_BASE 0x00000040 /* 9 GPIO pin registers */
#define IOC3_GPPR(x) (IOC3_GPPR_BASE + (x) * 4)
/* Keyboard controller registers. */
#define IOC3_KBC_CTRL_STATUS 0x0000009c
#define IOC3_KBC_KBD_RX 0x000000a0
#define IOC3_KBC_AUX_RX 0x000000a4
#define IOC3_KBC_KBD_TX 0x000000a8
#define IOC3_KBC_AUX_TX 0x000000ac
/* Non-16550 mode UART registers */
#define IOC3_UARTA_SSCR 0x000000b8 /* control register */
#define IOC3_UARTA_STPIR 0x000000bc /* TX producer index register */
#define IOC3_UARTA_STCIR 0x000000c0 /* TX consumer index register */
#define IOC3_UARTA_SRPIR 0x000000c4 /* RX producer index register */
#define IOC3_UARTA_SRCIR 0x000000c8 /* RX consumer index register */
#define IOC3_UARTA_SRTR 0x000000cc /* receive timer register */
#define IOC3_UARTA_SHADOW 0x000000d0 /* 16550 shadow register */
#define IOC3_UARTB_SSCR 0x000000d4
#define IOC3_UARTB_STPIR 0x000000d8
#define IOC3_UARTB_STCIR 0x000000dc
#define IOC3_UARTB_SRPIR 0x000000e0
#define IOC3_UARTB_SRCIR 0x000000e4
#define IOC3_UARTB_SRTR 0x000000e8
#define IOC3_UARTB_SHADOW 0x000000ec
/* Ethernet registers */
#define IOC3_ENET_MCR 0x000000f0 /* Master Control Register */
#define IOC3_ENET_ISR 0x000000f4 /* Interrupt Status Register */
#define IOC3_ENET_IER 0x000000f8 /* Interrupt Enable Register */
#define IOC3_ENET_RCSR 0x000000fc /* RX Control and Status Reg. */
#define IOC3_ENET_RBR_H 0x00000100 /* RX Base Register */
#define IOC3_ENET_RBR_L 0x00000104
#define IOC3_ENET_RBAR 0x00000108 /* RX Barrier Register */
#define IOC3_ENET_RCIR 0x0000010c /* RX Consumer Index Register */
#define IOC3_ENET_RPIR 0x00000110 /* RX Producer Index Register */
#define IOC3_ENET_RTR 0x00000114 /* RX Timer Register */
#define IOC3_ENET_TCSR 0x00000118 /* TX Control and Status Reg. */
#define IOC3_ENET_RSR 0x0000011c /* Random Seed Register */
#define IOC3_ENET_TCDC 0x00000120 /* TX Collision Detect Counter */
#define IOC3_ENET_BIR 0x00000124
#define IOC3_ENET_TBR_H 0x00000128 /* TX Base Register */
#define IOC3_ENET_TBR_L 0x0000012c
#define IOC3_ENET_TCIR 0x00000130 /* TX Consumer Index Register */
#define IOC3_ENET_TPIR 0x00000134 /* TX Producer Index Register */
#define IOC3_ENET_MAR_H 0x00000138 /* MAC Address Register */
#define IOC3_ENET_MAR_L 0x0000013c
#define IOC3_ENET_HAR_H 0x00000140 /* Hash filter Address Reg. */
#define IOC3_ENET_HAR_L 0x00000144
#define IOC3_ENET_MICR 0x00000148 /* MII Control Register */
#define IOC3_ENET_MIDR_R 0x0000014c /* MII Data Register (read) */
#define IOC3_ENET_MIDR_W 0x00000150 /* MII Data Register (write) */
/* bits in the SIO interrupt register */
#define IOC3_IRQ_UARTA 0x00000040 /* UART A passthrough */
#define IOC3_IRQ_UARTB 0x00008000 /* UART B passthrough */
#define IOC3_IRQ_LPT 0x00040000 /* parallel port passthrough */
#define IOC3_IRQ_KBC 0x00400000 /* keyboard controller */
/* bits in GPCR */
#define IOC3_GPCR_UARTA_PIO 0x00000040 /* UARTA in PIO mode */
#define IOC3_GPCR_UARTB_PIO 0x00000080 /* UARTB in PIO mode */
#define IOC3_GPCR_MLAN 0x00200000 /* MicroLan enable */
/* bits in SSCR */
#define IOC3_SSCR_RESET 0x80000000
/* bits in KBC_CTRL_STATUS */
#define IOC3_KBC_STATUS_KBD_WRITE_PENDING 0x00000001
#define IOC3_KBC_STATUS_AUX_WRITE_PENDING 0x00000002
/* bits in KBC_*_RX */
#define IOC3_KBC_DATA_0_VALID 0x80000000
#define IOC3_KBC_DATA_1_VALID 0x40000000
#define IOC3_KBC_DATA_2_VALID 0x20000000
#define IOC3_KBC_DATA_VALID (IOC3_KBC_DATA_0_VALID | \
IOC3_KBC_DATA_1_VALID | \
IOC3_KBC_DATA_2_VALID)
#define IOC3_KBC_DATA_0_MASK 0x00ff0000
#define IOC3_KBC_DATA_0_SHIFT 16
#define IOC3_KBC_DATA_1_MASK 0x0000ff00
#define IOC3_KBC_DATA_1_SHIFT 8
#define IOC3_KBC_DATA_2_MASK 0x000000ff
#define IOC3_KBC_DATA_2_SHIFT 0
/* bits in ENET_MCR */
#define IOC3_ENET_MCR_DUPLEX 0x00000001
#define IOC3_ENET_MCR_PROMISC 0x00000002
#define IOC3_ENET_MCR_PADEN 0x00000004
#define IOC3_ENET_MCR_RXOFF_MASK 0x000001f8
#define IOC3_ENET_MCR_RXOFF_SHIFT 3
#define IOC3_ENET_MCR_PARITY_ENABLE 0x00000200
#define IOC3_ENET_MCR_LARGE_SSRAM 0x00001000
#define IOC3_ENET_MCR_TX_DMA 0x00002000
#define IOC3_ENET_MCR_TX 0x00004000
#define IOC3_ENET_MCR_RX_DMA 0x00008000
#define IOC3_ENET_MCR_RX 0x00010000
#define IOC3_ENET_MCR_LOOPBACK 0x00020000
#define IOC3_ENET_MCR_RESET 0x80000000
/* bits in the ENET interrupt register */
#define IOC3_ENET_ISR_RX_TIMER 0x00000001 /* RX periodic int */
#define IOC3_ENET_ISR_RX_THRESHOLD 0x00000002 /* RX q above threshold */
#define IOC3_ENET_ISR_RX_OFLOW 0x00000004 /* RX q overflow */
#define IOC3_ENET_ISR_RX_BUF_OFLOW 0x00000008 /* RX buffer overflow */
#define IOC3_ENET_ISR_RX_MEMORY 0x00000010 /* RX memory acc. err */
#define IOC3_ENET_ISR_RX_PARITY 0x00000020 /* RX parity error */
#define IOC3_ENET_ISR_TX_EMPTY 0x00010000 /* TX q empty */
#define IOC3_ENET_ISR_TX_RETRY 0x00020000
#define IOC3_ENET_ISR_TX_EXDEF 0x00040000
#define IOC3_ENET_ISR_TX_LCOLL 0x00080000 /* TX Late Collision */
#define IOC3_ENET_ISR_TX_GIANT 0x00100000
#define IOC3_ENET_ISR_TX_BUF_UFLOW 0x00200000 /* TX buf underflow */
#define IOC3_ENET_ISR_TX_EXPLICIT 0x00400000 /* TX int requested */
#define IOC3_ENET_ISR_TX_COLL_WRAP 0x00800000
#define IOC3_ENET_ISR_TX_DEFER_WRAP 0x01000000
#define IOC3_ENET_ISR_TX_MEMORY 0x02000000 /* TX memory acc. err */
#define IOC3_ENET_ISR_TX_PARITY 0x04000000 /* TX parity error */
#define IOC3_ENET_ISR_TX_ALL 0x07ff0000 /* all TX bits */
/* bits in ENET_RCSR */
#define IOC3_ENET_RCSR_THRESHOLD_MASK 0x000001ff
/* bits in ENET_RPIR */
#define IOC3_ENET_PIR_SET 0x80000000 /* set new value */
/* bits in ENET_TCSR */
#define IOC3_ENET_TCSR_IPGT_MASK 0x0000007f /* interpacket gap */
#define IOC3_ENET_TCSR_IPGT_SHIFT 0
#define IOC3_ENET_TCSR_IPGR1_MASK 0x00007f00
#define IOC3_ENET_TCSR_IPGR1_SHIFT 8
#define IOC3_ENET_TCSR_IPGR2_MASK 0x007f0000
#define IOC3_ENET_TCSR_IPGR2_SHIFT 16
#define IOC3_ENET_TCSR_NOTXCLOCK 0x80000000
#define IOC3_ENET_TCSR_FULL_DUPLEX \
((17 << IOC3_ENET_TCSR_IPGR2_SHIFT) | \
(11 << IOC3_ENET_TCSR_IPGR1_SHIFT) | \
(21 << IOC3_ENET_TCSR_IPGT_SHIFT))
#define IOC3_ENET_TCSR_HALF_DUPLEX \
((21 << IOC3_ENET_TCSR_IPGR2_SHIFT) | \
(21 << IOC3_ENET_TCSR_IPGR1_SHIFT) | \
(21 << IOC3_ENET_TCSR_IPGT_SHIFT))
/* bits in ENET_TCDC */
#define IOC3_ENET_TCDC_COLLISION_MASK 0x0000ffff
#define IOC3_ENET_TCDC_DEFER_MASK 0xffff0000
#define IOC3_ENET_TCDC_DEFER_SHIFT 16
/* bits in ENET_TCIR */
#define IOC3_ENET_TCIR_IDLE 0x80000000
/* bits in ENET_MICR */
#define IOC3_ENET_MICR_REG_MASK 0x0000001f
#define IOC3_ENET_MICR_PHY_MASK 0x000003e0
#define IOC3_ENET_MICR_PHY_SHIFT 5
#define IOC3_ENET_MICR_READ 0x00000400
#define IOC3_ENET_MICR_WRITE 0x00000000
#define IOC3_ENET_MICR_BUSY 0x00000800
#define IOC3_ENET_MIDR_MASK 0x0000ffff
/*
* Offsets and sizes for subdevices handled by mi drivers.
*/
#define IOC3_UARTA_BASE 0x00020178
#define IOC3_UARTB_BASE 0x00020170
/*
* Ethernet SSRAM.
*/
#define IOC3_SSRAM_BASE 0x00040000
#define IOC3_SSRAM_SMALL_SIZE 0x00020000
#define IOC3_SSRAM_LARGE_SIZE 0x00040000
#define IOC3_SSRAM_PARITY_BIT 0x00010000
#define IOC3_SSRAM_DATA_MASK 0x0000ffff
/*
* Offsets of devices connected to the four IOC3 `bytebus'.
*/
#define IOC3_BYTEBUS_0 0x00080000
#define IOC3_BYTEBUS_1 0x000a0000
#define IOC3_BYTEBUS_2 0x000c0000
#define IOC3_BYTEBUS_3 0x000e0000
|
