1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
|
/* $OpenBSD: psl.h,v 1.23 2007/05/16 19:37:06 thib Exp $ */
/* $NetBSD: psl.h,v 1.12 1997/03/10 21:49:11 pk Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)psl.h 8.1 (Berkeley) 6/11/93
*/
#ifndef PSR_IMPL
/*
* SPARC Process Status Register (in psl.h for hysterical raisins).
*
* The picture in the Sun manuals looks like this:
* 1 1
* 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0
* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
* | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP |
* | | |n z v c| |C|F| | |S|T| |
* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
*/
#define PSR_IMPL 0xf0000000 /* implementation */
#define PSR_VER 0x0f000000 /* version */
#define PSR_ICC 0x00f00000 /* integer condition codes */
#define PSR_N 0x00800000 /* negative */
#define PSR_Z 0x00400000 /* zero */
#define PSR_O 0x00200000 /* overflow */
#define PSR_C 0x00100000 /* carry */
#define PSR_EC 0x00002000 /* coprocessor enable */
#define PSR_EF 0x00001000 /* FP enable */
#define PSR_PIL 0x00000f00 /* interrupt level */
#define PSR_S 0x00000080 /* supervisor (kernel) mode */
#define PSR_PS 0x00000040 /* previous supervisor mode (traps) */
#define PSR_ET 0x00000020 /* trap enable */
#define PSR_CWP 0x0000001f /* current window pointer */
#define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET"
/*
* Various interrupt levels.
*/
#define IPL_NONE 0
#define IPL_SOFTINT 1
#define IPL_SOFTCLOCK IPL_SOFTINT /* softclock() interrupts */
#define IPL_SOFTNET IPL_SOFTINT /* soft network interrupts */
#define IPL_AUSOFT 4 /* audio soft interrupts */
#define IPL_FDSOFT 4 /* floppy soft interrupts */
#define IPL_BIO 5 /* block devices are at 5 and below */
#define IPL_TTY 6 /* tty soft interrupts */
#define IPL_NET 7 /* network hardware at 7 or below */
#define IPL_VM 7 /* max(BIO, NET, TTY) */
#define IPL_FB 9 /* framebuffer interrupts */
#define IPL_CLOCK 10 /* hardclock() */
#define IPL_FD 11 /* hard floppy interrupts. */
#define IPL_ZS 12 /* zs interrupts */
/*
* XXX - this is called AUHARD instead of AUDIO because of some confusion
* with how MI audio code handles this. Stay tuned for a change in the future
*/
#define IPL_AUHARD 13 /* hard audio interrupts */
#define IPL_STATCLOCK 14 /* statclock() */
#define IPL_SCHED IPL_STATCLOCK
#define IPL_HIGH 15 /* splhigh() */
#if defined(_KERNEL) && !defined(_LOCORE)
static __inline int getpsr(void);
static __inline void setpsr(int);
static __inline int spl0(void);
static __inline int splhigh(void);
static __inline void splx(int);
static __inline int getmid(void);
/*
* GCC pseudo-functions for manipulating PSR (primarily PIL field).
*/
static __inline int
getpsr()
{
int psr;
__asm __volatile("rd %%psr,%0" : "=r" (psr));
return (psr);
}
static __inline int
getmid()
{
int mid;
__asm __volatile("rd %%tbr,%0" : "=r" (mid));
return ((mid >> 20) & 0x3);
}
static __inline void
setpsr(newpsr)
int newpsr;
{
__asm __volatile("wr %0,0,%%psr" : : "r" (newpsr));
__asm __volatile("nop");
__asm __volatile("nop");
__asm __volatile("nop");
}
static __inline int
spl0()
{
int psr, oldipl;
/*
* wrpsr xors two values: we choose old psr and old ipl here,
* which gives us the same value as the old psr but with all
* the old PIL bits turned off.
*/
__asm __volatile("rd %%psr,%0" : "=r" (psr));
oldipl = psr & PSR_PIL;
__asm __volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl));
/*
* Three instructions must execute before we can depend
* on the bits to be changed.
*/
__asm __volatile("nop; nop; nop");
return (oldipl);
}
#ifdef DIAGNOSTIC
/*
* Although this function is implemented in MI code, it must be in this MD
* header because we don't want this header to include MI includes.
*/
void splassert_fail(int, int, const char *);
extern int splassert_ctl;
void splassert_check(int, const char *);
#define splassert(__wantipl) do { \
if (splassert_ctl > 0) { \
splassert_check(__wantipl, __func__); \
} \
} while (0)
#else
#define splassert(wantipl) do { /* nada */ } while (0)
#endif
/*
* PIL 1 through 14 can use this macro.
* (spl0 and splhigh are special since they put all 0s or all 1s
* into the ipl field.)
*/
#define SPL(name, newipl) \
static __inline int name(void); \
static __inline int name() \
{ \
int psr, oldipl; \
__asm __volatile("rd %%psr,%0" : "=r" (psr)); \
oldipl = psr & PSR_PIL; \
psr &= ~oldipl; \
__asm __volatile("wr %0,%1,%%psr" : : \
"r" (psr), "n" ((newipl) << 8)); \
__asm __volatile("nop; nop; nop"); \
__asm __volatile("":::"memory"); /* protect from reordering */ \
return (oldipl); \
}
/* A non-priority-decreasing version of SPL */
#define SPLHOLD(name, newipl) \
static __inline int name(void); \
static __inline int name() \
{ \
int psr, oldipl; \
__asm __volatile("rd %%psr,%0" : "=r" (psr)); \
oldipl = psr & PSR_PIL; \
if ((newipl << 8) <= oldipl) \
return oldipl; \
psr &= ~oldipl; \
__asm __volatile("wr %0,%1,%%psr" : : \
"r" (psr), "n" ((newipl) << 8)); \
__asm __volatile("nop; nop; nop"); \
__asm __volatile("":::"memory"); /* protect from reordering */ \
return (oldipl); \
}
SPLHOLD(splsoftint, IPL_SOFTINT)
#define splsoftclock splsoftint
#define splsoftnet splsoftint
SPLHOLD(splausoft, IPL_AUSOFT)
SPLHOLD(splfdsoft, IPL_FDSOFT)
SPLHOLD(splbio, IPL_BIO)
SPLHOLD(splnet, IPL_NET)
SPLHOLD(spltty, IPL_TTY)
SPLHOLD(splvm, IPL_VM)
SPLHOLD(splclock, IPL_CLOCK)
SPLHOLD(splfd, IPL_FD)
SPLHOLD(splzs, IPL_ZS)
SPLHOLD(splaudio, IPL_AUHARD)
SPLHOLD(splsched, IPL_SCHED)
SPLHOLD(splstatclock, IPL_STATCLOCK)
static __inline int splhigh()
{
int psr, oldipl;
__asm __volatile("rd %%psr,%0" : "=r" (psr));
__asm __volatile("wr %0,0,%%psr" : : "r" (psr | PSR_PIL));
__asm __volatile("and %1,%2,%0; nop; nop" : "=r" (oldipl) : \
"r" (psr), "n" (PSR_PIL));
__asm __volatile("":::"memory"); /* protect from reordering */
return (oldipl);
}
/* splx does not have a return value */
static __inline void splx(newipl)
int newipl;
{
int psr;
__asm __volatile("":::"memory"); /* protect from reordering */
__asm __volatile("rd %%psr,%0" : "=r" (psr));
__asm __volatile("wr %0,%1,%%psr" : : \
"r" (psr & ~PSR_PIL), "rn" (newipl));
__asm __volatile("nop; nop; nop");
}
#endif /* KERNEL && !_LOCORE */
#endif /* PSR_IMPL */
|
