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/* $NetBSD: ncr.h,v 1.1 1996/07/20 18:55:15 ragge Exp $ */
/*
* Register map for the Sun3 SCSI Interface (si)
* The first part of this register map is an NCR5380
* SCSI Bus Interface Controller (SBIC). The rest is a
* DMA controller and custom logic in one of two flavors,
* one for the OBIO interface (3/50,3/60) and one for the
* VME interface (3/160,3/260,etc.), where some registers
* are implemented only on one or the other, some on both.
*/
/*
* Some of these registers apply to only one interface and some
* apply to both. The registers which apply to the Sun3/50 onboard
* version only are udc_rdata and udc_raddr. The registers which
* apply to the Sun3 vme version only are dma_addr, dma_count, bpr,
* iv_am, and bcrh. Thus, the sbc registers, fifo_data, bcr, and csr
* apply to both interfaces.
* One other feature of the vme interface: a write to the dma count
* register also causes a write to the fifo byte count register and
* vis versa.
*/
/*
* NCR5380 Register map (byte-registers at longword addresses)
*/
struct ncr5380regs {
volatile u_long sci_r0; /* 200C.0080: CUR_DATA/OUT_DATA (rw) */
volatile u_long sci_r1; /* 200C.0084: INI_CMD (rw) */
volatile u_long sci_r2; /* 200C.0088: MODE (rw) */
volatile u_long sci_r3; /* 200C.008C: TAR_CMD (rw) */
volatile u_long sci_r4; /* 200C.0090: CUR_STAT/SEL_ENA (rw) */
volatile u_long sci_r5; /* 200C.0094: STATUS/DMA_SEND (rw) */
volatile u_long sci_r6; /* 200C.0098: IN_DATA/DMA_TRCV (rw) */
volatile u_long sci_r7; /* 200C.009C: RESET/DMA_IRCV (rw) */
};
struct si_regs {
struct ncr5380regs sci;
};
/* possible values for the address modifier, sun3 vme version only */
#define VME_SUPV_DATA_24 0x3d00
/*
* Status Register.
* Note:
* (r) indicates bit is read only.
* (rw) indicates bit is read or write.
* (v) vme host adaptor interface only.
* (o) sun3/50 onboard host adaptor interface only.
* (b) both vme and sun3/50 host adaptor interfaces.
*/
#define SI_CSR_DMA_ACTIVE 0x8000 /* (r,o) dma transfer active */
#define SI_CSR_DMA_CONFLICT 0x4000 /* (r,b) reg accessed while dmaing */
#define SI_CSR_DMA_BUS_ERR 0x2000 /* (r,b) bus error during dma */
#define SI_CSR_ID 0x1000 /* (r,b) 0 for 3/50, 1 for SCSI-3, */
/* 0 if SCSI-3 unmodified */
#define SI_CSR_FIFO_FULL 0x0800 /* (r,b) fifo full */
#define SI_CSR_FIFO_EMPTY 0x0400 /* (r,b) fifo empty */
#define SI_CSR_SBC_IP 0x0200 /* (r,b) sbc interrupt pending */
#define SI_CSR_DMA_IP 0x0100 /* (r,b) dma interrupt pending */
#define SI_CSR_LOB 0x00c0 /* (r,v) number of leftover bytes */
#define SI_CSR_LOB_THREE 0x00c0 /* (r,v) three leftover bytes */
#define SI_CSR_LOB_TWO 0x0080 /* (r,v) two leftover bytes */
#define SI_CSR_LOB_ONE 0x0040 /* (r,v) one leftover byte */
#define SI_CSR_BPCON 0x0020 /* (rw,v) byte packing control */
/* dma is in 0=longwords, 1=words */
#define SI_CSR_DMA_EN 0x0010 /* (rw,v) dma/interrupt enable */
#define SI_CSR_SEND 0x0008 /* (rw,b) dma dir, 1=to device */
#define SI_CSR_INTR_EN 0x0004 /* (rw,b) interrupts enable */
#define SI_CSR_FIFO_RES 0x0002 /* (rw,b) inits fifo, 0=reset */
#define SI_CSR_SCSI_RES 0x0001 /* (rw,b) reset sbc and udc, 0=reset */
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