1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
|
/* $OpenBSD: ascreg.h,v 1.1 1997/02/06 16:02:42 pefo Exp $ */
/*-
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)ascreg.h 8.1 (Berkeley) 6/10/93
* $Id: ascreg.h,v 1.1 1997/02/06 16:02:42 pefo Exp $
*/
/*
* Mach Operating System
* Copyright (c) 1991,1990,1989 Carnegie Mellon University
* All Rights Reserved.
*
* Permission to use, copy, modify and distribute this software and its
* documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*
* HISTORY
* Log: scsi_53C94.h,v
* Revision 2.4 91/02/05 17:44:59 mrt
* Added author notices
* [91/02/04 11:18:32 mrt]
*
* Changed to use new Mach copyright
* [91/02/02 12:17:11 mrt]
*
* Revision 2.3 90/12/05 23:34:46 af
* Documented max DMA xfer size.
* [90/12/03 23:39:36 af]
*
* Revision 2.1.1.1 90/11/01 03:38:54 af
* Created, from the DEC specs:
* "PMAZ-AA TURBOchannel SCSI Module Functional Specification"
* Workstation Systems Engineering, Palo Alto, CA. Aug 27, 1990.
* And from the NCR data sheets
* "NCR 53C94, 53C95, 53C96 Advanced SCSI Controller"
* [90/09/03 af]
*/
/*
* File: scsi_53C94.h
* Author: Alessandro Forin, Carnegie Mellon University
* Date: 9/90
*
* Defines for the NCR 53C94 ASC (SCSI interface)
* Some gotcha came from the "86C01/53C94 DMA lab work" written
* by Ken Stewart (NCR MED Logic Products Applications Engineer)
* courtesy of NCR. Thanks Ken !
*/
#define ASC_OFFSET_53C94 0x0 /* from module base */
#define ASC_NCMD 7 /* Number of simultaneous cmds */
/*
* Synch xfer parameters, and timing conversions
*/
#define SCSI_MIN_PERIOD 50 /* in 4 nsecs units */
#define ASC_MIN_PERIOD40 8 /* in CLKS/BYTE, 1 CLK = 25nsecs */
#define ASC_MIN_PERIOD25 5 /* in CLKS/BYTE, 1 CLK = 40nsecs */
#define ASC_MIN_PERIOD20 4 /* in CLKS/BYTE, 1 CLK = 50nsecs */
#define ASC_MIN_PERIOD12 3 /* in CLKS/BYTE, 1 CLK = 80nsecs */
#define ASC_MAX_PERIOD40 56 /* in CLKS/BYTE, 1 CLK = 25nsecs */
#define ASC_MAX_PERIOD25 35 /* in CLKS/BYTE, 1 CLK = 40nsecs */
#define ASC_MAX_PERIOD20 28 /* in CLKS/BYTE, 1 CLK = 50nsecs */
#define ASC_MAX_PERIOD12 18 /* in CLKS/BYTE, 1 CLK = 80nsecs */
#define ASC_MAX_OFFSET 15 /* pure number */
/*
* Register map, padded as needed
*/
typedef volatile struct {
u_char asc_tc_lsb; /* 00 rw: Transfer Counter LSB */
u_char asc_tc_msb; /* 01 rw: Transfer Counter MSB */
u_char asc_fifo; /* 02 rw: FIFO top */
u_char asc_cmd; /* 03 rw: Command */
u_char asc_status; /* 04 r: Status */
#define asc_dbus_id asc_status /* 04 w: Destination Bus ID */
u_char asc_intr; /* 05 r: Interrupt */
#define asc_sel_timo asc_intr /* 05 w: (re)select timeout */
u_char asc_ss; /* 06 r: Sequence Step */
#define asc_syn_p asc_ss /* 06 w: synchronous period */
u_char asc_flags; /* 07 r: FIFO flags + seq step */
#define asc_syn_o asc_flags /* 07 w: synchronous offset */
u_char asc_cnfg1; /* 08 rw: Configuration 1 */
u_char asc_ccf; /* 09 w: Clock Conv. Factor */
u_char asc_test; /* 0a w: Test Mode */
u_char asc_cnfg2; /* 0b rw: Configuration 2 */
u_char asc_cnfg3; /* 0c rw: Configuration 3 */
u_char asc_res_fifo; /* 0d w: Reserve FIFO byte */
u_char asc_tc_xsb; /* 0e rw: Transfer Counter Xtended */
} asc_regmap_t;
/*
* Transfer Count: access macros
* That a NOP is required after loading the dma counter
* I learned on the NCR test code. Sic.
*/
#define ASC_TC_MAX 0x10000
#define ASC_TC_GET(ptr, val) \
val = (ptr)->asc_tc_lsb | ((ptr)->asc_tc_msb << 8) | ((ptr)->asc_tc_xsb << 16)
#define ASC_TC_PUT(ptr, val) \
(ptr)->asc_tc_lsb = (val); \
(ptr)->asc_tc_msb = (val) >> 8; \
(ptr)->asc_tc_xsb = (val) >> 16; \
(ptr)->asc_cmd = ASC_CMD_NOP | ASC_CMD_DMA;
/*
* Command register (command codes)
*/
#define ASC_CMD_DMA 0x80
/* Miscellaneous */
#define ASC_CMD_NOP 0x00
#define ASC_CMD_FLUSH 0x01
#define ASC_CMD_RESET 0x02
#define ASC_CMD_BUS_RESET 0x03
/* Initiator state */
#define ASC_CMD_XFER_INFO 0x10
#define ASC_CMD_I_COMPLETE 0x11
#define ASC_CMD_MSG_ACPT 0x12
#define ASC_CMD_XFER_PAD 0x18
#define ASC_CMD_SET_ATN 0x1a
#define ASC_CMD_CLR_ATN 0x1b
/* Target state */
#define ASC_CMD_SND_MSG 0x20
#define ASC_CMD_SND_STATUS 0x21
#define ASC_CMD_SND_DATA 0x22
#define ASC_CMD_DISC_SEQ 0x23
#define ASC_CMD_TERM 0x24
#define ASC_CMD_T_COMPLETE 0x25
#define ASC_CMD_DISC 0x27
#define ASC_CMD_RCV_MSG 0x28
#define ASC_CMD_RCV_CDB 0x29
#define ASC_CMD_RCV_DATA 0x2a
#define ASC_CMD_RCV_CMD 0x2b
#define ASC_CMD_ABRT_DMA 0x04
/* Disconnected state */
#define ASC_CMD_RESELECT 0x40
#define ASC_CMD_SEL 0x41
#define ASC_CMD_SEL_ATN 0x42
#define ASC_CMD_SEL_ATN_STOP 0x43
#define ASC_CMD_ENABLE_SEL 0x44
#define ASC_CMD_DISABLE_SEL 0x45
#define ASC_CMD_SEL_ATN3 0x46
/*
* Status register, and phase encoding
*/
#define ASC_CSR_INT 0x80
#define ASC_CSR_GE 0x40
#define ASC_CSR_PE 0x20
#define ASC_CSR_TC 0x10
#define ASC_CSR_VGC 0x08
#define ASC_CSR_MSG 0x04
#define ASC_CSR_CD 0x02
#define ASC_CSR_IO 0x01
#define ASC_PHASE(csr) ((csr) & 0x7)
#define ASC_PHASE_DATAO 0x0
#define ASC_PHASE_DATAI 0x1
#define ASC_PHASE_COMMAND 0x2
#define ASC_PHASE_STATUS 0x3
/* 4..5 ANSI reserved */
#define ASC_PHASE_MSG_OUT 0x6
#define ASC_PHASE_MSG_IN 0x7
/*
* Destination Bus ID
*/
#define ASC_DEST_ID_MASK 0x07
/*
* Interrupt register
*/
#define ASC_INT_RESET 0x80
#define ASC_INT_ILL 0x40
#define ASC_INT_DISC 0x20
#define ASC_INT_BS 0x10
#define ASC_INT_FC 0x08
#define ASC_INT_RESEL 0x04
#define ASC_INT_SEL_ATN 0x02
#define ASC_INT_SEL 0x01
/*
* Timeout register:
*
* val = (timeout * CLK_freq) / (8192 * CCF);
*/
#define ASC_TIMEOUT_250(clk, ccf) (((clk) * 31) / (ccf))
/*
* Sequence Step register
*/
#define ASC_SS_RESERVED 0xf0
#define ASC_SS_SOM 0x08
#define ASC_SS_MASK 0x07
#define ASC_SS(ss) ((ss) & ASC_SS_MASK)
/*
* Synchronous Transfer Period
*/
#define ASC_STP_MASK 0x1f
#define ASC_STP_MIN 0x05 /* 5 clk per byte */
#define ASC_STP_MAX 0x04 /* after ovfl, 35 clk/byte */
/*
* FIFO flags
*/
#define ASC_FLAGS_SEQ_STEP 0xe0
#define ASC_FLAGS_FIFO_CNT 0x1f
/*
* Synchronous offset
*/
#define ASC_SYNO_MASK 0x0f /* 0 -> asyn */
/*
* Configuration 1
*/
#define ASC_CNFG1_SLOW 0x80
#define ASC_CNFG1_SRD 0x40
#define ASC_CNFG1_P_TEST 0x20
#define ASC_CNFG1_P_CHECK 0x10
#define ASC_CNFG1_TEST 0x08
#define ASC_CNFG1_MY_BUS_ID 0x07
/*
* CCF register
*/
#define ASC_CCF(clk) ((((clk) - 1) / 5) + 1)
/*
* Test register
*/
#define ASC_TEST_XXXX 0xf8
#define ASC_TEST_HI_Z 0x04
#define ASC_TEST_I 0x02
#define ASC_TEST_T 0x01
/*
* Configuration 2
*/
#define ASC_CNFG2_RFB 0x80
#define ASC_CNFG2_EPL 0x40
#define ASC_CNFG2_EBC 0x20
#define ASC_CNFG2_DREQ_HIZ 0x10
#define ASC_CNFG2_SCSI2 0x08
#define ASC_CNFG2_BPA 0x04
#define ASC_CNFG2_RPE 0x02
#define ASC_CNFG2_DPE 0x01
/*
* Configuration 3
*/
#define ASC_CNFG3_RESERVED 0xf8
#define ASC_CNFG3_SRB 0x04
#define ASC_CNFG3_ALT_DMA 0x02
#define ASC_CNFG3_T8 0x01
#define ST_MASK 0x3e
|
