1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
|
/* $NetBSD: wd7000.c,v 1.22 1995/08/12 20:31:32 mycroft Exp $ */
/* XXX THIS DRIVER IS BROKEN. IT WILL NOT EVEN COMPILE. */
/*
* UNFINISHED! UNFINISHED! UNFINISHED! UNFINISHED! UNFINISHED! UNFINISHED!
*
* deraadt@fsa.ca 93/04/02
*
* I was writing this driver for a wd7000-ASC. Yeah, the "-ASC" not the
* "-FASST2". The difference is that the "-ASC" is missing scatter gather
* support.
*
* In any case, the real reason why I never finished it is because the
* motherboard I have has broken DMA. This card wants 8MHz 1 wait state
* operation, and my board munges about 30% of the words transferred.
*
* Hopefully someone can finish this for the wd7000-FASST2. It should be
* quite easy to do. Look at the Linux wd7000 device driver to see how
* scatter gather is done by the board, then look at one of the Adaptec
* drivers to finish off the job..
*/
#include "wds.h"
#if NWDS > 0
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/errno.h>
#include <sys/ioctl.h>
#include <sys/buf.h>
#include <sys/proc.h>
#include <sys/user.h>
#include <sys/dkbad.h>
#include <sys/disklabel.h>
#include <scsi/scsi_all.h>
#include <scsi/scsiconf.h>
#include <machine/cpu.h>
#include <machine/pio.h>
#include <i386/isa/isa_device.h> /* XXX BROKEN */
extern int delaycount; /* from clock setup code */
#define PHYSTOKV(x) ((x) + KERNBASE)
#define KVTOPHYS(x) vtophys(x)
#define PAGESIZ 4096
/* WD7000 registers */
#define WDS_STAT 0 /* read */
#define WDS_IRQSTAT 1 /* read */
#define WDS_CMD 0 /* write */
#define WDS_IRQACK 1 /* write */
#define WDS_HCR 2 /* write */
/* WDS_STAT (read) defs */
#define WDS_IRQ 0x80
#define WDS_RDY 0x40
#define WDS_REJ 0x20
#define WDS_INIT 0x10
/* WDS_IRQSTAT (read) defs */
#define WDSI_MASK 0xc0
#define WDSI_ERR 0x00
#define WDSI_MFREE 0x80
#define WDSI_MSVC 0xc0
/* WDS_CMD (write) defs */
#define WDSC_NOOP 0x00
#define WDSC_INIT 0x01
#define WDSC_DISUNSOL 0x02
#define WDSC_ENAUNSOL 0x03
#define WDSC_IRQMFREE 0x04
#define WDSC_SCSIRESETSOFT 0x05
#define WDSC_SCSIRESETHARD 0x06
#define WDSC_MSTART(m) (0x80 + (m))
#define WDSC_MMSTART(m) (0xc0 + (m))
/* WDS_HCR (write) defs */
#define WDSH_IRQEN 0x08
#define WDSH_DRQEN 0x04
#define WDSH_SCSIRESET 0x02
#define WDSH_ASCRESET 0x01
struct wds_cmd {
u_char cmd;
u_char targ;
struct scsi_generic scb; /*u_char scb[12];*/
u_char stat;
u_char venderr;
u_char len[3];
u_char data[3];
u_char next[3];
u_char write;
u_char xx[6];
};
struct wds_req {
struct wds_cmd cmd;
struct wds_cmd sense;
struct scsi_xfer *sxp;
int busy, polled;
int done, ret, ombn;
};
#define WDSX_SCSICMD 0x00
#define WDSX_OPEN_RCVBUF 0x80
#define WDSX_RCV_CMD 0x81
#define WDSX_RCV_DATA 0x82
#define WDSX_RCV_DATASTAT 0x83
#define WDSX_SND_DATA 0x84
#define WDSX_SND_DATASTAT 0x85
#define WDSX_SND_CMDSTAT 0x86
#define WDSX_READINIT 0x88
#define WDSX_READSCSIID 0x89
#define WDSX_SETUNSOLIRQMASK 0x8a
#define WDSX_GETUNSOLIRQMASK 0x8b
#define WDSX_GETFIRMREV 0x8c
#define WDSX_EXECDIAG 0x8d
#define WDSX_SETEXECPARM 0x8e
#define WDSX_GETEXECPARM 0x8f
struct wds_mb {
u_char stat;
u_char addr[3];
};
/* ICMB status value */
#define ICMB_OK 0x01
#define ICMB_OKERR 0x02
#define ICMB_ETIME 0x04
#define ICMB_ERESET 0x05
#define ICMB_ETARCMD 0x06
#define ICMB_ERESEL 0x80
#define ICMB_ESEL 0x81
#define ICMB_EABORT 0x82
#define ICMB_ESRESET 0x83
#define ICMB_EHRESET 0x84
struct wds_setup {
u_char cmd;
u_char scsi_id;
u_char buson_t;
u_char busoff_t;
u_char xx;
u_char mbaddr[3];
u_char nomb;
u_char nimb;
};
#define WDS_NOMB 16
#define WDS_NIMB 8
#define MAXSIMUL 8
struct wds {
int addr;
struct wds_req wdsr[MAXSIMUL];
struct wds_mb ombs[WDS_NOMB], imbs[WDS_NIMB];
} wds[NWDS];
static int wdsunit = 0;
int wds_debug = 0;
void p2x(u_char *, u_long);
u_char *x2p(u_char *);
int wdsprobe(struct isa_device *);
void wds_minphys(struct buf *);
struct wds_req *wdsr_alloc(int);
int wds_scsi_cmd(struct scsi_xfer *);
long wds_adapter_info(int);
int wdsintr(int);
int wds_done(int, struct wds_cmd *, u_char);
int wdsattach(struct isa_device *);
int wds_init(struct isa_device *);
int wds_cmd(int, u_char *, int);
void wds_wait(int, int, int);
struct scsi_switch wds_switch[NWDS];
struct isa_driver wdsdriver = {
wdsprobe,
wdsattach,
"wds",
};
void
flushcache(void)
{
extern main();
volatile char *p, c;
int i;
for(p=(char *)main, i=0; i<256*1024; i++)
c = *p++;
}
void
p2x(u_char *p, u_long x)
{
p[0] = (x & 0x00ff0000) >> 16;
p[1] = (x & 0x0000ff00) >> 8;
p[2] = (x & 0x000000ff);
}
u_char *
x2p(u_char *x)
{
u_long q;
q = ((x[0]<<16) & 0x00ff0000) + ((x[1]<<8) & 0x0000ff00) + (x[2] & 0x000000ff);
return (u_char *)q;
}
int
wdsprobe(struct isa_device *dev)
{
/*scsi_debug = PRINTROUTINES | TRACEOPENS | TRACEINTERRUPTS |
SHOWREQUESTS | SHOWSCATGATH | SHOWINQUIRY | SHOWCOMMANDS;*/
if (dev->id_parent)
return 1;
if(wdsunit > NWDS)
return 0;
dev->id_unit = wdsunit;
wds[wdsunit].addr = dev->id_iobase;
if(wds_init(dev) != 0)
return 0;
wdsunit++;
return 8;
}
void
wds_minphys(struct buf *bp)
{
int base = (int)bp->b_data & (PAGESIZ-1);
if (base + bp->b_bcount > PAGESIZ)
bp->b_bcount = PAGESIZ - base;
minphys(bp);
}
struct wds_req *
wdsr_alloc(int unit)
{
struct wds_req *r;
int x;
int i;
r = NULL;
x = splbio();
for(i=0; i<MAXSIMUL; i++)
if(wds[unit].wdsr[i].busy == 0) {
r = &wds[unit].wdsr[i];
r->busy = 1;
break;
}
if(r == NULL) {
splx(x);
return NULL;
}
r->ombn = -1;
for(i=0; i<WDS_NOMB; i++)
if(wds[unit].ombs[i].stat==0) {
wds[unit].ombs[i].stat = 1;
r->ombn = i;
break;
}
if(r->ombn == -1 ) {
r->busy = 0;
splx(x);
return NULL;
}
splx(x);
return r;
}
int
wds_scsi_cmd(struct scsi_xfer *sxp)
{
struct wds_req *r;
int unit = sxp->adapter;
int base;
u_char c, *p;
int i;
base = wds[unit].addr;
/*printf("scsi_cmd\n");*/
if( sxp->flags & SCSI_RESET) {
printf("reset!\n");
return COMPLETE;
}
r = wdsr_alloc(unit);
if(r==NULL) {
printf("no request slot available!\n");
sxp->error = XS_DRIVER_STUFFUP;
return TRY_AGAIN_LATER;
}
r->done = 0;
r->sxp = sxp;
printf("wds%d: target %d/%d req %8x flags %08x len %d: ", unit,
sxp->targ, sxp->lu, r, sxp->flags, sxp->cmdlen);
for(i=0, p=(u_char *)sxp->cmd; i<sxp->cmdlen; i++)
printf("%02x ", p[i]);
printf("\n");
printf(" data %08x datalen %08x\n", sxp->data, sxp->datalen);
if(sxp->flags & SCSI_DATA_UIO) {
printf("UIO!\n");
sxp->error = XS_DRIVER_STUFFUP;
return TRY_AGAIN_LATER;
}
p2x(&wds[unit].ombs[r->ombn].addr[0], KVTOPHYS(&r->cmd));
printf("%08x/%08x mbox@%08x: %02x %02x %02x %02x\n",
&r->cmd, KVTOPHYS(&r->cmd), &wds[unit].ombs[0],
wds[unit].ombs[r->ombn].stat, wds[unit].ombs[r->ombn].addr[0],
wds[unit].ombs[r->ombn].addr[1], wds[unit].ombs[r->ombn].addr[2]);
bzero(&r->cmd, sizeof r->cmd);
r->cmd.cmd = WDSX_SCSICMD;
r->cmd.targ = (sxp->targ << 5) | sxp->lu;
bcopy(sxp->cmd, &r->cmd.scb, sxp->cmdlen<12 ? sxp->cmdlen : 12);
p2x(&r->cmd.len[0], sxp->datalen);
p2x(&r->cmd.data[0], sxp->datalen ? KVTOPHYS(sxp->data) : 0);
r->cmd.write = (sxp->flags&SCSI_DATA_IN)? 0x80 : 0x00;
p2x(&r->cmd.next[0], KVTOPHYS(&r->sense));
bzero(&r->sense, sizeof r->sense);
r->sense.cmd = r->cmd.cmd;
r->sense.targ = r->cmd.targ;
r->sense.scb.opcode = REQUEST_SENSE;
p2x(&r->sense.data[0], KVTOPHYS(&sxp->sense));
p2x(&r->sense.len[0], sizeof sxp->sense);
r->sense.write = 0x80;
/*printf("wdscmd: ");
for(i=0, p=(u_char *)&r->cmd; i<sizeof r->cmd; i++)
printf("%02x ", p[i]);
printf("\n");*/
if(sxp->flags & SCSI_NOMASK) {
outb(base+WDS_HCR, WDSH_DRQEN);
r->polled = 1;
} else
r->polled = 0;
c = WDSC_MSTART(r->ombn);
flushcache();
if( wds_cmd(base, &c, sizeof c) != 0) {
printf("wds%d: unable to start outgoing mbox\n", unit);
r->busy = 0;
/* XXX need to free mailbox */
return TRY_AGAIN_LATER;
}
delay(10000);
/*printf("%08x/%08x mbox: %02x %02x %02x %02x\n", &r->cmd, KVTOPHYS(&r->cmd),
wds[unit].ombs[r->ombn].stat, wds[unit].ombs[r->ombn].addr[0],
wds[unit].ombs[r->ombn].addr[1], wds[unit].ombs[r->ombn].addr[2]);*/
if(sxp->flags & SCSI_NOMASK) {
repoll: printf("wds%d: polling.", unit);
i = 0;
while( (inb(base+WDS_STAT) & WDS_IRQ) == 0) {
printf(".");
delay(10000);
if(++i == 10) {
printf("failed %02x\n", inb(base+WDS_IRQSTAT));
/*r->busy = 0;*/
sxp->error = XS_TIMEOUT;
return HAD_ERROR;
}
}
flushcache();
printf("got one!\n");
wdsintr(unit);
if(r->done) {
r->sxp->flags |= ITSDONE;
if(r->sxp->when_done)
(*r->sxp->when_done)(r->sxp->done_arg,
r->sxp->done_arg2);
r->busy = 0;
return r->ret;
}
goto repoll;
}
outb(base+WDS_HCR, WDSH_IRQEN|WDSH_DRQEN);
printf("wds%d: successfully queued\n", unit);
return SUCCESSFULLY_QUEUED;
}
long
wds_adapter_info(int unit)
{
return 1;
}
int
wdsintr(int unit)
{
struct wds_cmd *pc, *vc;
struct wds_mb *in;
u_char stat;
u_char c;
/*printf("stat=%02x\n", inb(wds[unit].addr + WDS_STAT));*/
delay(1000);
c = inb(wds[unit].addr + WDS_IRQSTAT);
printf("wdsintr: %02x\n", c);
if( (c&WDSI_MASK) == WDSI_MSVC) {
delay(1000);
c = c & ~WDSI_MASK;
flushcache();
in = &wds[unit].imbs[c];
printf("incoming mailbox %02x@%08x: ", c, in);
printf("%02x %02x %02x %02x\n",
in->stat, in->addr[0], in->addr[1], in->addr[2]);
pc = (struct wds_cmd *)x2p(&in->addr[0]);
vc = (struct wds_cmd *)PHYSTOKV(pc);
stat = in->stat;
printf("p=%08x v=%08x stat %02x\n", pc, vc, stat);
wds_done(unit, vc, stat);
in->stat = 0;
outb(wds[unit].addr + WDS_IRQACK, 0xff);
}
return 1;
}
int
wds_done(int unit, struct wds_cmd *c, u_char stat)
{
struct wds_req *r;
int i;
r = (struct wds_req *)NULL;
for(i=0; i<MAXSIMUL; i++)
if( c == &wds[unit].wdsr[i].cmd ) {
/*printf("found at req slot %d\n", i);*/
r = &wds[unit].wdsr[i];
break;
}
if(r == (struct wds_req *)NULL) {
printf("failed to find request!\n");
return 1;
}
printf("wds%d: cmd %8x stat %2x/%2x %2x/%2x\n", unit, c,
r->cmd.stat, r->cmd.venderr, r->sense.stat, r->sense.venderr);
r->done = 1;
/* XXX need to free mailbox */
r->ret = HAD_ERROR;
switch(r->cmd.stat) {
case ICMB_OK:
/*XXX r->sxp->sense.valid = 0;
r->sxp->error = 0;*/
r->ret = COMPLETE;
break;
case ICMB_OKERR:
printf("scsi err %02x\n", c->venderr);
/*XXX r->sxp->sense.error_code = c->venderr;
r->sxp->sense.valid = 1;*/
r->ret = COMPLETE;
break;
case ICMB_ETIME:
r->sxp->error = XS_TIMEOUT;
r->ret = HAD_ERROR;
break;
case ICMB_ERESET:
case ICMB_ETARCMD:
case ICMB_ERESEL:
case ICMB_ESEL:
case ICMB_EABORT:
case ICMB_ESRESET:
case ICMB_EHRESET:
r->sxp->error = XS_DRIVER_STUFFUP;
r->ret = HAD_ERROR;
break;
}
if(r->polled==0) {
r->sxp->flags |= ITSDONE;
if(r->sxp->when_done)
(*r->sxp->when_done)(r->sxp->done_arg, r->sxp->done_arg2);
r->busy = 0;
}
return 0;
}
int
wds_getvers(int unit)
{
struct wds_req *r;
int base;
u_char c, *p;
int i;
base = wds[unit].addr;
/*printf("scsi_cmd\n");*/
r = wdsr_alloc(unit);
if(r==NULL) {
printf("wds%d: no request slot available!\n", unit);
return -1;
}
r->done = 0;
r->sxp = NULL;
printf("wds%d: getvers req %8x\n", unit, r);
p2x(&wds[unit].ombs[r->ombn].addr[0], KVTOPHYS(&r->cmd));
printf("%08x/%08x mbox@%08x: %02x %02x %02x %02x\n",
&r->cmd, KVTOPHYS(&r->cmd), &wds[unit].ombs[0],
wds[unit].ombs[r->ombn].stat, wds[unit].ombs[r->ombn].addr[0],
wds[unit].ombs[r->ombn].addr[1], wds[unit].ombs[r->ombn].addr[2]);
bzero(&r->cmd, sizeof r->cmd);
r->cmd.cmd = WDSX_GETFIRMREV;
r->cmd.write = 0x80;
printf("wdscmd: ");
for(i=0, p=(u_char *)&r->cmd; i<sizeof r->cmd; i++)
printf("%02x ", p[i]);
printf("\n");
outb(base+WDS_HCR, WDSH_DRQEN);
r->polled = 1;
c = WDSC_MSTART(r->ombn);
flushcache();
if( wds_cmd(base, &c, sizeof c) != 0) {
printf("wds%d: unable to start outgoing mbox\n", unit);
r->busy = 0;
/* XXX need to free mailbox */
return -1;
}
delay(10000);
/*printf("%08x/%08x mbox: %02x %02x %02x %02x\n", &r->cmd, KVTOPHYS(&r->cmd),
wds[unit].ombs[r->ombn].stat, wds[unit].ombs[r->ombn].addr[0],
wds[unit].ombs[r->ombn].addr[1], wds[unit].ombs[r->ombn].addr[2]);*/
while(1) {
printf("wds%d: polling.", unit);
i = 0;
while( (inb(base+WDS_STAT) & WDS_IRQ) == 0) {
printf(".");
delay(10000);
if(++i == 10) {
printf("failed %02x\n", inb(base+WDS_IRQSTAT));
/*r->busy = 0;*/
return -1;
}
}
flushcache();
printf("got one!\n");
wdsintr(unit);
if(r->done) {
printf("wds%d: version %02x %02x\n", unit,
r->cmd.targ, r->cmd.scb.opcode);
r->busy = 0;
return 0;
}
}
}
int
wdsattach(struct isa_device *dev)
{
int masunit;
static int firstswitch[NWDS];
static u_long versprobe /* max 32 controllers */
int r;
if (!dev->id_parent)
return 1;
masunit = dev->id_parent->id_unit;
if( !(versprobe & (1<<masunit))) {
versprobe |= (1<<masunit);
if(wds_getvers(masunit)==-1)
printf("wds%d: getvers failed\n", masunit);
}
if (!firstswitch[masunit]) {
firstswitch[masunit] = 1;
wds_switch[masunit].name = "wds";
wds_switch[masunit].scsi_cmd = wds_scsi_cmd;
wds_switch[masunit].scsi_minphys = wdsminphys;
wds_switch[masunit].open_target_lu = 0;
wds_switch[masunit].close_target_lu = 0;
wds_switch[masunit].adapter_info = wds_adapter_info;
for (r = 0; r < 8; r++) {
wds_switch[masunit].empty[r] = 0;
wds_switch[masunit].used[r] = 0;
wds_switch[masunit].printed[r] = 0;
}
}
r = scsi_attach(masunit, &wds_switch[masunit], &dev->id_physid,
&dev->id_unit, dev->id_flags);
return r;
}
int
wds_init(struct isa_device *dev)
{
struct wds_setup init;
int base;
u_char *p, c;
int unit, i;
unit = dev->id_unit;
base = wds[unit].addr;
/*
* Sending a command causes the CMDRDY bit to clear.
*/
c = inb(base+WDS_STAT);
for(i=0; i<4; i++)
if( (inb(base+WDS_STAT) & WDS_RDY) != 0) {
goto ready;
delay(10);
}
return 1;
ready:
outb(base+WDS_CMD, WDSC_NOOP);
if( inb(base+WDS_STAT) & WDS_RDY)
return 1;
/*
* the controller exists. reset and init.
*/
outb(base+WDS_HCR, WDSH_SCSIRESET|WDSH_ASCRESET);
delay(3);
outb(base+WDS_HCR, WDSH_DRQEN);
delay(20000);
#if 1
outb(0xd6, 0xc3);
outb(0xd4, 0x03);
#else
isa_dmacascade(dev->id_drq);
#endif
if( (inb(base+WDS_STAT) & (WDS_RDY)) != WDS_RDY) {
printf("wds%d: waiting for controller to become ready", unit);
for(i=0; i<6; i++) {
if( (inb(base+WDS_STAT) & (WDS_RDY)) == WDS_RDY)
break;
printf(".");
delay(10000);
}
if( (inb(base+WDS_STAT) & (WDS_RDY)) != WDS_RDY) {
printf("failed\n");
return 1;
}
}
bzero(&init, sizeof init);
init.cmd = WDSC_INIT;
init.scsi_id = 0;
init.buson_t = 24;
init.busoff_t = 48;
p2x(&init.mbaddr[0], KVTOPHYS(&wds[unit].ombs[0]));
init.xx = 0;
init.nomb = WDS_NOMB;
init.nimb = WDS_NIMB;
/*p = (u_char *)&init;
printf("wds%d: %08x %08x init: ", unit,
&wds[unit].ombs[0], KVTOPHYS(&wds[unit].ombs[0]));
for(i=0; i<sizeof init; i++)
printf("%02x ", p[i]);
printf("\n");*/
wds_wait(base+WDS_STAT, WDS_RDY, WDS_RDY);
flushcache();
if( wds_cmd(base, (u_char *)&init, sizeof init) != 0) {
printf("wds%d: wds_cmd failed\n", unit);
return 1;
}
wds_wait(base+WDS_STAT, WDS_INIT, WDS_INIT);
wds_wait(base+WDS_STAT, WDS_RDY, WDS_RDY);
c = WDSC_DISUNSOL;
if( wds_cmd(base, &c, sizeof c) != 0) {
printf("wds%d: wds_cmd failed\n", unit);
return 1;
}
return 0;
}
int
wds_cmd(int base, u_char *p, int l)
{
int i;
u_char c;
i = 0;
while(i < l) {
while( ((c=inb(base+WDS_STAT)) & WDS_RDY) == 0)
;
outb(base+WDS_CMD, *p);
while( ((c=inb(base+WDS_STAT)) & WDS_RDY) == 0)
;
if(c & WDS_REJ)
return 1;
p++;
i++;
}
while( ((c=inb(base+WDS_STAT)) & WDS_RDY) == 0)
;
if(c & WDS_REJ)
return 1;
/*printf("wds_cmd: %02x\n", inb(base+WDS_STAT));*/
return 0;
}
void
wds_wait(int reg, int mask, int val)
{
while( (inb(reg) & mask) != val)
;
}
#endif
|