diff options
| author | Matthieu Herrb <matthieu@cvs.openbsd.org> | 2009-04-26 13:59:42 +0000 |
|---|---|---|
| committer | Matthieu Herrb <matthieu@cvs.openbsd.org> | 2009-04-26 13:59:42 +0000 |
| commit | 88d6c378da6a2aa47085d1beb569e23c4aa52240 (patch) | |
| tree | 3f3562995697e5e006c1265b40d1e4848012d8e2 | |
| parent | 7973b90a12e9f0eec34b485f0183423f446a3c1f (diff) | |
Update to xf86-video-radeonhd 1.2.5. Tested by eric@
Version 1.2.5 improvements:
- Added 2D acceleration for R6xx and R7xx.
- Added XVideo support for R6xx and R7xx.
- Added support for RS880 and RV790.
- Added RandR 1.3 mandatory properties.
- Refactoring of MC code.
- Enable DRI support by default on R5xx and RS6xx.
- LUT (color lookup table) fixes.
- Tons of quirk table entries and bug fixes.
- Fix register accesses for processors that reorder memory writes.
90 files changed, 13847 insertions, 1433 deletions
diff --git a/driver/xf86-video-radeonhd/ChangeLog b/driver/xf86-video-radeonhd/ChangeLog index ba3908369..9232fc164 100644 --- a/driver/xf86-video-radeonhd/ChangeLog +++ b/driver/xf86-video-radeonhd/ChangeLog @@ -1,3 +1,1393 @@ +commit cb54f48b212d5ae54e13bbdf24575b6163798c0d +Author: Matthias Hopf <mhopf@suse.de> +Date: Thu Apr 9 15:11:37 2009 +0200 + + Bump to 1.2.5. Updated README. + +commit 9d2a508892f16572127d192497bcf505556538b8 +Author: Yang Zhao <yang@yangman.ca> +Date: Thu Apr 9 15:01:05 2009 +0200 + + Fix resume from suspend for r6xx/r7xx + + Move DRM calls to DRM_RADEON_CP_RESUME and RADEON_SETPARAM_VBLANK_CRTC + to after doing GART backup. Also move call to DRIUnlock() to end of + RHDEnterVT() from RHDDRIEnterVT(). + +commit 1137e0963e322dcb41816bdc76c57d3e3d407166 +Author: Matthias Hopf <mhopf@suse.de> +Date: Thu Apr 9 11:42:35 2009 +0200 + + RHDDRIGetIntGARTLocation is called too often to be logged. Nuked RHDFUNC there. + +commit 76d6973a5c18b5aff7e7027a2f87d3616179e2e9 +Author: Matthias Hopf <mhopf@suse.de> +Date: Wed Apr 8 17:01:49 2009 +0200 + + man: R6xx and R7xx 2D possible now. + +commit 0065697647401fd4b0df13df94bd9ebedcac96dc +Author: Yang Zhao <yang@yangman.ca> +Date: Wed Mar 25 19:26:02 2009 -0700 + + LUT: reduce number of writes to DC_LUT_RW_INDEX + + The value of DC_LUT_RW_INDEX is increased everytime DC_LUT_30_COLOR is + accessed. It is pointless to set this explicitly for each row of the + input colour table. + + Signed-off-by: Yang Zhao <yang@yangman.ca> + +commit 6d7f2486ea5f7794dee0c8d8d2655ddad378eff5 +Author: Matthias Hopf <mhopf@suse.de> +Date: Fri Apr 3 11:54:14 2009 +0200 + + Use () in macro arguments of new RHDRegMask. + +commit d6c3727751a2de2c333e654aea1bd9b1d9c2ef44 +Author: Yang Zhao <yang@yangman.ca> +Date: Fri Mar 27 21:21:25 2009 -0700 + + CS: Replace register read/write macros with ones from compiler.h + + Signed-off-by: Yang Zhao <yang@yangman.ca> + +commit c9d1af91acc579d7930ecf221090ff558cbc2f99 +Author: Yang Zhao <yang@yangman.ca> +Date: Fri Mar 27 19:46:11 2009 -0700 + + Use X MMIO macros instead of own register read/write functions + + The old functions were not portable. + + Signed-off-by: Yang Zhao <yang@yangman.ca> + +commit f65014d8dd50eb0d72a1d9da5371db0840c16d7e +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Apr 2 12:11:03 2009 -0400 + + Add RV790 (HD 4890) Support + +commit 79efc6093f26daea654d3f748ebe3d4aa1229fe4 +Author: Egbert Eich <eich@freedesktop.org> +Date: Wed Apr 1 09:38:41 2009 +0200 + + AtomBIOS: Fixed wrong logic: switch -> if. + +commit ecd616670e73d57397cc3e01017c84b9076c9f4f +Author: Yang Zhao <yang@yangman.ca> +Date: Sat Mar 21 15:21:50 2009 -0700 + + rhd_dump: fix error introduced by LUT dump addition + + 6e71f01f225a0cb13d10c7f7960db9d20c89a7db introduced a bug in rhd_dump + where register address is scanned as %d instead of %x. + + Thanks to Rafal for pointing out the regression. + +commit 7e4948a3ad80ae0885df89ac7320457cb90f0b55 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Mar 26 14:22:35 2009 -0400 + + R6xx/R7xx EXA: rework composite pixel shader + + - move to vram storage + - move swizzle logic to tex setup + +commit 461701c6abf76eef296a33fbdbda77a3bde2aa62 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Mar 26 14:08:14 2009 -0400 + + R6xx/R7xx: clean up bool const code + + 3 regs: 1 bit per bool, 32 bools per ps/vs/gs + +commit cc6e6fe4e8b4f4557dd43b97b2b864f6dda76087 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Sun Mar 22 01:31:57 2009 -0400 + + add new chip ids + +commit f0f640f105da161e7dbb08bdd85f7ff065696e72 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Mar 19 20:49:42 2009 -0400 + + R6xx/R7xx EXA: fix maxPitchBytes + + should now allow accel up the hw max of 8192x8192 + +commit 37da5e5abf7907f9341354732775d45ba88319f0 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Mar 19 20:18:50 2009 -0400 + + Add new pci ids + +commit 4fa650628d7688045cdda22683d49131f858ed4e +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Mar 19 10:56:04 2009 -0400 + + Really disable UTS/DFS on r6xx/r7xx AGP + + typo in the last patch + +commit b075ec9cee108061a1abb7c3f786a8b76da99997 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Mar 18 14:37:51 2009 -0400 + + R6xx/R7xx AGP: disable gart data transfers + + Doesn't seem to be reliable on AGP. + +commit d9c8f9ce4aabc7c1a85e4f015c6b19bde4f96866 +Author: Dave Airlie <airlied@redhat.com> +Date: Fri Mar 13 10:36:52 2009 -0400 + + r600: reload shaders into VRAM on resume + + As VRAM gets zeroed out over s/r, we need to reload the + shaders. + +commit 12611c8f1b3f6e6b2ed7f6cfb1b7271d9a313bdf +Author: Yang Zhao <yang@yangman.ca> +Date: Wed Mar 11 19:29:41 2009 -0700 + + R6xx/R7xx shader: Fix OFFSET_[XYZ] macro for TEX_DWORD2 to accept floats + + Values for OFFSET_[XYZ] are 5-bits two's-complement fixed-point with + one-bit after decimal point. Values in [-8.0, 7.5] are valid. Inputs + that do not exactly land on 0.5 increments are rounded towards 0 to the + nearest increment. + +commit 70490504ef74069e657daefff4f28a9bd9cb8778 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Mar 12 03:45:24 2009 -0400 + + RS600: fix page table size for rs600 as well + +commit 10ebf657755b993a09046a664311a8309a0950b9 +Author: Dave Airlie <airlied@redhat.com> +Date: Thu Mar 12 01:03:43 2009 -0400 + + r600: fix sizing of PCI GART table for r600 + +commit f27383df4a5f3a9349ead2d833142f82ee6acd92 +Author: Yang Zhao <yang@yangman.ca> +Date: Wed Mar 11 16:20:42 2009 +0100 + + R6xx/R7xx: Fix OFFSET_[XYZ] macros for negative values. + +commit 827fb141f5be6bf02acb8ab650602c56136433fa +Author: Matthias Hopf <mhopf@suse.de> +Date: Tue Mar 10 18:31:17 2009 +0100 + + randr: Set use_screen_monitor correctly using helper function. + + Fixes novell bug #370656. + +commit 76490dd8d052586f8737babdd8f383dbe39f4291 +Author: Matthias Hopf <mhopf@suse.de> +Date: Tue Mar 10 17:14:26 2009 +0100 + + Enable DRI by default on R5xx chips. + + R[67]xx still need an explicit 'Option "DRI"'. + +commit 093e5934a26f784f70b5febf8ae6d50a3459552c +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Mar 5 11:55:54 2009 -0500 + + R6xx/R7xx Xv: only stall on vline if the destination pixmap is the scanout buffer + + With composite we may be rendering to an offscreen pixmap. + +commit 70c6b680118097cddf72c0c82eabf7dc7e438f2f +Author: Rafał Miłecki <zajec5@gmail.com> +Date: Wed Mar 4 20:43:40 2009 +0100 + + Fixes to the radeonhd manpage + + Signed-off-by: Christian König <deathsimple@vodafone.de> + +commit ad21c9ccc56bfb0957e59eaad152f1c2fcdde73a +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Thu Dec 25 15:24:10 2008 +0100 + + Remove no interlaced modes limitation from TMDS outputs. + + This patch removes the limitation of displaying no interlaced modes from + the TMDS outputs. Since interlaced modes are just a matter of CRTC + programming this makes them work out of the box. + +commit 742a4b4e0e68e88bf91c28237675877831f605b0 +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Sat Dec 20 23:15:14 2008 +0100 + + Randr HDMI property + + Adds an HDMI property to randr and while we are at it rework the + property handling a bit. Also adds an RHDOutputAttachConnector function + which is called every time an output <-> connection relation is changed. + +commit 2013be5c86b11fd05cce25814213f9a2bf0bd704 +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Sat Dec 20 23:05:27 2008 +0100 + + Cleanup and include true/false as match in RhdParseBooleanOption + + Further improve RhdParseBooleanOption to include true/false as match, + since people seems to be used to it because of the behaviour of Boolean + options. + +commit 54600950219ddb83b73c4ac17546093c36402e36 +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Sat Dec 20 23:03:22 2008 +0100 + + Update RHDAudioInit to include RS600, RS690 and RS740 + + RHDAudioInit decides from the chipset type if there is an audio engine. + This commit changes this test to include more chipsets. It should be + removed entirely when i figure out how to get this information from + atombios. + +commit 9c8ab2dfbe61120298c4b46a2b49245c6779dbc2 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Mar 2 16:26:14 2009 -0500 + + R6xx/R7xx EXA: cleanup composite texture setup + +commit 3826cd76b04664f66b19892b9d937b27a1c69534 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Mar 2 16:16:36 2009 -0500 + + R6xx/R7xx: combine Xv packed/planar PS and EXA composite VS + + use bool consts to select the fetch routines + +commit 2a06a508dfe64212887192a3126b668415507d34 +Author: Evgeni Golov <sargentd@die-welt.net> +Date: Mon Mar 2 14:52:27 2009 -0500 + + Fix compile with EXA but no DRI + +commit b02af166bed7706d6909acd4037af2df646a18a6 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Mar 2 11:23:39 2009 -0500 + + R6xx/R7xx: fix build errors in some cases + +commit 7338dc0d9d2bff677e9f10bdd0f59d8694fe274d +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Mar 2 11:22:05 2009 -0500 + + R6xx/R7xx: fix regression in 347b23d419c877de0ac95b1f2f69d6953dddfebd + + Should fix bug 20426 + +commit 1935b2aae5cf53fe2777eb31ca39c4ce551b3292 +Author: Luc Verhaegen <libv@skynet.be> +Date: Mon Mar 2 15:07:43 2009 +0100 + + Byebye novell. + +commit b35c26fc4a318ec30b76bae6d420a1b73fa14fa6 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Mar 2 00:21:12 2009 -0500 + + R6xx/R7xx: write vertexes directly to the IB + + Reduces the vertex buffer setup overhead + +commit 347b23d419c877de0ac95b1f2f69d6953dddfebd +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Mar 2 00:07:23 2009 -0500 + + R6xx/R7xx: switch emit functions to macros + + This improves performance due to decreased function call + overhead. + +commit 89a835f03993da087c361de7ee3f6bc13bcb33f8 +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Sun Mar 1 23:03:24 2009 -0500 + + R6xx/R7xx cleanup: Replace Xv shaders with generated ones + + Replace Xv shaders with generated one fixing some minor typos in the + pixel shaders. + +commit 2b725913b1a91f2d178e77cd542c35067fc16d7c +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Sun Mar 1 23:01:32 2009 -0500 + + R6xx/R7xx cleanup: Move shaders to r600_shader.c + + Move all shaders from r600_exa.c to the new file r600_shader.c + +commit 6f9373384d3ebe58333e1ee0c64ddcc11d235a06 +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Sun Mar 1 22:38:06 2009 -0500 + + R6xx/R7xx cleanup: Fix comments in r600_exa.c + + Replace all C++ comments in r600_exa.c with C ones. + +commit 812ff17853d4d8a07418d0b28b2f3f80f6db74ed +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Sun Mar 1 12:22:14 2009 -0500 + + Fix R5xx Xv after r6xx/r7xx accel merge + +commit df71658688e47614a3f660c28ac1dc77970eb491 +Author: Matthias Hopf <mhopf@suse.de> +Date: Thu Feb 26 12:24:44 2009 +0100 + + EXA: fix for (now compatible) PREPARE_AUX buffers. + + Partially reverts commit 047bd7059bcfec55e06a35db4a2b16d52fe8dbf6. + +commit 10c211913de10bb4c7ec0747671f1b3e61231674 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Fri Feb 27 11:34:20 2009 -0500 + + Only pad the IB on r6xx+ + +commit f10c8c797f3a0b53625cf8850b949fb304bcc4da +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Feb 25 22:44:32 2009 -0500 + + CloseScreen(): Don't mess with the engine if the xserver isn't active + + This fixes problems with killing X when accel is active and the server + is switched away. + +commit a900f07b64bebe26d66b02decb146391937ea18d +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Feb 25 09:20:03 2009 -0500 + + R6xx/R7xx EXA: same surface and same coords equals nop + +commit fdf6150ad9988b2e6e391c54b2f5fb9bc1cda837 +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Tue Feb 24 16:57:48 2009 -0500 + + R6xx/R7xx: Bugfix for wait_vline_range + + Check if CurrentiMode is set, not if Active is true. + +commit c16e74a2d36781fee495a72005a2decfec0d1b91 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Feb 24 11:06:32 2009 -0500 + + R6xx/R7xx EXA: optimize overlapping copy using temp surface + + - allocate temp surface in PrepareCopy() + - fallback to old OverlapCopy() path is we're not able to + allocate a temp surface + +commit 435e159d5c15ff3f6631d038e02860681c541eb5 +Author: Mark van Doesburg <mark.vandoesburg@hetnet.nl> +Date: Tue Feb 24 11:01:56 2009 -0500 + + R6xx/R7xx EXA: use a temp surface for overlapping copies + +commit 0de4db723c4d9bd40dcaa7fd79b507f7fe9270aa +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Feb 24 10:10:08 2009 -0500 + + R6xx/R7xx EXA: switch to surface sync packet + +commit db97dd5db4f95c0c4e056a4a7c3e9055dce337c1 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Feb 24 03:11:36 2009 -0500 + + r7xx: Fix typo in cmd fifo mask + +commit 33a84c9b4fddc5bb396ec90b93e174e0a1a4f91b +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Feb 23 19:06:22 2009 -0500 + + R6xx/R7xx: add wait for idle MMIO path + +commit c2b2155fcc499a253bef99e2462369162640a37c +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Feb 23 18:35:04 2009 -0500 + + R6xx/R7xx: reset 3D state after VT switch + +commit ca198357d3f3f9906d35585f3e22bfd00e92d2ec +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Mon Feb 23 10:14:39 2009 -0500 + + R6xx/R7xx: Improve wait_vline_range + + Make shure the given crtc is active and the range we are waiting for is + in the visible area of this crtc. + +commit 793cebe3dccc176da1c326b6be979d63d09b3ba5 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Feb 18 20:23:55 2009 -0500 + + R6xx/R7xx EXA/Xv: properly deal with running out of vertex buffer space + + As noted by mhopf, if VGT_MAX/MIN_INDX, etc. regs change, you need to re-emit + CB blocks to avoid a hang. So, just set the VGT_MAX_INDX to a reasonably large value + in the default state and don't touch them when drawing. When we run out of VB space, + just draw the current buffer, grab a new one, and continue. + +commit ef9225f75d8376d1f648b1f673ee5f25fe40564c +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Feb 12 17:47:44 2009 -0500 + + R6xx/R7xx: switch to drm for wait for idle + + THIS REQUIRES AN UPDATED DRM + +commit 1442be75b3a8f72dbbd4c33b4c92d7754999e4b2 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Feb 12 15:16:27 2009 -0500 + + R6xx/R7xx EXA: handle running out of vertex space in the copy path + +commit e16691af2a4e35b14fbbc39aed1d527d21c80ad6 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Feb 12 15:09:15 2009 -0500 + + R6xx/R7xx EXA: properly handle non repeat cases in the texture setup + +commit 976d651b7f472ef44eecb8ef07b1ab8675418c19 +Author: Yang Zhao <yang@yangman.ca> +Date: Thu Feb 12 14:52:22 2009 -0500 + + R6xx/R7xx EXA: Further optimizations to overlapping copy + + Diagonal overlapping copies can be reduced to either horizontal- or + vertical-only offset, and the one with fewer copies is picked. + +commit f02dd7cbc523160aedaa21599234c58c53447dc1 +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Wed Feb 11 18:13:47 2009 -0500 + + R6xx/R7xx: Cleanup register definitions + + Comment every definition in r600_reg_r6xx.h and r600_reg_r7xx.h which + is also in rhd_regs.h, making it possible to include both files at the same + time. + +commit b9e0ef98ba846d8051e1ee7ad685e98394579493 +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Wed Feb 11 18:10:22 2009 -0500 + + R6xx/R7xx: Implements wait_vline_range + + Implements wait_vline_range function and use this in + R600DisplayTexturedVideo. Also fixes a nasty bug in "ereg". + + Based on radeon patch from Pierre Ossman. + +commit 47f375d7dee8a5291b87edc7d14238134be6ae15 +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Wed Feb 11 18:09:33 2009 -0500 + + R6xx/R7xx: Define WAIT_x constants for IT_WAIT_REG_MEM + + And also fix some compiler warnings. + +commit 936838143d5431f6a0b33c6a396ad0ff44cf9c35 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Feb 11 15:25:17 2009 -0500 + + R6xx/R7xx Xv: switch packed over to Yang's new shader code + +commit e315314c98ae7750fe5107625f35976697e4fa79 +Author: Yang Zhao <yang@yangman.ca> +Date: Mon Feb 9 22:28:03 2009 -0800 + + R6xx/R7xx Xv: Planar - Properly scale Y'CbCr values before converting to RGB + + According to MPEG-2 spec, Y' and Cb/Cr values are scaled to [16, 235] + and [16, 240], respectively, when packed into bytes. Properly take care + of the reverse scaling before translating to RGB. + + Conversion matrix has been simplified to remove 3rd column, as the fitting + to [-0.5, 0.5] can be done with scaling. + + Redundant MOV instructions were also removed, and now only 3 GPRs are + required. + +commit 8dc7161ce426fb3968bba02d62db0a9980b26197 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Feb 11 13:14:01 2009 -0500 + + R6xx/R7xx: be more verbose about what function ran out of VB space + +commit 78c0f342282a1105ec30305dc2a44324702b151e +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Feb 11 12:52:33 2009 -0500 + + R6xx/R7xx: move engine idle to sync function + +commit a04e5b212523d877cd6591c367125745c27049c7 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Feb 11 11:45:18 2009 -0500 + + R6xx/R7xx Xv: add support for packed uploads + +commit 4205f30ae97c4771078988c6494f82a0d7e1f8de +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Feb 11 11:40:23 2009 -0500 + + R6xx/R7xx Xv: Add native support for packed formats + +commit d4079f7a68392fe0486c0ea0ddd6f2ca6d376149 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Feb 10 19:38:12 2009 -0500 + + M82: Missed one in the previous commit + +commit 7ea3e14f4a3904ab2c5d858d26d23c793f393ade +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Feb 10 17:21:02 2009 -0500 + + R6xx/R7xx: fix M82 + + M82 is an RV620 + +commit 47c57d1d994a9427b3e6068326eeb5971d2664cf +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Feb 9 19:57:30 2009 -0500 + + R6xx/R7xx: Add checks to make sure we don't overrun VB space + +commit 531de3518857e585c869c1d4c004ff2174984389 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Feb 9 14:09:24 2009 -0500 + + R6xx/R7xx Xv: switch to native planar shader and add accelerated planar uploads + +commit 4e574120feec720dc1086596bf1b2a315a1f1e0e +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Feb 9 13:33:13 2009 -0500 + + R6xx/R7xx UTS: move actual upload to separate function + + So it can be shared with Xv + +commit 916a3a08255aeda24987ae32cc1369c0c10b7bcd +Author: Yang Zhao <yang@yangman.ca> +Date: Sat Feb 7 13:42:22 2009 -0500 + + R6xx/R7xx EXA: Optimize overlapping copy + + Overlapping copy is now done in chunks proportional to the + non-overlapping area. + + Diagonal overlaps are also handled properly. + +commit 295648454253f98e30e3680e8c9dd94c91bde6bb +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Sat Feb 7 10:34:12 2009 -0500 + + R6xx/R7xx Xv: fix typos in cache flushing + +commit fab5c673418a44aafb0314766ce0edc25740c51d +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Fri Feb 6 18:31:14 2009 -0500 + + R6xx/R7xx EXA: Fix typo in DFS + + noticed by pzad in IRC + +commit 8f7fca4bbe8e3d29026f8cf603602e09f00af9e3 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Fri Feb 6 18:04:43 2009 -0500 + + R6xx/R7xx EXA: fallback on overlapping blits for now + + Leave this disabled until we get a proper solution. + +commit 4120d13a4e1f84a97903c839193b39acbab0b5c9 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Fri Feb 6 17:56:42 2009 -0500 + + Revert "r6xx/r7xx EXA: Optimize overlapping copy" + + This reverts commit 262126ef7292a851bcb757462615c015639e50d7. + + This is also not adequate for all cases. + +commit f1b9c19683090272a29a3e4c9e2c054b4a32b47c +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Fri Feb 6 11:17:02 2009 -0500 + + R6xx/R7xx EXA: add accelerated UTS/DFS hooks + + I'm not sure how much of a win these are. I need to + do some benchmarking. + +commit 8f90a3432e0f234b4c0f778aed31367b3dc4110d +Author: Yang Zhao <yang@yangman.ca> +Date: Fri Feb 6 10:28:39 2009 -0500 + + r6xx/r7xx EXA: Optimize overlapping copy + + When source and destination blocks are only offset horizontally, it + appears to be unnecessary to perform careful, segment-by-segment copy. + The code path that does this is taken out completely. + + For the case where offset is only vertical, copying is now done by + height of the non-overlapping area each time, instead of always + line-by-line. + +commit c725d146e333930e410733073b88849e8fb91bf2 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Feb 5 19:26:12 2009 -0500 + + Revert "R6xx/R7xx EXA: improve overlapping copy performance" + + This reverts commit bd28b5817ed96e86a2cb275f72a7233d8fc5eccc. + + THis seems to cause corruption in some cases. + +commit 7ef8c0b06522477cc2abcc2c9f1fa65efd2fab02 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Feb 5 17:33:36 2009 -0500 + + r6xx/r7xx EXA: fix corruption when doing sw access + + need to wait until the engine is idle. Ideally we wait + on a timestamp shadowed in memory, but polling the + GRBM_STATUS reg will do for now. + +commit f0ac61a002debc29442492229c1465fe55d2a791 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Feb 5 16:25:06 2009 -0500 + + R6xx/R7xx EXA: improve overlapping copy performance + + send vertices for each line of the copy, but only draw once + +commit 9f160eaadb944bc80a62cc03195a3245cae2df2a +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Feb 5 16:12:28 2009 -0500 + + r6xx/r7xx EXA: cleanup overlapping copy + +commit 4d20f2ce1b3a248ebf7093b7b8c35f87dd1ec673 +Author: Christian Koenig <deathsimple@vodafone.de> +Date: Wed Feb 4 19:24:44 2009 -0500 + + Fix RHDDRIGARTBaseGet to work with AGP based card + + Remove a check in RHDDRIGARTBaseGet makes AGP based r6xx card working, + and also fix a minor debugging output typo. + +commit a5c129abb9e9ff9484c468056766f7281d8bc56e +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Feb 3 18:16:06 2009 -0500 + + EXA: fix and re-enable Solid() on R7xx + + last bit was set in final alu instruction. + +commit 59fa04881f598602a3163070c62349a3ec65f242 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Feb 2 16:38:05 2009 -0500 + + Updates the comments about SPI setup for Solid() + +commit ded1312e6478ca205d5b5f0c470e24cc77405436 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Feb 2 16:20:36 2009 -0500 + + R7xx: temporarily disable Solid() to prevent hangs + + Something about using a PS constant for color seems to + disagree with some r7xx cards. + +commit f723ad4a591c3940373566c56f8d03a01ddee67f +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Feb 2 16:08:00 2009 -0500 + + EXA solid fixes + + - fix fetch count in solid VS + - fix SPI PS input setup (we aren't using any VS outputs) + - always have at least one VS export besides position, even if + it's not used by the PS (SPI expects at least one). + +commit 53c1b328bda7103c06fa4545f72976ab71abce10 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Feb 2 11:34:09 2009 -0500 + + R6xx/R7xx: Avoid emitting default state when possible + +commit b32618d0c1799ed12ca4c2eaf96dde2700785ef5 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Feb 2 11:08:24 2009 -0500 + + Add R6xx/R7xx AGP support + + - Needs latest drm bits + - doesn't seem to be as reliable as PCIE + +commit 8ae410b1d9a7a19477c00794047eadf5c5400ff6 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Sat Jan 31 15:37:06 2009 -0500 + + Fix and enable composite mask + + bad offset into the vertex buffer for the mask coordinates + +commit 1a3fe25e9def5fa8f371d3a2c96566318ed4a195 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Fri Jan 30 20:22:07 2009 -0500 + + EXA: Remove repeat tile code + + As far as I can tell from documentation and experimentation, + all the clamp modes work fine with NPOT or POT textures. + +commit 84a7741e21c0293a4ac1c8693fc6010c2ff5c869 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Fri Jan 30 14:30:58 2009 -0500 + + EXA: Re-enable a8 solid and copy. + + it's just masks with repeat that are broken. + +commit efbd11d434f4b9327effa5792b219c3ba3505abe +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Jan 29 13:50:42 2009 -0500 + + R6xx/R7xx: move some VGT setup to drm + + This fixes accel on rs780/rv610/rv620, etc. + VGT_OUT_DEALLOC_CNTL and VGT_VERTEX_REUSE_BLOCK_CNTL + are set up based on the backend config so set them up + in the drm and forget them. + + YOU MUST UPDATE YOUR DRM! + +commit 8f4ab199975a76597dcf354996822af8816433d5 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Jan 29 13:06:41 2009 -0500 + + Discard command buffers when nothing is drawn + + This fixes hangs on r7xx. + + Changing the same SQ constant (ALU, VTX/TEX, etc.) + more than once between draw calls can result in a hang. + +commit cea356d9b0b89b34659c729e4781497fd81bee88 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 28 19:33:04 2009 -0500 + + switch to R600PitchMatches() due to changes in pitch alignment + + render repeat modes seem the be the last thing left to getting + this working properly + +commit 381ca1a2a1b9b05d41e07f7d0548da753b66753e +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 28 17:26:09 2009 -0500 + + EXA Composite: add a bit of missing state setup + +commit 68311d8865152bee1ffe1f1233ccde51a18bf4d3 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 28 02:34:25 2009 -0500 + + minor code re-org + +commit e6c753f409fbddfbd8f706061743d1d486de672d +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 28 02:31:01 2009 -0500 + + removed leftover vertex color param export + +commit 16b6e8d30db237acd354fc717d15939c45a6e095 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 28 02:16:44 2009 -0500 + + EXA: fix mask coordinate export + +commit f808fe852596c9a6d6742bd19d2bb972b2268dec +Author: Ludovic Aubry <ludovic.aubry@logilab.fr> +Date: Wed Jan 28 00:37:12 2009 -0500 + + use correct mask resource and sampler id + +commit c1db8638979e5e47eb580f0ebcf1b2db7043888b +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Jan 27 11:58:59 2009 -0500 + + Remove Xv vertex debugging output + +commit a4bfc7f0695db02dcea3bc07bf042b4b08930eb3 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Jan 26 20:46:04 2009 -0500 + + R6xx/R7xx: workaround text rendering issues + + - disable a8 acceleration until I figure out why it's not working properly + - disable DFS/UTS hooks. they are still SW at the moment anyway. + - fix pitch alignment (width has to be a multiple of 8, + bytes have to be a multiple of 256) + - fix height (height has to be a multiple of 8) + +commit 3b692f8ac29562d0b9b73037cd2b4dcf7a715adf +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Fri Jan 23 17:43:57 2009 -0500 + + R6xx/R7xx: add missing TEX instruction padding + +commit 43f54aa6c5014fcb81871d681b877f20673bccdb +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Jan 22 20:20:45 2009 -0500 + + R6xx/R7xx: flush TC on chips without VC + + On chips without a dedicated vertex cache, + the texture cache is used for vertexes and textures. + +commit f6315d535c0084771030884bad8894008902d318 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Jan 22 19:44:47 2009 -0500 + + R6xx/R7xx: get the SQ setup right + + based on info from the hw guys + +commit b6351dc4079cc343e865ce6dab8e7dbde552274c +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Jan 22 16:55:31 2009 -0500 + + Add missing return in PrepareAccess() + +commit a73ed442270077d9b148993ed1061224161c7e2f +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Jan 22 13:04:06 2009 -0500 + + R6xx:R7xx: add fine grained cache flushing support + + - also flush HDP caches when doing sw access + +commit 5c4b2c38f23076d5f829212c165c207f5140e153 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Sat Jan 17 15:51:34 2009 -0500 + + R6xx/R7xx: adjust SQ setup + +commit 73c131156b0beb9de214f68d08e5eddec46e8c2a +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 14 18:01:43 2009 -0500 + + R6xx/R7xx: add chip specific SQ setup + +commit 2dc272e8cee1df99dbf127a76bcfd28dbb0f0cd0 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 14 16:20:29 2009 -0500 + + R6xx/r7xx: re-arrange some code, adjust exa offset align + +commit 1f7e164ef9af7d18b4a7645983ca5b119460d676 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 14 15:06:51 2009 -0500 + + R6xx/r7xx: pull in fixes from r3xx render code + +commit ff359a560864c2ac7ba6e3d2e05ffaac036bb354 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 14 14:27:09 2009 -0500 + + r6xx:r7xx: load composite vertex shaders once + + rather than for each op. PS still need to be per op. + +commit 65d0304c20813dd7e764bdfc20108046c08fca65 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 14 14:16:58 2009 -0500 + + r6xx/r7xx: switch to different vertex buffer formats for composite + + mask vs no mask case + +commit b1d88bb197eabbcb6942e00656ccf5c2ef4fee90 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 14 13:38:12 2009 -0500 + + R6xx/r7xx: switch solid/copy/xv to static shaders + + load the shaders at startup rather than at each op + +commit 2e91043719efd0a60df6f1b33316da3b423aed1b +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 14 12:22:41 2009 -0500 + + R6xx/r7xx: use an alu const for solid color + + avoid sending the color with each vertex + +commit ebe31f230d00ce431124ee368833f8411a8f28dc +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 14 11:46:48 2009 -0500 + + R6xx/R7xx: clamp color values + +commit 10f3e75c31b8bd77b5545dc5010d51b49a0a7787 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Jan 12 19:00:27 2009 -0500 + + R6xx/r7xx: fix planemask handling + +commit 6224636d20a82964b3efe7d6754f14da55a8724f +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Jan 12 17:38:27 2009 -0500 + + R6xx/R7xx: use consistent swizzling and PS elem ordering + + - seems to fix up most text issues + - also remove some composite debugging + - masks still have issues + +commit 7e2dbeeb5c91f3d627f3486f9a360227bbf5bf6a +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Sat Jan 10 12:43:11 2009 -0500 + + R6xx/R7xx: fix bad GPR in mask PS + + noticed by Aidan Thornton (makomk on IRC) + +commit 969d8866465c1e7761880153b0dc60fedccab3cd +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Fri Jan 9 16:28:46 2009 -0500 + + R6xx/r7xx: use flat shading for solid() + +commit 75e108ca45fb5c76eed53c99ca6ebc6c5cb60c9e +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Fri Jan 9 15:40:46 2009 -0500 + + fix return type for R600DoPrepareCopy() + +commit 56a816a9328b5b5f43b4c97271a3af4f38a50cce +Author: Kevin Cody Jr <kcodyjr@gmail.com> +Date: Fri Jan 9 15:39:50 2009 -0500 + + Warning fixes + + See bug 19364 + +commit d096cef8bb2cf6d14031a6d2165a8f17af523197 +Author: Maciej Cencora <m.cencora@gmail.com> +Date: Fri Jan 9 15:11:38 2009 -0500 + + Don't crash if user selected EXA on R6xx, and no CS is available. + +commit decbd958d9fb8f7ed6af42c0c08047111bf8c770 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Fri Jan 9 15:07:34 2009 -0500 + + R6xx/r7xx: fix packed Xv formats + + - convert to nv12 + - also fix bad ordering in planar conversion + + Next step is to convert to native format specific shaders + +commit 54011f6a59592a8f4a3a22808f5eff8367348846 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Jan 8 17:44:45 2009 -0500 + + R6xx/R7xx: fix alignment + + pitch needs to be a multiple of 128 rather than 64 since + UV is pitch/2 + +commit dd2e8176f5d0fbb8f566c659f11a88a39b64ee63 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Jan 8 17:15:45 2009 -0500 + + R6xx/R7xx: Get Xv working (at least for me) + + - updated conversion matrix and swizzle fixes from Aidan Thornton + (makomk on IRC) + - set comp swap to 1 in the CB. shader to CB component ordering seems + to be ABGR rather than ARGB which would explain some of the other issues with EXA. + setting comp swap to 1 changes the ordering from ABGR to ARGB + +commit 09a2e6256ce2bbeb9eadc1a17908b196b7de17b0 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Thu Jan 8 16:06:00 2009 -0500 + + R6xx/r7xx Xv: fix pitch issues + + Image displays properly, but color components are wrong + +commit 781acf8dd217c79ac7b1b05558cdbf7291cc28d9 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 7 18:54:43 2009 -0500 + + R6/7xx Xv: fixup pitches + +commit 7be036736d8dc5ac30ee4f28002a4344d11cf6d3 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 7 16:57:50 2009 -0500 + + R6xx/R7xx: write to right offset in constant space + + PS consts start at offset 0, VS start at offset 256 + +commit 57c7090bdf23d7bd81d2e6d25e43be076e0baeea +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Wed Jan 7 16:01:04 2009 -0500 + + R6xx/R7xx: minor fixes + + - swizzle unused tex components to 0 + - we use 4 gprs in the PS not 3 + Xv still not working + +commit 4ed346d03b312ce789b8b8476250cc612cffb02e +Author: Hans Ulrich Niedermann <hun@n-dimensional.de> +Date: Thu Jan 1 14:08:06 2009 +0100 + + drm header mismatch port (6c91fed6 for r6xx-) + + Workaround for drm header mismatches (DEPRECATED and __user on Fedora + 10), now also in new file src/r6xx_accel.c. + +commit 35b5c2aafeaede89a70595a1a2cd33732757fa1c +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Dec 30 19:03:06 2008 -0500 + + R6xx/R7xx: adjust shader program state setup + +commit 949cb4bc7f3eb65424818b673a573b792360d9a3 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Dec 30 18:27:04 2008 -0500 + + R6xx/R7xx: VS_EXPORT_COUNT is n - 1, not n + +commit 05712027f2f78489f40a9c36b6d5fe13228259a5 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Dec 30 18:13:12 2008 -0500 + + R6xx/R7xx: fixup SPI setup + + Properly route export params from VS to PS + should probably switch to sematic defines to make the code easier + to follow. + +commit 863d5a30108d976ecac57a955d32d781b0eda169 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Dec 30 12:16:49 2008 -0500 + + R6xx AGP not currently supported + + don't try to init the dri + +commit b94b84016a89c50710a468646fb0461b30f19160 +Author: Hans Ulrich Niedermann <hun@n-dimensional.de> +Date: Tue Dec 30 12:17:05 2008 +0100 + + Ship all R6xx files in dist tarball + + Without these files, compiling a dist tarball will fail. + +commit da2d49ee054c3de8d9d73dcf9a3b2c8528ade2bd +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Dec 29 18:03:29 2008 -0500 + + Fix the build on some platforms + + Noticed by Michael Larabel on IRC + +commit 07cb75ebe7b476f9b6e4676e9a1233f44df95a0c +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Mon Dec 29 16:00:38 2008 -0500 + + R6xx/R7xx: Add initial EXA/Xv support + + First pass at r6xx/r7xx EXA and Xv support. This release + is mostly targeted at developers as the code is not really + ready for regular users. + + Current status: + - lack of direction blitter makes overlapping copy blits difficult. + current code breaks down overlapping blits into line by line + blits of non-overlapping regions. running xcompmgr -a is highly + recommended. + - a8 solids have issues + - planar Xv shader implemented, but not working properly yet + - missing Xv shader support for packed formats. should be easy to + adapt the planar Xv shader once that is working + - composite mask support is currently broken. I suspect the interpolater + setup. + - depth 16 is untested + +commit 047bd7059bcfec55e06a35db4a2b16d52fe8dbf6 +Author: Matthias Hopf <mhopf@suse.de> +Date: Wed Feb 25 16:54:24 2009 +0100 + + EXA: fix for (incompatible) upstream EXA version 3. + +commit ad6c789ad321e56cabdaf826d661ff53ef460e59 +Author: Matthias Hopf <mhopf@suse.de> +Date: Thu Feb 19 12:37:37 2009 +0100 + + (Hopefully) fix cursor corruptions, at least on some configs. fdo #13405 + + Yang Zhao found (already in November...) that enabling the HW cursor on all + CRTCs irrelevant of visibility fixes this issue on some configurations. + + This is a workaround until a real solution is known. + +commit c7735333c2e6c075f085a1f8d54d72f80e748730 +Author: Matthias Hopf <mhopf@suse.de> +Date: Tue Feb 17 17:24:33 2009 +0100 + + Fix some warnings. + +commit a5a7b08553e8dad505f983028b0a926b8af13db2 +Author: Matthias Hopf <mhopf@suse.de> +Date: Tue Feb 17 17:17:06 2009 +0100 + + Fix warning: only compile rhdRRCrtcSetOrigin() if required for RandR 1.3. + +commit 368bb0d792ee078cef2c78b1ea6b95b9eb1edb51 +Author: Yang Zhao <yang@yangman.ca> +Date: Tue Jan 13 19:38:00 2009 -0800 + + LUT: Fix incorrect shifts and masks for 15- and 16-bit depth + + Input values to LUTxSet() can be assumed to have the correct precision. + Shifting beyond the 10-bit boundaries give incorrect results. + +commit 4d208cdd38f7f5b595c71c77c62cbfac4c591bba +Author: Yang Zhao <yang@yangman.ca> +Date: Fri Jan 2 19:58:28 2009 -0800 + + Fix LUT precision handling for 8, 24, and 32bit depth + + Properly advertise 10bit precision for LUT entries, and adjust + truncation routines appropriately. + + Also fix rhdRRCrtcGammaSet() path such that it does not pass on 16-bit + precision entries onto LUTxSet() + +commit 6e71f01f225a0cb13d10c7f7960db9d20c89a7db +Author: Yang Zhao <yang@yangman.ca> +Date: Fri Jan 2 14:20:56 2009 -0800 + + rhd_dump: add LUT printing support + + rhd_dump -l {0|1} <pci_id> + + Argument to -l is lower and upper half of LUT for 0 and 1, respectively + +commit ed86b90a8379dd02430c3f3c6ce732f91f1f56f7 +Author: Matthias Hopf <mhopf@suse.de> +Date: Wed Feb 4 18:46:35 2009 +0100 + + Add missing definition of atom_Panel. + +commit b76bfbd7fdd5f0522962329653d12942b3dd6560 +Author: Matthias Hopf <mhopf@suse.de> +Date: Thu Jan 29 19:14:00 2009 +0100 + + Add 'force-shadowfb' AccelMethod. For testing purposes only. + + force-shadowfb will force shadowfb even if DRI is enabled. The driver + currently will spill out Damage events for DRI updates, which will overdraw + the rendered image immediately. + This is mostly useful for development of r600_demo, which programs the chip + directly, and will thus not create Damage events. + +commit 95aa911390bc9cece16ec999f79f548ea963e754 +Author: Egbert Eich <eich@freedesktop.org> +Date: Thu Jan 22 12:46:49 2009 +0100 + + AtomBIOS: Fix build for build w --disable-atombios-parser. + + This also removes commit f45e95cc37a2a9ddf72f5d59a27dd8df152b3ed5 + as --enable-atombios --disable-atombios-parser is in fact a valid + combination. + +commit c349a5238f00435c0617898a7fa1600686d7d5ff +Author: Matthias Hopf <mhopf@suse.de> +Date: Wed Jan 21 18:13:22 2009 +0100 + + Trivial typo in properties / man page. + +commit 68c317dafcc2bb30db17fbe6b9da7fcd05cd07cc +Author: Matthias Hopf <mhopf@suse.de> +Date: Tue Jan 20 12:55:36 2009 +0100 + + Unify and fix quirk table macros. + + Some were obviously wrong, some didn't stick to the standard naming scheme. + +commit e216e6863028f464982adb56cb989a6ecc5c327a +Author: Matthias Hopf <mhopf@suse.de> +Date: Tue Jan 20 12:10:28 2009 +0100 + + Add quirk table entry for HIS Radeon X1550 PCI. + +commit f45e95cc37a2a9ddf72f5d59a27dd8df152b3ed5 +Author: Hans Ulrich Niedermann <hun@n-dimensional.de> +Date: Thu Jan 15 13:30:30 2009 +0100 + + build: catch incompatible options in configure + + The configure option combination of + --enable-atombios --disable-atombios-parser + does not make sense with the radeonhd source code. + + We now have configure abort with an error message to that + effect instead of just letting the build fail later. + +commit e738e579a2da857a21fcf2bed8bc8faff8281744 +Author: Maciej Cencora <m.cencora@gmail.com> +Date: Tue Jan 13 13:07:14 2009 +0100 + + Quirk for PowerColor HD 3450. + + Set HPD detection to off. + +commit 127d362c960edc0c126fd8ebad4726d9c441d98f +Author: Egbert Eich <eich@freedesktop.org> +Date: Tue Jan 13 13:05:54 2009 +0100 + + I2C: Fix NULL pointer deference spotted by Maciej Cencora. + +commit 1652f150063cfa996581ec01a7a1e0563aba8749 +Author: Egbert Eich <eich@freedesktop.org> +Date: Tue Jan 13 11:59:27 2009 +0100 + + Build: Fix build when AtomBIOS subsystem is disabled. + +commit a981e2d0bfd732fe9af012b0b164534ea48c7e53 +Author: Alan Coopersmith <alan.coopersmith@sun.com> +Date: Fri Jan 9 16:32:34 2009 -0800 + + Remove xorgconfig & xorgcfg from See Also list in man page + +commit f57a410cd9f56d0cf336af84576342730998a5be +Author: Matthias Hopf <mhopf@suse.de> +Date: Wed Jan 7 19:53:45 2009 +0100 + + Fix scaling documentation. + +commit 4472020908c189cb35def46eda738adeed945cb4 +Author: Alex Deucher <alexdeucher@gmail.com> +Date: Tue Jan 6 18:21:41 2009 -0500 + + RS780: set bustype to PCIE + + Fixes DRI support + +commit 421edfd70cab0123d3e530bb590e88846cd20437 +Author: Luc Verhaegen <libv@skynet.be> +Date: Wed Dec 31 16:29:32 2008 +0100 + + MC: Fix warnings and streamline naming of MCGetFBLocation. + +commit 28956656d5f27b555714f3073fe5c181ed525d3b +Author: Luc Verhaegen <libv@skynet.be> +Date: Wed Dec 31 15:42:20 2008 +0100 + + Card quirks: fix warning introduced in b2e2693d + +commit 5eed0c4f0f3a60c8d1b51f71401b48f32b330955 +Author: Luc Verhaegen <libv@skynet.be> +Date: Wed Dec 31 15:41:10 2008 +0100 + + ID: add 0x944C (RV770). + + Reported by Michael Larabel. + +commit b2e2693d3393e14ccbbbd1e0b01553ce94eba0a8 +Author: Thomas Vander Stichele <thomas@apestaart.org> +Date: Tue Dec 30 14:29:10 2008 +0100 + + Add quirk table entry for GeCube Radeon HD 2400PRO + +commit 003325a56684649171b2c1af50aa490b1461ee16 +Author: Matthias Hopf <mhopf@suse.de> +Date: Thu Dec 18 17:14:16 2008 +0100 + + Implement RandR 1.3 mandatory properties. + +commit 33bf07be141b43b85d611d72ffe7bf9d7c313b39 +Author: Matthias Hopf <mhopf@suse.de> +Date: Wed Dec 17 18:43:13 2008 +0100 + + Renamed properties according to RandR 1.3 property guideline. + + SignalFormat and ConnectorType still return strings, and not Atoms, though. + +commit c990d6d781845709b30eb5fccadf812fe280277e +Author: Hans Ulrich Niedermann <hun@n-dimensional.de> +Date: Mon Dec 15 14:15:49 2008 +0100 + + Typo fix in man page + +commit 107c97a6cc128a3f491f5f7612acdabc2ca72273 +Author: Hans Ulrich Niedermann <hun@n-dimensional.de> +Date: Mon Dec 15 14:11:12 2008 +0100 + + Change all gitweb URL references to cgit + +commit 0b47e600cb1a0c5ed25e70269030b1d47e057e42 +Author: Hans Ulrich Niedermann <hun@n-dimensional.de> +Date: Sun Dec 14 23:29:53 2008 +0100 + + man page: Add R7xx to NAME section + +commit d46d50e69679bd892becfde961fb104f86cf7728 +Author: Egbert Eich <eich@freedesktop.org> +Date: Sat Dec 6 17:31:41 2008 +0100 + + MC: Pass FbLocation and FbSize to RHDMCFBLocationSetup(). + + This allows to change the value if needed. + Also clean up some names. + +commit 0fd284c01473572ca4a882d6a33c3a9ce0a14bef +Author: Egbert Eich <eich@freedesktop.org> +Date: Thu Dec 4 09:35:58 2008 +0100 + + MC/Idle: ASSERT() the right setup order, don't change an unidled MC. + + AllIdle() needs to be called before MCSetup() to make sure the + MC is idle. We can only idle the MC when the VGA subsystem is + disabled which happens in VGADisable() which therefore needs + to be called first. + If we are not idle in MCSetup() we fail without setting up the MC. + If MCSetup() fails we bail. If the MC is not idle during restore + we don't restore the MC. + + Conflicts: + +commit eeb66dc94417da000b90ec1b954bfa0fe0f3e36d +Author: Luc Verhaegen <libv@skynet.be> +Date: Fri Dec 12 17:57:02 2008 +0100 + + MC: Refactor MC code. + + * Simplify device specific code, order code per device. + * Remove the RV515 flag for RV515 specific callbacks. + * Conditionally run ->Restore and ->Setup depending on ->Idle, complain + when not Idle. This replaces the hard ASSERTS on register content. + * Document possible ->Idle failure reasons. + * MC Addresses are CARD64 now, the and possible consequences are + * documented. + * Clean up VGAFB Address reading and allocation/memcpy. + * Use ASSERTS for rhdPtr->MC (MC code) and rhdPtr->MapBase (VGA memcpy) + where needed. + commit 4e8972638db59d007bc61eb1bef8adb99cc67000 Author: Matthias Hopf <mhopf@suse.de> Date: Fri Dec 12 15:10:29 2008 +0100 diff --git a/driver/xf86-video-radeonhd/Makefile.am b/driver/xf86-video-radeonhd/Makefile.am index d445acc34..decd0aa19 100644 --- a/driver/xf86-video-radeonhd/Makefile.am +++ b/driver/xf86-video-radeonhd/Makefile.am @@ -1,4 +1,4 @@ -# Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> +# Copyright 2007 Luc Verhaegen <libv@exsuse.de> # Copyright 2007 Matthias Hopf <mhopf@novell.com> # Copyright 2007 Egbert Eich <eich@novell.com> # Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/Makefile.in b/driver/xf86-video-radeonhd/Makefile.in index 21a18220d..18ba296dd 100644 --- a/driver/xf86-video-radeonhd/Makefile.in +++ b/driver/xf86-video-radeonhd/Makefile.in @@ -14,7 +14,7 @@ @SET_MAKE@ -# Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> +# Copyright 2007 Luc Verhaegen <libv@exsuse.de> # Copyright 2007 Matthias Hopf <mhopf@novell.com> # Copyright 2007 Egbert Eich <eich@novell.com> # Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/README b/driver/xf86-video-radeonhd/README index 6f9d27fee..6ca6b2088 100644 --- a/driver/xf86-video-radeonhd/README +++ b/driver/xf86-video-radeonhd/README @@ -87,6 +87,18 @@ Major Changes Read ChangeLog for a complete list. +- Version 1.2.5 + + - Added 2D acceleration for R6xx and R7xx. + - Added XVideo support for R6xx and R7xx. + - Added support for RS880 and RV790. + - Added RandR 1.3 mandatory properties. + - Refactoring of MC code. + - Enable DRI support by default on R5xx and RS6xx. + - LUT (color lookup table) fixes. + - Tons of quirk table entries and bug fixes. + - Fix register accesses for processors that reorder memory writes. + - Version 1.2.4 - Added HDMI support. @@ -165,7 +177,7 @@ The mailing list on radeonhd: http://lists.opensuse.org/radeonhd/ Overview over recent updates to radeonhd: - http://gitweb.freedesktop.org/?p=xorg/driver/xf86-video-radeonhd + http://cgit.freedesktop.org/xorg/driver/xf86-video-radeonhd/ The git repository with the radeonhd source code: git://anongit.freedesktop.org/git/xorg/driver/xf86-video-radeonhd diff --git a/driver/xf86-video-radeonhd/aclocal.m4 b/driver/xf86-video-radeonhd/aclocal.m4 index a3a3008cb..3ec9c2c92 100644 --- a/driver/xf86-video-radeonhd/aclocal.m4 +++ b/driver/xf86-video-radeonhd/aclocal.m4 @@ -7631,6 +7631,7 @@ AC_SUBST([am__tar]) AC_SUBST([am__untar]) ]) # _AM_PROG_TAR +dnl xorg-macros.m4. Generated from xorg-macros.m4.in:xorgversion.m4 by configure. dnl dnl Copyright 2005-2006 Sun Microsystems, Inc. All rights reserved. dnl @@ -7678,7 +7679,7 @@ AC_DEFUN([XORG_MACROS_VERSION],[ XORG_MACROS_needed_major=`echo $XORG_MACROS_needed_version | sed 's/\..*$//'` XORG_MACROS_needed_minor=`echo $XORG_MACROS_needed_version | sed -e 's/^[0-9]*\.//' -e 's/\..*$//'`] AC_MSG_CHECKING([if xorg-macros used to generate configure is at least ${XORG_MACROS_needed_major}.${XORG_MACROS_needed_minor}]) - [XORG_MACROS_version=1.1.6 + [XORG_MACROS_version=1.2.1 XORG_MACROS_major=`echo $XORG_MACROS_version | sed 's/\..*$//'` XORG_MACROS_minor=`echo $XORG_MACROS_version | sed -e 's/^[0-9]*\.//' -e 's/\..*$//'`] if test $XORG_MACROS_major -ne $XORG_MACROS_needed_major ; then @@ -7712,6 +7713,10 @@ else if test `${RAWCPP} -undef < conftest.$ac_ext | grep -c 'unix'` -eq 1 ; then RAWCPPFLAGS=-undef AC_MSG_RESULT([yes]) + # under Cygwin unix is still defined even with -undef + elif test `${RAWCPP} -undef -ansi < conftest.$ac_ext | grep -c 'unix'` -eq 1 ; then + RAWCPPFLAGS="-undef -ansi" + AC_MSG_RESULT([yes, with -ansi]) else AC_MSG_ERROR([${RAWCPP} defines unix with or without -undef. I don't know what to do.]) fi @@ -7824,7 +7829,9 @@ AC_SUBST([ADMIN_MAN_DIR]) # Whether or not the necessary tools and files are found can be checked # with the AM_CONDITIONAL "BUILD_LINUXDOC" AC_DEFUN([XORG_CHECK_LINUXDOC],[ -XORG_SGML_PATH=$prefix/share/sgml +if test x$XORG_SGML_PATH = x ; then + XORG_SGML_PATH=$prefix/share/sgml +fi HAVE_DEFS_ENT= if test x"$cross_compiling" = x"yes" ; then @@ -7880,7 +7887,9 @@ AC_SUBST(MAKE_HTML) # indicates whether the necessary tools and files are found and, if set, # $(MAKE_XXX) blah.sgml will produce blah.xxx. AC_DEFUN([XORG_CHECK_DOCBOOK],[ -XORG_SGML_PATH=$prefix/share/sgml +if test x$XORG_SGML_PATH = x ; then + XORG_SGML_PATH=$prefix/share/sgml +fi HAVE_DEFS_ENT= BUILDTXTDOC=no BUILDPDFDOC=no @@ -8057,55 +8066,31 @@ AM_CONDITIONAL(MAKE_LINT_LIB, [test x$make_lint_lib != xno]) ]) # XORG_LINT_LIBRARY -dnl Copyright 2005 Red Hat, Inc -dnl -dnl Permission to use, copy, modify, distribute, and sell this software and its -dnl documentation for any purpose is hereby granted without fee, provided that -dnl the above copyright notice appear in all copies and that both that -dnl copyright notice and this permission notice appear in supporting -dnl documentation. -dnl -dnl The above copyright notice and this permission notice shall be included -dnl in all copies or substantial portions of the Software. -dnl -dnl THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -dnl OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -dnl MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -dnl IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR -dnl OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -dnl ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -dnl OTHER DEALINGS IN THE SOFTWARE. -dnl -dnl Except as contained in this notice, the name of the copyright holders shall -dnl not be used in advertising or otherwise to promote the sale, use or -dnl other dealings in this Software without prior written authorization -dnl from the copyright holders. -dnl - -# XORG_DRIVER_CHECK_EXT() -# -------------------------- -# Checks for the $1 define in xorg-server.h (from the sdk). If it -# is defined, then add $1 to $REQUIRED_MODULES. - -AC_DEFUN([XORG_DRIVER_CHECK_EXT],[ - SAVE_CFLAGS="$CFLAGS" - CFLAGS="$CFLAGS -I`pkg-config --variable=sdkdir xorg-server`" - AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ -#include "xorg-server.h" -#if !defined $1 -#error $1 not defined -#endif - ]])], - [_EXT_CHECK=yes], - [_EXT_CHECK=no]) - CFLAGS="$SAVE_CFLAGS" - AC_MSG_CHECKING([if $1 is defined]) - AC_MSG_RESULT([$_EXT_CHECK]) - if test "$_EXT_CHECK" != no; then - REQUIRED_MODULES="$REQUIRED_MODULES $2" - fi -]) - +# XORG_CWARNFLAGS +# --------------- +# Minimum version: 1.2.0 +# +# Defines CWARNFLAGS to enable C compiler warnings. +# +AC_DEFUN([XORG_CWARNFLAGS], [ +AC_REQUIRE([AC_PROG_CC]) +if test "x$GCC" = xyes ; then + CWARNFLAGS="-Wall -Wpointer-arith -Wstrict-prototypes -Wmissing-prototypes \ +-Wmissing-declarations -Wnested-externs -fno-strict-aliasing \ +-Wbad-function-cast" + case `gcc -dumpversion` in + 3.4.* | 4.*) + CWARNFLAGS+=" -Wold-style-definition -Wdeclaration-after-statement" + ;; + esac +else + AC_CHECK_DECL([__SUNPRO_C], [SUNCC="yes"], [SUNCC="no"]) + if test "x$SUNCC" = "xyes"; then + CWARNFLAGS="-v" + fi +fi +AC_SUBST(CWARNFLAGS) +]) # XORG_CWARNFLAGS dnl Copyright 2005 Red Hat, Inc dnl dnl Permission to use, copy, modify, distribute, and sell this software and its @@ -8168,3 +8153,69 @@ AC_DEFUN([XORG_RELEASE_VERSION],[ [Patch version of this package]) ]) +# XORG_CHANGELOG() +# ---------------- +# Minimum version: 1.2.0 +# +# Defines the variable CHANGELOG_CMD as the command to generate +# ChangeLog from git. +# +# Arrange that distcleancheck ignores ChangeLog left over by distclean. +# +AC_DEFUN([XORG_CHANGELOG], [ +CHANGELOG_CMD="(GIT_DIR=\$(top_srcdir)/.git git log > .changelog.tmp && \ +mv .changelog.tmp ChangeLog) || (rm -f .changelog.tmp; touch ChangeLog; \ +echo 'git directory not found: installing possibly empty changelog.' >&2)" +AC_SUBST([CHANGELOG_CMD]) +AC_SUBST([distcleancheck_listfiles], ['find . -type f ! -name ChangeLog -print']) +]) # XORG_CHANGELOG + +dnl Copyright 2005 Red Hat, Inc +dnl +dnl Permission to use, copy, modify, distribute, and sell this software and its +dnl documentation for any purpose is hereby granted without fee, provided that +dnl the above copyright notice appear in all copies and that both that +dnl copyright notice and this permission notice appear in supporting +dnl documentation. +dnl +dnl The above copyright notice and this permission notice shall be included +dnl in all copies or substantial portions of the Software. +dnl +dnl THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +dnl OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +dnl MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +dnl IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +dnl OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +dnl ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +dnl OTHER DEALINGS IN THE SOFTWARE. +dnl +dnl Except as contained in this notice, the name of the copyright holders shall +dnl not be used in advertising or otherwise to promote the sale, use or +dnl other dealings in this Software without prior written authorization +dnl from the copyright holders. +dnl + +# XORG_DRIVER_CHECK_EXT() +# -------------------------- +# Checks for the $1 define in xorg-server.h (from the sdk). If it +# is defined, then add $1 to $REQUIRED_MODULES. + +AC_DEFUN([XORG_DRIVER_CHECK_EXT],[ + SAVE_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS -I`pkg-config --variable=sdkdir xorg-server`" + AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ +#include "xorg-server.h" +#if !defined $1 +#error $1 not defined +#endif + ]])], + [_EXT_CHECK=yes], + [_EXT_CHECK=no]) + CFLAGS="$SAVE_CFLAGS" + AC_MSG_CHECKING([if $1 is defined]) + AC_MSG_RESULT([$_EXT_CHECK]) + if test "$_EXT_CHECK" != no; then + REQUIRED_MODULES="$REQUIRED_MODULES $2" + fi +]) + diff --git a/driver/xf86-video-radeonhd/configure b/driver/xf86-video-radeonhd/configure index e9abf0837..3c9370561 100644 --- a/driver/xf86-video-radeonhd/configure +++ b/driver/xf86-video-radeonhd/configure @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.59 for xf86-video-radeonhd 1.2.4. +# Generated by GNU Autoconf 2.59 for xf86-video-radeonhd 1.2.5. # # Report bugs to <https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/radeonhd>. # @@ -423,8 +423,8 @@ SHELL=${CONFIG_SHELL-/bin/sh} # Identity of this package. PACKAGE_NAME='xf86-video-radeonhd' PACKAGE_TARNAME='xf86-video-radeonhd' -PACKAGE_VERSION='1.2.4' -PACKAGE_STRING='xf86-video-radeonhd 1.2.4' +PACKAGE_VERSION='1.2.5' +PACKAGE_STRING='xf86-video-radeonhd 1.2.5' PACKAGE_BUGREPORT='https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/radeonhd' ac_unique_file="Makefile.am" @@ -990,7 +990,7 @@ if test "$ac_init_help" = "long"; then # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures xf86-video-radeonhd 1.2.4 to adapt to many kinds of systems. +\`configure' configures xf86-video-radeonhd 1.2.5 to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1056,7 +1056,7 @@ fi if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of xf86-video-radeonhd 1.2.4:";; + short | recursive ) echo "Configuration of xf86-video-radeonhd 1.2.5:";; esac cat <<\_ACEOF @@ -1220,7 +1220,7 @@ fi test -n "$ac_init_help" && exit 0 if $ac_init_version; then cat <<\_ACEOF -xf86-video-radeonhd configure 1.2.4 +xf86-video-radeonhd configure 1.2.5 generated by GNU Autoconf 2.59 Copyright (C) 2003 Free Software Foundation, Inc. @@ -1234,7 +1234,7 @@ cat >&5 <<_ACEOF This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by xf86-video-radeonhd $as_me 1.2.4, which was +It was created by xf86-video-radeonhd $as_me 1.2.5, which was generated by GNU Autoconf 2.59. Invocation command line was $ $0 $@ @@ -1837,7 +1837,7 @@ fi # Define the identity of the package. PACKAGE='xf86-video-radeonhd' - VERSION='1.2.4' + VERSION='1.2.5' cat >>confdefs.h <<_ACEOF @@ -19609,6 +19609,7 @@ echo "${ECHO_T}yes" >&6 fi sdkdir=$(pkg-config --variable=sdkdir xorg-server) + # Header files checks. echo "$as_me:$LINENO: checking for ANSI C header files" >&5 echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6 @@ -22398,7 +22399,7 @@ _ASBOX } >&5 cat >&5 <<_CSEOF -This file was extended by xf86-video-radeonhd $as_me 1.2.4, which was +This file was extended by xf86-video-radeonhd $as_me 1.2.5, which was generated by GNU Autoconf 2.59. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -22461,7 +22462,7 @@ _ACEOF cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ -xf86-video-radeonhd config.status 1.2.4 +xf86-video-radeonhd config.status 1.2.5 configured by $0, generated by GNU Autoconf 2.59, with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\" diff --git a/driver/xf86-video-radeonhd/configure.ac b/driver/xf86-video-radeonhd/configure.ac index 85a552083..c31f10adc 100644 --- a/driver/xf86-video-radeonhd/configure.ac +++ b/driver/xf86-video-radeonhd/configure.ac @@ -2,7 +2,7 @@ AC_PREREQ(2.57) AC_INIT([xf86-video-radeonhd], - 1.2.4, + 1.2.5, [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/radeonhd], xf86-video-radeonhd) @@ -78,6 +78,7 @@ XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto) PKG_CHECK_MODULES(XORG, [xorg-server xproto fontsproto $REQUIRED_MODULES]) sdkdir=$(pkg-config --variable=sdkdir xorg-server) + # Header files checks. AC_HEADER_STDC diff --git a/driver/xf86-video-radeonhd/ltmain.sh b/driver/xf86-video-radeonhd/ltmain.sh index 248cd4047..fccf69e28 100644 --- a/driver/xf86-video-radeonhd/ltmain.sh +++ b/driver/xf86-video-radeonhd/ltmain.sh @@ -2127,17 +2127,6 @@ EOF ;; esac for pass in $passes; do - # The preopen pass in lib mode reverses $deplibs; put it back here - # so that -L comes before libs that need it for instance... - if test "$linkmode,$pass" = "lib,link"; then - ## FIXME: Find the place where the list is rebuilt in the wrong - ## order, and fix it there properly - tmp_deplibs= - for deplib in $deplibs; do - tmp_deplibs="$deplib $tmp_deplibs" - done - deplibs="$tmp_deplibs" - fi if test "$linkmode,$pass" = "lib,link" || test "$linkmode,$pass" = "prog,scan"; then libs="$deplibs" diff --git a/driver/xf86-video-radeonhd/man/Makefile.in b/driver/xf86-video-radeonhd/man/Makefile.in index c47e112ca..25c1e7efa 100644 --- a/driver/xf86-video-radeonhd/man/Makefile.in +++ b/driver/xf86-video-radeonhd/man/Makefile.in @@ -14,7 +14,7 @@ @SET_MAKE@ -# $Id: Makefile.in,v 1.8 2009/01/28 14:43:56 matthieu Exp $ +# $Id: Makefile.in,v 1.9 2009/04/26 13:59:41 matthieu Exp $ # # Copyright 2005 Sun Microsystems, Inc. All rights reserved. # diff --git a/driver/xf86-video-radeonhd/man/radeonhd.man b/driver/xf86-video-radeonhd/man/radeonhd.man index 90cafce82..e7a4d9914 100644 --- a/driver/xf86-video-radeonhd/man/radeonhd.man +++ b/driver/xf86-video-radeonhd/man/radeonhd.man @@ -7,7 +7,7 @@ .\" .\" .SH NAME -radeonhd \- AMD GPG (ATI) R5xx/R6xx video driver +radeonhd \- AMD GPG (ATI) R5xx/R6xx/R7xx video driver .\" .\" .SH SYNOPSIS @@ -30,9 +30,7 @@ has the following limitations: .\".TP "\w'\fB\(bu\fR'u+1n" .TP 2 \(bu -On R6xx and R7xx based cards: -.B NO -support for hardware-based 2D & 3D acceleration, no support for Xvideo. +Support for hardware-based 2D acceleration and Xvideo needs more testing on R6xx and R7xx based cards. .TP \(bu No TV and Component connector support so far. @@ -231,10 +229,12 @@ Rotation isn't supported for the AccelMethods \*qnone\*q and \*qshadowfb\*q. .RE .TP .BI "Option \*qDRI\*q" -Use this option to enable 3D and Xv acceleration using DRI -(R5xx and RS6xx chips only for the moment). +Use this option to enable 3D and Xv acceleration using DRI. Currently, the default is -.BR off . +.B on +on R5xx and RS6xx chips, and +.B off +on all others. .TP .BI "Option \*qOffscreenSize\*q \*q" <integer>M|<integer>% \*q Specify the amount of framebuffer memory used for offscreen pixmaps, in @@ -245,7 +245,7 @@ is .TP .BI "Option \*qScaleType\*q \*q" none|center|scale|scale_keep_aspect_ratio|default \*q Sets the scaling mode for laptop flat panels when used together with an external -screen. The scaling engine is capable of scaling both up and down.i +screen. The scaling engine is capable of scaling both up and down. .RS .TP 9 .PD 0 @@ -256,8 +256,8 @@ the panel resolution. .TP .B center means not to scale but center the image on the panel i.e. apply a black frame -around the image on the panel in case the panel resolution is lower than the -one of the external display. +around the image on the panel if the resolution of the external display is +lower than the panel resolution. .TP .B scale means to always scale to the resolution of the external display filling @@ -399,13 +399,13 @@ mailing list. .RE .TP .BI "Option \*qAudio\*q \*q" boolean \*q -This option enables the audio hardware, wich is responsible for delivering audio data +This option enables the audio hardware, which is responsible for delivering audio data to the different HDMI capable conntectors and used to communicate with the audio driver of the operation system. The default is .BR off . .TP -.BI "Option \*qHDMI\*q \*q" boolean \*q -Possible values are "DVI-I 0", "DVI-I 1"..,"DVI-D 0","DVI-I 1",.., "all". +.BI "Option \*qHDMI\*q \*q" string \*q +Possible values are "DVI-I_0", "DVI-I_1"..,"DVI-D_0","DVI-I_1",.., "all". This option enables HDMI-Audio and HDMI-Info packets on the specified connector. This is the only way enabling HDMI at the moment, since decoding E-EDID data to check if monitor supports HDMI is not implemented (yet). .TP @@ -477,12 +477,12 @@ The following properties can be queried with .B xrandr --prop and some of them can be set with .BR "xrandr --output" " <output> " --set " <property> <value> ." -Those marked with RR13 will be merged into a RandR 1.3 standard, though -substantially changed. Properties marked Read-Only are provided by the driver -for informational purpose only, those marked Static won't change during -runtime. +Those not starting with an underscore '_' are RandR 1.3 standard properties. +See the RandR 1.3 protocol description for more details. Properties marked +Read-Only are provided by the driver for informational purpose only, those +marked Static won't change during runtime. .TP -.BR RANDR_SIGNAL_FORMAT " Read-Only RR13" +.BR SignalFormat " Read-Only" .RS .TP 16 .PD 0 @@ -490,24 +490,16 @@ runtime. string .TP .IR Range/List : -unknown VGA TMDS LVDS FBAS FBAS-PAL FBAS-NTSC FBAS-SECAM SVideo YPbPr -DisplayPort +unknown VGA TMDS LVDS DisplayPort .RE .RS .PD .PP Signal format / physical protocol format that is used for the specified output. -.br -A driver MAY change this property of an output if the underlying hardware -indicates a protocol change (e.g. TV formats). Values with dashes -.RI ( FBAS-PAL ) -describe more specific versions of the base values -.RI ( FBAS ) -and SHOULD be used if known to the driver. .RE .TP -.BR RANDR_CONNECTOR_TYPE " Read-Only Static RR13" +.BR ConnectorType " Read-Only Static" .RS .TP 16 .PD 0 @@ -515,38 +507,17 @@ and SHOULD be used if known to the driver. string .TP .IR Range/List : -unknown VGA DVI DVI-I DVI-A DVI-D HDMI PANEL TV TV-FBAS TV-SVideo TV-YPbPr -TV-SCART TV-C4 DisplayPort +unknown VGA DVI DVI-I DVI-A DVI-D HDMI Panel DisplayPort .RE .RS .PD .PP Connector type, as far as known to the driver. -.br -Values with dashes -.RI ( TV-FBAS ) -describe more specific versions of the base values -.RI ( TV ). -The former SHOULD be used if the connector is not capable of producing other -signal formats. The later SHOULD be used if the exact connector is unknown, or -the connector is a multi-format connector that is not described otherwise. -.IR DVI , -for instance, SHOULD be handled like a -.I DVI-I -connector, unless additional information is available to the user agent. -.I PANEL +.I Panel describes laptop-internal (normally LVDS) displays. -.IR TV , -.IR TV-SCART , -.IR TV-YPbPr , -and -.I TV-C4 -with signal format -.I VGA -are valid combinations and describe RGB TV signals. .RE .TP -.BR RANDR_CONNECTOR_NUMBER " Read-Only Static RR13" +.BR ConnectorNumber " Read-Only Static" .RS .TP 16 .PD 0 @@ -562,15 +533,10 @@ int32 Outputs that route their signal to the same connector MUST have the same connector number. Outputs with the same connector number MUST route their signal to the same connector, except if it is 0, which indicates unknown -connectivity. 1 is called the primary connector, 2 the secondary. 3 is often a -TV connector, but that is completely driver / hardware dependent. -.br -Outputs with the same connector number SHOULD have the same connector type. -Meaning and client behavior for mismatching connector types is undefined at -the moment. +connectivity. .RE .TP -.BR RANDR_OUTPUT_NUMBER " Read-Only Static RR13" +.BR _OutputNumber " Read-Only Static" .RS .TP 16 .PD 0 @@ -593,7 +559,7 @@ Internal outputs are numbered from 1, 0 indicates that output routing is unknown. .RE .TP -.B RANDR_PANNING_AREA +.B _PanningArea .RS .TP 16 .PD 0 @@ -623,6 +589,40 @@ Use of this option is considered deprecated. The driver supports .B RandR 1.3 panning, which is included in Xserver 1.6. It is considerable more flexible, and should support rotated pans. +.RE +.TP +.B _Backlight +.RS +.TP 16 +.PD 0 +.IR Type : +int32 +.TP +.IR Range/List : +0-255 +.RE +.RS +.PD +.PP +Specifies the backlight intensity on laptop panels, if controlable by the driver. +.RE +.TP +.B _Coherent +.RS +.TP 16 +.PD 0 +.IR Type : +int32 +.TP +.IR Range/List : +0-1 +.RE +.RS +.PD +.PP +Sets the coherent flag for TMDS signals. See also +.I Option +.IR "Coherent" . .\" .\" .SH KNOWN BUGS @@ -651,7 +651,7 @@ on the xrandr(__appmansuffix__) command line. .\" .\" .SH SEE ALSO -__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) +__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) .IP " 1." 4 The official radeonhd wiki .RS 4 @@ -665,7 +665,7 @@ The radeonhd mailing list .IP " 3." 4 Overview about radeonhd development code .RS 4 -\%http://gitweb.freedesktop.org/?p=xorg/driver/xf86-video-radeonhd +\%http://cgit.freedesktop.org/xorg/driver/xf86-video-radeonhd/ .RE .IP " 4." 4 Query the bugtracker for radeonhd bugs diff --git a/driver/xf86-video-radeonhd/src/Makefile.am b/driver/xf86-video-radeonhd/src/Makefile.am index be944a4f5..7156d63bd 100644 --- a/driver/xf86-video-radeonhd/src/Makefile.am +++ b/driver/xf86-video-radeonhd/src/Makefile.am @@ -23,6 +23,13 @@ radeonhd_drv_la_SOURCES = \ r5xx_accel.h \ r5xx_regs.h \ r5xx_xaa.c \ + r600_reg.h \ + r600_reg_auto_r6xx.h \ + r600_reg_r6xx.h \ + r600_reg_r7xx.h \ + r600_shader.h \ + r600_shader.c \ + r600_state.h \ radeon_3d.c \ radeon_textured_videofuncs.c \ rhd_atombios.c \ @@ -89,6 +96,8 @@ endif if USE_DRI radeonhd_drv_la_SOURCES += rhd_dri.c rhd_dri.h radeon_dri.h radeon_drm.h +radeonhd_drv_la_SOURCES += r6xx_accel.c r6xx_accel.h +radeonhd_drv_la_SOURCES += r600_exa.c r600_textured_videofuncs.c radeonhd_drv_la_LIBADD += @DRI_LIBS@ endif diff --git a/driver/xf86-video-radeonhd/src/Makefile.in b/driver/xf86-video-radeonhd/src/Makefile.in index 722eeabbf..4755d6c12 100644 --- a/driver/xf86-video-radeonhd/src/Makefile.in +++ b/driver/xf86-video-radeonhd/src/Makefile.in @@ -45,7 +45,9 @@ DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ $(top_srcdir)/RadeonHD.am @XSERVER_LIBPCIACCESS_TRUE@am__append_1 = @PCIACCESS_LIBS@ @USE_EXA_TRUE@am__append_2 = r5xx_exa.c radeon_exa_render.c -@USE_DRI_TRUE@am__append_3 = rhd_dri.c rhd_dri.h radeon_dri.h radeon_drm.h +@USE_DRI_TRUE@am__append_3 = rhd_dri.c rhd_dri.h radeon_dri.h \ +@USE_DRI_TRUE@ radeon_drm.h r6xx_accel.c r6xx_accel.h \ +@USE_DRI_TRUE@ r600_exa.c r600_textured_videofuncs.c @USE_DRI_TRUE@am__append_4 = @DRI_LIBS@ @ATOM_BIOS_TRUE@am__append_5 = \ @ATOM_BIOS_TRUE@ AtomBios/includes/atombios.h @@ -96,7 +98,9 @@ am__DEPENDENCIES_1 = radeonhd_drv_la_DEPENDENCIES = $(am__DEPENDENCIES_1) \ $(am__DEPENDENCIES_1) $(am__DEPENDENCIES_2) am__radeonhd_drv_la_SOURCES_DIST = r5xx_3dregs.h r5xx_accel.c \ - r5xx_accel.h r5xx_regs.h r5xx_xaa.c radeon_3d.c \ + r5xx_accel.h r5xx_regs.h r5xx_xaa.c r600_reg.h \ + r600_reg_auto_r6xx.h r600_reg_r6xx.h r600_reg_r7xx.h \ + r600_shader.h r600_shader.c r600_state.h radeon_3d.c \ radeon_textured_videofuncs.c rhd_atombios.c rhd_atombios.h \ rhd_atomcrtc.c rhd_atomout.c rhd_atomout.h rhd_atompll.c \ rhd_audio.c rhd_audio.h rhd_biosscratch.c rhd_biosscratch.h \ @@ -110,13 +114,19 @@ am__radeonhd_drv_la_SOURCES_DIST = r5xx_3dregs.h r5xx_accel.c \ rhd_randr.h rhd_regs.h rhd_shadow.c rhd_shadow.h rhd_tmds.c \ rhd_vga.c rhd_vga.h rhd_video.c rhd_video.h r5xx_exa.c \ radeon_exa_render.c rhd_dri.c rhd_dri.h radeon_dri.h \ - radeon_drm.h AtomBios/includes/atombios.h rhd_atomwrapper.h + radeon_drm.h r6xx_accel.c r6xx_accel.h r600_exa.c \ + r600_textured_videofuncs.c AtomBios/includes/atombios.h \ + rhd_atomwrapper.h @USE_EXA_TRUE@am__objects_1 = radeonhd_drv_la-r5xx_exa.lo \ @USE_EXA_TRUE@ radeonhd_drv_la-radeon_exa_render.lo -@USE_DRI_TRUE@am__objects_2 = radeonhd_drv_la-rhd_dri.lo +@USE_DRI_TRUE@am__objects_2 = radeonhd_drv_la-rhd_dri.lo \ +@USE_DRI_TRUE@ radeonhd_drv_la-r6xx_accel.lo \ +@USE_DRI_TRUE@ radeonhd_drv_la-r600_exa.lo \ +@USE_DRI_TRUE@ radeonhd_drv_la-r600_textured_videofuncs.lo am__objects_3 = am_radeonhd_drv_la_OBJECTS = radeonhd_drv_la-r5xx_accel.lo \ - radeonhd_drv_la-r5xx_xaa.lo radeonhd_drv_la-radeon_3d.lo \ + radeonhd_drv_la-r5xx_xaa.lo radeonhd_drv_la-r600_shader.lo \ + radeonhd_drv_la-radeon_3d.lo \ radeonhd_drv_la-radeon_textured_videofuncs.lo \ radeonhd_drv_la-rhd_atombios.lo \ radeonhd_drv_la-rhd_atomcrtc.lo radeonhd_drv_la-rhd_atomout.lo \ @@ -325,20 +335,22 @@ radeonhd_drv_la_CFLAGS = $(AM_CFLAGS) @PEDANTIC_CFLAGS@ radeonhd_drv_la_LIBADD = $(am__append_1) $(am__append_4) \ $(am__append_7) radeonhd_drv_la_SOURCES = r5xx_3dregs.h r5xx_accel.c r5xx_accel.h \ - r5xx_regs.h r5xx_xaa.c radeon_3d.c \ - radeon_textured_videofuncs.c rhd_atombios.c rhd_atombios.h \ - rhd_atomcrtc.c rhd_atomout.c rhd_atomout.h rhd_atompll.c \ - rhd_audio.c rhd_audio.h rhd_biosscratch.c rhd_biosscratch.h \ - rhd_card.h rhd_connector.c rhd_connector.h rhd_crtc.c \ - rhd_crtc.h rhd_cs.c rhd_cs.h rhd_cursor.c rhd_cursor.h \ - rhd_dac.c rhd_ddia.c rhd_dig.c rhd_driver.c rhd_edid.c rhd.h \ - rhd_hdmi.c rhd_hdmi.h rhd_helper.c rhd_i2c.c rhd_i2c.h \ - rhd_id.c rhd_lut.c rhd_lut.h rhd_lvtma.c rhd_mc.c rhd_mc.h \ - rhd_modes.c rhd_modes.h rhd_monitor.c rhd_monitor.h \ - rhd_output.c rhd_output.h rhd_pll.c rhd_pll.h rhd_randr.c \ - rhd_randr.h rhd_regs.h rhd_shadow.c rhd_shadow.h rhd_tmds.c \ - rhd_vga.c rhd_vga.h rhd_video.c rhd_video.h $(am__append_2) \ - $(am__append_3) $(am__append_5) $(am__append_6) + r5xx_regs.h r5xx_xaa.c r600_reg.h r600_reg_auto_r6xx.h \ + r600_reg_r6xx.h r600_reg_r7xx.h r600_shader.h r600_shader.c \ + r600_state.h radeon_3d.c radeon_textured_videofuncs.c \ + rhd_atombios.c rhd_atombios.h rhd_atomcrtc.c rhd_atomout.c \ + rhd_atomout.h rhd_atompll.c rhd_audio.c rhd_audio.h \ + rhd_biosscratch.c rhd_biosscratch.h rhd_card.h rhd_connector.c \ + rhd_connector.h rhd_crtc.c rhd_crtc.h rhd_cs.c rhd_cs.h \ + rhd_cursor.c rhd_cursor.h rhd_dac.c rhd_ddia.c rhd_dig.c \ + rhd_driver.c rhd_edid.c rhd.h rhd_hdmi.c rhd_hdmi.h \ + rhd_helper.c rhd_i2c.c rhd_i2c.h rhd_id.c rhd_lut.c rhd_lut.h \ + rhd_lvtma.c rhd_mc.c rhd_mc.h rhd_modes.c rhd_modes.h \ + rhd_monitor.c rhd_monitor.h rhd_output.c rhd_output.h \ + rhd_pll.c rhd_pll.h rhd_randr.c rhd_randr.h rhd_regs.h \ + rhd_shadow.c rhd_shadow.h rhd_tmds.c rhd_vga.c rhd_vga.h \ + rhd_video.c rhd_video.h $(am__append_2) $(am__append_3) \ + $(am__append_5) $(am__append_6) nodist_radeonhd_drv_la_SOURCES = \ git_version.h @@ -453,6 +465,10 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonhd_drv_la-r5xx_accel.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonhd_drv_la-r5xx_exa.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonhd_drv_la-r5xx_xaa.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonhd_drv_la-r600_exa.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonhd_drv_la-r600_shader.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonhd_drv_la-r600_textured_videofuncs.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonhd_drv_la-r6xx_accel.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonhd_drv_la-radeon_3d.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonhd_drv_la-radeon_exa_render.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonhd_drv_la-radeon_textured_videofuncs.Plo@am__quote@ @@ -552,6 +568,13 @@ radeonhd_drv_la-r5xx_xaa.lo: r5xx_xaa.c @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(radeonhd_drv_la_CFLAGS) $(CFLAGS) -c -o radeonhd_drv_la-r5xx_xaa.lo `test -f 'r5xx_xaa.c' || echo '$(srcdir)/'`r5xx_xaa.c +radeonhd_drv_la-r600_shader.lo: r600_shader.c +@am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(radeonhd_drv_la_CFLAGS) $(CFLAGS) -MT radeonhd_drv_la-r600_shader.lo -MD -MP -MF "$(DEPDIR)/radeonhd_drv_la-r600_shader.Tpo" -c -o radeonhd_drv_la-r600_shader.lo `test -f 'r600_shader.c' || echo '$(srcdir)/'`r600_shader.c; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/radeonhd_drv_la-r600_shader.Tpo" "$(DEPDIR)/radeonhd_drv_la-r600_shader.Plo"; else rm -f "$(DEPDIR)/radeonhd_drv_la-r600_shader.Tpo"; exit 1; fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='r600_shader.c' object='radeonhd_drv_la-r600_shader.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(radeonhd_drv_la_CFLAGS) $(CFLAGS) -c -o radeonhd_drv_la-r600_shader.lo `test -f 'r600_shader.c' || echo '$(srcdir)/'`r600_shader.c + radeonhd_drv_la-radeon_3d.lo: radeon_3d.c @am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(radeonhd_drv_la_CFLAGS) $(CFLAGS) -MT radeonhd_drv_la-radeon_3d.lo -MD -MP -MF "$(DEPDIR)/radeonhd_drv_la-radeon_3d.Tpo" -c -o radeonhd_drv_la-radeon_3d.lo `test -f 'radeon_3d.c' || echo '$(srcdir)/'`radeon_3d.c; \ @am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/radeonhd_drv_la-radeon_3d.Tpo" "$(DEPDIR)/radeonhd_drv_la-radeon_3d.Plo"; else rm -f "$(DEPDIR)/radeonhd_drv_la-radeon_3d.Tpo"; exit 1; fi @@ -804,6 +827,27 @@ radeonhd_drv_la-rhd_dri.lo: rhd_dri.c @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(radeonhd_drv_la_CFLAGS) $(CFLAGS) -c -o radeonhd_drv_la-rhd_dri.lo `test -f 'rhd_dri.c' || echo '$(srcdir)/'`rhd_dri.c +radeonhd_drv_la-r6xx_accel.lo: r6xx_accel.c +@am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(radeonhd_drv_la_CFLAGS) $(CFLAGS) -MT radeonhd_drv_la-r6xx_accel.lo -MD -MP -MF "$(DEPDIR)/radeonhd_drv_la-r6xx_accel.Tpo" -c -o radeonhd_drv_la-r6xx_accel.lo `test -f 'r6xx_accel.c' || echo '$(srcdir)/'`r6xx_accel.c; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/radeonhd_drv_la-r6xx_accel.Tpo" "$(DEPDIR)/radeonhd_drv_la-r6xx_accel.Plo"; else rm -f "$(DEPDIR)/radeonhd_drv_la-r6xx_accel.Tpo"; exit 1; fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='r6xx_accel.c' object='radeonhd_drv_la-r6xx_accel.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(radeonhd_drv_la_CFLAGS) $(CFLAGS) -c -o radeonhd_drv_la-r6xx_accel.lo `test -f 'r6xx_accel.c' || echo '$(srcdir)/'`r6xx_accel.c + +radeonhd_drv_la-r600_exa.lo: r600_exa.c +@am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(radeonhd_drv_la_CFLAGS) $(CFLAGS) -MT radeonhd_drv_la-r600_exa.lo -MD -MP -MF "$(DEPDIR)/radeonhd_drv_la-r600_exa.Tpo" -c -o radeonhd_drv_la-r600_exa.lo `test -f 'r600_exa.c' || echo '$(srcdir)/'`r600_exa.c; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/radeonhd_drv_la-r600_exa.Tpo" "$(DEPDIR)/radeonhd_drv_la-r600_exa.Plo"; else rm -f "$(DEPDIR)/radeonhd_drv_la-r600_exa.Tpo"; exit 1; fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='r600_exa.c' object='radeonhd_drv_la-r600_exa.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(radeonhd_drv_la_CFLAGS) $(CFLAGS) -c -o radeonhd_drv_la-r600_exa.lo `test -f 'r600_exa.c' || echo '$(srcdir)/'`r600_exa.c + +radeonhd_drv_la-r600_textured_videofuncs.lo: r600_textured_videofuncs.c +@am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(radeonhd_drv_la_CFLAGS) $(CFLAGS) -MT radeonhd_drv_la-r600_textured_videofuncs.lo -MD -MP -MF "$(DEPDIR)/radeonhd_drv_la-r600_textured_videofuncs.Tpo" -c -o radeonhd_drv_la-r600_textured_videofuncs.lo `test -f 'r600_textured_videofuncs.c' || echo '$(srcdir)/'`r600_textured_videofuncs.c; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/radeonhd_drv_la-r600_textured_videofuncs.Tpo" "$(DEPDIR)/radeonhd_drv_la-r600_textured_videofuncs.Plo"; else rm -f "$(DEPDIR)/radeonhd_drv_la-r600_textured_videofuncs.Tpo"; exit 1; fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='r600_textured_videofuncs.c' object='radeonhd_drv_la-r600_textured_videofuncs.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(radeonhd_drv_la_CFLAGS) $(CFLAGS) -c -o radeonhd_drv_la-r600_textured_videofuncs.lo `test -f 'r600_textured_videofuncs.c' || echo '$(srcdir)/'`r600_textured_videofuncs.c + mostlyclean-libtool: -rm -f *.lo diff --git a/driver/xf86-video-radeonhd/src/git_version.h b/driver/xf86-video-radeonhd/src/git_version.h index 25508ac50..a98f5f5d6 100644 --- a/driver/xf86-video-radeonhd/src/git_version.h +++ b/driver/xf86-video-radeonhd/src/git_version.h @@ -14,13 +14,13 @@ /* git utilities found */ #undef GIT_NOT_FOUND -#define GIT_VERSION "git version 1.5.6" +#define GIT_VERSION "git version 1.6.0.2" /* git repo found */ #define GIT_REPO 1 /* Git SHA ID of last commit */ -#define GIT_SHAID "4e897263" +#define GIT_SHAID "cb54f48b" /* Branch this tree is on */ #define GIT_BRANCH "master" diff --git a/driver/xf86-video-radeonhd/src/r5xx_accel.c b/driver/xf86-video-radeonhd/src/r5xx_accel.c index 0b098c894..d7b94e042 100644 --- a/driver/xf86-video-radeonhd/src/r5xx_accel.c +++ b/driver/xf86-video-radeonhd/src/r5xx_accel.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2008 Egbert Eich <eich@novell.com> * Copyright 2008 Advanced Micro Devices, Inc. @@ -121,9 +121,10 @@ R5xxFIFOWait(RHDPtr rhdPtr, CARD32 required) static Bool R5xx2DFlush(int scrnIndex) { + ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; int i; - _RHDRegMask(scrnIndex, R5XX_DSTCACHE_CTLSTAT, + RHDRegMask(pScrn, R5XX_DSTCACHE_CTLSTAT, /* Radeon code: R5XX_RB2D_DC_FLUSH_ALL, R5XX_RB2D_DC_FLUSH_ALL */ R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL); @@ -131,11 +132,11 @@ R5xx2DFlush(int scrnIndex) for (i = 0; i < R5XX_LOOP_COUNT; i++) /* Radeon code: & R5XX_RB2D_DC_BUSY */ - if (!(_RHDRegRead(scrnIndex, R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY)) + if (!(RHDRegRead(pScrn, R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY)) return TRUE; xf86DrvMsg(scrnIndex, X_ERROR, "%s: Timeout 0x%08x.\n", __func__, - (unsigned int)_RHDRegRead(scrnIndex, R5XX_DSTCACHE_CTLSTAT)); + (unsigned int) RHDRegRead(pScrn, R5XX_DSTCACHE_CTLSTAT)); return FALSE; } diff --git a/driver/xf86-video-radeonhd/src/r5xx_accel.h b/driver/xf86-video-radeonhd/src/r5xx_accel.h index 83461ef4a..50e44b3a9 100644 --- a/driver/xf86-video-radeonhd/src/r5xx_accel.h +++ b/driver/xf86-video-radeonhd/src/r5xx_accel.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2008 Egbert Eich <eich@novell.com> * Copyright 2008 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/r5xx_exa.c b/driver/xf86-video-radeonhd/src/r5xx_exa.c index 848fcb954..36e91ad45 100644 --- a/driver/xf86-video-radeonhd/src/r5xx_exa.c +++ b/driver/xf86-video-radeonhd/src/r5xx_exa.c @@ -2,7 +2,7 @@ * Copyright 2005 Eric Anholt * Copyright 2005 Benjamin Herrenschmidt * Copyright 2006 Tungsten Graphics, Inc. - * Copyright 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2008 Egbert Eich <eich@novell.com> * @@ -32,7 +32,7 @@ * Zack Rusin <zrusin@trolltech.com> * Benjamin Herrenschmidt <benh@kernel.crashing.org> * Michel Dänzer <michel@tungstengraphics.com> - * Luc Verhaegen <libv@skynet.be> + * Luc Verhaegen <libv@exsuse.de> * */ @@ -73,7 +73,7 @@ struct R5xxExaPrivate { int exaSyncMarker; int exaMarkerSynced; #if X_BYTE_ORDER == X_BIG_ENDIAN - unsigned long swapper_surfaces[3]; + unsigned long swapper_surfaces[6]; #endif /* X_BYTE_ORDER */ }; @@ -780,7 +780,11 @@ R5xxEXAInit(ScrnInfoPtr pScrn, ScreenPtr pScreen) EXAInfo->exa_major = EXA_VERSION_MAJOR; EXAInfo->exa_minor = EXA_VERSION_MINOR; - EXAInfo->flags = EXA_OFFSCREEN_PIXMAPS; + EXAInfo->flags = EXA_OFFSCREEN_PIXMAPS +#ifdef EXA_SUPPORTS_PREPARE_AUX + | EXA_SUPPORTS_PREPARE_AUX +#endif + ; EXAInfo->pixmapOffsetAlign = 0x1000; EXAInfo->pixmapPitchAlign = 64; diff --git a/driver/xf86-video-radeonhd/src/r5xx_xaa.c b/driver/xf86-video-radeonhd/src/r5xx_xaa.c index bcfaca9aa..2d591c276 100644 --- a/driver/xf86-video-radeonhd/src/r5xx_xaa.c +++ b/driver/xf86-video-radeonhd/src/r5xx_xaa.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2008 Egbert Eich <eich@novell.com> * Copyright 2008 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/r600_exa.c b/driver/xf86-video-radeonhd/src/r600_exa.c new file mode 100644 index 000000000..86da7af2f --- /dev/null +++ b/driver/xf86-video-radeonhd/src/r600_exa.c @@ -0,0 +1,2150 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Author: Alex Deucher <alexander.deucher@amd.com> + * + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "xf86.h" + +#include "exa.h" + +#include "rhd.h" +#include "rhd_cs.h" +#include "r6xx_accel.h" +#include "r600_shader.h" +#include "r600_reg.h" +#include "r600_state.h" + +/* #define SHOW_VERTEXES */ + +# define RADEON_ROP3_ZERO 0x00000000 +# define RADEON_ROP3_DSa 0x00880000 +# define RADEON_ROP3_SDna 0x00440000 +# define RADEON_ROP3_S 0x00cc0000 +# define RADEON_ROP3_DSna 0x00220000 +# define RADEON_ROP3_D 0x00aa0000 +# define RADEON_ROP3_DSx 0x00660000 +# define RADEON_ROP3_DSo 0x00ee0000 +# define RADEON_ROP3_DSon 0x00110000 +# define RADEON_ROP3_DSxn 0x00990000 +# define RADEON_ROP3_Dn 0x00550000 +# define RADEON_ROP3_SDno 0x00dd0000 +# define RADEON_ROP3_Sn 0x00330000 +# define RADEON_ROP3_DSno 0x00bb0000 +# define RADEON_ROP3_DSan 0x00770000 +# define RADEON_ROP3_ONE 0x00ff0000 + +uint32_t RADEON_ROP[16] = { + RADEON_ROP3_ZERO, /* GXclear */ + RADEON_ROP3_DSa, /* Gxand */ + RADEON_ROP3_SDna, /* GXandReverse */ + RADEON_ROP3_S, /* GXcopy */ + RADEON_ROP3_DSna, /* GXandInverted */ + RADEON_ROP3_D, /* GXnoop */ + RADEON_ROP3_DSx, /* GXxor */ + RADEON_ROP3_DSo, /* GXor */ + RADEON_ROP3_DSon, /* GXnor */ + RADEON_ROP3_DSxn, /* GXequiv */ + RADEON_ROP3_Dn, /* GXinvert */ + RADEON_ROP3_SDno, /* GXorReverse */ + RADEON_ROP3_Sn, /* GXcopyInverted */ + RADEON_ROP3_DSno, /* GXorInverted */ + RADEON_ROP3_DSan, /* GXnand */ + RADEON_ROP3_ONE, /* GXset */ +}; + +static void +R600DoneSolid(PixmapPtr pPix); + +static void +R600DoneComposite(PixmapPtr pDst); + +static Bool +R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) +{ + ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + cb_config_t cb_conf; + shader_config_t vs_conf, ps_conf; + int pmask = 0; + uint32_t a, r, g, b; + float ps_alu_consts[4]; + + accel_state->dst_mc_addr = exaGetPixmapOffset(pPix) + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + accel_state->dst_size = exaGetPixmapPitch(pPix) * pPix->drawable.height; + accel_state->dst_pitch = exaGetPixmapPitch(pPix) / (pPix->drawable.bitsPerPixel / 8); + + /* bad pitch */ + if (accel_state->dst_pitch & 7) + return FALSE; + + /* bad offset */ + if (accel_state->dst_mc_addr & 0xff) + return FALSE; + + if (pPix->drawable.bitsPerPixel == 24) + return FALSE; + + CLEAR (cb_conf); + CLEAR (vs_conf); + CLEAR (ps_conf); + + /* return FALSE; */ + +#ifdef SHOW_VERTEXES + ErrorF("%dx%d @ %dbpp, 0x%08x\n", pPix->drawable.width, pPix->drawable.height, + pPix->drawable.bitsPerPixel, exaGetPixmapPitch(pPix)); +#endif + + accel_state->ib = RHDDRMCPBuffer(pScrn->scrnIndex); + + /* Init */ + start_3d(pScrn, accel_state->ib); + + /* cp_set_surface_sync(pScrn, accel_state->ib); */ + + set_default_state(pScrn, accel_state->ib); + + /* Scissor / viewport */ + EREG(accel_state->ib, PA_CL_VTE_CNTL, VTX_XY_FMT_bit); + EREG(accel_state->ib, PA_CL_CLIP_CNTL, CLIP_DISABLE_bit); + + accel_state->vs_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset + + accel_state->solid_vs_offset; + accel_state->ps_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset + + accel_state->solid_ps_offset; + accel_state->vs_size = 512; + accel_state->ps_size = 512; + + /* Shader */ + + /* flush SQ cache */ + cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit, + accel_state->vs_size, accel_state->vs_mc_addr); + + vs_conf.shader_addr = accel_state->vs_mc_addr; + vs_conf.num_gprs = 2; + vs_conf.stack_size = 0; + vs_setup (pScrn, accel_state->ib, &vs_conf); + + /* flush SQ cache */ + cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit, + accel_state->ps_size, accel_state->ps_mc_addr); + + ps_conf.shader_addr = accel_state->ps_mc_addr; + ps_conf.num_gprs = 1; + ps_conf.stack_size = 0; + ps_conf.uncached_first_inst = 1; + ps_conf.clamp_consts = 0; + ps_conf.export_mode = 2; + ps_setup (pScrn, accel_state->ib, &ps_conf); + + /* Render setup */ + if (pm & 0x000000ff) + pmask |= 4; /* B */ + if (pm & 0x0000ff00) + pmask |= 2; /* G */ + if (pm & 0x00ff0000) + pmask |= 1; /* R */ + if (pm & 0xff000000) + pmask |= 8; /* A */ + EREG(accel_state->ib, CB_SHADER_MASK, (pmask << OUTPUT0_ENABLE_shift)); + EREG(accel_state->ib, R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit)); + EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[alu]); + + + cb_conf.id = 0; + cb_conf.w = accel_state->dst_pitch; + cb_conf.h = pPix->drawable.height; + cb_conf.base = accel_state->dst_mc_addr; + + if (pPix->drawable.bitsPerPixel == 8) { + cb_conf.format = COLOR_8; + cb_conf.comp_swap = 3; /* A */ + } else if (pPix->drawable.bitsPerPixel == 16) { + cb_conf.format = COLOR_5_6_5; + cb_conf.comp_swap = 2; /* RGB */ + } else { + cb_conf.format = COLOR_8_8_8_8; + cb_conf.comp_swap = 1; /* ARGB */ + } + cb_conf.source_format = 1; + cb_conf.blend_clamp = 1; + set_render_target(pScrn, accel_state->ib, &cb_conf); + + EREG(accel_state->ib, PA_SU_SC_MODE_CNTL, (FACE_bit | + (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) | + (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift))); + EREG(accel_state->ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */ + DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */ + + /* Interpolator setup */ + /* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */ + EREG(accel_state->ib, SPI_VS_OUT_CONFIG, (0 << VS_EXPORT_COUNT_shift)); + EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift)); + + /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x + * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */ + /* no VS exports as PS input (NUM_INTERP is not zero based, no minus one) */ + EREG(accel_state->ib, SPI_PS_IN_CONTROL_0, (0 << NUM_INTERP_shift)); + EREG(accel_state->ib, SPI_PS_IN_CONTROL_1, 0); + /* color semantic id 0 -> GPR[0] */ + EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 <<2), ((0 << SEMANTIC_shift) | + (0x03 << DEFAULT_VAL_shift) | + FLAT_SHADE_bit | + SEL_CENTROID_bit)); + EREG(accel_state->ib, SPI_INTERP_CONTROL_0, FLAT_SHADE_ENA_bit | 0); + + /* PS alu constants */ + if (pPix->drawable.bitsPerPixel == 16) { + r = (fg >> 11) & 0x1f; + g = (fg >> 5) & 0x3f; + b = (fg >> 0) & 0x1f; + ps_alu_consts[0] = (float)r / 31; /* R */ + ps_alu_consts[1] = (float)g / 63; /* G */ + ps_alu_consts[2] = (float)b / 31; /* B */ + ps_alu_consts[3] = 1.0; /* A */ + } else if (pPix->drawable.bitsPerPixel == 8) { + a = (fg >> 0) & 0xff; + ps_alu_consts[0] = 0.0; /* R */ + ps_alu_consts[1] = 0.0; /* G */ + ps_alu_consts[2] = 0.0; /* B */ + ps_alu_consts[3] = (float)a / 255; /* A */ + } else { + a = (fg >> 24) & 0xff; + r = (fg >> 16) & 0xff; + g = (fg >> 8) & 0xff; + b = (fg >> 0) & 0xff; + ps_alu_consts[0] = (float)r / 255; /* R */ + ps_alu_consts[1] = (float)g / 255; /* G */ + ps_alu_consts[2] = (float)b / 255; /* B */ + ps_alu_consts[3] = (float)a / 255; /* A */ + } + set_alu_consts(pScrn, accel_state->ib, 0, sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); + + accel_state->vb_index = 0; + +#ifdef SHOW_VERTEXES + ErrorF("PM: 0x%08x\n", pm); +#endif + + return TRUE; +} + + +static void +R600Solid(PixmapPtr pPix, int x1, int y1, int x2, int y2) +{ + ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + float *vb; + + if (((accel_state->vb_index + 3) * 8) > (accel_state->ib->total / 2)) { + R600DoneSolid(pPix); + accel_state->vb_index = 0; + accel_state->ib = RHDDRMCPBuffer(pScrn->scrnIndex); + } + + vb = (pointer)((char*)accel_state->ib->address + + (accel_state->ib->total / 2) + + accel_state->vb_index * 8); + + vb[0] = (float)x1; + vb[1] = (float)y1; + + vb[2] = (float)x1; + vb[3] = (float)y2; + + vb[4] = (float)x2; + vb[5] = (float)y2; + + accel_state->vb_index += 3; + +} + +static void +R600DoneSolid(PixmapPtr pPix) +{ + ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + draw_config_t draw_conf; + vtx_resource_t vtx_res; + + CLEAR (draw_conf); + CLEAR (vtx_res); + + if (accel_state->vb_index == 0) { + R600IBDiscard(pScrn, accel_state->ib); + return; + } + + accel_state->vb_mc_addr = RHDDRIGetIntGARTLocation(pScrn) + + (accel_state->ib->idx * accel_state->ib->total) + (accel_state->ib->total / 2); + accel_state->vb_size = accel_state->vb_index * 8; + + /* flush vertex cache */ + if ((rhdPtr->ChipSet == RHD_RV610) || + (rhdPtr->ChipSet == RHD_RV620) || + (rhdPtr->ChipSet == RHD_M72) || + (rhdPtr->ChipSet == RHD_M74) || + (rhdPtr->ChipSet == RHD_M82) || + (rhdPtr->ChipSet == RHD_RS780) || + (rhdPtr->ChipSet == RHD_RV710)) + cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, + accel_state->vb_size, accel_state->vb_mc_addr); + else + cp_set_surface_sync(pScrn, accel_state->ib, VC_ACTION_ENA_bit, + accel_state->vb_size, accel_state->vb_mc_addr); + + /* Vertex buffer setup */ + vtx_res.id = SQ_VTX_RESOURCE_vs; + vtx_res.vtx_size_dw = 8 / 4; + vtx_res.vtx_num_entries = accel_state->vb_size / 4; + vtx_res.mem_req_size = 1; + vtx_res.vb_addr = accel_state->vb_mc_addr; + set_vtx_resource (pScrn, accel_state->ib, &vtx_res); + + /* Draw */ + draw_conf.prim_type = DI_PT_RECTLIST; + draw_conf.vgt_draw_initiator = DI_SRC_SEL_AUTO_INDEX; + draw_conf.num_instances = 1; + draw_conf.num_indices = vtx_res.vtx_num_entries / vtx_res.vtx_size_dw; + draw_conf.index_type = DI_INDEX_SIZE_16_BIT; + + draw_auto(pScrn, accel_state->ib, &draw_conf); + + wait_3d_idle_clean(pScrn, accel_state->ib); + + /* sync dst surface */ + cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit), + accel_state->dst_size, accel_state->dst_mc_addr); + + R600CPFlushIndirect(pScrn, accel_state->ib); +} + +static void +R600DoPrepareCopy(ScrnInfoPtr pScrn, + int src_pitch, int src_width, int src_height, uint32_t src_offset, int src_bpp, + int dst_pitch, int dst_height, uint32_t dst_offset, int dst_bpp, + int rop, Pixel planemask) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + int pmask = 0; + cb_config_t cb_conf; + tex_resource_t tex_res; + tex_sampler_t tex_samp; + shader_config_t vs_conf, ps_conf; + + CLEAR (cb_conf); + CLEAR (tex_res); + CLEAR (tex_samp); + CLEAR (vs_conf); + CLEAR (ps_conf); + + accel_state->ib = RHDDRMCPBuffer(pScrn->scrnIndex); + + /* Init */ + start_3d(pScrn, accel_state->ib); + + /* cp_set_surface_sync(pScrn, accel_state->ib); */ + + set_default_state(pScrn, accel_state->ib); + + /* Scissor / viewport */ + EREG(accel_state->ib, PA_CL_VTE_CNTL, VTX_XY_FMT_bit); + EREG(accel_state->ib, PA_CL_CLIP_CNTL, CLIP_DISABLE_bit); + + accel_state->vs_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset + + accel_state->copy_vs_offset; + accel_state->ps_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset + + accel_state->copy_ps_offset; + accel_state->vs_size = 512; + accel_state->ps_size = 512; + + /* Shader */ + + /* flush SQ cache */ + cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit, + accel_state->vs_size, accel_state->vs_mc_addr); + + vs_conf.shader_addr = accel_state->vs_mc_addr; + vs_conf.num_gprs = 2; + vs_conf.stack_size = 0; + vs_setup (pScrn, accel_state->ib, &vs_conf); + + /* flush SQ cache */ + cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit, + accel_state->ps_size, accel_state->ps_mc_addr); + + ps_conf.shader_addr = accel_state->ps_mc_addr; + ps_conf.num_gprs = 1; + ps_conf.stack_size = 0; + ps_conf.uncached_first_inst = 1; + ps_conf.clamp_consts = 0; + ps_conf.export_mode = 2; + ps_setup (pScrn, accel_state->ib, &ps_conf); + + accel_state->src_size[0] = src_pitch * src_height * (src_bpp/8); + accel_state->src_mc_addr[0] = src_offset; + accel_state->src_pitch[0] = src_pitch; + accel_state->src_width[0] = src_width; + accel_state->src_height[0] = src_height; + accel_state->src_bpp[0] = src_bpp; + + /* flush texture cache */ + cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, + accel_state->src_size[0], accel_state->src_mc_addr[0]); + + /* Texture */ + tex_res.id = 0; + tex_res.w = src_width; + tex_res.h = src_height; + tex_res.pitch = accel_state->src_pitch[0]; + tex_res.depth = 0; + tex_res.dim = SQ_TEX_DIM_2D; + tex_res.base = accel_state->src_mc_addr[0]; + tex_res.mip_base = accel_state->src_mc_addr[0]; + if (src_bpp == 8) { + tex_res.format = FMT_8; + tex_res.dst_sel_x = SQ_SEL_1; /* R */ + tex_res.dst_sel_y = SQ_SEL_1; /* G */ + tex_res.dst_sel_z = SQ_SEL_1; /* B */ + tex_res.dst_sel_w = SQ_SEL_X; /* A */ + } else if (src_bpp == 16) { + tex_res.format = FMT_5_6_5; + tex_res.dst_sel_x = SQ_SEL_Z; /* R */ + tex_res.dst_sel_y = SQ_SEL_Y; /* G */ + tex_res.dst_sel_z = SQ_SEL_X; /* B */ + tex_res.dst_sel_w = SQ_SEL_1; /* A */ + } else { + tex_res.format = FMT_8_8_8_8; + tex_res.dst_sel_x = SQ_SEL_Z; /* R */ + tex_res.dst_sel_y = SQ_SEL_Y; /* G */ + tex_res.dst_sel_z = SQ_SEL_X; /* B */ + tex_res.dst_sel_w = SQ_SEL_W; /* A */ + } + + tex_res.request_size = 1; + tex_res.base_level = 0; + tex_res.last_level = 0; + tex_res.perf_modulation = 0; + set_tex_resource (pScrn, accel_state->ib, &tex_res); + + tex_samp.id = 0; + tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; + tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; + tex_samp.clamp_z = SQ_TEX_WRAP; + tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_POINT; + tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT; + tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; + tex_samp.mip_filter = 0; /* no mipmap */ + set_tex_sampler (pScrn, accel_state->ib, &tex_samp); + + + /* Render setup */ + if (planemask & 0x000000ff) + pmask |= 4; /* B */ + if (planemask & 0x0000ff00) + pmask |= 2; /* G */ + if (planemask & 0x00ff0000) + pmask |= 1; /* R */ + if (planemask & 0xff000000) + pmask |= 8; /* A */ + EREG (accel_state->ib, CB_SHADER_MASK, (pmask << OUTPUT0_ENABLE_shift)); + EREG (accel_state->ib, R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit)); + EREG (accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[rop]); + + accel_state->dst_size = dst_pitch * dst_height * (dst_bpp/8); + accel_state->dst_mc_addr = dst_offset; + accel_state->dst_pitch = dst_pitch; + accel_state->dst_height = dst_height; + accel_state->dst_bpp = dst_bpp; + + cb_conf.id = 0; + cb_conf.w = accel_state->dst_pitch; + cb_conf.h = dst_height; + cb_conf.base = accel_state->dst_mc_addr; + if (dst_bpp == 8) { + cb_conf.format = COLOR_8; + cb_conf.comp_swap = 3; /* A */ + } else if (dst_bpp == 16) { + cb_conf.format = COLOR_5_6_5; + cb_conf.comp_swap = 2; /* RGB */ + } else { + cb_conf.format = COLOR_8_8_8_8; + cb_conf.comp_swap = 1; /* ARGB */ + } + cb_conf.source_format = 1; + cb_conf.blend_clamp = 1; + set_render_target(pScrn, accel_state->ib, &cb_conf); + + EREG(accel_state->ib, PA_SU_SC_MODE_CNTL, (FACE_bit | + (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) | + (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift))); + EREG(accel_state->ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */ + DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */ + + /* Interpolator setup */ + /* export tex coord from VS */ + EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift)); + EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift)); + + /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x + * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */ + /* input tex coord from VS */ + EREG(accel_state->ib, SPI_PS_IN_CONTROL_0, ((1 << NUM_INTERP_shift))); + EREG(accel_state->ib, SPI_PS_IN_CONTROL_1, 0); + /* color semantic id 0 -> GPR[0] */ + EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 <<2), ((0 << SEMANTIC_shift) | + (0x01 << DEFAULT_VAL_shift) | + SEL_CENTROID_bit)); + EREG(accel_state->ib, SPI_INTERP_CONTROL_0, 0); + + accel_state->vb_index = 0; + +} + +static void +R600DoCopy(ScrnInfoPtr pScrn) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + draw_config_t draw_conf; + vtx_resource_t vtx_res; + + CLEAR (draw_conf); + CLEAR (vtx_res); + + if (accel_state->vb_index == 0) { + R600IBDiscard(pScrn, accel_state->ib); + return; + } + + accel_state->vb_mc_addr = RHDDRIGetIntGARTLocation(pScrn) + + (accel_state->ib->idx * accel_state->ib->total) + (accel_state->ib->total / 2); + accel_state->vb_size = accel_state->vb_index * 16; + + /* flush vertex cache */ + if ((rhdPtr->ChipSet == RHD_RV610) || + (rhdPtr->ChipSet == RHD_RV620) || + (rhdPtr->ChipSet == RHD_M72) || + (rhdPtr->ChipSet == RHD_M74) || + (rhdPtr->ChipSet == RHD_M82) || + (rhdPtr->ChipSet == RHD_RS780) || + (rhdPtr->ChipSet == RHD_RV710)) + cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, + accel_state->vb_size, accel_state->vb_mc_addr); + else + cp_set_surface_sync(pScrn, accel_state->ib, VC_ACTION_ENA_bit, + accel_state->vb_size, accel_state->vb_mc_addr); + + /* Vertex buffer setup */ + vtx_res.id = SQ_VTX_RESOURCE_vs; + vtx_res.vtx_size_dw = 16 / 4; + vtx_res.vtx_num_entries = accel_state->vb_size / 4; + vtx_res.mem_req_size = 1; + vtx_res.vb_addr = accel_state->vb_mc_addr; + set_vtx_resource (pScrn, accel_state->ib, &vtx_res); + + draw_conf.prim_type = DI_PT_RECTLIST; + draw_conf.vgt_draw_initiator = DI_SRC_SEL_AUTO_INDEX; + draw_conf.num_instances = 1; + draw_conf.num_indices = vtx_res.vtx_num_entries / vtx_res.vtx_size_dw; + draw_conf.index_type = DI_INDEX_SIZE_16_BIT; + + draw_auto(pScrn, accel_state->ib, &draw_conf); + + wait_3d_idle_clean(pScrn, accel_state->ib); + + /* sync dst surface */ + cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit), + accel_state->dst_size, accel_state->dst_mc_addr); + + R600CPFlushIndirect(pScrn, accel_state->ib); +} + +static void +R600AppendCopyVertex(ScrnInfoPtr pScrn, + int srcX, int srcY, + int dstX, int dstY, + int w, int h) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + float *vb; + + if (((accel_state->vb_index + 3) * 16) > (accel_state->ib->total / 2)) { + R600DoCopy(pScrn); + accel_state->vb_index = 0; + accel_state->ib = RHDDRMCPBuffer(pScrn->scrnIndex); + } + + vb = (pointer)((char*)accel_state->ib->address + + (accel_state->ib->total / 2) + + accel_state->vb_index * 16); + + vb[0] = (float)dstX; + vb[1] = (float)dstY; + vb[2] = (float)srcX; + vb[3] = (float)srcY; + + vb[4] = (float)dstX; + vb[5] = (float)(dstY + h); + vb[6] = (float)srcX; + vb[7] = (float)(srcY + h); + + vb[8] = (float)(dstX + w); + vb[9] = (float)(dstY + h); + vb[10] = (float)(srcX + w); + vb[11] = (float)(srcY + h); + + accel_state->vb_index += 3; +} + +static Bool +R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, + int xdir, int ydir, + int rop, + Pixel planemask) +{ + ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + + accel_state->dst_pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); + accel_state->src_pitch[0] = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8); + + accel_state->src_mc_addr[0] = exaGetPixmapOffset(pSrc) + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + accel_state->dst_mc_addr = exaGetPixmapOffset(pDst) + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + + accel_state->src_width[0] = pSrc->drawable.width; + accel_state->src_height[0] = pSrc->drawable.height; + accel_state->src_bpp[0] = pSrc->drawable.bitsPerPixel; + accel_state->dst_height = pDst->drawable.height; + accel_state->dst_bpp = pDst->drawable.bitsPerPixel; + + /* bad pitch */ + if (accel_state->src_pitch[0] & 7) + return FALSE; + if (accel_state->dst_pitch & 7) + return FALSE; + + /* bad offset */ + if (accel_state->src_mc_addr[0] & 0xff) + return FALSE; + if (accel_state->dst_mc_addr & 0xff) + return FALSE; + + if (pSrc->drawable.bitsPerPixel == 24) + return FALSE; + if (pDst->drawable.bitsPerPixel == 24) + return FALSE; + + /* return FALSE; */ + +#ifdef SHOW_VERTEXES + ErrorF("src: %dx%d @ %dbpp, 0x%08x\n", pSrc->drawable.width, pSrc->drawable.height, + pSrc->drawable.bitsPerPixel, exaGetPixmapPitch(pSrc)); + ErrorF("dst: %dx%d @ %dbpp, 0x%08x\n", pDst->drawable.width, pDst->drawable.height, + pDst->drawable.bitsPerPixel, exaGetPixmapPitch(pDst)); +#endif + + accel_state->rop = rop; + accel_state->planemask = planemask; + + if (exaGetPixmapOffset(pSrc) == exaGetPixmapOffset(pDst)) { + unsigned long size = pDst->drawable.height * accel_state->dst_pitch * pDst->drawable.bitsPerPixel/8; + accel_state->same_surface = TRUE; + + if (accel_state->copy_area) { + exaOffscreenFree(pDst->drawable.pScreen, accel_state->copy_area); + accel_state->copy_area = NULL; + } + accel_state->copy_area = exaOffscreenAlloc(pDst->drawable.pScreen, size, 256, TRUE, NULL, NULL); + } else { + + accel_state->same_surface = FALSE; + + R600DoPrepareCopy(pScrn, + accel_state->src_pitch[0], pSrc->drawable.width, pSrc->drawable.height, + accel_state->src_mc_addr[0], pSrc->drawable.bitsPerPixel, + accel_state->dst_pitch, pDst->drawable.height, + accel_state->dst_mc_addr, pDst->drawable.bitsPerPixel, + rop, planemask); + + } + + return TRUE; +} + +static Bool +is_overlap(int sx1, int sx2, int sy1, int sy2, int dx1, int dx2, int dy1, int dy2) +{ + if (((sx1 >= dx1) && (sx1 <= dx2) && (sy1 >= dy1) && (sy1 <= dy2)) || /* TL x1, y1 */ + ((sx2 >= dx1) && (sx2 <= dx2) && (sy1 >= dy1) && (sy1 <= dy2)) || /* TR x2, y1 */ + ((sx1 >= dx1) && (sx1 <= dx2) && (sy2 >= dy1) && (sy2 <= dy2)) || /* BL x1, y2 */ + ((sx2 >= dx1) && (sx2 <= dx2) && (sy2 >= dy1) && (sy2 <= dy2))) /* BR x2, y2 */ + return TRUE; + else + return FALSE; +} + +static void +R600OverlapCopy(PixmapPtr pDst, + int srcX, int srcY, + int dstX, int dstY, + int w, int h) +{ + ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + uint32_t dst_pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); + uint32_t dst_offset = exaGetPixmapOffset(pDst) + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + int i, hchunk, vchunk; + + if (is_overlap(srcX, srcX + w, srcY, srcY + h, + dstX, dstX + w, dstY, dstY + h)) { + /* Calculate height/width of non-overlapping area */ + hchunk = (srcX < dstX) ? (dstX - srcX) : (srcX - dstX); + vchunk = (srcY < dstY) ? (dstY - srcY) : (srcY - dstY); + + /* Diagonally offset overlap is reduced to either horizontal or vertical offset-only + * by copying a part of the non-overlapping portion, then adjusting coordinates + * Choose horizontal vs vertical to minimize the total number of copy operations + */ + if (vchunk != 0 && hchunk != 0) { /* diagonal */ + if ((w / hchunk) <= (h / vchunk)) { /* reduce to horizontal */ + if (srcY > dstY ) { /* diagonal up */ + R600DoPrepareCopy(pScrn, + dst_pitch, pDst->drawable.width, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + dst_pitch, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, vchunk); + R600DoCopy(pScrn); + + srcY = srcY + vchunk; + dstY = dstY + vchunk; + } else { /* diagonal down */ + R600DoPrepareCopy(pScrn, + dst_pitch, pDst->drawable.width, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + dst_pitch, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + R600AppendCopyVertex(pScrn, srcX, srcY + h - vchunk, dstX, dstY + h - vchunk, w, vchunk); + R600DoCopy(pScrn); + } + h = h - vchunk; + vchunk = 0; + } else { /* reduce to vertical */ + if (srcX > dstX ) { /* diagonal left */ + R600DoPrepareCopy(pScrn, + dst_pitch, pDst->drawable.width, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + dst_pitch, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, hchunk, h); + R600DoCopy(pScrn); + + srcX = srcX + hchunk; + dstX = dstX + hchunk; + } else { /* diagonal right */ + R600DoPrepareCopy(pScrn, + dst_pitch, pDst->drawable.width, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + dst_pitch, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + R600AppendCopyVertex(pScrn, srcX + w - hchunk, srcY, dstX + w - hchunk, dstY, hchunk, h); + R600DoCopy(pScrn); + } + w = w - hchunk; + hchunk = 0; + } + } + + if (vchunk == 0) { /* left/right */ + if (srcX < dstX) { /* right */ + /* copy right to left */ + for (i = w; i > 0; i -= hchunk) { + R600DoPrepareCopy(pScrn, + dst_pitch, pDst->drawable.width, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + dst_pitch, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + R600AppendCopyVertex(pScrn, srcX + i - hchunk, srcY, dstX + i - hchunk, dstY, hchunk, h); + R600DoCopy(pScrn); + } + } else { /* left */ + /* copy left to right */ + for (i = 0; i < w; i += hchunk) { + R600DoPrepareCopy(pScrn, + dst_pitch, pDst->drawable.width, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + dst_pitch, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + + R600AppendCopyVertex(pScrn, srcX + i, srcY, dstX + i, dstY, hchunk, h); + R600DoCopy(pScrn); + } + } + } else { /* up/down */ + if (srcY > dstY) { /* up */ + /* copy top to bottom */ + for (i = 0; i < h; i += vchunk) { + R600DoPrepareCopy(pScrn, + dst_pitch, pDst->drawable.width, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + dst_pitch, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + + if (vchunk > h - i) vchunk = h - i; + R600AppendCopyVertex(pScrn, srcX, srcY + i, dstX, dstY + i, w, vchunk); + R600DoCopy(pScrn); + } + } else { /* down */ + /* copy bottom to top */ + for (i = h; i > 0; i -= vchunk) { + R600DoPrepareCopy(pScrn, + dst_pitch, pDst->drawable.width, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + dst_pitch, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + + if (vchunk > i) vchunk = i; + R600AppendCopyVertex(pScrn, srcX, srcY + i - vchunk, dstX, dstY + i - vchunk, w, vchunk); + R600DoCopy(pScrn); + } + } + } + } else { + R600DoPrepareCopy(pScrn, + dst_pitch, pDst->drawable.width, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + dst_pitch, pDst->drawable.height, dst_offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + + R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h); + R600DoCopy(pScrn); + } +} + +static void +R600Copy(PixmapPtr pDst, + int srcX, int srcY, + int dstX, int dstY, + int w, int h) +{ + ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + + if (accel_state->same_surface && (srcX == dstX) && (srcY == dstY)) + return; + + if (accel_state->same_surface && is_overlap(srcX, srcX + w, srcY, srcY + h, dstX, dstX + w, dstY, dstY + h)) { + if (accel_state->copy_area) { + uint32_t pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); + uint32_t orig_offset, tmp_offset; + + tmp_offset = accel_state->copy_area->offset + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + orig_offset = exaGetPixmapOffset(pDst) + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + + R600DoPrepareCopy(pScrn, + pitch, pDst->drawable.width, pDst->drawable.height, orig_offset, pDst->drawable.bitsPerPixel, + pitch, pDst->drawable.height, tmp_offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h); + R600DoCopy(pScrn); + R600DoPrepareCopy(pScrn, + pitch, pDst->drawable.width, pDst->drawable.height, tmp_offset, pDst->drawable.bitsPerPixel, + pitch, pDst->drawable.height, orig_offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + R600AppendCopyVertex(pScrn, dstX, dstY, dstX, dstY, w, h); + R600DoCopy(pScrn); + } else + R600OverlapCopy(pDst, srcX, srcY, dstX, dstY, w, h); + } else if (accel_state->same_surface) { + uint32_t pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); + uint32_t offset = exaGetPixmapOffset(pDst) + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + + R600DoPrepareCopy(pScrn, + pitch, pDst->drawable.width, pDst->drawable.height, offset, pDst->drawable.bitsPerPixel, + pitch, pDst->drawable.height, offset, pDst->drawable.bitsPerPixel, + accel_state->rop, accel_state->planemask); + R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h); + R600DoCopy(pScrn); + } else { + R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h); + } + +} + +static void +R600DoneCopy(PixmapPtr pDst) +{ + ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + + if (!accel_state->same_surface) + R600DoCopy(pScrn); + + if (accel_state->copy_area) { + exaOffscreenFree(pDst->drawable.pScreen, accel_state->copy_area); + accel_state->copy_area = NULL; + } +} + +#define RADEON_TRACE_FALL 0 +#define RADEON_TRACE_DRAW 0 + +#if RADEON_TRACE_FALL +#define RADEON_FALLBACK(x) \ +do { \ + ErrorF("%s: ", __FUNCTION__); \ + ErrorF x; \ + return FALSE; \ +} while (0) +#else +#define RADEON_FALLBACK(x) return FALSE +#endif + +#define xFixedToFloat(f) (((float) (f)) / 65536) + +static inline void transformPoint(PictTransform *transform, xPointFixed *point) +{ + PictVector v; + v.vector[0] = point->x; + v.vector[1] = point->y; + v.vector[2] = xFixed1; + PictureTransformPoint(transform, &v); + point->x = v.vector[0]; + point->y = v.vector[1]; +} + +struct blendinfo { + Bool dst_alpha; + Bool src_alpha; + uint32_t blend_cntl; +}; + +static struct blendinfo R600BlendOp[] = { + /* Clear */ + {0, 0, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, + /* Src */ + {0, 0, (BLEND_ONE << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, + /* Dst */ + {0, 0, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_ONE << COLOR_DESTBLEND_shift)}, + /* Over */ + {0, 1, (BLEND_ONE << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, + /* OverReverse */ + {1, 0, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ONE << COLOR_DESTBLEND_shift)}, + /* In */ + {1, 0, (BLEND_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, + /* InReverse */ + {0, 1, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_SRC_ALPHA << COLOR_DESTBLEND_shift)}, + /* Out */ + {1, 0, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ZERO << COLOR_DESTBLEND_shift)}, + /* OutReverse */ + {0, 1, (BLEND_ZERO << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, + /* Atop */ + {1, 1, (BLEND_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, + /* AtopReverse */ + {1, 1, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_SRC_ALPHA << COLOR_DESTBLEND_shift)}, + /* Xor */ + {1, 1, (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift) | (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)}, + /* Add */ + {0, 0, (BLEND_ONE << COLOR_SRCBLEND_shift) | (BLEND_ONE << COLOR_DESTBLEND_shift)}, +}; + +struct formatinfo { + unsigned int fmt; + uint32_t card_fmt; +}; + +static struct formatinfo R600TexFormats[] = { + {PICT_a8r8g8b8, FMT_8_8_8_8}, + {PICT_x8r8g8b8, FMT_8_8_8_8}, + {PICT_a8b8g8r8, FMT_8_8_8_8}, + {PICT_x8b8g8r8, FMT_8_8_8_8}, + {PICT_r5g6b5, FMT_5_6_5}, + {PICT_a1r5g5b5, FMT_1_5_5_5}, + {PICT_x1r5g5b5, FMT_1_5_5_5}, + {PICT_a8, FMT_8}, +}; + +static uint32_t R600GetBlendCntl(int op, PicturePtr pMask, uint32_t dst_format) +{ + uint32_t sblend, dblend; + + sblend = R600BlendOp[op].blend_cntl & COLOR_SRCBLEND_mask; + dblend = R600BlendOp[op].blend_cntl & COLOR_DESTBLEND_mask; + + /* If there's no dst alpha channel, adjust the blend op so that we'll treat + * it as always 1. + */ + if (PICT_FORMAT_A(dst_format) == 0 && R600BlendOp[op].dst_alpha) { + if (sblend == (BLEND_DST_ALPHA << COLOR_SRCBLEND_shift)) + sblend = (BLEND_ONE << COLOR_SRCBLEND_shift); + else if (sblend == (BLEND_ONE_MINUS_DST_ALPHA << COLOR_SRCBLEND_shift)) + sblend = (BLEND_ZERO << COLOR_SRCBLEND_shift); + } + + /* If the source alpha is being used, then we should only be in a case where + * the source blend factor is 0, and the source blend value is the mask + * channels multiplied by the source picture's alpha. + */ + if (pMask && pMask->componentAlpha && R600BlendOp[op].src_alpha) { + if (dblend == (BLEND_SRC_ALPHA << COLOR_DESTBLEND_shift)) { + dblend = (BLEND_SRC_COLOR << COLOR_DESTBLEND_shift); + } else if (dblend == (BLEND_ONE_MINUS_SRC_ALPHA << COLOR_DESTBLEND_shift)) { + dblend = (BLEND_ONE_MINUS_SRC_COLOR << COLOR_DESTBLEND_shift); + } + } + + return sblend | dblend; +} + +static Bool R600GetDestFormat(PicturePtr pDstPicture, uint32_t *dst_format) +{ + switch (pDstPicture->format) { + case PICT_a8r8g8b8: + case PICT_x8r8g8b8: + *dst_format = COLOR_8_8_8_8; + break; + case PICT_r5g6b5: + *dst_format = COLOR_5_6_5; + break; + case PICT_a1r5g5b5: + case PICT_x1r5g5b5: + *dst_format = COLOR_1_5_5_5; + break; + case PICT_a8: + *dst_format = COLOR_8; + break; + default: + RADEON_FALLBACK(("Unsupported dest format 0x%x\n", + (int)pDstPicture->format)); + } + return TRUE; +} + +static Bool R600CheckCompositeTexture(PicturePtr pPict, + PicturePtr pDstPict, + int op, + int unit) +{ + int w = pPict->pDrawable->width; + int h = pPict->pDrawable->height; + unsigned int i; + int max_tex_w, max_tex_h; + + max_tex_w = 8192; + max_tex_h = 8192; + + if ((w > max_tex_w) || (h > max_tex_h)) + RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h)); + + for (i = 0; i < sizeof(R600TexFormats) / sizeof(R600TexFormats[0]); i++) { + if (R600TexFormats[i].fmt == pPict->format) + break; + } + if (i == sizeof(R600TexFormats) / sizeof(R600TexFormats[0])) + RADEON_FALLBACK(("Unsupported picture format 0x%x\n", + (int)pPict->format)); + + if (pPict->filter != PictFilterNearest && + pPict->filter != PictFilterBilinear) + RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter)); + + /* for REPEAT_NONE, Render semantics are that sampling outside the source + * picture results in alpha=0 pixels. We can implement this with a border color + * *if* our source texture has an alpha channel, otherwise we need to fall + * back. If we're not transformed then we hope that upper layers have clipped + * rendering to the bounds of the source drawable, in which case it doesn't + * matter. I have not, however, verified that the X server always does such + * clipping. + */ + /* FIXME R6xx */ + if (pPict->transform != 0 && !pPict->repeat && PICT_FORMAT_A(pPict->format) == 0) { + if (!(((op == PictOpSrc) || (op == PictOpClear)) && (PICT_FORMAT_A(pDstPict->format) == 0))) + RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB source\n")); + } + + return TRUE; +} + +static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, + int unit) +{ + ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + int w = pPict->pDrawable->width; + int h = pPict->pDrawable->height; + unsigned int i; + tex_resource_t tex_res; + tex_sampler_t tex_samp; + int pix_r, pix_g, pix_b, pix_a; + + CLEAR (tex_res); + CLEAR (tex_samp); + + accel_state->src_pitch[unit] = exaGetPixmapPitch(pPix) / (pPix->drawable.bitsPerPixel / 8); + accel_state->src_size[unit] = exaGetPixmapPitch(pPix) * h; + accel_state->src_mc_addr[unit] = exaGetPixmapOffset(pPix) + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + + if (accel_state->src_pitch[1] & 7) + RADEON_FALLBACK(("Bad pitch %d 0x%x\n", (int)accel_state->src_pitch[unit], unit)); + + if (accel_state->src_mc_addr[1] & 0xff) + RADEON_FALLBACK(("Bad offset %d 0x%x\n", (int)accel_state->src_mc_addr[unit], unit)); + + for (i = 0; i < sizeof(R600TexFormats) / sizeof(R600TexFormats[0]); i++) { + if (R600TexFormats[i].fmt == pPict->format) + break; + } + + accel_state->texW[unit] = w; + accel_state->texH[unit] = h; + + /* ErrorF("Tex %d setup %dx%d\n", unit, w, h); */ + + /* flush texture cache */ + cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, + accel_state->src_size[unit], accel_state->src_mc_addr[unit]); + + /* Texture */ + tex_res.id = unit; + tex_res.w = w; + tex_res.h = h; + tex_res.pitch = accel_state->src_pitch[unit]; + tex_res.depth = 0; + tex_res.dim = SQ_TEX_DIM_2D; + tex_res.base = accel_state->src_mc_addr[unit]; + tex_res.mip_base = accel_state->src_mc_addr[unit]; + tex_res.format = R600TexFormats[i].card_fmt; + tex_res.request_size = 1; + + /* component swizzles */ + switch (pPict->format) { + case PICT_a1r5g5b5: + case PICT_a8r8g8b8: + pix_r = SQ_SEL_Z; /* R */ + pix_g = SQ_SEL_Y; /* G */ + pix_b = SQ_SEL_X; /* B */ + pix_a = SQ_SEL_W; /* A */ + break; + case PICT_a8b8g8r8: + pix_r = SQ_SEL_X; /* R */ + pix_g = SQ_SEL_Y; /* G */ + pix_b = SQ_SEL_Z; /* B */ + pix_a = SQ_SEL_W; /* A */ + break; + case PICT_x8b8g8r8: + pix_r = SQ_SEL_X; /* R */ + pix_g = SQ_SEL_Y; /* G */ + pix_b = SQ_SEL_Z; /* B */ + pix_a = SQ_SEL_1; /* A */ + break; + case PICT_x1r5g5b5: + case PICT_x8r8g8b8: + case PICT_r5g6b5: + pix_r = SQ_SEL_Z; /* R */ + pix_g = SQ_SEL_Y; /* G */ + pix_b = SQ_SEL_X; /* B */ + pix_a = SQ_SEL_1; /* A */ + break; + case PICT_a8: + pix_r = SQ_SEL_0; /* R */ + pix_g = SQ_SEL_0; /* G */ + pix_b = SQ_SEL_0; /* B */ + pix_a = SQ_SEL_X; /* A */ + break; + default: + RADEON_FALLBACK(("Bad format 0x%x\n", pPict->format)); + } + + if (unit == 0) { + if (!accel_state->has_mask) { + if (PICT_FORMAT_RGB(pPict->format) == 0) { + pix_r = SQ_SEL_0; + pix_g = SQ_SEL_0; + pix_b = SQ_SEL_0; + } + + if (PICT_FORMAT_A(pPict->format) == 0) + pix_a = SQ_SEL_1; + } else { + if (accel_state->component_alpha) { + if (accel_state->src_alpha) { + if (PICT_FORMAT_A(pPict->format) == 0) { + pix_r = SQ_SEL_1; + pix_g = SQ_SEL_1; + pix_b = SQ_SEL_1; + pix_a = SQ_SEL_1; + } else { + pix_r = pix_a; + pix_g = pix_a; + pix_b = pix_a; + } + } else { + if (PICT_FORMAT_A(pPict->format) == 0) + pix_a = SQ_SEL_1; + } + } else { + if (PICT_FORMAT_RGB(pPict->format) == 0) { + pix_r = SQ_SEL_0; + pix_g = SQ_SEL_0; + pix_b = SQ_SEL_0; + } + + if (PICT_FORMAT_A(pPict->format) == 0) + pix_a = SQ_SEL_1; + } + } + } else { + if (accel_state->component_alpha) { + if (PICT_FORMAT_A(pPict->format) == 0) + pix_a = SQ_SEL_1; + } else { + if (PICT_FORMAT_A(pPict->format) == 0) { + pix_r = SQ_SEL_1; + pix_g = SQ_SEL_1; + pix_b = SQ_SEL_1; + pix_a = SQ_SEL_1; + } else { + pix_r = pix_a; + pix_g = pix_a; + pix_b = pix_a; + } + } + } + + tex_res.dst_sel_x = pix_r; /* R */ + tex_res.dst_sel_y = pix_g; /* G */ + tex_res.dst_sel_z = pix_b; /* B */ + tex_res.dst_sel_w = pix_a; /* A */ + + tex_res.base_level = 0; + tex_res.last_level = 0; + tex_res.perf_modulation = 0; + set_tex_resource (pScrn, accel_state->ib, &tex_res); + + tex_samp.id = unit; + tex_samp.border_color = SQ_TEX_BORDER_COLOR_TRANS_BLACK; + + if (pPict->repeat) { + switch (pPict->repeatType) { + case RepeatNormal: + tex_samp.clamp_x = SQ_TEX_WRAP; + tex_samp.clamp_y = SQ_TEX_WRAP; + break; + case RepeatPad: + tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; + tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; + break; + case RepeatReflect: + tex_samp.clamp_x = SQ_TEX_MIRROR; + tex_samp.clamp_y = SQ_TEX_MIRROR; + break; + case RepeatNone: + tex_samp.clamp_x = SQ_TEX_CLAMP_BORDER; + tex_samp.clamp_y = SQ_TEX_CLAMP_BORDER; + break; + default: + RADEON_FALLBACK(("Bad repeat 0x%x\n", pPict->repeatType)); + } + } else { + tex_samp.clamp_x = SQ_TEX_CLAMP_BORDER; + tex_samp.clamp_y = SQ_TEX_CLAMP_BORDER; + } + + switch (pPict->filter) { + case PictFilterNearest: + tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_POINT; + tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT; + break; + case PictFilterBilinear: + tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; + tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; + break; + default: + RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); + } + + tex_samp.clamp_z = SQ_TEX_WRAP; + tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; + tex_samp.mip_filter = 0; /* no mipmap */ + set_tex_sampler (pScrn, accel_state->ib, &tex_samp); + + if (pPict->transform != 0) { + accel_state->is_transform[unit] = TRUE; + accel_state->transform[unit] = pPict->transform; + } else + accel_state->is_transform[unit] = FALSE; + + return TRUE; +} + +static Bool R600CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, + PicturePtr pDstPicture) +{ + uint32_t tmp1; +/* ScreenPtr pScreen = pDstPicture->pDrawable->pScreen; */ + PixmapPtr pSrcPixmap, pDstPixmap; +/* ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; */ +/* RHDPtr rhdPtr = RHDPTR(pScrn); */ + int max_tex_w, max_tex_h, max_dst_w, max_dst_h; + + /* Check for unsupported compositing operations. */ + if (op >= (int) (sizeof(R600BlendOp) / sizeof(R600BlendOp[0]))) + RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op)); + + pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable); + + max_tex_w = 8192; + max_tex_h = 8192; + max_dst_w = 8192; + max_dst_h = 8192; + + if (pSrcPixmap->drawable.width >= max_tex_w || + pSrcPixmap->drawable.height >= max_tex_h) { + RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", + pSrcPixmap->drawable.width, + pSrcPixmap->drawable.height)); + } + + pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); + + if (pDstPixmap->drawable.width >= max_dst_w || + pDstPixmap->drawable.height >= max_dst_h) { + RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", + pDstPixmap->drawable.width, + pDstPixmap->drawable.height)); + } + + if (pMaskPicture) { + PixmapPtr pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); + + if (pMaskPixmap->drawable.width >= max_tex_w || + pMaskPixmap->drawable.height >= max_tex_h) { + RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", + pMaskPixmap->drawable.width, + pMaskPixmap->drawable.height)); + } + + if (pMaskPicture->componentAlpha) { + /* Check if it's component alpha that relies on a source alpha and + * on the source value. We can only get one of those into the + * single source value that we get to blend with. + */ + if (R600BlendOp[op].src_alpha && + (R600BlendOp[op].blend_cntl & COLOR_SRCBLEND_mask) != + (BLEND_ZERO << COLOR_SRCBLEND_shift)) { + RADEON_FALLBACK(("Component alpha not supported with source " + "alpha and source value blending.\n")); + } + } + + if (!R600CheckCompositeTexture(pMaskPicture, pDstPicture, op, 1)) + return FALSE; + } + + if (!R600CheckCompositeTexture(pSrcPicture, pDstPicture, op, 0)) + return FALSE; + + if (!R600GetDestFormat(pDstPicture, &tmp1)) + return FALSE; + + return TRUE; + +} + +static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, + PicturePtr pMaskPicture, PicturePtr pDstPicture, + PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) +{ + ScrnInfoPtr pScrn = xf86Screens[pSrc->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + uint32_t blendcntl, dst_format; + cb_config_t cb_conf; + shader_config_t vs_conf, ps_conf; + + /* return FALSE; */ + + if (pMask) { + accel_state->has_mask = TRUE; + if (pMaskPicture->componentAlpha) { + accel_state->component_alpha = TRUE; + if (R600BlendOp[op].src_alpha) + accel_state->src_alpha = TRUE; + else + accel_state->src_alpha = FALSE; + } else { + accel_state->component_alpha = FALSE; + accel_state->src_alpha = FALSE; + } + } else { + accel_state->has_mask = FALSE; + accel_state->component_alpha = FALSE; + accel_state->src_alpha = FALSE; + } + + accel_state->dst_mc_addr = exaGetPixmapOffset(pDst) + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + accel_state->dst_pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); + accel_state->dst_size = exaGetPixmapPitch(pDst) * pDst->drawable.height; + + if (accel_state->dst_pitch & 7) + RADEON_FALLBACK(("Bad dst pitch 0x%x\n", (int)accel_state->dst_pitch)); + + if (accel_state->dst_mc_addr & 0xff) + RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)accel_state->dst_mc_addr)); + + if (!R600GetDestFormat(pDstPicture, &dst_format)) + return FALSE; + + CLEAR (cb_conf); + CLEAR (vs_conf); + CLEAR (ps_conf); + + accel_state->ib = RHDDRMCPBuffer(pScrn->scrnIndex); + + /* Init */ + start_3d(pScrn, accel_state->ib); + + /* cp_set_surface_sync(pScrn, accel_state->ib); */ + + set_default_state(pScrn, accel_state->ib); + + /* Scissor / viewport */ + EREG (accel_state->ib, PA_CL_VTE_CNTL, VTX_XY_FMT_bit); + EREG (accel_state->ib, PA_CL_CLIP_CNTL, CLIP_DISABLE_bit); + + if (!R600TextureSetup(pSrcPicture, pSrc, 0)) { + R600IBDiscard(pScrn, accel_state->ib); + return FALSE; + } + + if (pMask != NULL) { + if (!R600TextureSetup(pMaskPicture, pMask, 1)) { + R600IBDiscard(pScrn, accel_state->ib); + return FALSE; + } + } else + accel_state->is_transform[1] = FALSE; + + if (pMask) { + set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (1 << 0)); + accel_state->ps_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset + + accel_state->comp_mask_ps_offset; + } else { + set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (0 << 0)); + accel_state->ps_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset + + accel_state->comp_ps_offset; + } + + accel_state->vs_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset + + accel_state->comp_vs_offset; + + accel_state->vs_size = 512; + accel_state->ps_size = 512; + + /* Shader */ + + /* flush SQ cache */ + cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit, + accel_state->vs_size, accel_state->vs_mc_addr); + + vs_conf.shader_addr = accel_state->vs_mc_addr; + vs_conf.num_gprs = 3; + vs_conf.stack_size = 1; + vs_setup (pScrn, accel_state->ib, &vs_conf); + + /* flush SQ cache */ + cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit, + accel_state->ps_size, accel_state->ps_mc_addr); + + ps_conf.shader_addr = accel_state->ps_mc_addr; + ps_conf.num_gprs = 3; + ps_conf.stack_size = 0; + ps_conf.uncached_first_inst = 1; + ps_conf.clamp_consts = 0; + ps_conf.export_mode = 2; + ps_setup (pScrn, accel_state->ib, &ps_conf); + + EREG (accel_state->ib, CB_SHADER_MASK, (0xf << OUTPUT0_ENABLE_shift)); + EREG (accel_state->ib, R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit)); + + blendcntl = R600GetBlendCntl(op, pMaskPicture, pDstPicture->format); + + if (rhdPtr->ChipSet == RHD_R600) { + /* no per-MRT blend on R600 */ + EREG (accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[3] | (1 << TARGET_BLEND_ENABLE_shift)); + EREG (accel_state->ib, CB_BLEND_CONTROL, blendcntl); + } else { + EREG (accel_state->ib, CB_COLOR_CONTROL, (RADEON_ROP[3] | + (1 << TARGET_BLEND_ENABLE_shift) | + PER_MRT_BLEND_bit)); + EREG (accel_state->ib, CB_BLEND0_CONTROL, blendcntl); + } + + cb_conf.id = 0; + cb_conf.w = accel_state->dst_pitch; + cb_conf.h = pDst->drawable.height; + cb_conf.base = accel_state->dst_mc_addr; + cb_conf.format = dst_format; + + switch (pDstPicture->format) { + case PICT_a8r8g8b8: + case PICT_x8r8g8b8: + case PICT_a1r5g5b5: + case PICT_x1r5g5b5: + default: + cb_conf.comp_swap = 1; /* ARGB */ + break; + case PICT_r5g6b5: + cb_conf.comp_swap = 2; /* RGB */ + break; + case PICT_a8: + cb_conf.comp_swap = 3; /* A */ + break; + } + cb_conf.source_format = 1; + cb_conf.blend_clamp = 1; + set_render_target(pScrn, accel_state->ib, &cb_conf); + + EREG(accel_state->ib, PA_SU_SC_MODE_CNTL, (FACE_bit | + (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) | + (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift))); + EREG(accel_state->ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */ + DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */ + + /* Interpolator setup */ + if (pMask) { + /* export 2 tex coords from VS */ + EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((2 - 1) << VS_EXPORT_COUNT_shift)); + /* src = semantic id 0; mask = semantic id 1 */ + EREG(accel_state->ib, SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) | + (1 << SEMANTIC_1_shift))); + /* input 2 tex coords from VS */ + EREG(accel_state->ib, SPI_PS_IN_CONTROL_0, (2 << NUM_INTERP_shift)); + } else { + /* export 1 tex coords from VS */ + EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift)); + /* src = semantic id 0 */ + EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift)); + /* input 1 tex coords from VS */ + EREG(accel_state->ib, SPI_PS_IN_CONTROL_0, (1 << NUM_INTERP_shift)); + } + EREG(accel_state->ib, SPI_PS_IN_CONTROL_1, 0); + /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */ + EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 <<2), ((0 << SEMANTIC_shift) | + (0x01 << DEFAULT_VAL_shift) | + SEL_CENTROID_bit)); + /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */ + EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (1 <<2), ((1 << SEMANTIC_shift) | + (0x01 << DEFAULT_VAL_shift) | + SEL_CENTROID_bit)); + EREG(accel_state->ib, SPI_INTERP_CONTROL_0, 0); + + accel_state->vb_index = 0; + + return TRUE; +} + +static void R600Composite(PixmapPtr pDst, + int srcX, int srcY, + int maskX, int maskY, + int dstX, int dstY, + int w, int h) +{ + ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + float *vb; + xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; + + /* ErrorF("R600Composite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", + srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ + + srcTopLeft.x = IntToxFixed(srcX); + srcTopLeft.y = IntToxFixed(srcY); + srcTopRight.x = IntToxFixed(srcX + w); + srcTopRight.y = IntToxFixed(srcY); + srcBottomLeft.x = IntToxFixed(srcX); + srcBottomLeft.y = IntToxFixed(srcY + h); + srcBottomRight.x = IntToxFixed(srcX + w); + srcBottomRight.y = IntToxFixed(srcY + h); + + /* XXX do transform in vertex shader */ + if (accel_state->is_transform[0]) { + transformPoint(accel_state->transform[0], &srcTopLeft); + transformPoint(accel_state->transform[0], &srcTopRight); + transformPoint(accel_state->transform[0], &srcBottomLeft); + transformPoint(accel_state->transform[0], &srcBottomRight); + } + + if (accel_state->has_mask) { + xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; + + if (((accel_state->vb_index + 3) * 24) > (accel_state->ib->total / 2)) { + R600DoneComposite(pDst); + accel_state->vb_index = 0; + accel_state->ib = RHDDRMCPBuffer(pScrn->scrnIndex); + } + + vb = (pointer)((char*)accel_state->ib->address + + (accel_state->ib->total / 2) + + accel_state->vb_index * 24); + + maskTopLeft.x = IntToxFixed(maskX); + maskTopLeft.y = IntToxFixed(maskY); + maskTopRight.x = IntToxFixed(maskX + w); + maskTopRight.y = IntToxFixed(maskY); + maskBottomLeft.x = IntToxFixed(maskX); + maskBottomLeft.y = IntToxFixed(maskY + h); + maskBottomRight.x = IntToxFixed(maskX + w); + maskBottomRight.y = IntToxFixed(maskY + h); + + if (accel_state->is_transform[1]) { + transformPoint(accel_state->transform[1], &maskTopLeft); + transformPoint(accel_state->transform[1], &maskTopRight); + transformPoint(accel_state->transform[1], &maskBottomLeft); + transformPoint(accel_state->transform[1], &maskBottomRight); + } + + vb[0] = (float)dstX; + vb[1] = (float)dstY; + vb[2] = xFixedToFloat(srcTopLeft.x) / accel_state->texW[0]; + vb[3] = xFixedToFloat(srcTopLeft.y) / accel_state->texH[0]; + vb[4] = xFixedToFloat(maskTopLeft.x) / accel_state->texW[1]; + vb[5] = xFixedToFloat(maskTopLeft.y) / accel_state->texH[1]; + + vb[6] = (float)dstX; + vb[7] = (float)(dstY + h); + vb[8] = xFixedToFloat(srcBottomLeft.x) / accel_state->texW[0]; + vb[9] = xFixedToFloat(srcBottomLeft.y) / accel_state->texH[0]; + vb[10] = xFixedToFloat(maskBottomLeft.x) / accel_state->texW[1]; + vb[11] = xFixedToFloat(maskBottomLeft.y) / accel_state->texH[1]; + + vb[12] = (float)(dstX + w); + vb[13] = (float)(dstY + h); + vb[14] = xFixedToFloat(srcBottomRight.x) / accel_state->texW[0]; + vb[15] = xFixedToFloat(srcBottomRight.y) / accel_state->texH[0]; + vb[16] = xFixedToFloat(maskBottomRight.x) / accel_state->texW[1]; + vb[17] = xFixedToFloat(maskBottomRight.y) / accel_state->texH[1]; + + } else { + vb = (pointer)((char*)accel_state->ib->address + + (accel_state->ib->total / 2) + + accel_state->vb_index * 16); + + vb[0] = (float)dstX; + vb[1] = (float)dstY; + vb[2] = xFixedToFloat(srcTopLeft.x) / accel_state->texW[0]; + vb[3] = xFixedToFloat(srcTopLeft.y) / accel_state->texH[0]; + + vb[4] = (float)dstX; + vb[5] = (float)(dstY + h); + vb[6] = xFixedToFloat(srcBottomLeft.x) / accel_state->texW[0]; + vb[7] = xFixedToFloat(srcBottomLeft.y) / accel_state->texH[0]; + + vb[8] = (float)(dstX + w); + vb[9] = (float)(dstY + h); + vb[10] = xFixedToFloat(srcBottomRight.x) / accel_state->texW[0]; + vb[11] = xFixedToFloat(srcBottomRight.y) / accel_state->texH[0]; + } + + accel_state->vb_index += 3; + +} + +static void R600DoneComposite(PixmapPtr pDst) +{ + ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + draw_config_t draw_conf; + vtx_resource_t vtx_res; + + CLEAR (draw_conf); + CLEAR (vtx_res); + + if (accel_state->vb_index == 0) { + R600IBDiscard(pScrn, accel_state->ib); + return; + } + + accel_state->vb_mc_addr = RHDDRIGetIntGARTLocation(pScrn) + + (accel_state->ib->idx * accel_state->ib->total) + (accel_state->ib->total / 2); + + + /* Vertex buffer setup */ + if (accel_state->has_mask) { + accel_state->vb_size = accel_state->vb_index * 24; + vtx_res.id = SQ_VTX_RESOURCE_vs; + vtx_res.vtx_size_dw = 24 / 4; + vtx_res.vtx_num_entries = accel_state->vb_size / 4; + vtx_res.mem_req_size = 1; + vtx_res.vb_addr = accel_state->vb_mc_addr; + } else { + accel_state->vb_size = accel_state->vb_index * 16; + vtx_res.id = SQ_VTX_RESOURCE_vs; + vtx_res.vtx_size_dw = 16 / 4; + vtx_res.vtx_num_entries = accel_state->vb_size / 4; + vtx_res.mem_req_size = 1; + vtx_res.vb_addr = accel_state->vb_mc_addr; + } + /* flush vertex cache */ + if ((rhdPtr->ChipSet == RHD_RV610) || + (rhdPtr->ChipSet == RHD_RV620) || + (rhdPtr->ChipSet == RHD_M72) || + (rhdPtr->ChipSet == RHD_M74) || + (rhdPtr->ChipSet == RHD_M82) || + (rhdPtr->ChipSet == RHD_RS780) || + (rhdPtr->ChipSet == RHD_RV710)) + cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, + accel_state->vb_size, accel_state->vb_mc_addr); + else + cp_set_surface_sync(pScrn, accel_state->ib, VC_ACTION_ENA_bit, + accel_state->vb_size, accel_state->vb_mc_addr); + + set_vtx_resource (pScrn, accel_state->ib, &vtx_res); + + draw_conf.prim_type = DI_PT_RECTLIST; + draw_conf.vgt_draw_initiator = DI_SRC_SEL_AUTO_INDEX; + draw_conf.num_instances = 1; + draw_conf.num_indices = vtx_res.vtx_num_entries / vtx_res.vtx_size_dw; + draw_conf.index_type = DI_INDEX_SIZE_16_BIT; + + draw_auto(pScrn, accel_state->ib, &draw_conf); + + wait_3d_idle_clean(pScrn, accel_state->ib); + + cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit), + accel_state->dst_size, accel_state->dst_mc_addr); + + R600CPFlushIndirect(pScrn, accel_state->ib); +} + +Bool +R600CopyToVRAM(ScrnInfoPtr pScrn, + char *src, int src_pitch, + uint32_t dst_pitch, uint32_t dst_mc_addr, uint32_t dst_height, int bpp, + int x, int y, int w, int h) +{ + struct RhdCS *CS = RHDPTR(pScrn)->CS; + uint32_t scratch_mc_addr; + int wpass = w * (bpp/8); + int scratch_pitch_bytes = (wpass + 255) & ~255; + uint32_t scratch_pitch = scratch_pitch_bytes / (bpp / 8); + int scratch_offset = 0, hpass, temph; + char *dst; + drmBufPtr scratch; + + if (dst_pitch & 7) + return FALSE; + + if (dst_mc_addr & 0xff) + return FALSE; + + scratch = RHDDRMCPBuffer(pScrn->scrnIndex); + if (scratch == NULL) + return FALSE; + + scratch_mc_addr = RHDDRIGetIntGARTLocation(pScrn) + (scratch->idx * scratch->total); + temph = hpass = min(h, scratch->total/2 / scratch_pitch_bytes); + dst = (char *)scratch->address; + + /* memcopy from sys to scratch */ + while (temph--) { + memcpy (dst, src, wpass); + src += src_pitch; + dst += scratch_pitch_bytes; + } + + while (h) { + uint32_t offset = scratch_mc_addr + scratch_offset; + int oldhpass = hpass; + h -= oldhpass; + temph = hpass = min(h, scratch->total/2 / scratch_pitch_bytes); + + if (hpass) { + scratch_offset = scratch->total/2 - scratch_offset; + dst = (char *)scratch->address + scratch_offset; + /* wait for the engine to be idle */ + RHDCSIdle(CS); + /* memcopy from sys to scratch */ + while (temph--) { + memcpy (dst, src, wpass); + src += src_pitch; + dst += scratch_pitch_bytes; + } + } + /* blit from scratch to vram */ + R600DoPrepareCopy(pScrn, + scratch_pitch, w, oldhpass, offset, bpp, + dst_pitch, dst_height, dst_mc_addr, bpp, + 3, 0xffffffff); + R600AppendCopyVertex(pScrn, 0, 0, x, y, w, oldhpass); + R600DoCopy(pScrn); + y += oldhpass; + } + + R600IBDiscard(pScrn, scratch); + + return TRUE; +} + +static Bool +R600UploadToScreen(PixmapPtr pDst, int x, int y, int w, int h, + char *src, int src_pitch) +{ + ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + uint32_t dst_pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); + uint32_t dst_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + exaGetPixmapOffset(pDst); + uint32_t dst_height = pDst->drawable.height; + int bpp = pDst->drawable.bitsPerPixel; + + return R600CopyToVRAM(pScrn, + src, src_pitch, + dst_pitch, dst_mc_addr, dst_height, bpp, + x, y, w, h); +} + +static Bool +R600DownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h, + char *dst, int dst_pitch) +{ + ScrnInfoPtr pScrn = xf86Screens[pSrc->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct RhdCS *CS = rhdPtr->CS; + uint32_t src_pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8); + uint32_t src_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + exaGetPixmapOffset(pSrc); + uint32_t src_width = pSrc->drawable.width; + uint32_t src_height = pSrc->drawable.height; + int bpp = pSrc->drawable.bitsPerPixel; + uint32_t scratch_mc_addr; + int scratch_pitch_bytes = (dst_pitch + 255) & ~255; + int scratch_offset = 0, hpass; + uint32_t scratch_pitch = scratch_pitch_bytes / (bpp / 8); + int wpass = w * (bpp/8); + drmBufPtr scratch; + + if (src_pitch & 7) + return FALSE; + + scratch = RHDDRMCPBuffer(pScrn->scrnIndex); + if (scratch == NULL) + return FALSE; + + scratch_mc_addr = RHDDRIGetIntGARTLocation(pScrn) + (scratch->idx * scratch->total); + hpass = min(h, scratch->total/2 / scratch_pitch_bytes); + + /* blit from vram to scratch */ + R600DoPrepareCopy(pScrn, + src_pitch, src_width, src_height, src_mc_addr, bpp, + scratch_pitch, hpass, scratch_mc_addr, bpp, + 3, 0xffffffff); + R600AppendCopyVertex(pScrn, x, y, 0, 0, w, hpass); + R600DoCopy(pScrn); + + while (h) { + char *src = (char *)scratch->address + scratch_offset; + int oldhpass = hpass; + h -= oldhpass; + y += oldhpass; + hpass = min(h, scratch->total/2 / scratch_pitch_bytes); + + if (hpass) { + scratch_offset = scratch->total/2 - scratch_offset; + /* blit from vram to scratch */ + R600DoPrepareCopy(pScrn, + src_pitch, src_width, src_height, src_mc_addr, bpp, + scratch_pitch, hpass, scratch_mc_addr + scratch_offset, bpp, + 3, 0xffffffff); + R600AppendCopyVertex(pScrn, x, y, 0, 0, w, hpass); + R600DoCopy(pScrn); + } + + /* wait for the engine to be idle */ + RHDCSIdle(CS); + /* memcopy from scratch to sys */ + while (oldhpass--) { + memcpy (dst, src, wpass); + dst += dst_pitch; + src += scratch_pitch_bytes; + } + } + + R600IBDiscard(pScrn, scratch); + + return TRUE; + +} + +void +R6xxEXACloseScreen(ScreenPtr pScreen) +{ + exaDriverFini(pScreen); +} + +void +R6xxEXADestroy(ScrnInfoPtr pScrn) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + + if (rhdPtr->EXAInfo) { + xfree(rhdPtr->EXAInfo); + rhdPtr->EXAInfo = NULL; + } + + if (rhdPtr->TwoDPrivate) { + xfree(rhdPtr->TwoDPrivate); + rhdPtr->TwoDPrivate = NULL; + } +} + +/* no need to needlessly flush the caches/wait for idle + * the drawing code does this already (and mesa code should be designed to do so as well) + * excessive idling/flushing seems to cause stability problems on + * r7xx and drawing glitches on r6xx. + */ +void +R6xxCacheFlush(struct RhdCS *CS) +{ + CS = CS; /* nop - avoid compiler warning */ +} + +void +R6xxEngineWaitIdleFull(struct RhdCS *CS) +{ + CS = CS; /* nop - avoid compiler warning */ +} + +static int +R600EXAMarkSync(ScreenPtr pScreen) +{ + struct r6xx_accel_state *accel_state = RHDPTR(xf86Screens[pScreen->myNum])->TwoDPrivate; + + return ++accel_state->exaSyncMarker; + +} + +static void +R600EXASync(ScreenPtr pScreen, int marker) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + struct r6xx_accel_state *accel_state = RHDPTR(pScrn)->TwoDPrivate; + + if (accel_state->exaMarkerSynced != marker) { + struct RhdCS *CS = RHDPTR(pScrn)->CS; + + RHDCSIdle(CS); + + accel_state->exaMarkerSynced = marker; + } +} + +static Bool +R600AllocShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + /* 512 bytes per shader for now */ + int size = 512 * 9; + + accel_state->shaders = NULL; + + accel_state->shaders = exaOffscreenAlloc(pScreen, size, 256, + TRUE, NULL, NULL); + + if (accel_state->shaders == NULL) + return FALSE; + return TRUE; +} + +Bool +R600LoadShaders(ScrnInfoPtr pScrn) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + enum RHD_CHIPSETS ChipSet = rhdPtr->ChipSet; + uint32_t *shader; + + shader = (pointer)((char *)rhdPtr->FbBase + rhdPtr->FbScanoutStart + accel_state->shaders->offset); + + /* solid vs --------------------------------------- */ + accel_state->solid_vs_offset = 0; + R600_solid_vs(ChipSet, shader + accel_state->solid_vs_offset / 4); + + /* solid ps --------------------------------------- */ + accel_state->solid_ps_offset = 512; + R600_solid_ps(ChipSet, shader + accel_state->solid_ps_offset / 4); + + /* copy vs --------------------------------------- */ + accel_state->copy_vs_offset = 1024; + R600_copy_vs(ChipSet, shader + accel_state->copy_vs_offset / 4); + + /* copy ps --------------------------------------- */ + accel_state->copy_ps_offset = 1536; + R600_copy_ps(ChipSet, shader + accel_state->copy_ps_offset / 4); + + /* comp vs --------------------------------------- */ + accel_state->comp_vs_offset = 2048; + R600_comp_vs(ChipSet, shader + accel_state->comp_vs_offset / 4); + + /* comp ps --------------------------------------- */ + accel_state->comp_ps_offset = 2560; + R600_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4); + + /* comp mask ps --------------------------------------- */ + accel_state->comp_mask_ps_offset = 3072; + R600_comp_mask_ps(ChipSet, shader + accel_state->comp_mask_ps_offset / 4); + + /* xv vs --------------------------------------- */ + accel_state->xv_vs_offset = 3584; + R600_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4); + + /* xv ps --------------------------------------- */ + accel_state->xv_ps_offset = 4096; + R600_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4); + + return TRUE; +} + +static Bool +R600PrepareAccess(PixmapPtr pPix, int index) +{ + ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + + /* flush HDP read/write caches */ + RHDRegWrite(rhdPtr, HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); + + return TRUE; +} + +static void +R600FinishAccess(PixmapPtr pPix, int index) +{ + ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + + /* flush HDP read/write caches */ + RHDRegWrite(rhdPtr, HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); + +} + + +Bool +R6xxEXAInit(ScrnInfoPtr pScrn, ScreenPtr pScreen) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + struct RhdCS *CS = rhdPtr->CS; + ExaDriverRec *EXAInfo; + struct r6xx_accel_state *accel_state; + + RHDFUNC(pScrn); + + EXAInfo = exaDriverAlloc(); + if (EXAInfo == NULL || !CS) + return FALSE; + + accel_state = xnfcalloc(1, sizeof(struct r6xx_accel_state)); + + EXAInfo->exa_major = EXA_VERSION_MAJOR; + EXAInfo->exa_minor = EXA_VERSION_MINOR; + + EXAInfo->flags = EXA_OFFSCREEN_PIXMAPS; + EXAInfo->pixmapOffsetAlign = 256; + EXAInfo->pixmapPitchAlign = 256; + +#if EXA_VERSION_MAJOR > 2 || (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 3) + EXAInfo->maxPitchBytes = 32768; + EXAInfo->maxX = 8192; +#else + EXAInfo->maxX = 8192; +#endif + EXAInfo->maxY = 8192; + + EXAInfo->memoryBase = (CARD8 *) rhdPtr->FbBase + rhdPtr->FbScanoutStart; + EXAInfo->offScreenBase = rhdPtr->FbOffscreenStart - rhdPtr->FbScanoutStart; + EXAInfo->memorySize = rhdPtr->FbScanoutSize + rhdPtr->FbOffscreenSize; + + EXAInfo->PrepareSolid = R600PrepareSolid; + EXAInfo->Solid = R600Solid; + EXAInfo->DoneSolid = R600DoneSolid; + + EXAInfo->PrepareCopy = R600PrepareCopy; + EXAInfo->Copy = R600Copy; + EXAInfo->DoneCopy = R600DoneCopy; + + EXAInfo->CheckComposite = R600CheckComposite; + EXAInfo->PrepareComposite = R600PrepareComposite; + EXAInfo->Composite = R600Composite; + EXAInfo->DoneComposite = R600DoneComposite; + + if (rhdPtr->cardType != RHD_CARD_AGP) { + EXAInfo->UploadToScreen = R600UploadToScreen; + EXAInfo->DownloadFromScreen = R600DownloadFromScreen; + } + + EXAInfo->PrepareAccess = R600PrepareAccess; + EXAInfo->FinishAccess = R600FinishAccess; + + EXAInfo->MarkSync = R600EXAMarkSync; + EXAInfo->WaitMarker = R600EXASync; + + if (!exaDriverInit(pScreen, EXAInfo)) { + xfree(accel_state); + xfree(EXAInfo); + return FALSE; + } + + RHDPTR(pScrn)->EXAInfo = EXAInfo; + + accel_state->XHas3DEngineState = FALSE; + accel_state->copy_area = NULL; + + rhdPtr->TwoDPrivate = accel_state; + + if (!R600AllocShaders(pScrn, pScreen)) { + xfree(accel_state); + xfree(EXAInfo); + return FALSE; + } + + if (!R600LoadShaders(pScrn)) { + xfree(accel_state); + xfree(EXAInfo); + return FALSE; + } + + exaMarkSync(pScreen); + + return TRUE; +} + diff --git a/driver/xf86-video-radeonhd/src/r600_reg.h b/driver/xf86-video-radeonhd/src/r600_reg.h new file mode 100644 index 000000000..66dba68f0 --- /dev/null +++ b/driver/xf86-video-radeonhd/src/r600_reg.h @@ -0,0 +1,140 @@ +/* + * RadeonHD R6xx, R7xx Register documentation + * + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2009 Matthias Hopf + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _R600_REG_H_ +#define _R600_REG_H_ + +/* + * Register definitions + */ + +#include "r600_reg_auto_r6xx.h" +#include "r600_reg_r6xx.h" +#include "r600_reg_r7xx.h" + + +/* SET_*_REG offsets + ends */ +enum { + SET_CONFIG_REG_offset = 0x00008000, + SET_CONFIG_REG_end = 0x0000ac00, + SET_CONTEXT_REG_offset = 0x00028000, + SET_CONTEXT_REG_end = 0x00029000, + SET_ALU_CONST_offset = 0x00030000, + SET_ALU_CONST_end = 0x00032000, + SET_RESOURCE_offset = 0x00038000, + SET_RESOURCE_end = 0x0003c000, + SET_SAMPLER_offset = 0x0003c000, + SET_SAMPLER_end = 0x0003cff0, + SET_CTL_CONST_offset = 0x0003cff0, + SET_CTL_CONST_end = 0x0003e200, + SET_LOOP_CONST_offset = 0x0003e200, + SET_LOOP_CONST_end = 0x0003e380, + SET_BOOL_CONST_offset = 0x0003e380, + SET_BOOL_CONST_end = 0x0003e38c, +}; + +/* packet3 IT_SURFACE_BASE_UPDATE bits */ +enum { + DEPTH_BASE = (1 << 0), + COLOR0_BASE = (1 << 1), + COLOR1_BASE = (1 << 2), + COLOR2_BASE = (1 << 3), + COLOR3_BASE = (1 << 4), + COLOR4_BASE = (1 << 5), + COLOR5_BASE = (1 << 6), + COLOR6_BASE = (1 << 7), + COLOR7_BASE = (1 << 8), + STRMOUT_BASE0 = (1 << 9), + STRMOUT_BASE1 = (1 << 10), + STRMOUT_BASE2 = (1 << 11), + STRMOUT_BASE3 = (1 << 12), + COHER_BASE0 = (1 << 13), + COHER_BASE1 = (1 << 14) +}; + +/* packet3 IT_WAIT_REG_MEM operation encoding */ +enum { + WAIT_ALWAYS = (0<<0), + WAIT_LT = (1<<0), + WAIT_LE = (2<<0), + WAIT_EQ = (3<<0), + WAIT_NE = (4<<0), + WAIT_GE = (5<<0), + WAIT_GT = (6<<0), + + WAIT_REG = (0<<4), + WAIT_MEM = (1<<4) +}; + +/* CP packet types */ +enum { + RADEON_CP_PACKET0 = 0x00000000, + RADEON_CP_PACKET1 = 0x40000000, + RADEON_CP_PACKET2 = 0x80000000, + RADEON_CP_PACKET3 = 0xC0000000 +}; + +/* Packet3 commands */ +enum { + IT_NOP = 0x10, + IT_INDIRECT_BUFFER_END = 0x17, + IT_SET_PREDICATION = 0x20, + IT_REG_RMW = 0x21, + IT_COND_EXEC = 0x22, + IT_PRED_EXEC = 0x23, + IT_START_3D_CMDBUF = 0x24, + IT_DRAW_INDEX_2 = 0x27, + IT_CONTEXT_CONTROL = 0x28, + IT_DRAW_INDEX_IMMD_BE = 0x29, + IT_INDEX_TYPE = 0x2A, + IT_DRAW_INDEX = 0x2B, + IT_DRAW_INDEX_AUTO = 0x2D, + IT_DRAW_INDEX_IMMD = 0x2E, + IT_NUM_INSTANCES = 0x2F, + IT_STRMOUT_BUFFER_UPDATE = 0x34, + IT_INDIRECT_BUFFER_MP = 0x38, + IT_MEM_SEMAPHORE = 0x39, + IT_MPEG_INDEX = 0x3A, + IT_WAIT_REG_MEM = 0x3C, + IT_MEM_WRITE = 0x3D, + IT_INDIRECT_BUFFER = 0x32, + IT_CP_INTERRUPT = 0x40, + IT_SURFACE_SYNC = 0x43, + IT_ME_INITIALIZE = 0x44, + IT_COND_WRITE = 0x45, + IT_EVENT_WRITE = 0x46, + IT_EVENT_WRITE_EOP = 0x47, + IT_ONE_REG_WRITE = 0x57, + IT_SET_CONFIG_REG = 0x68, + IT_SET_CONTEXT_REG = 0x69, + IT_SET_ALU_CONST = 0x6A, + IT_SET_BOOL_CONST = 0x6B, + IT_SET_LOOP_CONST = 0x6C, + IT_SET_RESOURCE = 0x6D, + IT_SET_SAMPLER = 0x6E, + IT_SET_CTL_CONST = 0x6F, + IT_SURFACE_BASE_UPDATE = 0x73 +}; + +#endif diff --git a/driver/xf86-video-radeonhd/src/r600_reg_auto_r6xx.h b/driver/xf86-video-radeonhd/src/r600_reg_auto_r6xx.h new file mode 100644 index 000000000..9d5aa3c7e --- /dev/null +++ b/driver/xf86-video-radeonhd/src/r600_reg_auto_r6xx.h @@ -0,0 +1,3087 @@ +/* + * RadeonHD R6xx, R7xx Register documentation + * + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2009 Matthias Hopf + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _AUTOREGS +#define _AUTOREGS + +enum { + + VGT_VTX_VECT_EJECT_REG = 0x000088b0, + PRIM_COUNT_mask = 0x3ff << 0, + PRIM_COUNT_shift = 0, + VGT_LAST_COPY_STATE = 0x000088c0, + SRC_STATE_ID_mask = 0x07 << 0, + SRC_STATE_ID_shift = 0, + DST_STATE_ID_mask = 0x07 << 16, + DST_STATE_ID_shift = 16, + VGT_CACHE_INVALIDATION = 0x000088c4, + CACHE_INVALIDATION_mask = 0x03 << 0, + CACHE_INVALIDATION_shift = 0, + VC_ONLY = 0x00, + TC_ONLY = 0x01, + VC_AND_TC = 0x02, + VS_NO_EXTRA_BUFFER_bit = 1 << 5, + VGT_GS_PER_ES = 0x000088c8, + VGT_ES_PER_GS = 0x000088cc, + VGT_GS_VERTEX_REUSE = 0x000088d4, + VERT_REUSE_mask = 0x1f << 0, + VERT_REUSE_shift = 0, + VGT_MC_LAT_CNTL = 0x000088d8, + MC_TIME_STAMP_RES_mask = 0x03 << 0, + MC_TIME_STAMP_RES_shift = 0, + X_0_992_MAX_LATENCY = 0x00, + X_0_496_MAX_LATENCY = 0x01, + X_0_248_MAX_LATENCY = 0x02, + X_0_124_MAX_LATENCY = 0x03, + VGT_GS_PER_VS = 0x000088e8, + GS_PER_VS_mask = 0x0f << 0, + GS_PER_VS_shift = 0, + VGT_CNTL_STATUS = 0x000088f0, + VGT_OUT_INDX_BUSY_bit = 1 << 0, + VGT_OUT_BUSY_bit = 1 << 1, + VGT_PT_BUSY_bit = 1 << 2, + VGT_TE_BUSY_bit = 1 << 3, + VGT_VR_BUSY_bit = 1 << 4, + VGT_GRP_BUSY_bit = 1 << 5, + VGT_DMA_REQ_BUSY_bit = 1 << 6, + VGT_DMA_BUSY_bit = 1 << 7, + VGT_GS_BUSY_bit = 1 << 8, + VGT_BUSY_bit = 1 << 9, + VGT_PRIMITIVE_TYPE = 0x00008958, + VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask = 0x3f << 0, + VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift = 0, + DI_PT_NONE = 0x00, + DI_PT_POINTLIST = 0x01, + DI_PT_LINELIST = 0x02, + DI_PT_LINESTRIP = 0x03, + DI_PT_TRILIST = 0x04, + DI_PT_TRIFAN = 0x05, + DI_PT_TRISTRIP = 0x06, + DI_PT_UNUSED_0 = 0x07, + DI_PT_UNUSED_1 = 0x08, + DI_PT_UNUSED_2 = 0x09, + DI_PT_LINELIST_ADJ = 0x0a, + DI_PT_LINESTRIP_ADJ = 0x0b, + DI_PT_TRILIST_ADJ = 0x0c, + DI_PT_TRISTRIP_ADJ = 0x0d, + DI_PT_UNUSED_3 = 0x0e, + DI_PT_UNUSED_4 = 0x0f, + DI_PT_TRI_WITH_WFLAGS = 0x10, + DI_PT_RECTLIST = 0x11, + DI_PT_LINELOOP = 0x12, + DI_PT_QUADLIST = 0x13, + DI_PT_QUADSTRIP = 0x14, + DI_PT_POLYGON = 0x15, + DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, + DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, + DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, + DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, + DI_PT_2D_FILL_RECT_LIST = 0x1a, + DI_PT_2D_LINE_STRIP = 0x1b, + DI_PT_2D_TRI_STRIP = 0x1c, + VGT_INDEX_TYPE = 0x0000895c, + INDEX_TYPE_mask = 0x03 << 0, + INDEX_TYPE_shift = 0, + DI_INDEX_SIZE_16_BIT = 0x00, + DI_INDEX_SIZE_32_BIT = 0x01, + VGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x00008960, + VGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x00008964, + VGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x00008968, + VGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x0000896c, + VGT_NUM_INDICES = 0x00008970, + VGT_NUM_INSTANCES = 0x00008974, + PA_CL_CNTL_STATUS = 0x00008a10, + CL_BUSY_bit = 1 << 31, + PA_CL_ENHANCE = 0x00008a14, + CLIP_VTX_REORDER_ENA_bit = 1 << 0, + NUM_CLIP_SEQ_mask = 0x03 << 1, + NUM_CLIP_SEQ_shift = 1, + CLIPPED_PRIM_SEQ_STALL_bit = 1 << 3, + VE_NAN_PROC_DISABLE_bit = 1 << 4, + PA_SU_CNTL_STATUS = 0x00008a50, + SU_BUSY_bit = 1 << 31, + PA_SC_LINE_STIPPLE_STATE = 0x00008b10, + CURRENT_PTR_mask = 0x0f << 0, + CURRENT_PTR_shift = 0, + CURRENT_COUNT_mask = 0xff << 8, + CURRENT_COUNT_shift = 8, + PA_SC_MULTI_CHIP_CNTL = 0x00008b20, + LOG2_NUM_CHIPS_mask = 0x07 << 0, + LOG2_NUM_CHIPS_shift = 0, + MULTI_CHIP_TILE_SIZE_mask = 0x03 << 3, + MULTI_CHIP_TILE_SIZE_shift = 3, + X_16_X_16_PIXEL_TILE_PER_CHIP = 0x00, + X_32_X_32_PIXEL_TILE_PER_CHIP = 0x01, + X_64_X_64_PIXEL_TILE_PER_CHIP = 0x02, + X_128X128_PIXEL_TILE_PER_CHIP = 0x03, + CHIP_TILE_X_LOC_mask = 0x07 << 5, + CHIP_TILE_X_LOC_shift = 5, + CHIP_TILE_Y_LOC_mask = 0x07 << 8, + CHIP_TILE_Y_LOC_shift = 8, + CHIP_SUPER_TILE_B_bit = 1 << 11, + PA_SC_AA_SAMPLE_LOCS_2S = 0x00008b40, + S0_X_mask = 0x0f << 0, + S0_X_shift = 0, + S0_Y_mask = 0x0f << 4, + S0_Y_shift = 4, + S1_X_mask = 0x0f << 8, + S1_X_shift = 8, + S1_Y_mask = 0x0f << 12, + S1_Y_shift = 12, + PA_SC_AA_SAMPLE_LOCS_4S = 0x00008b44, +/* S0_X_mask = 0x0f << 0, */ +/* S0_X_shift = 0, */ +/* S0_Y_mask = 0x0f << 4, */ +/* S0_Y_shift = 4, */ +/* S1_X_mask = 0x0f << 8, */ +/* S1_X_shift = 8, */ +/* S1_Y_mask = 0x0f << 12, */ +/* S1_Y_shift = 12, */ + S2_X_mask = 0x0f << 16, + S2_X_shift = 16, + S2_Y_mask = 0x0f << 20, + S2_Y_shift = 20, + S3_X_mask = 0x0f << 24, + S3_X_shift = 24, + S3_Y_mask = 0x0f << 28, + S3_Y_shift = 28, + PA_SC_AA_SAMPLE_LOCS_8S_WD0 = 0x00008b48, +/* S0_X_mask = 0x0f << 0, */ +/* S0_X_shift = 0, */ +/* S0_Y_mask = 0x0f << 4, */ +/* S0_Y_shift = 4, */ +/* S1_X_mask = 0x0f << 8, */ +/* S1_X_shift = 8, */ +/* S1_Y_mask = 0x0f << 12, */ +/* S1_Y_shift = 12, */ +/* S2_X_mask = 0x0f << 16, */ +/* S2_X_shift = 16, */ +/* S2_Y_mask = 0x0f << 20, */ +/* S2_Y_shift = 20, */ +/* S3_X_mask = 0x0f << 24, */ +/* S3_X_shift = 24, */ +/* S3_Y_mask = 0x0f << 28, */ +/* S3_Y_shift = 28, */ + PA_SC_AA_SAMPLE_LOCS_8S_WD1 = 0x00008b4c, + S4_X_mask = 0x0f << 0, + S4_X_shift = 0, + S4_Y_mask = 0x0f << 4, + S4_Y_shift = 4, + S5_X_mask = 0x0f << 8, + S5_X_shift = 8, + S5_Y_mask = 0x0f << 12, + S5_Y_shift = 12, + S6_X_mask = 0x0f << 16, + S6_X_shift = 16, + S6_Y_mask = 0x0f << 20, + S6_Y_shift = 20, + S7_X_mask = 0x0f << 24, + S7_X_shift = 24, + S7_Y_mask = 0x0f << 28, + S7_Y_shift = 28, + PA_SC_CNTL_STATUS = 0x00008be0, + MPASS_OVERFLOW_bit = 1 << 30, + PA_SC_ENHANCE = 0x00008bf0, + FORCE_EOV_MAX_CLK_CNT_mask = 0xfff << 0, + FORCE_EOV_MAX_CLK_CNT_shift = 0, + FORCE_EOV_MAX_TILE_CNT_mask = 0xfff << 12, + FORCE_EOV_MAX_TILE_CNT_shift = 12, + SQ_CONFIG = 0x00008c00, + VC_ENABLE_bit = 1 << 0, + EXPORT_SRC_C_bit = 1 << 1, + DX9_CONSTS_bit = 1 << 2, + ALU_INST_PREFER_VECTOR_bit = 1 << 3, + SQ_CONFIG__DX10_CLAMP_bit = 1 << 4, + ALU_PREFER_ONE_WATERFALL_bit = 1 << 5, + ALU_MAX_ONE_WATERFALL_bit = 1 << 6, + CLAUSE_SEQ_PRIO_mask = 0x03 << 8, + CLAUSE_SEQ_PRIO_shift = 8, + SQ_CL_PRIO_RND_ROBIN = 0x00, + SQ_CL_PRIO_MACRO_SEQ = 0x01, + SQ_CL_PRIO_NONE = 0x02, + PS_PRIO_mask = 0x03 << 24, + PS_PRIO_shift = 24, + VS_PRIO_mask = 0x03 << 26, + VS_PRIO_shift = 26, + GS_PRIO_mask = 0x03 << 28, + GS_PRIO_shift = 28, + ES_PRIO_mask = 0x03 << 30, + ES_PRIO_shift = 30, + SQ_GPR_RESOURCE_MGMT_1 = 0x00008c04, + NUM_PS_GPRS_mask = 0xff << 0, + NUM_PS_GPRS_shift = 0, + NUM_VS_GPRS_mask = 0xff << 16, + NUM_VS_GPRS_shift = 16, + NUM_CLAUSE_TEMP_GPRS_mask = 0x0f << 28, + NUM_CLAUSE_TEMP_GPRS_shift = 28, + SQ_GPR_RESOURCE_MGMT_2 = 0x00008c08, + NUM_GS_GPRS_mask = 0xff << 0, + NUM_GS_GPRS_shift = 0, + NUM_ES_GPRS_mask = 0xff << 16, + NUM_ES_GPRS_shift = 16, + SQ_THREAD_RESOURCE_MGMT = 0x00008c0c, + NUM_PS_THREADS_mask = 0xff << 0, + NUM_PS_THREADS_shift = 0, + NUM_VS_THREADS_mask = 0xff << 8, + NUM_VS_THREADS_shift = 8, + NUM_GS_THREADS_mask = 0xff << 16, + NUM_GS_THREADS_shift = 16, + NUM_ES_THREADS_mask = 0xff << 24, + NUM_ES_THREADS_shift = 24, + SQ_STACK_RESOURCE_MGMT_1 = 0x00008c10, + NUM_PS_STACK_ENTRIES_mask = 0xfff << 0, + NUM_PS_STACK_ENTRIES_shift = 0, + NUM_VS_STACK_ENTRIES_mask = 0xfff << 16, + NUM_VS_STACK_ENTRIES_shift = 16, + SQ_STACK_RESOURCE_MGMT_2 = 0x00008c14, + NUM_GS_STACK_ENTRIES_mask = 0xfff << 0, + NUM_GS_STACK_ENTRIES_shift = 0, + NUM_ES_STACK_ENTRIES_mask = 0xfff << 16, + NUM_ES_STACK_ENTRIES_shift = 16, + SQ_ESGS_RING_BASE = 0x00008c40, + SQ_ESGS_RING_SIZE = 0x00008c44, + SQ_GSVS_RING_BASE = 0x00008c48, + SQ_GSVS_RING_SIZE = 0x00008c4c, + SQ_ESTMP_RING_BASE = 0x00008c50, + SQ_ESTMP_RING_SIZE = 0x00008c54, + SQ_GSTMP_RING_BASE = 0x00008c58, + SQ_GSTMP_RING_SIZE = 0x00008c5c, + SQ_VSTMP_RING_BASE = 0x00008c60, + SQ_VSTMP_RING_SIZE = 0x00008c64, + SQ_PSTMP_RING_BASE = 0x00008c68, + SQ_PSTMP_RING_SIZE = 0x00008c6c, + SQ_FBUF_RING_BASE = 0x00008c70, + SQ_FBUF_RING_SIZE = 0x00008c74, + SQ_REDUC_RING_BASE = 0x00008c78, + SQ_REDUC_RING_SIZE = 0x00008c7c, + SQ_ALU_WORD1_OP3 = 0x00008dfc, + SRC2_SEL_mask = 0x1ff << 0, + SRC2_SEL_shift = 0, + SQ_ALU_SRC_0 = 0xf8, + SQ_ALU_SRC_1 = 0xf9, + SQ_ALU_SRC_1_INT = 0xfa, + SQ_ALU_SRC_M_1_INT = 0xfb, + SQ_ALU_SRC_0_5 = 0xfc, + SQ_ALU_SRC_LITERAL = 0xfd, + SQ_ALU_SRC_PV = 0xfe, + SQ_ALU_SRC_PS = 0xff, + SRC2_REL_bit = 1 << 9, + SRC2_CHAN_mask = 0x03 << 10, + SRC2_CHAN_shift = 10, + SQ_CHAN_X = 0x00, + SQ_CHAN_Y = 0x01, + SQ_CHAN_Z = 0x02, + SQ_CHAN_W = 0x03, + SRC2_NEG_bit = 1 << 12, + SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, + SQ_ALU_WORD1_OP3__ALU_INST_shift = 13, + SQ_OP3_INST_MUL_LIT = 0x0c, + SQ_OP3_INST_MUL_LIT_M2 = 0x0d, + SQ_OP3_INST_MUL_LIT_M4 = 0x0e, + SQ_OP3_INST_MUL_LIT_D2 = 0x0f, + SQ_OP3_INST_MULADD = 0x10, + SQ_OP3_INST_MULADD_M2 = 0x11, + SQ_OP3_INST_MULADD_M4 = 0x12, + SQ_OP3_INST_MULADD_D2 = 0x13, + SQ_OP3_INST_MULADD_IEEE = 0x14, + SQ_OP3_INST_MULADD_IEEE_M2 = 0x15, + SQ_OP3_INST_MULADD_IEEE_M4 = 0x16, + SQ_OP3_INST_MULADD_IEEE_D2 = 0x17, + SQ_OP3_INST_CNDE = 0x18, + SQ_OP3_INST_CNDGT = 0x19, + SQ_OP3_INST_CNDGE = 0x1a, + SQ_OP3_INST_CNDE_INT = 0x1c, + SQ_OP3_INST_CNDGT_INT = 0x1d, + SQ_OP3_INST_CNDGE_INT = 0x1e, + SQ_TEX_WORD2 = 0x00008dfc, + OFFSET_X_mask = 0x1f << 0, + OFFSET_X_shift = 0, + OFFSET_Y_mask = 0x1f << 5, + OFFSET_Y_shift = 5, + OFFSET_Z_mask = 0x1f << 10, + OFFSET_Z_shift = 10, + SAMPLER_ID_mask = 0x1f << 15, + SAMPLER_ID_shift = 15, + SQ_TEX_WORD2__SRC_SEL_X_mask = 0x07 << 20, + SQ_TEX_WORD2__SRC_SEL_X_shift = 20, + SQ_SEL_X = 0x00, + SQ_SEL_Y = 0x01, + SQ_SEL_Z = 0x02, + SQ_SEL_W = 0x03, + SQ_SEL_0 = 0x04, + SQ_SEL_1 = 0x05, + SRC_SEL_Y_mask = 0x07 << 23, + SRC_SEL_Y_shift = 23, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SRC_SEL_Z_mask = 0x07 << 26, + SRC_SEL_Z_shift = 26, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SRC_SEL_W_mask = 0x07 << 29, + SRC_SEL_W_shift = 29, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, + BURST_COUNT_mask = 0x0f << 17, + BURST_COUNT_shift = 17, + END_OF_PROGRAM_bit = 1 << 21, + VALID_PIXEL_MODE_bit = 1 << 22, + SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23, + SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 23, + SQ_CF_INST_MEM_STREAM0 = 0x20, + SQ_CF_INST_MEM_STREAM1 = 0x21, + SQ_CF_INST_MEM_STREAM2 = 0x22, + SQ_CF_INST_MEM_STREAM3 = 0x23, + SQ_CF_INST_MEM_SCRATCH = 0x24, + SQ_CF_INST_MEM_REDUCTION = 0x25, + SQ_CF_INST_MEM_RING = 0x26, + SQ_CF_INST_EXPORT = 0x27, + SQ_CF_INST_EXPORT_DONE = 0x28, + WHOLE_QUAD_MODE_bit = 1 << 30, + BARRIER_bit = 1 << 31, + SQ_CF_ALU_WORD1 = 0x00008dfc, + KCACHE_MODE1_mask = 0x03 << 0, + KCACHE_MODE1_shift = 0, + SQ_CF_KCACHE_NOP = 0x00, + SQ_CF_KCACHE_LOCK_1 = 0x01, + SQ_CF_KCACHE_LOCK_2 = 0x02, + SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, + KCACHE_ADDR0_mask = 0xff << 2, + KCACHE_ADDR0_shift = 2, + KCACHE_ADDR1_mask = 0xff << 10, + KCACHE_ADDR1_shift = 10, + SQ_CF_ALU_WORD1__COUNT_mask = 0x7f << 18, + SQ_CF_ALU_WORD1__COUNT_shift = 18, + SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25, + SQ_CF_ALU_WORD1__CF_INST_mask = 0x0f << 26, + SQ_CF_ALU_WORD1__CF_INST_shift = 26, + SQ_CF_INST_ALU = 0x08, + SQ_CF_INST_ALU_PUSH_BEFORE = 0x09, + SQ_CF_INST_ALU_POP_AFTER = 0x0a, + SQ_CF_INST_ALU_POP2_AFTER = 0x0b, + SQ_CF_INST_ALU_CONTINUE = 0x0d, + SQ_CF_INST_ALU_BREAK = 0x0e, + SQ_CF_INST_ALU_ELSE_AFTER = 0x0f, +/* WHOLE_QUAD_MODE_bit = 1 << 30, */ +/* BARRIER_bit = 1 << 31, */ + SQ_TEX_WORD1 = 0x00008dfc, + SQ_TEX_WORD1__DST_GPR_mask = 0x7f << 0, + SQ_TEX_WORD1__DST_GPR_shift = 0, + SQ_TEX_WORD1__DST_REL_bit = 1 << 7, + SQ_TEX_WORD1__DST_SEL_X_mask = 0x07 << 9, + SQ_TEX_WORD1__DST_SEL_X_shift = 9, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SQ_SEL_MASK = 0x07, + SQ_TEX_WORD1__DST_SEL_Y_mask = 0x07 << 12, + SQ_TEX_WORD1__DST_SEL_Y_shift = 12, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_TEX_WORD1__DST_SEL_Z_mask = 0x07 << 15, + SQ_TEX_WORD1__DST_SEL_Z_shift = 15, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_TEX_WORD1__DST_SEL_W_mask = 0x07 << 18, + SQ_TEX_WORD1__DST_SEL_W_shift = 18, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_TEX_WORD1__LOD_BIAS_mask = 0x7f << 21, + SQ_TEX_WORD1__LOD_BIAS_shift = 21, + COORD_TYPE_X_bit = 1 << 28, + COORD_TYPE_Y_bit = 1 << 29, + COORD_TYPE_Z_bit = 1 << 30, + COORD_TYPE_W_bit = 1 << 31, + SQ_VTX_WORD0 = 0x00008dfc, + VTX_INST_mask = 0x1f << 0, + VTX_INST_shift = 0, + SQ_VTX_INST_FETCH = 0x00, + SQ_VTX_INST_SEMANTIC = 0x01, + FETCH_TYPE_mask = 0x03 << 5, + FETCH_TYPE_shift = 5, + SQ_VTX_FETCH_VERTEX_DATA = 0x00, + SQ_VTX_FETCH_INSTANCE_DATA = 0x01, + SQ_VTX_FETCH_NO_INDEX_OFFSET = 0x02, + FETCH_WHOLE_QUAD_bit = 1 << 7, + BUFFER_ID_mask = 0xff << 8, + BUFFER_ID_shift = 8, + SRC_GPR_mask = 0x7f << 16, + SRC_GPR_shift = 16, + SRC_REL_bit = 1 << 23, + SQ_VTX_WORD0__SRC_SEL_X_mask = 0x03 << 24, + SQ_VTX_WORD0__SRC_SEL_X_shift = 24, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ + MEGA_FETCH_COUNT_mask = 0x3f << 26, + MEGA_FETCH_COUNT_shift = 26, + SQ_CF_ALLOC_EXPORT_WORD1_SWIZ = 0x00008dfc, + SEL_X_mask = 0x07 << 0, + SEL_X_shift = 0, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SEL_Y_mask = 0x07 << 3, + SEL_Y_shift = 3, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SEL_Z_mask = 0x07 << 6, + SEL_Z_shift = 6, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SEL_W_mask = 0x07 << 9, + SEL_W_shift = 9, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_ALU_WORD1 = 0x00008dfc, + ENCODING_mask = 0x07 << 15, + ENCODING_shift = 15, + BANK_SWIZZLE_mask = 0x07 << 18, + BANK_SWIZZLE_shift = 18, + SQ_ALU_VEC_012 = 0x00, + SQ_ALU_VEC_021 = 0x01, + SQ_ALU_VEC_120 = 0x02, + SQ_ALU_VEC_102 = 0x03, + SQ_ALU_VEC_201 = 0x04, + SQ_ALU_VEC_210 = 0x05, + SQ_ALU_WORD1__DST_GPR_mask = 0x7f << 21, + SQ_ALU_WORD1__DST_GPR_shift = 21, + SQ_ALU_WORD1__DST_REL_bit = 1 << 28, + DST_CHAN_mask = 0x03 << 29, + DST_CHAN_shift = 29, + CHAN_X = 0x00, + CHAN_Y = 0x01, + CHAN_Z = 0x02, + CHAN_W = 0x03, + SQ_ALU_WORD1__CLAMP_bit = 1 << 31, + SQ_CF_ALU_WORD0 = 0x00008dfc, + SQ_CF_ALU_WORD0__ADDR_mask = 0x3fffff << 0, + SQ_CF_ALU_WORD0__ADDR_shift = 0, + KCACHE_BANK0_mask = 0x0f << 22, + KCACHE_BANK0_shift = 22, + KCACHE_BANK1_mask = 0x0f << 26, + KCACHE_BANK1_shift = 26, + KCACHE_MODE0_mask = 0x03 << 30, + KCACHE_MODE0_shift = 30, +/* SQ_CF_KCACHE_NOP = 0x00, */ +/* SQ_CF_KCACHE_LOCK_1 = 0x01, */ +/* SQ_CF_KCACHE_LOCK_2 = 0x02, */ +/* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ + SQ_VTX_WORD2 = 0x00008dfc, + SQ_VTX_WORD2__OFFSET_mask = 0xffff << 0, + SQ_VTX_WORD2__OFFSET_shift = 0, + SQ_VTX_WORD2__ENDIAN_SWAP_mask = 0x03 << 16, + SQ_VTX_WORD2__ENDIAN_SWAP_shift = 16, + SQ_ENDIAN_NONE = 0x00, + SQ_ENDIAN_8IN16 = 0x01, + SQ_ENDIAN_8IN32 = 0x02, + CONST_BUF_NO_STRIDE_bit = 1 << 18, + MEGA_FETCH_bit = 1 << 19, + SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20, + SQ_ALU_WORD1_OP2_V2 = 0x00008dfc, + SRC0_ABS_bit = 1 << 0, + SRC1_ABS_bit = 1 << 1, + UPDATE_EXECUTE_MASK_bit = 1 << 2, + UPDATE_PRED_bit = 1 << 3, + WRITE_MASK_bit = 1 << 4, + SQ_ALU_WORD1_OP2_V2__OMOD_mask = 0x03 << 5, + SQ_ALU_WORD1_OP2_V2__OMOD_shift = 5, + SQ_ALU_OMOD_OFF = 0x00, + SQ_ALU_OMOD_M2 = 0x01, + SQ_ALU_OMOD_M4 = 0x02, + SQ_ALU_OMOD_D2 = 0x03, + SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7, + SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7, + SQ_OP2_INST_ADD = 0x00, + SQ_OP2_INST_MUL = 0x01, + SQ_OP2_INST_MUL_IEEE = 0x02, + SQ_OP2_INST_MAX = 0x03, + SQ_OP2_INST_MIN = 0x04, + SQ_OP2_INST_MAX_DX10 = 0x05, + SQ_OP2_INST_MIN_DX10 = 0x06, + SQ_OP2_INST_SETE = 0x08, + SQ_OP2_INST_SETGT = 0x09, + SQ_OP2_INST_SETGE = 0x0a, + SQ_OP2_INST_SETNE = 0x0b, + SQ_OP2_INST_SETE_DX10 = 0x0c, + SQ_OP2_INST_SETGT_DX10 = 0x0d, + SQ_OP2_INST_SETGE_DX10 = 0x0e, + SQ_OP2_INST_SETNE_DX10 = 0x0f, + SQ_OP2_INST_FRACT = 0x10, + SQ_OP2_INST_TRUNC = 0x11, + SQ_OP2_INST_CEIL = 0x12, + SQ_OP2_INST_RNDNE = 0x13, + SQ_OP2_INST_FLOOR = 0x14, + SQ_OP2_INST_MOVA = 0x15, + SQ_OP2_INST_MOVA_FLOOR = 0x16, + SQ_OP2_INST_MOVA_INT = 0x18, + SQ_OP2_INST_MOV = 0x19, + SQ_OP2_INST_NOP = 0x1a, + SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, + SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, + SQ_OP2_INST_PRED_SETE = 0x20, + SQ_OP2_INST_PRED_SETGT = 0x21, + SQ_OP2_INST_PRED_SETGE = 0x22, + SQ_OP2_INST_PRED_SETNE = 0x23, + SQ_OP2_INST_PRED_SET_INV = 0x24, + SQ_OP2_INST_PRED_SET_POP = 0x25, + SQ_OP2_INST_PRED_SET_CLR = 0x26, + SQ_OP2_INST_PRED_SET_RESTORE = 0x27, + SQ_OP2_INST_PRED_SETE_PUSH = 0x28, + SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, + SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, + SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, + SQ_OP2_INST_KILLE = 0x2c, + SQ_OP2_INST_KILLGT = 0x2d, + SQ_OP2_INST_KILLGE = 0x2e, + SQ_OP2_INST_KILLNE = 0x2f, + SQ_OP2_INST_AND_INT = 0x30, + SQ_OP2_INST_OR_INT = 0x31, + SQ_OP2_INST_XOR_INT = 0x32, + SQ_OP2_INST_NOT_INT = 0x33, + SQ_OP2_INST_ADD_INT = 0x34, + SQ_OP2_INST_SUB_INT = 0x35, + SQ_OP2_INST_MAX_INT = 0x36, + SQ_OP2_INST_MIN_INT = 0x37, + SQ_OP2_INST_MAX_UINT = 0x38, + SQ_OP2_INST_MIN_UINT = 0x39, + SQ_OP2_INST_SETE_INT = 0x3a, + SQ_OP2_INST_SETGT_INT = 0x3b, + SQ_OP2_INST_SETGE_INT = 0x3c, + SQ_OP2_INST_SETNE_INT = 0x3d, + SQ_OP2_INST_SETGT_UINT = 0x3e, + SQ_OP2_INST_SETGE_UINT = 0x3f, + SQ_OP2_INST_KILLGT_UINT = 0x40, + SQ_OP2_INST_KILLGE_UINT = 0x41, + SQ_OP2_INST_PRED_SETE_INT = 0x42, + SQ_OP2_INST_PRED_SETGT_INT = 0x43, + SQ_OP2_INST_PRED_SETGE_INT = 0x44, + SQ_OP2_INST_PRED_SETNE_INT = 0x45, + SQ_OP2_INST_KILLE_INT = 0x46, + SQ_OP2_INST_KILLGT_INT = 0x47, + SQ_OP2_INST_KILLGE_INT = 0x48, + SQ_OP2_INST_KILLNE_INT = 0x49, + SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, + SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, + SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, + SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, + SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, + SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, + SQ_OP2_INST_DOT4 = 0x50, + SQ_OP2_INST_DOT4_IEEE = 0x51, + SQ_OP2_INST_CUBE = 0x52, + SQ_OP2_INST_MAX4 = 0x53, + SQ_OP2_INST_MOVA_GPR_INT = 0x60, + SQ_OP2_INST_EXP_IEEE = 0x61, + SQ_OP2_INST_LOG_CLAMPED = 0x62, + SQ_OP2_INST_LOG_IEEE = 0x63, + SQ_OP2_INST_RECIP_CLAMPED = 0x64, + SQ_OP2_INST_RECIP_FF = 0x65, + SQ_OP2_INST_RECIP_IEEE = 0x66, + SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67, + SQ_OP2_INST_RECIPSQRT_FF = 0x68, + SQ_OP2_INST_RECIPSQRT_IEEE = 0x69, + SQ_OP2_INST_SQRT_IEEE = 0x6a, + SQ_OP2_INST_FLT_TO_INT = 0x6b, + SQ_OP2_INST_INT_TO_FLT = 0x6c, + SQ_OP2_INST_UINT_TO_FLT = 0x6d, + SQ_OP2_INST_SIN = 0x6e, + SQ_OP2_INST_COS = 0x6f, + SQ_OP2_INST_ASHR_INT = 0x70, + SQ_OP2_INST_LSHR_INT = 0x71, + SQ_OP2_INST_LSHL_INT = 0x72, + SQ_OP2_INST_MULLO_INT = 0x73, + SQ_OP2_INST_MULHI_INT = 0x74, + SQ_OP2_INST_MULLO_UINT = 0x75, + SQ_OP2_INST_MULHI_UINT = 0x76, + SQ_OP2_INST_RECIP_INT = 0x77, + SQ_OP2_INST_RECIP_UINT = 0x78, + SQ_OP2_INST_FLT_TO_UINT = 0x79, + SQ_CF_ALLOC_EXPORT_WORD1_BUF = 0x00008dfc, + ARRAY_SIZE_mask = 0xfff << 0, + ARRAY_SIZE_shift = 0, + COMP_MASK_mask = 0x0f << 12, + COMP_MASK_shift = 12, + SQ_CF_WORD0 = 0x00008dfc, + SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, + ARRAY_BASE_mask = 0x1fff << 0, + ARRAY_BASE_shift = 0, + SQ_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x03 << 13, + SQ_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13, + SQ_EXPORT_PIXEL = 0x00, + SQ_EXPORT_POS = 0x01, + SQ_EXPORT_PARAM = 0x02, + X_UNUSED_FOR_SX_EXPORTS = 0x03, + RW_GPR_mask = 0x7f << 15, + RW_GPR_shift = 15, + RW_REL_bit = 1 << 22, + INDEX_GPR_mask = 0x7f << 23, + INDEX_GPR_shift = 23, + ELEM_SIZE_mask = 0x03 << 30, + ELEM_SIZE_shift = 30, + SQ_VTX_WORD1 = 0x00008dfc, + SQ_VTX_WORD1__DST_SEL_X_mask = 0x07 << 9, + SQ_VTX_WORD1__DST_SEL_X_shift = 9, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_VTX_WORD1__DST_SEL_Y_mask = 0x07 << 12, + SQ_VTX_WORD1__DST_SEL_Y_shift = 12, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_VTX_WORD1__DST_SEL_Z_mask = 0x07 << 15, + SQ_VTX_WORD1__DST_SEL_Z_shift = 15, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_VTX_WORD1__DST_SEL_W_mask = 0x07 << 18, + SQ_VTX_WORD1__DST_SEL_W_shift = 18, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + USE_CONST_FIELDS_bit = 1 << 21, + SQ_VTX_WORD1__DATA_FORMAT_mask = 0x3f << 22, + SQ_VTX_WORD1__DATA_FORMAT_shift = 22, + SQ_VTX_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28, + SQ_VTX_WORD1__NUM_FORMAT_ALL_shift = 28, + SQ_NUM_FORMAT_NORM = 0x00, + SQ_NUM_FORMAT_INT = 0x01, + SQ_NUM_FORMAT_SCALED = 0x02, + SQ_VTX_WORD1__FORMAT_COMP_ALL_bit = 1 << 30, + SQ_VTX_WORD1__SRF_MODE_ALL_bit = 1 << 31, + SQ_ALU_WORD1_OP2 = 0x00008dfc, +/* SRC0_ABS_bit = 1 << 0, */ +/* SRC1_ABS_bit = 1 << 1, */ +/* UPDATE_EXECUTE_MASK_bit = 1 << 2, */ +/* UPDATE_PRED_bit = 1 << 3, */ +/* WRITE_MASK_bit = 1 << 4, */ + FOG_MERGE_bit = 1 << 5, + SQ_ALU_WORD1_OP2__OMOD_mask = 0x03 << 6, + SQ_ALU_WORD1_OP2__OMOD_shift = 6, +/* SQ_ALU_OMOD_OFF = 0x00, */ +/* SQ_ALU_OMOD_M2 = 0x01, */ +/* SQ_ALU_OMOD_M4 = 0x02, */ +/* SQ_ALU_OMOD_D2 = 0x03, */ + SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8, + SQ_ALU_WORD1_OP2__ALU_INST_shift = 8, +/* SQ_OP2_INST_ADD = 0x00, */ +/* SQ_OP2_INST_MUL = 0x01, */ +/* SQ_OP2_INST_MUL_IEEE = 0x02, */ +/* SQ_OP2_INST_MAX = 0x03, */ +/* SQ_OP2_INST_MIN = 0x04, */ +/* SQ_OP2_INST_MAX_DX10 = 0x05, */ +/* SQ_OP2_INST_MIN_DX10 = 0x06, */ +/* SQ_OP2_INST_SETE = 0x08, */ +/* SQ_OP2_INST_SETGT = 0x09, */ +/* SQ_OP2_INST_SETGE = 0x0a, */ +/* SQ_OP2_INST_SETNE = 0x0b, */ +/* SQ_OP2_INST_SETE_DX10 = 0x0c, */ +/* SQ_OP2_INST_SETGT_DX10 = 0x0d, */ +/* SQ_OP2_INST_SETGE_DX10 = 0x0e, */ +/* SQ_OP2_INST_SETNE_DX10 = 0x0f, */ +/* SQ_OP2_INST_FRACT = 0x10, */ +/* SQ_OP2_INST_TRUNC = 0x11, */ +/* SQ_OP2_INST_CEIL = 0x12, */ +/* SQ_OP2_INST_RNDNE = 0x13, */ +/* SQ_OP2_INST_FLOOR = 0x14, */ +/* SQ_OP2_INST_MOVA = 0x15, */ +/* SQ_OP2_INST_MOVA_FLOOR = 0x16, */ +/* SQ_OP2_INST_MOVA_INT = 0x18, */ +/* SQ_OP2_INST_MOV = 0x19, */ +/* SQ_OP2_INST_NOP = 0x1a, */ +/* SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, */ +/* SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, */ +/* SQ_OP2_INST_PRED_SETE = 0x20, */ +/* SQ_OP2_INST_PRED_SETGT = 0x21, */ +/* SQ_OP2_INST_PRED_SETGE = 0x22, */ +/* SQ_OP2_INST_PRED_SETNE = 0x23, */ +/* SQ_OP2_INST_PRED_SET_INV = 0x24, */ +/* SQ_OP2_INST_PRED_SET_POP = 0x25, */ +/* SQ_OP2_INST_PRED_SET_CLR = 0x26, */ +/* SQ_OP2_INST_PRED_SET_RESTORE = 0x27, */ +/* SQ_OP2_INST_PRED_SETE_PUSH = 0x28, */ +/* SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, */ +/* SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, */ +/* SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, */ +/* SQ_OP2_INST_KILLE = 0x2c, */ +/* SQ_OP2_INST_KILLGT = 0x2d, */ +/* SQ_OP2_INST_KILLGE = 0x2e, */ +/* SQ_OP2_INST_KILLNE = 0x2f, */ +/* SQ_OP2_INST_AND_INT = 0x30, */ +/* SQ_OP2_INST_OR_INT = 0x31, */ +/* SQ_OP2_INST_XOR_INT = 0x32, */ +/* SQ_OP2_INST_NOT_INT = 0x33, */ +/* SQ_OP2_INST_ADD_INT = 0x34, */ +/* SQ_OP2_INST_SUB_INT = 0x35, */ +/* SQ_OP2_INST_MAX_INT = 0x36, */ +/* SQ_OP2_INST_MIN_INT = 0x37, */ +/* SQ_OP2_INST_MAX_UINT = 0x38, */ +/* SQ_OP2_INST_MIN_UINT = 0x39, */ +/* SQ_OP2_INST_SETE_INT = 0x3a, */ +/* SQ_OP2_INST_SETGT_INT = 0x3b, */ +/* SQ_OP2_INST_SETGE_INT = 0x3c, */ +/* SQ_OP2_INST_SETNE_INT = 0x3d, */ +/* SQ_OP2_INST_SETGT_UINT = 0x3e, */ +/* SQ_OP2_INST_SETGE_UINT = 0x3f, */ +/* SQ_OP2_INST_KILLGT_UINT = 0x40, */ +/* SQ_OP2_INST_KILLGE_UINT = 0x41, */ +/* SQ_OP2_INST_PRED_SETE_INT = 0x42, */ +/* SQ_OP2_INST_PRED_SETGT_INT = 0x43, */ +/* SQ_OP2_INST_PRED_SETGE_INT = 0x44, */ +/* SQ_OP2_INST_PRED_SETNE_INT = 0x45, */ +/* SQ_OP2_INST_KILLE_INT = 0x46, */ +/* SQ_OP2_INST_KILLGT_INT = 0x47, */ +/* SQ_OP2_INST_KILLGE_INT = 0x48, */ +/* SQ_OP2_INST_KILLNE_INT = 0x49, */ +/* SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, */ +/* SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, */ +/* SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, */ +/* SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, */ +/* SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, */ +/* SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, */ +/* SQ_OP2_INST_DOT4 = 0x50, */ +/* SQ_OP2_INST_DOT4_IEEE = 0x51, */ +/* SQ_OP2_INST_CUBE = 0x52, */ +/* SQ_OP2_INST_MAX4 = 0x53, */ +/* SQ_OP2_INST_MOVA_GPR_INT = 0x60, */ +/* SQ_OP2_INST_EXP_IEEE = 0x61, */ +/* SQ_OP2_INST_LOG_CLAMPED = 0x62, */ +/* SQ_OP2_INST_LOG_IEEE = 0x63, */ +/* SQ_OP2_INST_RECIP_CLAMPED = 0x64, */ +/* SQ_OP2_INST_RECIP_FF = 0x65, */ +/* SQ_OP2_INST_RECIP_IEEE = 0x66, */ +/* SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67, */ +/* SQ_OP2_INST_RECIPSQRT_FF = 0x68, */ +/* SQ_OP2_INST_RECIPSQRT_IEEE = 0x69, */ +/* SQ_OP2_INST_SQRT_IEEE = 0x6a, */ +/* SQ_OP2_INST_FLT_TO_INT = 0x6b, */ +/* SQ_OP2_INST_INT_TO_FLT = 0x6c, */ +/* SQ_OP2_INST_UINT_TO_FLT = 0x6d, */ +/* SQ_OP2_INST_SIN = 0x6e, */ +/* SQ_OP2_INST_COS = 0x6f, */ +/* SQ_OP2_INST_ASHR_INT = 0x70, */ +/* SQ_OP2_INST_LSHR_INT = 0x71, */ +/* SQ_OP2_INST_LSHL_INT = 0x72, */ +/* SQ_OP2_INST_MULLO_INT = 0x73, */ +/* SQ_OP2_INST_MULHI_INT = 0x74, */ +/* SQ_OP2_INST_MULLO_UINT = 0x75, */ +/* SQ_OP2_INST_MULHI_UINT = 0x76, */ +/* SQ_OP2_INST_RECIP_INT = 0x77, */ +/* SQ_OP2_INST_RECIP_UINT = 0x78, */ +/* SQ_OP2_INST_FLT_TO_UINT = 0x79, */ + SQ_CF_WORD1 = 0x00008dfc, + POP_COUNT_mask = 0x07 << 0, + POP_COUNT_shift = 0, + CF_CONST_mask = 0x1f << 3, + CF_CONST_shift = 3, + COND_mask = 0x03 << 8, + COND_shift = 8, + SQ_CF_COND_ACTIVE = 0x00, + SQ_CF_COND_FALSE = 0x01, + SQ_CF_COND_BOOL = 0x02, + SQ_CF_COND_NOT_BOOL = 0x03, + SQ_CF_WORD1__COUNT_mask = 0x07 << 10, + SQ_CF_WORD1__COUNT_shift = 10, + CALL_COUNT_mask = 0x3f << 13, + CALL_COUNT_shift = 13, + COUNT_3_bit = 1 << 19, +/* END_OF_PROGRAM_bit = 1 << 21, */ +/* VALID_PIXEL_MODE_bit = 1 << 22, */ + SQ_CF_WORD1__CF_INST_mask = 0x7f << 23, + SQ_CF_WORD1__CF_INST_shift = 23, + SQ_CF_INST_NOP = 0x00, + SQ_CF_INST_TEX = 0x01, + SQ_CF_INST_VTX = 0x02, + SQ_CF_INST_VTX_TC = 0x03, + SQ_CF_INST_LOOP_START = 0x04, + SQ_CF_INST_LOOP_END = 0x05, + SQ_CF_INST_LOOP_START_DX10 = 0x06, + SQ_CF_INST_LOOP_START_NO_AL = 0x07, + SQ_CF_INST_LOOP_CONTINUE = 0x08, + SQ_CF_INST_LOOP_BREAK = 0x09, + SQ_CF_INST_JUMP = 0x0a, + SQ_CF_INST_PUSH = 0x0b, + SQ_CF_INST_PUSH_ELSE = 0x0c, + SQ_CF_INST_ELSE = 0x0d, + SQ_CF_INST_POP = 0x0e, + SQ_CF_INST_POP_JUMP = 0x0f, + SQ_CF_INST_POP_PUSH = 0x10, + SQ_CF_INST_POP_PUSH_ELSE = 0x11, + SQ_CF_INST_CALL = 0x12, + SQ_CF_INST_CALL_FS = 0x13, + SQ_CF_INST_RETURN = 0x14, + SQ_CF_INST_EMIT_VERTEX = 0x15, + SQ_CF_INST_EMIT_CUT_VERTEX = 0x16, + SQ_CF_INST_CUT_VERTEX = 0x17, + SQ_CF_INST_KILL = 0x18, +/* WHOLE_QUAD_MODE_bit = 1 << 30, */ +/* BARRIER_bit = 1 << 31, */ + SQ_VTX_WORD1_SEM = 0x00008dfc, + SEMANTIC_ID_mask = 0xff << 0, + SEMANTIC_ID_shift = 0, + SQ_TEX_WORD0 = 0x00008dfc, + TEX_INST_mask = 0x1f << 0, + TEX_INST_shift = 0, + SQ_TEX_INST_VTX_FETCH = 0x00, + SQ_TEX_INST_VTX_SEMANTIC = 0x01, + SQ_TEX_INST_LD = 0x03, + SQ_TEX_INST_GET_TEXTURE_RESINFO = 0x04, + SQ_TEX_INST_GET_NUMBER_OF_SAMPLES = 0x05, + SQ_TEX_INST_GET_LOD = 0x06, + SQ_TEX_INST_GET_GRADIENTS_H = 0x07, + SQ_TEX_INST_GET_GRADIENTS_V = 0x08, + SQ_TEX_INST_GET_LERP = 0x09, + SQ_TEX_INST_RESERVED_10 = 0x0a, + SQ_TEX_INST_SET_GRADIENTS_H = 0x0b, + SQ_TEX_INST_SET_GRADIENTS_V = 0x0c, + SQ_TEX_INST_PASS = 0x0d, + X_Z_SET_INDEX_FOR_ARRAY_OF_CUBEMAPS = 0x0e, + SQ_TEX_INST_SAMPLE = 0x10, + SQ_TEX_INST_SAMPLE_L = 0x11, + SQ_TEX_INST_SAMPLE_LB = 0x12, + SQ_TEX_INST_SAMPLE_LZ = 0x13, + SQ_TEX_INST_SAMPLE_G = 0x14, + SQ_TEX_INST_SAMPLE_G_L = 0x15, + SQ_TEX_INST_SAMPLE_G_LB = 0x16, + SQ_TEX_INST_SAMPLE_G_LZ = 0x17, + SQ_TEX_INST_SAMPLE_C = 0x18, + SQ_TEX_INST_SAMPLE_C_L = 0x19, + SQ_TEX_INST_SAMPLE_C_LB = 0x1a, + SQ_TEX_INST_SAMPLE_C_LZ = 0x1b, + SQ_TEX_INST_SAMPLE_C_G = 0x1c, + SQ_TEX_INST_SAMPLE_C_G_L = 0x1d, + SQ_TEX_INST_SAMPLE_C_G_LB = 0x1e, + SQ_TEX_INST_SAMPLE_C_G_LZ = 0x1f, + BC_FRAC_MODE_bit = 1 << 5, +/* FETCH_WHOLE_QUAD_bit = 1 << 7, */ + RESOURCE_ID_mask = 0xff << 8, + RESOURCE_ID_shift = 8, +/* SRC_GPR_mask = 0x7f << 16, */ +/* SRC_GPR_shift = 16, */ +/* SRC_REL_bit = 1 << 23, */ + SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24, + SQ_VTX_WORD1_GPR = 0x00008dfc, + SQ_VTX_WORD1_GPR__DST_GPR_mask = 0x7f << 0, + SQ_VTX_WORD1_GPR__DST_GPR_shift = 0, + SQ_VTX_WORD1_GPR__DST_REL_bit = 1 << 7, + SQ_ALU_WORD0 = 0x00008dfc, + SRC0_SEL_mask = 0x1ff << 0, + SRC0_SEL_shift = 0, +/* SQ_ALU_SRC_0 = 0xf8, */ +/* SQ_ALU_SRC_1 = 0xf9, */ +/* SQ_ALU_SRC_1_INT = 0xfa, */ +/* SQ_ALU_SRC_M_1_INT = 0xfb, */ +/* SQ_ALU_SRC_0_5 = 0xfc, */ +/* SQ_ALU_SRC_LITERAL = 0xfd, */ +/* SQ_ALU_SRC_PV = 0xfe, */ +/* SQ_ALU_SRC_PS = 0xff, */ + SRC0_REL_bit = 1 << 9, + SRC0_CHAN_mask = 0x03 << 10, + SRC0_CHAN_shift = 10, +/* SQ_CHAN_X = 0x00, */ +/* SQ_CHAN_Y = 0x01, */ +/* SQ_CHAN_Z = 0x02, */ +/* SQ_CHAN_W = 0x03, */ + SRC0_NEG_bit = 1 << 12, + SRC1_SEL_mask = 0x1ff << 13, + SRC1_SEL_shift = 13, +/* SQ_ALU_SRC_0 = 0xf8, */ +/* SQ_ALU_SRC_1 = 0xf9, */ +/* SQ_ALU_SRC_1_INT = 0xfa, */ +/* SQ_ALU_SRC_M_1_INT = 0xfb, */ +/* SQ_ALU_SRC_0_5 = 0xfc, */ +/* SQ_ALU_SRC_LITERAL = 0xfd, */ +/* SQ_ALU_SRC_PV = 0xfe, */ +/* SQ_ALU_SRC_PS = 0xff, */ + SRC1_REL_bit = 1 << 22, + SRC1_CHAN_mask = 0x03 << 23, + SRC1_CHAN_shift = 23, +/* SQ_CHAN_X = 0x00, */ +/* SQ_CHAN_Y = 0x01, */ +/* SQ_CHAN_Z = 0x02, */ +/* SQ_CHAN_W = 0x03, */ + SRC1_NEG_bit = 1 << 25, + INDEX_MODE_mask = 0x07 << 26, + INDEX_MODE_shift = 26, + SQ_INDEX_AR_X = 0x00, + SQ_INDEX_AR_Y = 0x01, + SQ_INDEX_AR_Z = 0x02, + SQ_INDEX_AR_W = 0x03, + SQ_INDEX_LOOP = 0x04, + PRED_SEL_mask = 0x03 << 29, + PRED_SEL_shift = 29, + SQ_PRED_SEL_OFF = 0x00, + SQ_PRED_SEL_ZERO = 0x02, + SQ_PRED_SEL_ONE = 0x03, + LAST_bit = 1 << 31, + SX_EXPORT_BUFFER_SIZES = 0x0000900c, + COLOR_BUFFER_SIZE_mask = 0xff << 0, + COLOR_BUFFER_SIZE_shift = 0, + POSITION_BUFFER_SIZE_mask = 0xff << 8, + POSITION_BUFFER_SIZE_shift = 8, + SMX_BUFFER_SIZE_mask = 0xff << 16, + SMX_BUFFER_SIZE_shift = 16, + SX_MEMORY_EXPORT_BASE = 0x00009010, + SX_MEMORY_EXPORT_SIZE = 0x00009014, + SPI_CONFIG_CNTL = 0x00009100, + GPR_WRITE_PRIORITY_mask = 0x1f << 0, + GPR_WRITE_PRIORITY_shift = 0, + X_PRIORITY_ORDER = 0x00, + X_PRIORITY_ORDER_VS = 0x01, + DISABLE_INTERP_1_bit = 1 << 5, + DEBUG_THREAD_TYPE_SEL_mask = 0x03 << 6, + DEBUG_THREAD_TYPE_SEL_shift = 6, + DEBUG_GROUP_SEL_mask = 0x1f << 8, + DEBUG_GROUP_SEL_shift = 8, + DEBUG_GRBM_OVERRIDE_bit = 1 << 13, + SPI_CONFIG_CNTL_1 = 0x0000913c, + VTX_DONE_DELAY_mask = 0x0f << 0, + VTX_DONE_DELAY_shift = 0, + X_DELAY_10_CLKS = 0x00, + X_DELAY_11_CLKS = 0x01, + X_DELAY_12_CLKS = 0x02, + X_DELAY_13_CLKS = 0x03, + X_DELAY_14_CLKS = 0x04, + X_DELAY_15_CLKS = 0x05, + X_DELAY_16_CLKS = 0x06, + X_DELAY_17_CLKS = 0x07, + X_DELAY_2_CLKS = 0x08, + X_DELAY_3_CLKS = 0x09, + X_DELAY_4_CLKS = 0x0a, + X_DELAY_5_CLKS = 0x0b, + X_DELAY_6_CLKS = 0x0c, + X_DELAY_7_CLKS = 0x0d, + X_DELAY_8_CLKS = 0x0e, + X_DELAY_9_CLKS = 0x0f, + INTERP_ONE_PRIM_PER_ROW_bit = 1 << 4, + TD_FILTER4 = 0x00009400, + WEIGHT_1_mask = 0x7ff << 0, + WEIGHT_1_shift = 0, + WEIGHT_0_mask = 0x7ff << 11, + WEIGHT_0_shift = 11, + WEIGHT_PAIR_bit = 1 << 22, + PHASE_mask = 0x0f << 23, + PHASE_shift = 23, + DIRECTION_bit = 1 << 27, + TD_FILTER4_1 = 0x00009404, + TD_FILTER4_1_num = 35, +/* WEIGHT_1_mask = 0x7ff << 0, */ +/* WEIGHT_1_shift = 0, */ +/* WEIGHT_0_mask = 0x7ff << 11, */ +/* WEIGHT_0_shift = 11, */ + TD_CNTL = 0x00009490, + SYNC_PHASE_SH_mask = 0x03 << 0, + SYNC_PHASE_SH_shift = 0, + SYNC_PHASE_VC_SMX_mask = 0x03 << 4, + SYNC_PHASE_VC_SMX_shift = 4, + TD0_CNTL = 0x00009494, + TD0_CNTL_num = 4, + ID_OVERRIDE_mask = 0x03 << 28, + ID_OVERRIDE_shift = 28, + TD0_STATUS = 0x000094a4, + TD0_STATUS_num = 4, + BUSY_bit = 1 << 31, + TA_CNTL = 0x00009504, + GRADIENT_CREDIT_mask = 0x1f << 0, + GRADIENT_CREDIT_shift = 0, + WALKER_CREDIT_mask = 0x1f << 8, + WALKER_CREDIT_shift = 8, + ALIGNER_CREDIT_mask = 0x1f << 16, + ALIGNER_CREDIT_shift = 16, + TD_FIFO_CREDIT_mask = 0x3ff << 22, + TD_FIFO_CREDIT_shift = 22, + TA_CNTL_AUX = 0x00009508, + DISABLE_CUBE_WRAP_bit = 1 << 0, + SYNC_GRADIENT_bit = 1 << 24, + SYNC_WALKER_bit = 1 << 25, + SYNC_ALIGNER_bit = 1 << 26, + BILINEAR_PRECISION_bit = 1 << 31, + TA0_CNTL = 0x00009510, +/* ID_OVERRIDE_mask = 0x03 << 28, */ +/* ID_OVERRIDE_shift = 28, */ + TA1_CNTL = 0x00009514, +/* ID_OVERRIDE_mask = 0x03 << 28, */ +/* ID_OVERRIDE_shift = 28, */ + TA2_CNTL = 0x00009518, +/* ID_OVERRIDE_mask = 0x03 << 28, */ +/* ID_OVERRIDE_shift = 28, */ + TA3_CNTL = 0x0000951c, +/* ID_OVERRIDE_mask = 0x03 << 28, */ +/* ID_OVERRIDE_shift = 28, */ + TA0_STATUS = 0x00009520, + FG_PFIFO_EMPTYB_bit = 1 << 12, + FG_LFIFO_EMPTYB_bit = 1 << 13, + FG_SFIFO_EMPTYB_bit = 1 << 14, + FL_PFIFO_EMPTYB_bit = 1 << 16, + FL_LFIFO_EMPTYB_bit = 1 << 17, + FL_SFIFO_EMPTYB_bit = 1 << 18, + FA_PFIFO_EMPTYB_bit = 1 << 20, + FA_LFIFO_EMPTYB_bit = 1 << 21, + FA_SFIFO_EMPTYB_bit = 1 << 22, + IN_BUSY_bit = 1 << 24, + FG_BUSY_bit = 1 << 25, + FL_BUSY_bit = 1 << 27, + TA_BUSY_bit = 1 << 28, + FA_BUSY_bit = 1 << 29, + AL_BUSY_bit = 1 << 30, +/* BUSY_bit = 1 << 31, */ + TA1_STATUS = 0x00009524, +/* FG_PFIFO_EMPTYB_bit = 1 << 12, */ +/* FG_LFIFO_EMPTYB_bit = 1 << 13, */ +/* FG_SFIFO_EMPTYB_bit = 1 << 14, */ +/* FL_PFIFO_EMPTYB_bit = 1 << 16, */ +/* FL_LFIFO_EMPTYB_bit = 1 << 17, */ +/* FL_SFIFO_EMPTYB_bit = 1 << 18, */ +/* FA_PFIFO_EMPTYB_bit = 1 << 20, */ +/* FA_LFIFO_EMPTYB_bit = 1 << 21, */ +/* FA_SFIFO_EMPTYB_bit = 1 << 22, */ +/* IN_BUSY_bit = 1 << 24, */ +/* FG_BUSY_bit = 1 << 25, */ +/* FL_BUSY_bit = 1 << 27, */ +/* TA_BUSY_bit = 1 << 28, */ +/* FA_BUSY_bit = 1 << 29, */ +/* AL_BUSY_bit = 1 << 30, */ +/* BUSY_bit = 1 << 31, */ + TA2_STATUS = 0x00009528, +/* FG_PFIFO_EMPTYB_bit = 1 << 12, */ +/* FG_LFIFO_EMPTYB_bit = 1 << 13, */ +/* FG_SFIFO_EMPTYB_bit = 1 << 14, */ +/* FL_PFIFO_EMPTYB_bit = 1 << 16, */ +/* FL_LFIFO_EMPTYB_bit = 1 << 17, */ +/* FL_SFIFO_EMPTYB_bit = 1 << 18, */ +/* FA_PFIFO_EMPTYB_bit = 1 << 20, */ +/* FA_LFIFO_EMPTYB_bit = 1 << 21, */ +/* FA_SFIFO_EMPTYB_bit = 1 << 22, */ +/* IN_BUSY_bit = 1 << 24, */ +/* FG_BUSY_bit = 1 << 25, */ +/* FL_BUSY_bit = 1 << 27, */ +/* TA_BUSY_bit = 1 << 28, */ +/* FA_BUSY_bit = 1 << 29, */ +/* AL_BUSY_bit = 1 << 30, */ +/* BUSY_bit = 1 << 31, */ + TA3_STATUS = 0x0000952c, +/* FG_PFIFO_EMPTYB_bit = 1 << 12, */ +/* FG_LFIFO_EMPTYB_bit = 1 << 13, */ +/* FG_SFIFO_EMPTYB_bit = 1 << 14, */ +/* FL_PFIFO_EMPTYB_bit = 1 << 16, */ +/* FL_LFIFO_EMPTYB_bit = 1 << 17, */ +/* FL_SFIFO_EMPTYB_bit = 1 << 18, */ +/* FA_PFIFO_EMPTYB_bit = 1 << 20, */ +/* FA_LFIFO_EMPTYB_bit = 1 << 21, */ +/* FA_SFIFO_EMPTYB_bit = 1 << 22, */ +/* IN_BUSY_bit = 1 << 24, */ +/* FG_BUSY_bit = 1 << 25, */ +/* FL_BUSY_bit = 1 << 27, */ +/* TA_BUSY_bit = 1 << 28, */ +/* FA_BUSY_bit = 1 << 29, */ +/* AL_BUSY_bit = 1 << 30, */ +/* BUSY_bit = 1 << 31, */ + TC_STATUS = 0x00009600, + TC_BUSY_bit = 1 << 0, + TC_INVALIDATE = 0x00009604, + START_bit = 1 << 0, + TC_CNTL = 0x00009608, + FORCE_HIT_bit = 1 << 0, + FORCE_MISS_bit = 1 << 1, + L2_SIZE_mask = 0x0f << 5, + L2_SIZE_shift = 5, + _256K = 0x00, + _224K = 0x01, + _192K = 0x02, + _160K = 0x03, + _128K = 0x04, + _96K = 0x05, + _64K = 0x06, + _32K = 0x07, + L2_DISABLE_LATE_HIT_bit = 1 << 9, + DISABLE_VERT_PERF_bit = 1 << 10, + DISABLE_INVAL_BUSY_bit = 1 << 11, + DISABLE_INVAL_SAME_SURFACE_bit = 1 << 12, + PARTITION_MODE_mask = 0x03 << 13, + PARTITION_MODE_shift = 13, + X_VERTEX = 0x00, + MISS_ARB_MODE_bit = 1 << 15, + HIT_ARB_MODE_bit = 1 << 16, + DISABLE_WRITE_DELAY_bit = 1 << 17, + HIT_FIFO_DEPTH_bit = 1 << 18, + VC_CNTL = 0x00009700, + L2_INVALIDATE_bit = 1 << 0, + RESERVED_bit = 1 << 1, + CC_FORCE_MISS_bit = 1 << 2, + MI_CHAN_SEL_mask = 0x03 << 3, + MI_CHAN_SEL_shift = 3, + X_MC0_USES_CH_0_1 = 0x00, + X_MC0_USES_CH_0_3 = 0x01, + X_VC_MC0_IS_ACTIVE = 0x02, + X_VC_MC1_IS_DISABLED = 0x03, + MI_STEER_DISABLE_bit = 1 << 5, + MI_CREDIT_CTR_mask = 0x0f << 6, + MI_CREDIT_CTR_shift = 6, + MI_CREDIT_WE_bit = 1 << 10, + MI_REQ_STALL_THLD_mask = 0x07 << 11, + MI_REQ_STALL_THLD_shift = 11, + X_LATENCY_EXCEEDS_399_CLOCKS = 0x00, + X_LATENCY_EXCEEDS_415_CLOCKS = 0x01, + X_LATENCY_EXCEEDS_431_CLOCKS = 0x02, + X_LATENCY_EXCEEDS_447_CLOCKS = 0x03, + X_LATENCY_EXCEEDS_463_CLOCKS = 0x04, + X_LATENCY_EXCEEDS_479_CLOCKS = 0x05, + X_LATENCY_EXCEEDS_495_CLOCKS = 0x06, + X_LATENCY_EXCEEDS_511_CLOCKS = 0x07, + VC_CNTL__MI_TIMESTAMP_RES_mask = 0x1f << 14, + VC_CNTL__MI_TIMESTAMP_RES_shift = 14, + X_1X_SYSTEM_CLOCK = 0x00, + X_2X_SYSTEM_CLOCK = 0x01, + X_4X_SYSTEM_CLOCK = 0x02, + X_8X_SYSTEM_CLOCK = 0x03, + X_16X_SYSTEM_CLOCK = 0x04, + X_32X_SYSTEM_CLOCK = 0x05, + X_64X_SYSTEM_CLOCK = 0x06, + X_128X_SYSTEM_CLOCK = 0x07, + X_256X_SYSTEM_CLOCK = 0x08, + X_512X_SYSTEM_CLOCK = 0x09, + X_1024X_SYSTEM_CLOCK = 0x0a, + X_2048X_SYSTEM_CLOCK = 0x0b, + X_4092X_SYSTEM_CLOCK = 0x0c, + X_8192X_SYSTEM_CLOCK = 0x0d, + X_16384X_SYSTEM_CLOCK = 0x0e, + X_32768X_SYSTEM_CLOCK = 0x0f, + VC_CNTL_STATUS = 0x00009704, + RP_BUSY_bit = 1 << 0, + RG_BUSY_bit = 1 << 1, + VC_BUSY_bit = 1 << 2, + CLAMP_DETECT_bit = 1 << 3, + VC_CONFIG = 0x00009718, + WRITE_DIS_bit = 1 << 0, + GPR_DATA_PHASE_ADJ_mask = 0x07 << 1, + GPR_DATA_PHASE_ADJ_shift = 1, + X_LATENCY_BASE_0_CYCLES = 0x00, + X_LATENCY_BASE_1_CYCLES = 0x01, + X_LATENCY_BASE_2_CYCLES = 0x02, + X_LATENCY_BASE_3_CYCLES = 0x03, + TD_SIMD_SYNC_ADJ_mask = 0x07 << 4, + TD_SIMD_SYNC_ADJ_shift = 4, + X_0_CYCLES_DELAY = 0x00, + X_1_CYCLES_DELAY = 0x01, + X_2_CYCLES_DELAY = 0x02, + X_3_CYCLES_DELAY = 0x03, + X_4_CYCLES_DELAY = 0x04, + X_5_CYCLES_DELAY = 0x05, + X_6_CYCLES_DELAY = 0x06, + X_7_CYCLES_DELAY = 0x07, + SMX_DC_CTL0 = 0x0000a020, + WR_GATHER_STREAM0_bit = 1 << 0, + WR_GATHER_STREAM1_bit = 1 << 1, + WR_GATHER_STREAM2_bit = 1 << 2, + WR_GATHER_STREAM3_bit = 1 << 3, + WR_GATHER_SCRATCH_bit = 1 << 4, + WR_GATHER_REDUC_BUF_bit = 1 << 5, + WR_GATHER_RING_BUF_bit = 1 << 6, + WR_GATHER_F_BUF_bit = 1 << 7, + DISABLE_CACHES_bit = 1 << 8, + AUTO_FLUSH_INVAL_EN_bit = 1 << 10, + AUTO_FLUSH_EN_bit = 1 << 11, + AUTO_FLUSH_CNT_mask = 0xffff << 12, + AUTO_FLUSH_CNT_shift = 12, + MC_RD_STALL_FACTOR_mask = 0x03 << 28, + MC_RD_STALL_FACTOR_shift = 28, + MC_WR_STALL_FACTOR_mask = 0x03 << 30, + MC_WR_STALL_FACTOR_shift = 30, + SMX_DC_CTL1 = 0x0000a024, + OP_FIFO_SKID_mask = 0x7f << 0, + OP_FIFO_SKID_shift = 0, + CACHE_LINE_SIZE_bit = 1 << 8, + MULTI_FLUSH_MODE_bit = 1 << 9, + MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_mask = 0x0f << 10, + MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_shift = 10, + DISABLE_WR_GATHER_RD_HIT_FORCE_EVICT_bit = 1 << 16, + DISABLE_WR_GATHER_RD_HIT_COMP_VLDS_CHECK_bit = 1 << 17, + DISABLE_FLUSH_ES_ALSO_INVALS_bit = 1 << 18, + DISABLE_FLUSH_GS_ALSO_INVALS_bit = 1 << 19, + SMX_DC_CTL2 = 0x0000a028, + INVALIDATE_CACHES_bit = 1 << 0, + CACHES_INVALID_bit = 1 << 1, + CACHES_DIRTY_bit = 1 << 2, + FLUSH_ALL_bit = 1 << 4, + FLUSH_GS_THREADS_bit = 1 << 8, + FLUSH_ES_THREADS_bit = 1 << 9, + SMX_DC_MC_INTF_CTL = 0x0000a02c, + MC_RD_REQ_CRED_mask = 0xff << 0, + MC_RD_REQ_CRED_shift = 0, + MC_WR_REQ_CRED_mask = 0xff << 16, + MC_WR_REQ_CRED_shift = 16, + TD_PS_SAMPLER0_BORDER_RED = 0x0000a400, + TD_PS_SAMPLER0_BORDER_RED_num = 18, + TD_PS_SAMPLER0_BORDER_RED_offset = 16, + TD_PS_SAMPLER0_BORDER_GREEN = 0x0000a404, + TD_PS_SAMPLER0_BORDER_GREEN_num = 18, + TD_PS_SAMPLER0_BORDER_GREEN_offset = 16, + TD_PS_SAMPLER0_BORDER_BLUE = 0x0000a408, + TD_PS_SAMPLER0_BORDER_BLUE_num = 18, + TD_PS_SAMPLER0_BORDER_BLUE_offset = 16, + TD_PS_SAMPLER0_BORDER_ALPHA = 0x0000a40c, + TD_PS_SAMPLER0_BORDER_ALPHA_num = 18, + TD_PS_SAMPLER0_BORDER_ALPHA_offset = 16, + TD_VS_SAMPLER0_BORDER_RED = 0x0000a600, + TD_VS_SAMPLER0_BORDER_RED_num = 18, + TD_VS_SAMPLER0_BORDER_RED_offset = 16, + TD_VS_SAMPLER0_BORDER_GREEN = 0x0000a604, + TD_VS_SAMPLER0_BORDER_GREEN_num = 18, + TD_VS_SAMPLER0_BORDER_GREEN_offset = 16, + TD_VS_SAMPLER0_BORDER_BLUE = 0x0000a608, + TD_VS_SAMPLER0_BORDER_BLUE_num = 18, + TD_VS_SAMPLER0_BORDER_BLUE_offset = 16, + TD_VS_SAMPLER0_BORDER_ALPHA = 0x0000a60c, + TD_VS_SAMPLER0_BORDER_ALPHA_num = 18, + TD_VS_SAMPLER0_BORDER_ALPHA_offset = 16, + TD_GS_SAMPLER0_BORDER_RED = 0x0000a800, + TD_GS_SAMPLER0_BORDER_RED_num = 18, + TD_GS_SAMPLER0_BORDER_RED_offset = 16, + TD_GS_SAMPLER0_BORDER_GREEN = 0x0000a804, + TD_GS_SAMPLER0_BORDER_GREEN_num = 18, + TD_GS_SAMPLER0_BORDER_GREEN_offset = 16, + TD_GS_SAMPLER0_BORDER_BLUE = 0x0000a808, + TD_GS_SAMPLER0_BORDER_BLUE_num = 18, + TD_GS_SAMPLER0_BORDER_BLUE_offset = 16, + TD_GS_SAMPLER0_BORDER_ALPHA = 0x0000a80c, + TD_GS_SAMPLER0_BORDER_ALPHA_num = 18, + TD_GS_SAMPLER0_BORDER_ALPHA_offset = 16, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL = 0x0000aa00, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL_num = 18, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_mask = 0x07 << 0, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_shift = 0, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_mask = 0x07 << 3, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_shift = 3, + DB_DEPTH_SIZE = 0x00028000, + PITCH_TILE_MAX_mask = 0x3ff << 0, + PITCH_TILE_MAX_shift = 0, + SLICE_TILE_MAX_mask = 0xfffff << 10, + SLICE_TILE_MAX_shift = 10, + DB_DEPTH_VIEW = 0x00028004, + SLICE_START_mask = 0x7ff << 0, + SLICE_START_shift = 0, + SLICE_MAX_mask = 0x7ff << 13, + SLICE_MAX_shift = 13, + DB_DEPTH_BASE = 0x0002800c, + DB_DEPTH_INFO = 0x00028010, + DB_DEPTH_INFO__FORMAT_mask = 0x07 << 0, + DB_DEPTH_INFO__FORMAT_shift = 0, + DEPTH_INVALID = 0x00, + DEPTH_16 = 0x01, + DEPTH_X8_24 = 0x02, + DEPTH_8_24 = 0x03, + DEPTH_X8_24_FLOAT = 0x04, + DEPTH_8_24_FLOAT = 0x05, + DEPTH_32_FLOAT = 0x06, + DEPTH_X24_8_32_FLOAT = 0x07, + DB_DEPTH_INFO__READ_SIZE_bit = 1 << 3, + DB_DEPTH_INFO__ARRAY_MODE_mask = 0x0f << 15, + DB_DEPTH_INFO__ARRAY_MODE_shift = 15, + ARRAY_2D_TILED_THIN1 = 0x04, + TILE_SURFACE_ENABLE_bit = 1 << 25, + TILE_COMPACT_bit = 1 << 26, + ZRANGE_PRECISION_bit = 1 << 31, + DB_HTILE_DATA_BASE = 0x00028014, + DB_STENCIL_CLEAR = 0x00028028, + DB_STENCIL_CLEAR__CLEAR_mask = 0xff << 0, + DB_STENCIL_CLEAR__CLEAR_shift = 0, + MIN_mask = 0xff << 16, + MIN_shift = 16, + DB_DEPTH_CLEAR = 0x0002802c, + PA_SC_SCREEN_SCISSOR_TL = 0x00028030, + PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0x7fff << 0, + PA_SC_SCREEN_SCISSOR_TL__TL_X_shift = 0, + PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0x7fff << 16, + PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift = 16, + PA_SC_SCREEN_SCISSOR_BR = 0x00028034, + PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0x7fff << 0, + PA_SC_SCREEN_SCISSOR_BR__BR_X_shift = 0, + PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0x7fff << 16, + PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift = 16, + CB_COLOR0_BASE = 0x00028040, + CB_COLOR0_BASE_num = 8, + CB_COLOR0_SIZE = 0x00028060, + CB_COLOR0_SIZE_num = 8, +/* PITCH_TILE_MAX_mask = 0x3ff << 0, */ +/* PITCH_TILE_MAX_shift = 0, */ +/* SLICE_TILE_MAX_mask = 0xfffff << 10, */ +/* SLICE_TILE_MAX_shift = 10, */ + CB_COLOR0_VIEW = 0x00028080, + CB_COLOR0_VIEW_num = 8, +/* SLICE_START_mask = 0x7ff << 0, */ +/* SLICE_START_shift = 0, */ +/* SLICE_MAX_mask = 0x7ff << 13, */ +/* SLICE_MAX_shift = 13, */ + CB_COLOR0_INFO = 0x000280a0, + CB_COLOR0_INFO_num = 8, + ENDIAN_mask = 0x03 << 0, + ENDIAN_shift = 0, + ENDIAN_NONE = 0x00, + ENDIAN_8IN16 = 0x01, + ENDIAN_8IN32 = 0x02, + ENDIAN_8IN64 = 0x03, + CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2, + CB_COLOR0_INFO__FORMAT_shift = 2, + COLOR_INVALID = 0x00, + COLOR_8 = 0x01, + COLOR_4_4 = 0x02, + COLOR_3_3_2 = 0x03, + COLOR_16 = 0x05, + COLOR_16_FLOAT = 0x06, + COLOR_8_8 = 0x07, + COLOR_5_6_5 = 0x08, + COLOR_6_5_5 = 0x09, + COLOR_1_5_5_5 = 0x0a, + COLOR_4_4_4_4 = 0x0b, + COLOR_5_5_5_1 = 0x0c, + COLOR_32 = 0x0d, + COLOR_32_FLOAT = 0x0e, + COLOR_16_16 = 0x0f, + COLOR_16_16_FLOAT = 0x10, + COLOR_8_24 = 0x11, + COLOR_8_24_FLOAT = 0x12, + COLOR_24_8 = 0x13, + COLOR_24_8_FLOAT = 0x14, + COLOR_10_11_11 = 0x15, + COLOR_10_11_11_FLOAT = 0x16, + COLOR_11_11_10 = 0x17, + COLOR_11_11_10_FLOAT = 0x18, + COLOR_2_10_10_10 = 0x19, + COLOR_8_8_8_8 = 0x1a, + COLOR_10_10_10_2 = 0x1b, + COLOR_X24_8_32_FLOAT = 0x1c, + COLOR_32_32 = 0x1d, + COLOR_32_32_FLOAT = 0x1e, + COLOR_16_16_16_16 = 0x1f, + COLOR_16_16_16_16_FLOAT = 0x20, + COLOR_32_32_32_32 = 0x22, + COLOR_32_32_32_32_FLOAT = 0x23, + CB_COLOR0_INFO__ARRAY_MODE_mask = 0x0f << 8, + CB_COLOR0_INFO__ARRAY_MODE_shift = 8, + ARRAY_LINEAR_GENERAL = 0x00, + ARRAY_LINEAR_ALIGNED = 0x01, +/* ARRAY_2D_TILED_THIN1 = 0x04, */ + NUMBER_TYPE_mask = 0x07 << 12, + NUMBER_TYPE_shift = 12, + NUMBER_UNORM = 0x00, + NUMBER_SNORM = 0x01, + NUMBER_USCALED = 0x02, + NUMBER_SSCALED = 0x03, + NUMBER_UINT = 0x04, + NUMBER_SINT = 0x05, + NUMBER_SRGB = 0x06, + NUMBER_FLOAT = 0x07, + CB_COLOR0_INFO__READ_SIZE_bit = 1 << 15, + COMP_SWAP_mask = 0x03 << 16, + COMP_SWAP_shift = 16, + SWAP_STD = 0x00, + SWAP_ALT = 0x01, + SWAP_STD_REV = 0x02, + SWAP_ALT_REV = 0x03, + CB_COLOR0_INFO__TILE_MODE_mask = 0x03 << 18, + CB_COLOR0_INFO__TILE_MODE_shift = 18, + TILE_DISABLE = 0x00, + TILE_CLEAR_ENABLE = 0x01, + TILE_FRAG_ENABLE = 0x02, + BLEND_CLAMP_bit = 1 << 20, + CLEAR_COLOR_bit = 1 << 21, + BLEND_BYPASS_bit = 1 << 22, + BLEND_FLOAT32_bit = 1 << 23, + SIMPLE_FLOAT_bit = 1 << 24, + CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 25, +/* TILE_COMPACT_bit = 1 << 26, */ + SOURCE_FORMAT_bit = 1 << 27, + CB_COLOR0_TILE = 0x000280c0, + CB_COLOR0_TILE_num = 8, + CB_COLOR0_FRAG = 0x000280e0, + CB_COLOR0_FRAG_num = 8, + CB_COLOR0_MASK = 0x00028100, + CB_COLOR0_MASK_num = 8, + CMASK_BLOCK_MAX_mask = 0xfff << 0, + CMASK_BLOCK_MAX_shift = 0, + FMASK_TILE_MAX_mask = 0xfffff << 12, + FMASK_TILE_MAX_shift = 12, + CB_CLEAR_RED = 0x00028120, + CB_CLEAR_GREEN = 0x00028124, + CB_CLEAR_BLUE = 0x00028128, + CB_CLEAR_ALPHA = 0x0002812c, + SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x00028140, + SQ_ALU_CONST_BUFFER_SIZE_PS_0_num = 16, + SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_mask = 0x1ff << 0, + SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_shift = 0, + SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x00028180, + SQ_ALU_CONST_BUFFER_SIZE_VS_0_num = 16, + SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_mask = 0x1ff << 0, + SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_shift = 0, + SQ_ALU_CONST_BUFFER_SIZE_GS_0 = 0x000281c0, + SQ_ALU_CONST_BUFFER_SIZE_GS_0_num = 16, + SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_mask = 0x1ff << 0, + SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_shift = 0, + PA_SC_WINDOW_OFFSET = 0x00028200, + WINDOW_X_OFFSET_mask = 0x7fff << 0, + WINDOW_X_OFFSET_shift = 0, + WINDOW_Y_OFFSET_mask = 0x7fff << 16, + WINDOW_Y_OFFSET_shift = 16, + PA_SC_WINDOW_SCISSOR_TL = 0x00028204, + PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x3fff << 0, + PA_SC_WINDOW_SCISSOR_TL__TL_X_shift = 0, + PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x3fff << 16, + PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift = 16, + WINDOW_OFFSET_DISABLE_bit = 1 << 31, + PA_SC_WINDOW_SCISSOR_BR = 0x00028208, + PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x3fff << 0, + PA_SC_WINDOW_SCISSOR_BR__BR_X_shift = 0, + PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x3fff << 16, + PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift = 16, + PA_SC_CLIPRECT_RULE = 0x0002820c, + CLIP_RULE_mask = 0xffff << 0, + CLIP_RULE_shift = 0, + PA_SC_CLIPRECT_0_TL = 0x00028210, + PA_SC_CLIPRECT_0_TL_num = 4, + PA_SC_CLIPRECT_0_TL_offset = 8, + PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x3fff << 0, + PA_SC_CLIPRECT_0_TL__TL_X_shift = 0, + PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x3fff << 16, + PA_SC_CLIPRECT_0_TL__TL_Y_shift = 16, + PA_SC_CLIPRECT_0_BR = 0x00028214, + PA_SC_CLIPRECT_0_BR_num = 4, + PA_SC_CLIPRECT_0_BR_offset = 8, + PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x3fff << 0, + PA_SC_CLIPRECT_0_BR__BR_X_shift = 0, + PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x3fff << 16, + PA_SC_CLIPRECT_0_BR__BR_Y_shift = 16, + CB_TARGET_MASK = 0x00028238, + TARGET0_ENABLE_mask = 0x0f << 0, + TARGET0_ENABLE_shift = 0, + TARGET1_ENABLE_mask = 0x0f << 4, + TARGET1_ENABLE_shift = 4, + TARGET2_ENABLE_mask = 0x0f << 8, + TARGET2_ENABLE_shift = 8, + TARGET3_ENABLE_mask = 0x0f << 12, + TARGET3_ENABLE_shift = 12, + TARGET4_ENABLE_mask = 0x0f << 16, + TARGET4_ENABLE_shift = 16, + TARGET5_ENABLE_mask = 0x0f << 20, + TARGET5_ENABLE_shift = 20, + TARGET6_ENABLE_mask = 0x0f << 24, + TARGET6_ENABLE_shift = 24, + TARGET7_ENABLE_mask = 0x0f << 28, + TARGET7_ENABLE_shift = 28, + CB_SHADER_MASK = 0x0002823c, + OUTPUT0_ENABLE_mask = 0x0f << 0, + OUTPUT0_ENABLE_shift = 0, + OUTPUT1_ENABLE_mask = 0x0f << 4, + OUTPUT1_ENABLE_shift = 4, + OUTPUT2_ENABLE_mask = 0x0f << 8, + OUTPUT2_ENABLE_shift = 8, + OUTPUT3_ENABLE_mask = 0x0f << 12, + OUTPUT3_ENABLE_shift = 12, + OUTPUT4_ENABLE_mask = 0x0f << 16, + OUTPUT4_ENABLE_shift = 16, + OUTPUT5_ENABLE_mask = 0x0f << 20, + OUTPUT5_ENABLE_shift = 20, + OUTPUT6_ENABLE_mask = 0x0f << 24, + OUTPUT6_ENABLE_shift = 24, + OUTPUT7_ENABLE_mask = 0x0f << 28, + OUTPUT7_ENABLE_shift = 28, + PA_SC_GENERIC_SCISSOR_TL = 0x00028240, + PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x3fff << 0, + PA_SC_GENERIC_SCISSOR_TL__TL_X_shift = 0, + PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x3fff << 16, + PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift = 16, +/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ + PA_SC_GENERIC_SCISSOR_BR = 0x00028244, + PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x3fff << 0, + PA_SC_GENERIC_SCISSOR_BR__BR_X_shift = 0, + PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x3fff << 16, + PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift = 16, + PA_SC_VPORT_SCISSOR_0_TL = 0x00028250, + PA_SC_VPORT_SCISSOR_0_TL_num = 16, + PA_SC_VPORT_SCISSOR_0_TL_offset = 8, + PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x3fff << 0, + PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift = 0, + PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x3fff << 16, + PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift = 16, +/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ + PA_SC_VPORT_SCISSOR_0_BR = 0x00028254, + PA_SC_VPORT_SCISSOR_0_BR_num = 16, + PA_SC_VPORT_SCISSOR_0_BR_offset = 8, + PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x3fff << 0, + PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift = 0, + PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x3fff << 16, + PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift = 16, + PA_SC_VPORT_ZMIN_0 = 0x000282d0, + PA_SC_VPORT_ZMIN_0_num = 16, + PA_SC_VPORT_ZMIN_0_offset = 8, + PA_SC_VPORT_ZMAX_0 = 0x000282d4, + PA_SC_VPORT_ZMAX_0_num = 16, + PA_SC_VPORT_ZMAX_0_offset = 8, + SX_MISC = 0x00028350, + MULTIPASS_bit = 1 << 0, + SQ_VTX_SEMANTIC_0 = 0x00028380, + SQ_VTX_SEMANTIC_0_num = 32, +/* SEMANTIC_ID_mask = 0xff << 0, */ +/* SEMANTIC_ID_shift = 0, */ + VGT_MAX_VTX_INDX = 0x00028400, + VGT_MIN_VTX_INDX = 0x00028404, + VGT_INDX_OFFSET = 0x00028408, + VGT_MULTI_PRIM_IB_RESET_INDX = 0x0002840c, + SX_ALPHA_TEST_CONTROL = 0x00028410, + ALPHA_FUNC_mask = 0x07 << 0, + ALPHA_FUNC_shift = 0, + REF_NEVER = 0x00, + REF_LESS = 0x01, + REF_EQUAL = 0x02, + REF_LEQUAL = 0x03, + REF_GREATER = 0x04, + REF_NOTEQUAL = 0x05, + REF_GEQUAL = 0x06, + REF_ALWAYS = 0x07, + ALPHA_TEST_ENABLE_bit = 1 << 3, + ALPHA_TEST_BYPASS_bit = 1 << 8, + CB_BLEND_RED = 0x00028414, + CB_BLEND_GREEN = 0x00028418, + CB_BLEND_BLUE = 0x0002841c, + CB_BLEND_ALPHA = 0x00028420, + CB_FOG_RED = 0x00028424, + CB_FOG_GREEN = 0x00028428, + CB_FOG_BLUE = 0x0002842c, + DB_STENCILREFMASK = 0x00028430, + STENCILREF_mask = 0xff << 0, + STENCILREF_shift = 0, + STENCILMASK_mask = 0xff << 8, + STENCILMASK_shift = 8, + STENCILWRITEMASK_mask = 0xff << 16, + STENCILWRITEMASK_shift = 16, + DB_STENCILREFMASK_BF = 0x00028434, + STENCILREF_BF_mask = 0xff << 0, + STENCILREF_BF_shift = 0, + STENCILMASK_BF_mask = 0xff << 8, + STENCILMASK_BF_shift = 8, + STENCILWRITEMASK_BF_mask = 0xff << 16, + STENCILWRITEMASK_BF_shift = 16, + SX_ALPHA_REF = 0x00028438, + PA_CL_VPORT_XSCALE_0 = 0x0002843c, + PA_CL_VPORT_XSCALE_0_num = 16, + PA_CL_VPORT_XSCALE_0_offset = 24, + PA_CL_VPORT_XOFFSET_0 = 0x00028440, + PA_CL_VPORT_XOFFSET_0_num = 16, + PA_CL_VPORT_XOFFSET_0_offset = 24, + PA_CL_VPORT_YSCALE_0 = 0x00028444, + PA_CL_VPORT_YSCALE_0_num = 16, + PA_CL_VPORT_YSCALE_0_offset = 24, + PA_CL_VPORT_YOFFSET_0 = 0x00028448, + PA_CL_VPORT_YOFFSET_0_num = 16, + PA_CL_VPORT_YOFFSET_0_offset = 24, + PA_CL_VPORT_ZSCALE_0 = 0x0002844c, + PA_CL_VPORT_ZSCALE_0_num = 16, + PA_CL_VPORT_ZSCALE_0_offset = 24, + PA_CL_VPORT_ZOFFSET_0 = 0x00028450, + PA_CL_VPORT_ZOFFSET_0_num = 16, + PA_CL_VPORT_ZOFFSET_0_offset = 24, + SPI_VS_OUT_ID_0 = 0x00028614, + SPI_VS_OUT_ID_0_num = 10, + SEMANTIC_0_mask = 0xff << 0, + SEMANTIC_0_shift = 0, + SEMANTIC_1_mask = 0xff << 8, + SEMANTIC_1_shift = 8, + SEMANTIC_2_mask = 0xff << 16, + SEMANTIC_2_shift = 16, + SEMANTIC_3_mask = 0xff << 24, + SEMANTIC_3_shift = 24, + SPI_PS_INPUT_CNTL_0 = 0x00028644, + SPI_PS_INPUT_CNTL_0_num = 32, + SEMANTIC_mask = 0xff << 0, + SEMANTIC_shift = 0, + DEFAULT_VAL_mask = 0x03 << 8, + DEFAULT_VAL_shift = 8, + X_0_0F = 0x00, + FLAT_SHADE_bit = 1 << 10, + SEL_CENTROID_bit = 1 << 11, + SEL_LINEAR_bit = 1 << 12, + CYL_WRAP_mask = 0x0f << 13, + CYL_WRAP_shift = 13, + PT_SPRITE_TEX_bit = 1 << 17, + SEL_SAMPLE_bit = 1 << 18, + SPI_VS_OUT_CONFIG = 0x000286c4, + VS_PER_COMPONENT_bit = 1 << 0, + VS_EXPORT_COUNT_mask = 0x1f << 1, + VS_EXPORT_COUNT_shift = 1, + VS_EXPORTS_FOG_bit = 1 << 8, + VS_OUT_FOG_VEC_ADDR_mask = 0x1f << 9, + VS_OUT_FOG_VEC_ADDR_shift = 9, + SPI_PS_IN_CONTROL_0 = 0x000286cc, + NUM_INTERP_mask = 0x3f << 0, + NUM_INTERP_shift = 0, + POSITION_ENA_bit = 1 << 8, + POSITION_CENTROID_bit = 1 << 9, + POSITION_ADDR_mask = 0x1f << 10, + POSITION_ADDR_shift = 10, + PARAM_GEN_mask = 0x0f << 15, + PARAM_GEN_shift = 15, + PARAM_GEN_ADDR_mask = 0x7f << 19, + PARAM_GEN_ADDR_shift = 19, + BARYC_SAMPLE_CNTL_mask = 0x03 << 26, + BARYC_SAMPLE_CNTL_shift = 26, + CENTROIDS_ONLY = 0x00, + CENTERS_ONLY = 0x01, + CENTROIDS_AND_CENTERS = 0x02, + UNDEF = 0x03, + PERSP_GRADIENT_ENA_bit = 1 << 28, + LINEAR_GRADIENT_ENA_bit = 1 << 29, + POSITION_SAMPLE_bit = 1 << 30, + BARYC_AT_SAMPLE_ENA_bit = 1 << 31, + SPI_PS_IN_CONTROL_1 = 0x000286d0, + GEN_INDEX_PIX_bit = 1 << 0, + GEN_INDEX_PIX_ADDR_mask = 0x7f << 1, + GEN_INDEX_PIX_ADDR_shift = 1, + FRONT_FACE_ENA_bit = 1 << 8, + FRONT_FACE_CHAN_mask = 0x03 << 9, + FRONT_FACE_CHAN_shift = 9, + FRONT_FACE_ALL_BITS_bit = 1 << 11, + FRONT_FACE_ADDR_mask = 0x1f << 12, + FRONT_FACE_ADDR_shift = 12, + FOG_ADDR_mask = 0x7f << 17, + FOG_ADDR_shift = 17, + FIXED_PT_POSITION_ENA_bit = 1 << 24, + FIXED_PT_POSITION_ADDR_mask = 0x1f << 25, + FIXED_PT_POSITION_ADDR_shift = 25, + SPI_INTERP_CONTROL_0 = 0x000286d4, + FLAT_SHADE_ENA_bit = 1 << 0, + PNT_SPRITE_ENA_bit = 1 << 1, + PNT_SPRITE_OVRD_X_mask = 0x07 << 2, + PNT_SPRITE_OVRD_X_shift = 2, + SPI_PNT_SPRITE_SEL_0 = 0x00, + SPI_PNT_SPRITE_SEL_1 = 0x01, + SPI_PNT_SPRITE_SEL_S = 0x02, + SPI_PNT_SPRITE_SEL_T = 0x03, + SPI_PNT_SPRITE_SEL_NONE = 0x04, + PNT_SPRITE_OVRD_Y_mask = 0x07 << 5, + PNT_SPRITE_OVRD_Y_shift = 5, +/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ +/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ +/* SPI_PNT_SPRITE_SEL_S = 0x02, */ +/* SPI_PNT_SPRITE_SEL_T = 0x03, */ +/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ + PNT_SPRITE_OVRD_Z_mask = 0x07 << 8, + PNT_SPRITE_OVRD_Z_shift = 8, +/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ +/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ +/* SPI_PNT_SPRITE_SEL_S = 0x02, */ +/* SPI_PNT_SPRITE_SEL_T = 0x03, */ +/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ + PNT_SPRITE_OVRD_W_mask = 0x07 << 11, + PNT_SPRITE_OVRD_W_shift = 11, +/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ +/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ +/* SPI_PNT_SPRITE_SEL_S = 0x02, */ +/* SPI_PNT_SPRITE_SEL_T = 0x03, */ +/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ + PNT_SPRITE_TOP_1_bit = 1 << 14, + SPI_INPUT_Z = 0x000286d8, + PROVIDE_Z_TO_SPI_bit = 1 << 0, + SPI_FOG_CNTL = 0x000286dc, + PASS_FOG_THROUGH_PS_bit = 1 << 0, + PIXEL_FOG_FUNC_mask = 0x03 << 1, + PIXEL_FOG_FUNC_shift = 1, + SPI_FOG_NONE = 0x00, + SPI_FOG_EXP = 0x01, + SPI_FOG_EXP2 = 0x02, + SPI_FOG_LINEAR = 0x03, + PIXEL_FOG_SRC_SEL_bit = 1 << 3, + VS_FOG_CLAMP_DISABLE_bit = 1 << 4, + SPI_FOG_FUNC_SCALE = 0x000286e0, + SPI_FOG_FUNC_BIAS = 0x000286e4, + CB_BLEND0_CONTROL = 0x00028780, + CB_BLEND0_CONTROL_num = 8, + COLOR_SRCBLEND_mask = 0x1f << 0, + COLOR_SRCBLEND_shift = 0, + COLOR_COMB_FCN_mask = 0x07 << 5, + COLOR_COMB_FCN_shift = 5, + COLOR_DESTBLEND_mask = 0x1f << 8, + COLOR_DESTBLEND_shift = 8, + OPACITY_WEIGHT_bit = 1 << 13, + ALPHA_SRCBLEND_mask = 0x1f << 16, + ALPHA_SRCBLEND_shift = 16, + ALPHA_COMB_FCN_mask = 0x07 << 21, + ALPHA_COMB_FCN_shift = 21, + ALPHA_DESTBLEND_mask = 0x1f << 24, + ALPHA_DESTBLEND_shift = 24, + SEPARATE_ALPHA_BLEND_bit = 1 << 29, + VGT_DMA_BASE_HI = 0x000287e4, + VGT_DMA_BASE_HI__BASE_ADDR_mask = 0xff << 0, + VGT_DMA_BASE_HI__BASE_ADDR_shift = 0, + VGT_DMA_BASE = 0x000287e8, + VGT_DRAW_INITIATOR = 0x000287f0, + SOURCE_SELECT_mask = 0x03 << 0, + SOURCE_SELECT_shift = 0, + DI_SRC_SEL_DMA = 0x00, + DI_SRC_SEL_IMMEDIATE = 0x01, + DI_SRC_SEL_AUTO_INDEX = 0x02, + DI_SRC_SEL_RESERVED = 0x03, + MAJOR_MODE_mask = 0x03 << 2, + MAJOR_MODE_shift = 2, + DI_MAJOR_MODE_0 = 0x00, + DI_MAJOR_MODE_1 = 0x01, + SPRITE_EN_bit = 1 << 4, + NOT_EOP_bit = 1 << 5, + USE_OPAQUE_bit = 1 << 6, + VGT_IMMED_DATA = 0x000287f4, + VGT_EVENT_ADDRESS_REG = 0x000287f8, + ADDRESS_LOW_mask = 0xfffffff << 0, + ADDRESS_LOW_shift = 0, + DB_DEPTH_CONTROL = 0x00028800, + STENCIL_ENABLE_bit = 1 << 0, + Z_ENABLE_bit = 1 << 1, + Z_WRITE_ENABLE_bit = 1 << 2, + ZFUNC_mask = 0x07 << 4, + ZFUNC_shift = 4, + FRAG_NEVER = 0x00, + FRAG_LESS = 0x01, + FRAG_EQUAL = 0x02, + FRAG_LEQUAL = 0x03, + FRAG_GREATER = 0x04, + FRAG_NOTEQUAL = 0x05, + FRAG_GEQUAL = 0x06, + FRAG_ALWAYS = 0x07, + BACKFACE_ENABLE_bit = 1 << 7, + STENCILFUNC_mask = 0x07 << 8, + STENCILFUNC_shift = 8, +/* REF_NEVER = 0x00, */ +/* REF_LESS = 0x01, */ +/* REF_EQUAL = 0x02, */ +/* REF_LEQUAL = 0x03, */ +/* REF_GREATER = 0x04, */ +/* REF_NOTEQUAL = 0x05, */ +/* REF_GEQUAL = 0x06, */ +/* REF_ALWAYS = 0x07, */ + STENCILFAIL_mask = 0x07 << 11, + STENCILFAIL_shift = 11, + STENCIL_KEEP = 0x00, + STENCIL_ZERO = 0x01, + STENCIL_REPLACE = 0x02, + STENCIL_INCR_CLAMP = 0x03, + STENCIL_DECR_CLAMP = 0x04, + STENCIL_INVERT = 0x05, + STENCIL_INCR_WRAP = 0x06, + STENCIL_DECR_WRAP = 0x07, + STENCILZPASS_mask = 0x07 << 14, + STENCILZPASS_shift = 14, +/* STENCIL_KEEP = 0x00, */ +/* STENCIL_ZERO = 0x01, */ +/* STENCIL_REPLACE = 0x02, */ +/* STENCIL_INCR_CLAMP = 0x03, */ +/* STENCIL_DECR_CLAMP = 0x04, */ +/* STENCIL_INVERT = 0x05, */ +/* STENCIL_INCR_WRAP = 0x06, */ +/* STENCIL_DECR_WRAP = 0x07, */ + STENCILZFAIL_mask = 0x07 << 17, + STENCILZFAIL_shift = 17, +/* STENCIL_KEEP = 0x00, */ +/* STENCIL_ZERO = 0x01, */ +/* STENCIL_REPLACE = 0x02, */ +/* STENCIL_INCR_CLAMP = 0x03, */ +/* STENCIL_DECR_CLAMP = 0x04, */ +/* STENCIL_INVERT = 0x05, */ +/* STENCIL_INCR_WRAP = 0x06, */ +/* STENCIL_DECR_WRAP = 0x07, */ + STENCILFUNC_BF_mask = 0x07 << 20, + STENCILFUNC_BF_shift = 20, +/* REF_NEVER = 0x00, */ +/* REF_LESS = 0x01, */ +/* REF_EQUAL = 0x02, */ +/* REF_LEQUAL = 0x03, */ +/* REF_GREATER = 0x04, */ +/* REF_NOTEQUAL = 0x05, */ +/* REF_GEQUAL = 0x06, */ +/* REF_ALWAYS = 0x07, */ + STENCILFAIL_BF_mask = 0x07 << 23, + STENCILFAIL_BF_shift = 23, +/* STENCIL_KEEP = 0x00, */ +/* STENCIL_ZERO = 0x01, */ +/* STENCIL_REPLACE = 0x02, */ +/* STENCIL_INCR_CLAMP = 0x03, */ +/* STENCIL_DECR_CLAMP = 0x04, */ +/* STENCIL_INVERT = 0x05, */ +/* STENCIL_INCR_WRAP = 0x06, */ +/* STENCIL_DECR_WRAP = 0x07, */ + STENCILZPASS_BF_mask = 0x07 << 26, + STENCILZPASS_BF_shift = 26, +/* STENCIL_KEEP = 0x00, */ +/* STENCIL_ZERO = 0x01, */ +/* STENCIL_REPLACE = 0x02, */ +/* STENCIL_INCR_CLAMP = 0x03, */ +/* STENCIL_DECR_CLAMP = 0x04, */ +/* STENCIL_INVERT = 0x05, */ +/* STENCIL_INCR_WRAP = 0x06, */ +/* STENCIL_DECR_WRAP = 0x07, */ + STENCILZFAIL_BF_mask = 0x07 << 29, + STENCILZFAIL_BF_shift = 29, +/* STENCIL_KEEP = 0x00, */ +/* STENCIL_ZERO = 0x01, */ +/* STENCIL_REPLACE = 0x02, */ +/* STENCIL_INCR_CLAMP = 0x03, */ +/* STENCIL_DECR_CLAMP = 0x04, */ +/* STENCIL_INVERT = 0x05, */ +/* STENCIL_INCR_WRAP = 0x06, */ +/* STENCIL_DECR_WRAP = 0x07, */ + CB_BLEND_CONTROL = 0x00028804, +/* COLOR_SRCBLEND_mask = 0x1f << 0, */ +/* COLOR_SRCBLEND_shift = 0, */ + BLEND_ZERO = 0x00, + BLEND_ONE = 0x01, + BLEND_SRC_COLOR = 0x02, + BLEND_ONE_MINUS_SRC_COLOR = 0x03, + BLEND_SRC_ALPHA = 0x04, + BLEND_ONE_MINUS_SRC_ALPHA = 0x05, + BLEND_DST_ALPHA = 0x06, + BLEND_ONE_MINUS_DST_ALPHA = 0x07, + BLEND_DST_COLOR = 0x08, + BLEND_ONE_MINUS_DST_COLOR = 0x09, + BLEND_SRC_ALPHA_SATURATE = 0x0a, + BLEND_BOTH_SRC_ALPHA = 0x0b, + BLEND_BOTH_INV_SRC_ALPHA = 0x0c, + BLEND_CONSTANT_COLOR = 0x0d, + BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, + BLEND_SRC1_COLOR = 0x0f, + BLEND_INV_SRC1_COLOR = 0x10, + BLEND_SRC1_ALPHA = 0x11, + BLEND_INV_SRC1_ALPHA = 0x12, + BLEND_CONSTANT_ALPHA = 0x13, + BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, +/* COLOR_COMB_FCN_mask = 0x07 << 5, */ +/* COLOR_COMB_FCN_shift = 5, */ + COMB_DST_PLUS_SRC = 0x00, + COMB_SRC_MINUS_DST = 0x01, + COMB_MIN_DST_SRC = 0x02, + COMB_MAX_DST_SRC = 0x03, + COMB_DST_MINUS_SRC = 0x04, +/* COLOR_DESTBLEND_mask = 0x1f << 8, */ +/* COLOR_DESTBLEND_shift = 8, */ +/* BLEND_ZERO = 0x00, */ +/* BLEND_ONE = 0x01, */ +/* BLEND_SRC_COLOR = 0x02, */ +/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ +/* BLEND_SRC_ALPHA = 0x04, */ +/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ +/* BLEND_DST_ALPHA = 0x06, */ +/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ +/* BLEND_DST_COLOR = 0x08, */ +/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ +/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ +/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ +/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ +/* BLEND_CONSTANT_COLOR = 0x0d, */ +/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ +/* BLEND_SRC1_COLOR = 0x0f, */ +/* BLEND_INV_SRC1_COLOR = 0x10, */ +/* BLEND_SRC1_ALPHA = 0x11, */ +/* BLEND_INV_SRC1_ALPHA = 0x12, */ +/* BLEND_CONSTANT_ALPHA = 0x13, */ +/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ +/* OPACITY_WEIGHT_bit = 1 << 13, */ +/* ALPHA_SRCBLEND_mask = 0x1f << 16, */ +/* ALPHA_SRCBLEND_shift = 16, */ +/* BLEND_ZERO = 0x00, */ +/* BLEND_ONE = 0x01, */ +/* BLEND_SRC_COLOR = 0x02, */ +/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ +/* BLEND_SRC_ALPHA = 0x04, */ +/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ +/* BLEND_DST_ALPHA = 0x06, */ +/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ +/* BLEND_DST_COLOR = 0x08, */ +/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ +/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ +/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ +/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ +/* BLEND_CONSTANT_COLOR = 0x0d, */ +/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ +/* BLEND_SRC1_COLOR = 0x0f, */ +/* BLEND_INV_SRC1_COLOR = 0x10, */ +/* BLEND_SRC1_ALPHA = 0x11, */ +/* BLEND_INV_SRC1_ALPHA = 0x12, */ +/* BLEND_CONSTANT_ALPHA = 0x13, */ +/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ +/* ALPHA_COMB_FCN_mask = 0x07 << 21, */ +/* ALPHA_COMB_FCN_shift = 21, */ +/* COMB_DST_PLUS_SRC = 0x00, */ +/* COMB_SRC_MINUS_DST = 0x01, */ +/* COMB_MIN_DST_SRC = 0x02, */ +/* COMB_MAX_DST_SRC = 0x03, */ +/* COMB_DST_MINUS_SRC = 0x04, */ +/* ALPHA_DESTBLEND_mask = 0x1f << 24, */ +/* ALPHA_DESTBLEND_shift = 24, */ +/* BLEND_ZERO = 0x00, */ +/* BLEND_ONE = 0x01, */ +/* BLEND_SRC_COLOR = 0x02, */ +/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ +/* BLEND_SRC_ALPHA = 0x04, */ +/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ +/* BLEND_DST_ALPHA = 0x06, */ +/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ +/* BLEND_DST_COLOR = 0x08, */ +/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ +/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ +/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ +/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ +/* BLEND_CONSTANT_COLOR = 0x0d, */ +/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ +/* BLEND_SRC1_COLOR = 0x0f, */ +/* BLEND_INV_SRC1_COLOR = 0x10, */ +/* BLEND_SRC1_ALPHA = 0x11, */ +/* BLEND_INV_SRC1_ALPHA = 0x12, */ +/* BLEND_CONSTANT_ALPHA = 0x13, */ +/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ +/* SEPARATE_ALPHA_BLEND_bit = 1 << 29, */ + CB_COLOR_CONTROL = 0x00028808, + FOG_ENABLE_bit = 1 << 0, + MULTIWRITE_ENABLE_bit = 1 << 1, + DITHER_ENABLE_bit = 1 << 2, + DEGAMMA_ENABLE_bit = 1 << 3, + SPECIAL_OP_mask = 0x07 << 4, + SPECIAL_OP_shift = 4, + SPECIAL_NORMAL = 0x00, + SPECIAL_DISABLE = 0x01, + SPECIAL_FAST_CLEAR = 0x02, + SPECIAL_FORCE_CLEAR = 0x03, + SPECIAL_EXPAND_COLOR = 0x04, + SPECIAL_EXPAND_TEXTURE = 0x05, + SPECIAL_EXPAND_SAMPLES = 0x06, + SPECIAL_RESOLVE_BOX = 0x07, + PER_MRT_BLEND_bit = 1 << 7, + TARGET_BLEND_ENABLE_mask = 0xff << 8, + TARGET_BLEND_ENABLE_shift = 8, + ROP3_mask = 0xff << 16, + ROP3_shift = 16, + DB_SHADER_CONTROL = 0x0002880c, + Z_EXPORT_ENABLE_bit = 1 << 0, + STENCIL_REF_EXPORT_ENABLE_bit = 1 << 1, + Z_ORDER_mask = 0x03 << 4, + Z_ORDER_shift = 4, + LATE_Z = 0x00, + EARLY_Z_THEN_LATE_Z = 0x01, + RE_Z = 0x02, + EARLY_Z_THEN_RE_Z = 0x03, + KILL_ENABLE_bit = 1 << 6, + COVERAGE_TO_MASK_ENABLE_bit = 1 << 7, + MASK_EXPORT_ENABLE_bit = 1 << 8, + DUAL_EXPORT_ENABLE_bit = 1 << 9, + EXEC_ON_HIER_FAIL_bit = 1 << 10, + EXEC_ON_NOOP_bit = 1 << 11, + PA_CL_CLIP_CNTL = 0x00028810, + UCP_ENA_0_bit = 1 << 0, + UCP_ENA_1_bit = 1 << 1, + UCP_ENA_2_bit = 1 << 2, + UCP_ENA_3_bit = 1 << 3, + UCP_ENA_4_bit = 1 << 4, + UCP_ENA_5_bit = 1 << 5, + PS_UCP_Y_SCALE_NEG_bit = 1 << 13, + PS_UCP_MODE_mask = 0x03 << 14, + PS_UCP_MODE_shift = 14, + CLIP_DISABLE_bit = 1 << 16, + UCP_CULL_ONLY_ENA_bit = 1 << 17, + BOUNDARY_EDGE_FLAG_ENA_bit = 1 << 18, + DX_CLIP_SPACE_DEF_bit = 1 << 19, + DIS_CLIP_ERR_DETECT_bit = 1 << 20, + VTX_KILL_OR_bit = 1 << 21, + DX_LINEAR_ATTR_CLIP_ENA_bit = 1 << 24, + VTE_VPORT_PROVOKE_DISABLE_bit = 1 << 25, + ZCLIP_NEAR_DISABLE_bit = 1 << 26, + ZCLIP_FAR_DISABLE_bit = 1 << 27, + PA_SU_SC_MODE_CNTL = 0x00028814, + CULL_FRONT_bit = 1 << 0, + CULL_BACK_bit = 1 << 1, + FACE_bit = 1 << 2, + POLY_MODE_mask = 0x03 << 3, + POLY_MODE_shift = 3, + X_DISABLE_POLY_MODE = 0x00, + X_DUAL_MODE = 0x01, + POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, + POLYMODE_FRONT_PTYPE_shift = 5, + X_DRAW_POINTS = 0x00, + X_DRAW_LINES = 0x01, + X_DRAW_TRIANGLES = 0x02, + POLYMODE_BACK_PTYPE_mask = 0x07 << 8, + POLYMODE_BACK_PTYPE_shift = 8, +/* X_DRAW_POINTS = 0x00, */ +/* X_DRAW_LINES = 0x01, */ +/* X_DRAW_TRIANGLES = 0x02, */ + POLY_OFFSET_FRONT_ENABLE_bit = 1 << 11, + POLY_OFFSET_BACK_ENABLE_bit = 1 << 12, + POLY_OFFSET_PARA_ENABLE_bit = 1 << 13, + VTX_WINDOW_OFFSET_ENABLE_bit = 1 << 16, + PROVOKING_VTX_LAST_bit = 1 << 19, + PERSP_CORR_DIS_bit = 1 << 20, + MULTI_PRIM_IB_ENA_bit = 1 << 21, + PA_CL_VTE_CNTL = 0x00028818, + VPORT_X_SCALE_ENA_bit = 1 << 0, + VPORT_X_OFFSET_ENA_bit = 1 << 1, + VPORT_Y_SCALE_ENA_bit = 1 << 2, + VPORT_Y_OFFSET_ENA_bit = 1 << 3, + VPORT_Z_SCALE_ENA_bit = 1 << 4, + VPORT_Z_OFFSET_ENA_bit = 1 << 5, + VTX_XY_FMT_bit = 1 << 8, + VTX_Z_FMT_bit = 1 << 9, + VTX_W0_FMT_bit = 1 << 10, + PERFCOUNTER_REF_bit = 1 << 11, + PA_CL_VS_OUT_CNTL = 0x0002881c, + CLIP_DIST_ENA_0_bit = 1 << 0, + CLIP_DIST_ENA_1_bit = 1 << 1, + CLIP_DIST_ENA_2_bit = 1 << 2, + CLIP_DIST_ENA_3_bit = 1 << 3, + CLIP_DIST_ENA_4_bit = 1 << 4, + CLIP_DIST_ENA_5_bit = 1 << 5, + CLIP_DIST_ENA_6_bit = 1 << 6, + CLIP_DIST_ENA_7_bit = 1 << 7, + CULL_DIST_ENA_0_bit = 1 << 8, + CULL_DIST_ENA_1_bit = 1 << 9, + CULL_DIST_ENA_2_bit = 1 << 10, + CULL_DIST_ENA_3_bit = 1 << 11, + CULL_DIST_ENA_4_bit = 1 << 12, + CULL_DIST_ENA_5_bit = 1 << 13, + CULL_DIST_ENA_6_bit = 1 << 14, + CULL_DIST_ENA_7_bit = 1 << 15, + USE_VTX_POINT_SIZE_bit = 1 << 16, + USE_VTX_EDGE_FLAG_bit = 1 << 17, + USE_VTX_RENDER_TARGET_INDX_bit = 1 << 18, + USE_VTX_VIEWPORT_INDX_bit = 1 << 19, + USE_VTX_KILL_FLAG_bit = 1 << 20, + VS_OUT_MISC_VEC_ENA_bit = 1 << 21, + VS_OUT_CCDIST0_VEC_ENA_bit = 1 << 22, + VS_OUT_CCDIST1_VEC_ENA_bit = 1 << 23, + PA_CL_NANINF_CNTL = 0x00028820, + VTE_XY_INF_DISCARD_bit = 1 << 0, + VTE_Z_INF_DISCARD_bit = 1 << 1, + VTE_W_INF_DISCARD_bit = 1 << 2, + VTE_0XNANINF_IS_0_bit = 1 << 3, + VTE_XY_NAN_RETAIN_bit = 1 << 4, + VTE_Z_NAN_RETAIN_bit = 1 << 5, + VTE_W_NAN_RETAIN_bit = 1 << 6, + VTE_W_RECIP_NAN_IS_0_bit = 1 << 7, + VS_XY_NAN_TO_INF_bit = 1 << 8, + VS_XY_INF_RETAIN_bit = 1 << 9, + VS_Z_NAN_TO_INF_bit = 1 << 10, + VS_Z_INF_RETAIN_bit = 1 << 11, + VS_W_NAN_TO_INF_bit = 1 << 12, + VS_W_INF_RETAIN_bit = 1 << 13, + VS_CLIP_DIST_INF_DISCARD_bit = 1 << 14, + VTE_NO_OUTPUT_NEG_0_bit = 1 << 20, + SQ_PGM_START_PS = 0x00028840, + SQ_PGM_RESOURCES_PS = 0x00028850, + NUM_GPRS_mask = 0xff << 0, + NUM_GPRS_shift = 0, + STACK_SIZE_mask = 0xff << 8, + STACK_SIZE_shift = 8, + SQ_PGM_RESOURCES_PS__DX10_CLAMP_bit = 1 << 21, + FETCH_CACHE_LINES_mask = 0x07 << 24, + FETCH_CACHE_LINES_shift = 24, + UNCACHED_FIRST_INST_bit = 1 << 28, + CLAMP_CONSTS_bit = 1 << 31, + SQ_PGM_EXPORTS_PS = 0x00028854, + EXPORT_MODE_mask = 0x1f << 0, + EXPORT_MODE_shift = 0, + SQ_PGM_START_VS = 0x00028858, + SQ_PGM_RESOURCES_VS = 0x00028868, +/* NUM_GPRS_mask = 0xff << 0, */ +/* NUM_GPRS_shift = 0, */ +/* STACK_SIZE_mask = 0xff << 8, */ +/* STACK_SIZE_shift = 8, */ + SQ_PGM_RESOURCES_VS__DX10_CLAMP_bit = 1 << 21, +/* FETCH_CACHE_LINES_mask = 0x07 << 24, */ +/* FETCH_CACHE_LINES_shift = 24, */ +/* UNCACHED_FIRST_INST_bit = 1 << 28, */ + SQ_PGM_START_GS = 0x0002886c, + SQ_PGM_RESOURCES_GS = 0x0002887c, +/* NUM_GPRS_mask = 0xff << 0, */ +/* NUM_GPRS_shift = 0, */ +/* STACK_SIZE_mask = 0xff << 8, */ +/* STACK_SIZE_shift = 8, */ + SQ_PGM_RESOURCES_GS__DX10_CLAMP_bit = 1 << 21, +/* FETCH_CACHE_LINES_mask = 0x07 << 24, */ +/* FETCH_CACHE_LINES_shift = 24, */ +/* UNCACHED_FIRST_INST_bit = 1 << 28, */ + SQ_PGM_START_ES = 0x00028880, + SQ_PGM_RESOURCES_ES = 0x00028890, +/* NUM_GPRS_mask = 0xff << 0, */ +/* NUM_GPRS_shift = 0, */ +/* STACK_SIZE_mask = 0xff << 8, */ +/* STACK_SIZE_shift = 8, */ + SQ_PGM_RESOURCES_ES__DX10_CLAMP_bit = 1 << 21, +/* FETCH_CACHE_LINES_mask = 0x07 << 24, */ +/* FETCH_CACHE_LINES_shift = 24, */ +/* UNCACHED_FIRST_INST_bit = 1 << 28, */ + SQ_PGM_START_FS = 0x00028894, + SQ_PGM_RESOURCES_FS = 0x000288a4, +/* NUM_GPRS_mask = 0xff << 0, */ +/* NUM_GPRS_shift = 0, */ +/* STACK_SIZE_mask = 0xff << 8, */ +/* STACK_SIZE_shift = 8, */ + SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit = 1 << 21, + SQ_ESGS_RING_ITEMSIZE = 0x000288a8, + ITEMSIZE_mask = 0x7fff << 0, + ITEMSIZE_shift = 0, + SQ_GSVS_RING_ITEMSIZE = 0x000288ac, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_ESTMP_RING_ITEMSIZE = 0x000288b0, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_GSTMP_RING_ITEMSIZE = 0x000288b4, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_VSTMP_RING_ITEMSIZE = 0x000288b8, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_PSTMP_RING_ITEMSIZE = 0x000288bc, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_FBUF_RING_ITEMSIZE = 0x000288c0, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_REDUC_RING_ITEMSIZE = 0x000288c4, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_GS_VERT_ITEMSIZE = 0x000288c8, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_PGM_CF_OFFSET_PS = 0x000288cc, + PGM_CF_OFFSET_mask = 0xfffff << 0, + PGM_CF_OFFSET_shift = 0, + SQ_PGM_CF_OFFSET_VS = 0x000288d0, +/* PGM_CF_OFFSET_mask = 0xfffff << 0, */ +/* PGM_CF_OFFSET_shift = 0, */ + SQ_PGM_CF_OFFSET_GS = 0x000288d4, +/* PGM_CF_OFFSET_mask = 0xfffff << 0, */ +/* PGM_CF_OFFSET_shift = 0, */ + SQ_PGM_CF_OFFSET_ES = 0x000288d8, +/* PGM_CF_OFFSET_mask = 0xfffff << 0, */ +/* PGM_CF_OFFSET_shift = 0, */ + SQ_PGM_CF_OFFSET_FS = 0x000288dc, +/* PGM_CF_OFFSET_mask = 0xfffff << 0, */ +/* PGM_CF_OFFSET_shift = 0, */ + SQ_VTX_SEMANTIC_CLEAR = 0x000288e0, + SQ_ALU_CONST_CACHE_PS_0 = 0x00028940, + SQ_ALU_CONST_CACHE_PS_0_num = 16, + SQ_ALU_CONST_CACHE_VS_0 = 0x00028980, + SQ_ALU_CONST_CACHE_VS_0_num = 16, + SQ_ALU_CONST_CACHE_GS_0 = 0x000289c0, + SQ_ALU_CONST_CACHE_GS_0_num = 16, + PA_SU_POINT_SIZE = 0x00028a00, + PA_SU_POINT_SIZE__HEIGHT_mask = 0xffff << 0, + PA_SU_POINT_SIZE__HEIGHT_shift = 0, + PA_SU_POINT_SIZE__WIDTH_mask = 0xffff << 16, + PA_SU_POINT_SIZE__WIDTH_shift = 16, + PA_SU_POINT_MINMAX = 0x00028a04, + MIN_SIZE_mask = 0xffff << 0, + MIN_SIZE_shift = 0, + MAX_SIZE_mask = 0xffff << 16, + MAX_SIZE_shift = 16, + PA_SU_LINE_CNTL = 0x00028a08, + PA_SU_LINE_CNTL__WIDTH_mask = 0xffff << 0, + PA_SU_LINE_CNTL__WIDTH_shift = 0, + PA_SC_LINE_STIPPLE = 0x00028a0c, + LINE_PATTERN_mask = 0xffff << 0, + LINE_PATTERN_shift = 0, + REPEAT_COUNT_mask = 0xff << 16, + REPEAT_COUNT_shift = 16, + PATTERN_BIT_ORDER_bit = 1 << 28, + AUTO_RESET_CNTL_mask = 0x03 << 29, + AUTO_RESET_CNTL_shift = 29, + VGT_OUTPUT_PATH_CNTL = 0x00028a10, + PATH_SELECT_mask = 0x03 << 0, + PATH_SELECT_shift = 0, + VGT_OUTPATH_VTX_REUSE = 0x00, + VGT_OUTPATH_TESS_EN = 0x01, + VGT_OUTPATH_PASSTHRU = 0x02, + VGT_OUTPATH_GS_BLOCK = 0x03, + VGT_HOS_CNTL = 0x00028a14, + TESS_MODE_mask = 0x03 << 0, + TESS_MODE_shift = 0, + VGT_HOS_MAX_TESS_LEVEL = 0x00028a18, + VGT_HOS_MIN_TESS_LEVEL = 0x00028a1c, + VGT_HOS_REUSE_DEPTH = 0x00028a20, + REUSE_DEPTH_mask = 0xff << 0, + REUSE_DEPTH_shift = 0, + VGT_GROUP_PRIM_TYPE = 0x00028a24, + VGT_GROUP_PRIM_TYPE__PRIM_TYPE_mask = 0x1f << 0, + VGT_GROUP_PRIM_TYPE__PRIM_TYPE_shift = 0, + VGT_GRP_3D_POINT = 0x00, + VGT_GRP_3D_LINE = 0x01, + VGT_GRP_3D_TRI = 0x02, + VGT_GRP_3D_RECT = 0x03, + VGT_GRP_3D_QUAD = 0x04, + VGT_GRP_2D_COPY_RECT_V0 = 0x05, + VGT_GRP_2D_COPY_RECT_V1 = 0x06, + VGT_GRP_2D_COPY_RECT_V2 = 0x07, + VGT_GRP_2D_COPY_RECT_V3 = 0x08, + VGT_GRP_2D_FILL_RECT = 0x09, + VGT_GRP_2D_LINE = 0x0a, + VGT_GRP_2D_TRI = 0x0b, + VGT_GRP_PRIM_INDEX_LINE = 0x0c, + VGT_GRP_PRIM_INDEX_TRI = 0x0d, + VGT_GRP_PRIM_INDEX_QUAD = 0x0e, + VGT_GRP_3D_LINE_ADJ = 0x0f, + VGT_GRP_3D_TRI_ADJ = 0x10, + RETAIN_ORDER_bit = 1 << 14, + RETAIN_QUADS_bit = 1 << 15, + PRIM_ORDER_mask = 0x07 << 16, + PRIM_ORDER_shift = 16, + VGT_GRP_LIST = 0x00, + VGT_GRP_STRIP = 0x01, + VGT_GRP_FAN = 0x02, + VGT_GRP_LOOP = 0x03, + VGT_GRP_POLYGON = 0x04, + VGT_GROUP_FIRST_DECR = 0x00028a28, + FIRST_DECR_mask = 0x0f << 0, + FIRST_DECR_shift = 0, + VGT_GROUP_DECR = 0x00028a2c, + DECR_mask = 0x0f << 0, + DECR_shift = 0, + VGT_GROUP_VECT_0_CNTL = 0x00028a30, + COMP_X_EN_bit = 1 << 0, + COMP_Y_EN_bit = 1 << 1, + COMP_Z_EN_bit = 1 << 2, + COMP_W_EN_bit = 1 << 3, + VGT_GROUP_VECT_0_CNTL__STRIDE_mask = 0xff << 8, + VGT_GROUP_VECT_0_CNTL__STRIDE_shift = 8, + SHIFT_mask = 0xff << 16, + SHIFT_shift = 16, + VGT_GROUP_VECT_1_CNTL = 0x00028a34, +/* COMP_X_EN_bit = 1 << 0, */ +/* COMP_Y_EN_bit = 1 << 1, */ +/* COMP_Z_EN_bit = 1 << 2, */ +/* COMP_W_EN_bit = 1 << 3, */ + VGT_GROUP_VECT_1_CNTL__STRIDE_mask = 0xff << 8, + VGT_GROUP_VECT_1_CNTL__STRIDE_shift = 8, +/* SHIFT_mask = 0xff << 16, */ +/* SHIFT_shift = 16, */ + VGT_GROUP_VECT_0_FMT_CNTL = 0x00028a38, + X_CONV_mask = 0x0f << 0, + X_CONV_shift = 0, + VGT_GRP_INDEX_16 = 0x00, + VGT_GRP_INDEX_32 = 0x01, + VGT_GRP_UINT_16 = 0x02, + VGT_GRP_UINT_32 = 0x03, + VGT_GRP_SINT_16 = 0x04, + VGT_GRP_SINT_32 = 0x05, + VGT_GRP_FLOAT_32 = 0x06, + VGT_GRP_AUTO_PRIM = 0x07, + VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, + X_OFFSET_mask = 0x0f << 4, + X_OFFSET_shift = 4, + Y_CONV_mask = 0x0f << 8, + Y_CONV_shift = 8, +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ + Y_OFFSET_mask = 0x0f << 12, + Y_OFFSET_shift = 12, + Z_CONV_mask = 0x0f << 16, + Z_CONV_shift = 16, +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ + Z_OFFSET_mask = 0x0f << 20, + Z_OFFSET_shift = 20, + W_CONV_mask = 0x0f << 24, + W_CONV_shift = 24, +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ + W_OFFSET_mask = 0x0f << 28, + W_OFFSET_shift = 28, + VGT_GROUP_VECT_1_FMT_CNTL = 0x00028a3c, +/* X_CONV_mask = 0x0f << 0, */ +/* X_CONV_shift = 0, */ +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ +/* X_OFFSET_mask = 0x0f << 4, */ +/* X_OFFSET_shift = 4, */ +/* Y_CONV_mask = 0x0f << 8, */ +/* Y_CONV_shift = 8, */ +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ +/* Y_OFFSET_mask = 0x0f << 12, */ +/* Y_OFFSET_shift = 12, */ +/* Z_CONV_mask = 0x0f << 16, */ +/* Z_CONV_shift = 16, */ +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ +/* Z_OFFSET_mask = 0x0f << 20, */ +/* Z_OFFSET_shift = 20, */ +/* W_CONV_mask = 0x0f << 24, */ +/* W_CONV_shift = 24, */ +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ +/* W_OFFSET_mask = 0x0f << 28, */ +/* W_OFFSET_shift = 28, */ + VGT_GS_MODE = 0x00028a40, + MODE_mask = 0x03 << 0, + MODE_shift = 0, + GS_OFF = 0x00, + GS_SCENARIO_A = 0x01, + GS_SCENARIO_B = 0x02, + GS_SCENARIO_G = 0x03, + ES_PASSTHRU_bit = 1 << 2, + CUT_MODE_mask = 0x03 << 3, + CUT_MODE_shift = 3, + GS_CUT_1024 = 0x00, + GS_CUT_512 = 0x01, + GS_CUT_256 = 0x02, + GS_CUT_128 = 0x03, + PA_SC_MPASS_PS_CNTL = 0x00028a48, + MPASS_PIX_VEC_PER_PASS_mask = 0xfffff << 0, + MPASS_PIX_VEC_PER_PASS_shift = 0, + MPASS_PS_ENA_bit = 1 << 31, + PA_SC_MODE_CNTL = 0x00028a4c, + MSAA_ENABLE_bit = 1 << 0, + CLIPRECT_ENABLE_bit = 1 << 1, + LINE_STIPPLE_ENABLE_bit = 1 << 2, + MULTI_CHIP_PRIM_DISCARD_ENAB_bit = 1 << 3, + WALK_ORDER_ENABLE_bit = 1 << 4, + HALVE_DETAIL_SAMPLE_PERF_bit = 1 << 5, + WALK_SIZE_bit = 1 << 6, + WALK_ALIGNMENT_bit = 1 << 7, + WALK_ALIGN8_PRIM_FITS_ST_bit = 1 << 8, + TILE_COVER_NO_SCISSOR_bit = 1 << 9, + KILL_PIX_POST_HI_Z_bit = 1 << 10, + KILL_PIX_POST_DETAIL_MASK_bit = 1 << 11, + MULTI_CHIP_SUPERTILE_ENABLE_bit = 1 << 12, + TILE_COVER_DISABLE_bit = 1 << 13, + FORCE_EOV_CNTDWN_ENABLE_bit = 1 << 14, + FORCE_EOV_TILE_ENABLE_bit = 1 << 15, + FORCE_EOV_REZ_ENABLE_bit = 1 << 16, + PS_ITER_SAMPLE_bit = 1 << 17, + VGT_ENHANCE = 0x00028a50, + VGT_ENHANCE__MI_TIMESTAMP_RES_mask = 0x03 << 0, + VGT_ENHANCE__MI_TIMESTAMP_RES_shift = 0, + X_0_992_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_32 = 0x00, + X_0_496_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_16 = 0x01, + X_0_248_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_8 = 0x02, + X_0_124_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_4 = 0x03, + MISC_mask = 0x3fffffff << 2, + MISC_shift = 2, + VGT_GS_OUT_PRIM_TYPE = 0x00028a6c, + OUTPRIM_TYPE_mask = 0x3f << 0, + OUTPRIM_TYPE_shift = 0, + POINTLIST = 0x00, + LINESTRIP = 0x01, + TRISTRIP = 0x02, + VGT_DMA_SIZE = 0x00028a74, + VGT_DMA_INDEX_TYPE = 0x00028a7c, +/* INDEX_TYPE_mask = 0x03 << 0, */ +/* INDEX_TYPE_shift = 0, */ + VGT_INDEX_16 = 0x00, + VGT_INDEX_32 = 0x01, + SWAP_MODE_mask = 0x03 << 2, + SWAP_MODE_shift = 2, + VGT_DMA_SWAP_NONE = 0x00, + VGT_DMA_SWAP_16_BIT = 0x01, + VGT_DMA_SWAP_32_BIT = 0x02, + VGT_DMA_SWAP_WORD = 0x03, + VGT_PRIMITIVEID_EN = 0x00028a84, + PRIMITIVEID_EN_bit = 1 << 0, + VGT_DMA_NUM_INSTANCES = 0x00028a88, + VGT_EVENT_INITIATOR = 0x00028a90, + EVENT_TYPE_mask = 0x3f << 0, + EVENT_TYPE_shift = 0, + CACHE_FLUSH_TS = 0x04, + CONTEXT_DONE = 0x05, + CACHE_FLUSH = 0x06, + VIZQUERY_START = 0x07, + VIZQUERY_END = 0x08, + SC_WAIT_WC = 0x09, + MPASS_PS_CP_REFETCH = 0x0a, + MPASS_PS_RST_START = 0x0b, + MPASS_PS_INCR_START = 0x0c, + RST_PIX_CNT = 0x0d, + RST_VTX_CNT = 0x0e, + VS_PARTIAL_FLUSH = 0x0f, + PS_PARTIAL_FLUSH = 0x10, + CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, + ZPASS_DONE = 0x15, + CACHE_FLUSH_AND_INV_EVENT = 0x16, + PERFCOUNTER_START = 0x17, + PERFCOUNTER_STOP = 0x18, + PIPELINESTAT_START = 0x19, + PIPELINESTAT_STOP = 0x1a, + PERFCOUNTER_SAMPLE = 0x1b, + FLUSH_ES_OUTPUT = 0x1c, + FLUSH_GS_OUTPUT = 0x1d, + SAMPLE_PIPELINESTAT = 0x1e, + SO_VGTSTREAMOUT_FLUSH = 0x1f, + SAMPLE_STREAMOUTSTATS = 0x20, + RESET_VTX_CNT = 0x21, + BLOCK_CONTEXT_DONE = 0x22, + CR_CONTEXT_DONE = 0x23, + VGT_FLUSH = 0x24, + CR_DONE_TS = 0x25, + SQ_NON_EVENT = 0x26, + SC_SEND_DB_VPZ = 0x27, + BOTTOM_OF_PIPE_TS = 0x28, + DB_CACHE_FLUSH_AND_INV = 0x2a, + ADDRESS_HI_mask = 0xff << 19, + ADDRESS_HI_shift = 19, + EXTENDED_EVENT_bit = 1 << 27, + VGT_MULTI_PRIM_IB_RESET_EN = 0x00028a94, + RESET_EN_bit = 1 << 0, + VGT_INSTANCE_STEP_RATE_0 = 0x00028aa0, + VGT_INSTANCE_STEP_RATE_1 = 0x00028aa4, + VGT_STRMOUT_EN = 0x00028ab0, + STREAMOUT_bit = 1 << 0, + VGT_REUSE_OFF = 0x00028ab4, + REUSE_OFF_bit = 1 << 0, + VGT_VTX_CNT_EN = 0x00028ab8, + VTX_CNT_EN_bit = 1 << 0, + VGT_STRMOUT_BUFFER_SIZE_0 = 0x00028ad0, + VGT_STRMOUT_VTX_STRIDE_0 = 0x00028ad4, + VGT_STRMOUT_VTX_STRIDE_0__STRIDE_mask = 0x3ff << 0, + VGT_STRMOUT_VTX_STRIDE_0__STRIDE_shift = 0, + VGT_STRMOUT_BUFFER_BASE_0 = 0x00028ad8, + VGT_STRMOUT_BUFFER_OFFSET_0 = 0x00028adc, + VGT_STRMOUT_BUFFER_SIZE_1 = 0x00028ae0, + VGT_STRMOUT_VTX_STRIDE_1 = 0x00028ae4, + VGT_STRMOUT_VTX_STRIDE_1__STRIDE_mask = 0x3ff << 0, + VGT_STRMOUT_VTX_STRIDE_1__STRIDE_shift = 0, + VGT_STRMOUT_BUFFER_BASE_1 = 0x00028ae8, + VGT_STRMOUT_BUFFER_OFFSET_1 = 0x00028aec, + VGT_STRMOUT_BUFFER_SIZE_2 = 0x00028af0, + VGT_STRMOUT_VTX_STRIDE_2 = 0x00028af4, + VGT_STRMOUT_VTX_STRIDE_2__STRIDE_mask = 0x3ff << 0, + VGT_STRMOUT_VTX_STRIDE_2__STRIDE_shift = 0, + VGT_STRMOUT_BUFFER_BASE_2 = 0x00028af8, + VGT_STRMOUT_BUFFER_OFFSET_2 = 0x00028afc, + VGT_STRMOUT_BUFFER_SIZE_3 = 0x00028b00, + VGT_STRMOUT_VTX_STRIDE_3 = 0x00028b04, + VGT_STRMOUT_VTX_STRIDE_3__STRIDE_mask = 0x3ff << 0, + VGT_STRMOUT_VTX_STRIDE_3__STRIDE_shift = 0, + VGT_STRMOUT_BUFFER_BASE_3 = 0x00028b08, + VGT_STRMOUT_BUFFER_OFFSET_3 = 0x00028b0c, + VGT_STRMOUT_BASE_OFFSET_0 = 0x00028b10, + VGT_STRMOUT_BASE_OFFSET_1 = 0x00028b14, + VGT_STRMOUT_BASE_OFFSET_2 = 0x00028b18, + VGT_STRMOUT_BASE_OFFSET_3 = 0x00028b1c, + VGT_STRMOUT_BUFFER_EN = 0x00028b20, + BUFFER_0_EN_bit = 1 << 0, + BUFFER_1_EN_bit = 1 << 1, + BUFFER_2_EN_bit = 1 << 2, + BUFFER_3_EN_bit = 1 << 3, + VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x00028b28, + VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x00028b2c, + VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x00028b30, + VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x00028b44, + VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_mask = 0x3f << 0, + VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_shift = 0, + VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x00028b48, + VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_mask = 0x3f << 0, + VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_shift = 0, + VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x00028b4c, + VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_mask = 0x3f << 0, + VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_shift = 0, + VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x00028b50, + VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_mask = 0x3f << 0, + VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_shift = 0, + PA_SC_LINE_CNTL = 0x00028c00, + BRES_CNTL_mask = 0xff << 0, + BRES_CNTL_shift = 0, + USE_BRES_CNTL_bit = 1 << 8, + EXPAND_LINE_WIDTH_bit = 1 << 9, + LAST_PIXEL_bit = 1 << 10, + PA_SC_AA_CONFIG = 0x00028c04, + MSAA_NUM_SAMPLES_mask = 0x03 << 0, + MSAA_NUM_SAMPLES_shift = 0, + AA_MASK_CENTROID_DTMN_bit = 1 << 4, + MAX_SAMPLE_DIST_mask = 0x0f << 13, + MAX_SAMPLE_DIST_shift = 13, + PA_SU_VTX_CNTL = 0x00028c08, + PIX_CENTER_bit = 1 << 0, + PA_SU_VTX_CNTL__ROUND_MODE_mask = 0x03 << 1, + PA_SU_VTX_CNTL__ROUND_MODE_shift = 1, + X_TRUNCATE = 0x00, + X_ROUND = 0x01, + X_ROUND_TO_EVEN = 0x02, + X_ROUND_TO_ODD = 0x03, + QUANT_MODE_mask = 0x07 << 3, + QUANT_MODE_shift = 3, + X_1_16TH = 0x00, + X_1_8TH = 0x01, + X_1_4TH = 0x02, + X_1_2 = 0x03, + X_1 = 0x04, + X_1_256TH = 0x05, + PA_CL_GB_VERT_CLIP_ADJ = 0x00028c0c, + PA_CL_GB_VERT_DISC_ADJ = 0x00028c10, + PA_CL_GB_HORZ_CLIP_ADJ = 0x00028c14, + PA_CL_GB_HORZ_DISC_ADJ = 0x00028c18, + PA_SC_AA_SAMPLE_LOCS_MCTX = 0x00028c1c, +/* S0_X_mask = 0x0f << 0, */ +/* S0_X_shift = 0, */ +/* S0_Y_mask = 0x0f << 4, */ +/* S0_Y_shift = 4, */ +/* S1_X_mask = 0x0f << 8, */ +/* S1_X_shift = 8, */ +/* S1_Y_mask = 0x0f << 12, */ +/* S1_Y_shift = 12, */ +/* S2_X_mask = 0x0f << 16, */ +/* S2_X_shift = 16, */ +/* S2_Y_mask = 0x0f << 20, */ +/* S2_Y_shift = 20, */ +/* S3_X_mask = 0x0f << 24, */ +/* S3_X_shift = 24, */ +/* S3_Y_mask = 0x0f << 28, */ +/* S3_Y_shift = 28, */ + PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX = 0x00028c20, +/* S4_X_mask = 0x0f << 0, */ +/* S4_X_shift = 0, */ +/* S4_Y_mask = 0x0f << 4, */ +/* S4_Y_shift = 4, */ +/* S5_X_mask = 0x0f << 8, */ +/* S5_X_shift = 8, */ +/* S5_Y_mask = 0x0f << 12, */ +/* S5_Y_shift = 12, */ +/* S6_X_mask = 0x0f << 16, */ +/* S6_X_shift = 16, */ +/* S6_Y_mask = 0x0f << 20, */ +/* S6_Y_shift = 20, */ +/* S7_X_mask = 0x0f << 24, */ +/* S7_X_shift = 24, */ +/* S7_Y_mask = 0x0f << 28, */ +/* S7_Y_shift = 28, */ + CB_CLRCMP_CONTROL = 0x00028c30, + CLRCMP_FCN_SRC_mask = 0x07 << 0, + CLRCMP_FCN_SRC_shift = 0, + CLRCMP_DRAW_ALWAYS = 0x00, + CLRCMP_DRAW_NEVER = 0x01, + CLRCMP_DRAW_ON_NEQ = 0x04, + CLRCMP_DRAW_ON_EQ = 0x05, + CLRCMP_FCN_DST_mask = 0x07 << 8, + CLRCMP_FCN_DST_shift = 8, +/* CLRCMP_DRAW_ALWAYS = 0x00, */ +/* CLRCMP_DRAW_NEVER = 0x01, */ +/* CLRCMP_DRAW_ON_NEQ = 0x04, */ +/* CLRCMP_DRAW_ON_EQ = 0x05, */ + CLRCMP_FCN_SEL_mask = 0x03 << 24, + CLRCMP_FCN_SEL_shift = 24, + CLRCMP_SEL_DST = 0x00, + CLRCMP_SEL_SRC = 0x01, + CLRCMP_SEL_AND = 0x02, + CB_CLRCMP_SRC = 0x00028c34, + CB_CLRCMP_DST = 0x00028c38, + CB_CLRCMP_MSK = 0x00028c3c, + PA_SC_AA_MASK = 0x00028c48, + VGT_VERTEX_REUSE_BLOCK_CNTL = 0x00028c58, + VTX_REUSE_DEPTH_mask = 0xff << 0, + VTX_REUSE_DEPTH_shift = 0, + VGT_OUT_DEALLOC_CNTL = 0x00028c5c, + DEALLOC_DIST_mask = 0x7f << 0, + DEALLOC_DIST_shift = 0, + DB_RENDER_CONTROL = 0x00028d0c, + DEPTH_CLEAR_ENABLE_bit = 1 << 0, + STENCIL_CLEAR_ENABLE_bit = 1 << 1, + DEPTH_COPY_bit = 1 << 2, + STENCIL_COPY_bit = 1 << 3, + RESUMMARIZE_ENABLE_bit = 1 << 4, + STENCIL_COMPRESS_DISABLE_bit = 1 << 5, + DEPTH_COMPRESS_DISABLE_bit = 1 << 6, + COPY_CENTROID_bit = 1 << 7, + COPY_SAMPLE_mask = 0x07 << 8, + COPY_SAMPLE_shift = 8, + ZPASS_INCREMENT_DISABLE_bit = 1 << 11, + DB_RENDER_OVERRIDE = 0x00028d10, + FORCE_HIZ_ENABLE_mask = 0x03 << 0, + FORCE_HIZ_ENABLE_shift = 0, + FORCE_OFF = 0x00, + FORCE_ENABLE = 0x01, + FORCE_DISABLE = 0x02, + FORCE_RESERVED = 0x03, + FORCE_HIS_ENABLE0_mask = 0x03 << 2, + FORCE_HIS_ENABLE0_shift = 2, +/* FORCE_OFF = 0x00, */ +/* FORCE_ENABLE = 0x01, */ +/* FORCE_DISABLE = 0x02, */ +/* FORCE_RESERVED = 0x03, */ + FORCE_HIS_ENABLE1_mask = 0x03 << 4, + FORCE_HIS_ENABLE1_shift = 4, +/* FORCE_OFF = 0x00, */ +/* FORCE_ENABLE = 0x01, */ +/* FORCE_DISABLE = 0x02, */ +/* FORCE_RESERVED = 0x03, */ + FORCE_SHADER_Z_ORDER_bit = 1 << 6, + FAST_Z_DISABLE_bit = 1 << 7, + FAST_STENCIL_DISABLE_bit = 1 << 8, + NOOP_CULL_DISABLE_bit = 1 << 9, + FORCE_COLOR_KILL_bit = 1 << 10, + FORCE_Z_READ_bit = 1 << 11, + FORCE_STENCIL_READ_bit = 1 << 12, + FORCE_FULL_Z_RANGE_mask = 0x03 << 13, + FORCE_FULL_Z_RANGE_shift = 13, +/* FORCE_OFF = 0x00, */ +/* FORCE_ENABLE = 0x01, */ +/* FORCE_DISABLE = 0x02, */ +/* FORCE_RESERVED = 0x03, */ + FORCE_QC_SMASK_CONFLICT_bit = 1 << 15, + DISABLE_VIEWPORT_CLAMP_bit = 1 << 16, + IGNORE_SC_ZRANGE_bit = 1 << 17, + DB_HTILE_SURFACE = 0x00028d24, + HTILE_WIDTH_bit = 1 << 0, + HTILE_HEIGHT_bit = 1 << 1, + LINEAR_bit = 1 << 2, + FULL_CACHE_bit = 1 << 3, + HTILE_USES_PRELOAD_WIN_bit = 1 << 4, + PRELOAD_bit = 1 << 5, + PREFETCH_WIDTH_mask = 0x3f << 6, + PREFETCH_WIDTH_shift = 6, + PREFETCH_HEIGHT_mask = 0x3f << 12, + PREFETCH_HEIGHT_shift = 12, + DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, + COMPAREFUNC1_mask = 0x07 << 0, + COMPAREFUNC1_shift = 0, +/* REF_NEVER = 0x00, */ +/* REF_LESS = 0x01, */ +/* REF_EQUAL = 0x02, */ +/* REF_LEQUAL = 0x03, */ +/* REF_GREATER = 0x04, */ +/* REF_NOTEQUAL = 0x05, */ +/* REF_GEQUAL = 0x06, */ +/* REF_ALWAYS = 0x07, */ + COMPAREVALUE1_mask = 0xff << 4, + COMPAREVALUE1_shift = 4, + COMPAREMASK1_mask = 0xff << 12, + COMPAREMASK1_shift = 12, + ENABLE1_bit = 1 << 24, + DB_PRELOAD_CONTROL = 0x00028d30, + START_X_mask = 0xff << 0, + START_X_shift = 0, + START_Y_mask = 0xff << 8, + START_Y_shift = 8, + MAX_X_mask = 0xff << 16, + MAX_X_shift = 16, + MAX_Y_mask = 0xff << 24, + MAX_Y_shift = 24, + DB_PREFETCH_LIMIT = 0x00028d34, + DEPTH_HEIGHT_TILE_MAX_mask = 0x3ff << 0, + DEPTH_HEIGHT_TILE_MAX_shift = 0, + PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x00028df8, + POLY_OFFSET_NEG_NUM_DB_BITS_mask = 0xff << 0, + POLY_OFFSET_NEG_NUM_DB_BITS_shift = 0, + POLY_OFFSET_DB_IS_FLOAT_FMT_bit = 1 << 8, + PA_SU_POLY_OFFSET_CLAMP = 0x00028dfc, + PA_SU_POLY_OFFSET_FRONT_SCALE = 0x00028e00, + PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x00028e04, + PA_SU_POLY_OFFSET_BACK_SCALE = 0x00028e08, + PA_SU_POLY_OFFSET_BACK_OFFSET = 0x00028e0c, + PA_CL_POINT_X_RAD = 0x00028e10, + PA_CL_POINT_Y_RAD = 0x00028e14, + PA_CL_POINT_SIZE = 0x00028e18, + PA_CL_POINT_CULL_RAD = 0x00028e1c, + PA_CL_UCP_0_X = 0x00028e20, + PA_CL_UCP_0_X_num = 6, + PA_CL_UCP_0_X_offset = 16, + PA_CL_UCP_0_Y = 0x00028e24, + PA_CL_UCP_0_Y_num = 6, + PA_CL_UCP_0_Y_offset = 16, + PA_CL_UCP_0_Z = 0x00028e28, + PA_CL_UCP_0_Z_num = 6, + PA_CL_UCP_0_Z_offset = 16, + SQ_ALU_CONSTANT0_0 = 0x00030000, + SQ_ALU_CONSTANT1_0 = 0x00030004, + SQ_ALU_CONSTANT2_0 = 0x00030008, + SQ_ALU_CONSTANT3_0 = 0x0003000c, + SQ_VTX_CONSTANT_WORD0_0 = 0x00038000, + SQ_TEX_RESOURCE_WORD0_0 = 0x00038000, + DIM_mask = 0x07 << 0, + DIM_shift = 0, + SQ_TEX_DIM_1D = 0x00, + SQ_TEX_DIM_2D = 0x01, + SQ_TEX_DIM_3D = 0x02, + SQ_TEX_DIM_CUBEMAP = 0x03, + SQ_TEX_DIM_1D_ARRAY = 0x04, + SQ_TEX_DIM_2D_ARRAY = 0x05, + SQ_TEX_DIM_2D_MSAA = 0x06, + SQ_TEX_DIM_2D_ARRAY_MSAA = 0x07, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask = 0x0f << 3, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift = 3, + TILE_TYPE_bit = 1 << 7, + PITCH_mask = 0x7ff << 8, + PITCH_shift = 8, + TEX_WIDTH_mask = 0x1fff << 19, + TEX_WIDTH_shift = 19, + SQ_VTX_CONSTANT_WORD1_0 = 0x00038004, + SQ_TEX_RESOURCE_WORD1_0 = 0x00038004, + TEX_HEIGHT_mask = 0x1fff << 0, + TEX_HEIGHT_shift = 0, + TEX_DEPTH_mask = 0x1fff << 13, + TEX_DEPTH_shift = 13, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask = 0x3f << 26, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift = 26, + SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, + BASE_ADDRESS_HI_mask = 0xff << 0, + BASE_ADDRESS_HI_shift = 0, + SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask = 0x7ff << 8, + SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift = 8, + SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit = 1 << 19, + SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, + SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift = 20, + SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask = 0x03 << 26, + SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift = 26, +/* SQ_NUM_FORMAT_NORM = 0x00, */ +/* SQ_NUM_FORMAT_INT = 0x01, */ +/* SQ_NUM_FORMAT_SCALED = 0x02, */ + SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit = 1 << 28, + SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit = 1 << 29, + SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask = 0x03 << 30, + SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift = 30, +/* SQ_ENDIAN_NONE = 0x00, */ +/* SQ_ENDIAN_8IN16 = 0x01, */ +/* SQ_ENDIAN_8IN32 = 0x02, */ + SQ_TEX_RESOURCE_WORD2_0 = 0x00038008, + SQ_VTX_CONSTANT_WORD3_0 = 0x0003800c, + MEM_REQUEST_SIZE_mask = 0x03 << 0, + MEM_REQUEST_SIZE_shift = 0, + SQ_TEX_RESOURCE_WORD3_0 = 0x0003800c, + SQ_TEX_RESOURCE_WORD4_0 = 0x00038010, + FORMAT_COMP_X_mask = 0x03 << 0, + FORMAT_COMP_X_shift = 0, + SQ_FORMAT_COMP_UNSIGNED = 0x00, + SQ_FORMAT_COMP_SIGNED = 0x01, + SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, + FORMAT_COMP_Y_mask = 0x03 << 2, + FORMAT_COMP_Y_shift = 2, +/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ +/* SQ_FORMAT_COMP_SIGNED = 0x01, */ +/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ + FORMAT_COMP_Z_mask = 0x03 << 4, + FORMAT_COMP_Z_shift = 4, +/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ +/* SQ_FORMAT_COMP_SIGNED = 0x01, */ +/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ + FORMAT_COMP_W_mask = 0x03 << 6, + FORMAT_COMP_W_shift = 6, +/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ +/* SQ_FORMAT_COMP_SIGNED = 0x01, */ +/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ + SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask = 0x03 << 8, + SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift = 8, +/* SQ_NUM_FORMAT_NORM = 0x00, */ +/* SQ_NUM_FORMAT_INT = 0x01, */ +/* SQ_NUM_FORMAT_SCALED = 0x02, */ + SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit = 1 << 10, + SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit = 1 << 11, + SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask = 0x03 << 12, + SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift = 12, +/* SQ_ENDIAN_NONE = 0x00, */ +/* SQ_ENDIAN_8IN16 = 0x01, */ +/* SQ_ENDIAN_8IN32 = 0x02, */ + REQUEST_SIZE_mask = 0x03 << 14, + REQUEST_SIZE_shift = 14, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask = 0x07 << 16, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift = 16, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask = 0x07 << 19, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift = 19, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask = 0x07 << 22, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift = 22, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask = 0x07 << 25, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift = 25, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + BASE_LEVEL_mask = 0x0f << 28, + BASE_LEVEL_shift = 28, + SQ_TEX_RESOURCE_WORD5_0 = 0x00038014, + LAST_LEVEL_mask = 0x0f << 0, + LAST_LEVEL_shift = 0, + BASE_ARRAY_mask = 0x1fff << 4, + BASE_ARRAY_shift = 4, + LAST_ARRAY_mask = 0x1fff << 17, + LAST_ARRAY_shift = 17, + SQ_TEX_RESOURCE_WORD6_0 = 0x00038018, + MPEG_CLAMP_mask = 0x03 << 0, + MPEG_CLAMP_shift = 0, + SQ_TEX_MPEG_CLAMP_OFF = 0x00, + SQ_TEX_MPEG_9 = 0x01, + SQ_TEX_MPEG_10 = 0x02, + PERF_MODULATION_mask = 0x07 << 5, + PERF_MODULATION_shift = 5, + INTERLACED_bit = 1 << 8, + SQ_TEX_RESOURCE_WORD6_0__TYPE_mask = 0x03 << 30, + SQ_TEX_RESOURCE_WORD6_0__TYPE_shift = 30, + SQ_TEX_VTX_INVALID_TEXTURE = 0x00, + SQ_TEX_VTX_INVALID_BUFFER = 0x01, + SQ_TEX_VTX_VALID_TEXTURE = 0x02, + SQ_TEX_VTX_VALID_BUFFER = 0x03, + SQ_VTX_CONSTANT_WORD6_0 = 0x00038018, + SQ_VTX_CONSTANT_WORD6_0__TYPE_mask = 0x03 << 30, + SQ_VTX_CONSTANT_WORD6_0__TYPE_shift = 30, +/* SQ_TEX_VTX_INVALID_TEXTURE = 0x00, */ +/* SQ_TEX_VTX_INVALID_BUFFER = 0x01, */ +/* SQ_TEX_VTX_VALID_TEXTURE = 0x02, */ +/* SQ_TEX_VTX_VALID_BUFFER = 0x03, */ + SQ_TEX_SAMPLER_WORD0_0 = 0x0003c000, + SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask = 0x07 << 0, + SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift = 0, + SQ_TEX_WRAP = 0x00, + SQ_TEX_MIRROR = 0x01, + SQ_TEX_CLAMP_LAST_TEXEL = 0x02, + SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, + SQ_TEX_CLAMP_HALF_BORDER = 0x04, + SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, + SQ_TEX_CLAMP_BORDER = 0x06, + SQ_TEX_MIRROR_ONCE_BORDER = 0x07, + CLAMP_Y_mask = 0x07 << 3, + CLAMP_Y_shift = 3, +/* SQ_TEX_WRAP = 0x00, */ +/* SQ_TEX_MIRROR = 0x01, */ +/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ +/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ +/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ +/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ +/* SQ_TEX_CLAMP_BORDER = 0x06, */ +/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ + CLAMP_Z_mask = 0x07 << 6, + CLAMP_Z_shift = 6, +/* SQ_TEX_WRAP = 0x00, */ +/* SQ_TEX_MIRROR = 0x01, */ +/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ +/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ +/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ +/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ +/* SQ_TEX_CLAMP_BORDER = 0x06, */ +/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ + XY_MAG_FILTER_mask = 0x07 << 9, + XY_MAG_FILTER_shift = 9, + SQ_TEX_XY_FILTER_POINT = 0x00, + SQ_TEX_XY_FILTER_BILINEAR = 0x01, + SQ_TEX_XY_FILTER_BICUBIC = 0x02, + XY_MIN_FILTER_mask = 0x07 << 12, + XY_MIN_FILTER_shift = 12, +/* SQ_TEX_XY_FILTER_POINT = 0x00, */ +/* SQ_TEX_XY_FILTER_BILINEAR = 0x01, */ +/* SQ_TEX_XY_FILTER_BICUBIC = 0x02, */ + Z_FILTER_mask = 0x03 << 15, + Z_FILTER_shift = 15, + SQ_TEX_Z_FILTER_NONE = 0x00, + SQ_TEX_Z_FILTER_POINT = 0x01, + SQ_TEX_Z_FILTER_LINEAR = 0x02, + MIP_FILTER_mask = 0x03 << 17, + MIP_FILTER_shift = 17, +/* SQ_TEX_Z_FILTER_NONE = 0x00, */ +/* SQ_TEX_Z_FILTER_POINT = 0x01, */ +/* SQ_TEX_Z_FILTER_LINEAR = 0x02, */ + BORDER_COLOR_TYPE_mask = 0x03 << 22, + BORDER_COLOR_TYPE_shift = 22, + SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00, + SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x01, + SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x02, + SQ_TEX_BORDER_COLOR_REGISTER = 0x03, + POINT_SAMPLING_CLAMP_bit = 1 << 24, + TEX_ARRAY_OVERRIDE_bit = 1 << 25, + DEPTH_COMPARE_FUNCTION_mask = 0x07 << 26, + DEPTH_COMPARE_FUNCTION_shift = 26, + SQ_TEX_DEPTH_COMPARE_NEVER = 0x00, + SQ_TEX_DEPTH_COMPARE_LESS = 0x01, + SQ_TEX_DEPTH_COMPARE_EQUAL = 0x02, + SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x03, + SQ_TEX_DEPTH_COMPARE_GREATER = 0x04, + SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x05, + SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x06, + SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x07, + CHROMA_KEY_mask = 0x03 << 29, + CHROMA_KEY_shift = 29, + SQ_TEX_CHROMA_KEY_DISABLED = 0x00, + SQ_TEX_CHROMA_KEY_KILL = 0x01, + SQ_TEX_CHROMA_KEY_BLEND = 0x02, + LOD_USES_MINOR_AXIS_bit = 1 << 31, + SQ_TEX_SAMPLER_WORD1_0 = 0x0003c004, + MIN_LOD_mask = 0x3ff << 0, + MIN_LOD_shift = 0, + MAX_LOD_mask = 0x3ff << 10, + MAX_LOD_shift = 10, + SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_mask = 0xfff << 20, + SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift = 20, + SQ_TEX_SAMPLER_WORD2_0 = 0x0003c008, + LOD_BIAS_SEC_mask = 0xfff << 0, + LOD_BIAS_SEC_shift = 0, + MC_COORD_TRUNCATE_bit = 1 << 12, + SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 13, + HIGH_PRECISION_FILTER_bit = 1 << 14, + PERF_MIP_mask = 0x07 << 15, + PERF_MIP_shift = 15, + PERF_Z_mask = 0x03 << 18, + PERF_Z_shift = 18, + FETCH_4_bit = 1 << 26, + SAMPLE_IS_PCF_bit = 1 << 27, + SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31, + SQ_VTX_BASE_VTX_LOC = 0x0003cff0, + SQ_VTX_START_INST_LOC = 0x0003cff4, + SQ_LOOP_CONST_DX10_0 = 0x0003e200, + SQ_LOOP_CONST_0 = 0x0003e200, + SQ_LOOP_CONST_0__COUNT_mask = 0xfff << 0, + SQ_LOOP_CONST_0__COUNT_shift = 0, + INIT_mask = 0xfff << 12, + INIT_shift = 12, + INC_mask = 0xff << 24, + INC_shift = 24, + SQ_BOOL_CONST_0 = 0x0003e380, + SQ_BOOL_CONST_0_num = 3, + +} ; + +#endif /* _AUTOREGS */ + diff --git a/driver/xf86-video-radeonhd/src/r600_reg_r6xx.h b/driver/xf86-video-radeonhd/src/r600_reg_r6xx.h new file mode 100644 index 000000000..425bee4b1 --- /dev/null +++ b/driver/xf86-video-radeonhd/src/r600_reg_r6xx.h @@ -0,0 +1,504 @@ +/* + * RadeonHD R6xx, R7xx Register documentation + * + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2009 Matthias Hopf + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _R600_REG_R6xx_H_ +#define _R600_REG_R6xx_H_ + +/* + * Registers for R6xx chips that are not documented yet + */ + +enum { + + MM_INDEX = 0x0000, + MM_DATA = 0x0004, + + /*SRBM_STATUS = 0x0e50, */ + RLC_RQ_PENDING_bit = 1 << 3, + RCU_RQ_PENDING_bit = 1 << 4, + GRBM_RQ_PENDING_bit = 1 << 5, + HI_RQ_PENDING_bit = 1 << 6, + IO_EXTERN_SIGNAL_bit = 1 << 7, + VMC_BUSY_bit = 1 << 8, + MCB_BUSY_bit = 1 << 9, + MCDZ_BUSY_bit = 1 << 10, + MCDY_BUSY_bit = 1 << 11, + MCDX_BUSY_bit = 1 << 12, + MCDW_BUSY_bit = 1 << 13, + SEM_BUSY_bit = 1 << 14, + SRBM_STATUS__RLC_BUSY_bit = 1 << 15, + PDMA_BUSY_bit = 1 << 16, + IH_BUSY_bit = 1 << 17, + CSC_BUSY_bit = 1 << 20, + CMC7_BUSY_bit = 1 << 21, + CMC6_BUSY_bit = 1 << 22, + CMC5_BUSY_bit = 1 << 23, + CMC4_BUSY_bit = 1 << 24, + CMC3_BUSY_bit = 1 << 25, + CMC2_BUSY_bit = 1 << 26, + CMC1_BUSY_bit = 1 << 27, + CMC0_BUSY_bit = 1 << 28, + BIF_BUSY_bit = 1 << 29, + IDCT_BUSY_bit = 1 << 30, + + SRBM_READ_ERROR = 0x0e98, + READ_ADDRESS_mask = 0xffff << 2, + READ_ADDRESS_shift = 2, + READ_REQUESTER_HI_bit = 1 << 24, + READ_REQUESTER_GRBM_bit = 1 << 25, + READ_REQUESTER_RCU_bit = 1 << 26, + READ_REQUESTER_RLC_bit = 1 << 27, + READ_ERROR_bit = 1 << 31, + + SRBM_INT_STATUS = 0x0ea4, + RDERR_INT_STAT_bit = 1 << 0, + GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1, + SRBM_INT_ACK = 0x0ea8, + RDERR_INT_ACK_bit = 1 << 0, + GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1, + + /* R6XX_MC_VM_FB_LOCATION = 0x2180, */ + + VENDOR_DEVICE_ID = 0x4000, + + HDP_MEM_COHERENCY_FLUSH_CNTL = 0x5480, + + /* D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, */ + /* D1GRPH_PITCH = 0x6120, */ + /* D1GRPH_Y_END = 0x6138, */ + + GRBM_STATUS = 0x8010, + R600_CMDFIFO_AVAIL_mask = 0x1f << 0, + R700_CMDFIFO_AVAIL_mask = 0xf << 0, + CMDFIFO_AVAIL_shift = 0, + SRBM_RQ_PENDING_bit = 1 << 5, + CP_RQ_PENDING_bit = 1 << 6, + CF_RQ_PENDING_bit = 1 << 7, + PF_RQ_PENDING_bit = 1 << 8, + GRBM_EE_BUSY_bit = 1 << 10, + GRBM_STATUS__VC_BUSY_bit = 1 << 11, + DB03_CLEAN_bit = 1 << 12, + CB03_CLEAN_bit = 1 << 13, + VGT_BUSY_NO_DMA_bit = 1 << 16, + GRBM_STATUS__VGT_BUSY_bit = 1 << 17, + TA03_BUSY_bit = 1 << 18, + GRBM_STATUS__TC_BUSY_bit = 1 << 19, + SX_BUSY_bit = 1 << 20, + SH_BUSY_bit = 1 << 21, + SPI03_BUSY_bit = 1 << 22, + SMX_BUSY_bit = 1 << 23, + SC_BUSY_bit = 1 << 24, + PA_BUSY_bit = 1 << 25, + DB03_BUSY_bit = 1 << 26, + CR_BUSY_bit = 1 << 27, + CP_COHERENCY_BUSY_bit = 1 << 28, + GRBM_STATUS__CP_BUSY_bit = 1 << 29, + CB03_BUSY_bit = 1 << 30, + GUI_ACTIVE_bit = 1 << 31, + GRBM_STATUS2 = 0x8014, + CR_CLEAN_bit = 1 << 0, + SMX_CLEAN_bit = 1 << 1, + SPI0_BUSY_bit = 1 << 8, + SPI1_BUSY_bit = 1 << 9, + SPI2_BUSY_bit = 1 << 10, + SPI3_BUSY_bit = 1 << 11, + TA0_BUSY_bit = 1 << 12, + TA1_BUSY_bit = 1 << 13, + TA2_BUSY_bit = 1 << 14, + TA3_BUSY_bit = 1 << 15, + DB0_BUSY_bit = 1 << 16, + DB1_BUSY_bit = 1 << 17, + DB2_BUSY_bit = 1 << 18, + DB3_BUSY_bit = 1 << 19, + CB0_BUSY_bit = 1 << 20, + CB1_BUSY_bit = 1 << 21, + CB2_BUSY_bit = 1 << 22, + CB3_BUSY_bit = 1 << 23, + GRBM_SOFT_RESET = 0x8020, + SOFT_RESET_CP_bit = 1 << 0, + SOFT_RESET_CB_bit = 1 << 1, + SOFT_RESET_CR_bit = 1 << 2, + SOFT_RESET_DB_bit = 1 << 3, + SOFT_RESET_PA_bit = 1 << 5, + SOFT_RESET_SC_bit = 1 << 6, + SOFT_RESET_SMX_bit = 1 << 7, + SOFT_RESET_SPI_bit = 1 << 8, + SOFT_RESET_SH_bit = 1 << 9, + SOFT_RESET_SX_bit = 1 << 10, + SOFT_RESET_TC_bit = 1 << 11, + SOFT_RESET_TA_bit = 1 << 12, + SOFT_RESET_VC_bit = 1 << 13, + SOFT_RESET_VGT_bit = 1 << 14, + SOFT_RESET_GRBM_GCA_bit = 1 << 15, + + WAIT_UNTIL = 0x8040, + WAIT_CP_DMA_IDLE_bit = 1 << 8, + WAIT_CMDFIFO_bit = 1 << 10, + WAIT_2D_IDLE_bit = 1 << 14, + WAIT_3D_IDLE_bit = 1 << 15, + WAIT_2D_IDLECLEAN_bit = 1 << 16, + WAIT_3D_IDLECLEAN_bit = 1 << 17, + WAIT_EXTERN_SIG_bit = 1 << 19, + CMDFIFO_ENTRIES_mask = 0x1f << 20, + CMDFIFO_ENTRIES_shift = 20, + + GRBM_READ_ERROR = 0x8058, +/* READ_ADDRESS_mask = 0xffff << 2, */ +/* READ_ADDRESS_shift = 2, */ + READ_REQUESTER_SRBM_bit = 1 << 28, + READ_REQUESTER_CP_bit = 1 << 29, + READ_REQUESTER_WU_POLL_bit = 1 << 30, +/* READ_ERROR_bit = 1 << 31, */ + + SCRATCH_REG0 = 0x8500, + SCRATCH_REG1 = 0x8504, + SCRATCH_REG2 = 0x8508, + SCRATCH_REG3 = 0x850c, + SCRATCH_REG4 = 0x8510, + SCRATCH_REG5 = 0x8514, + SCRATCH_REG6 = 0x8518, + SCRATCH_REG7 = 0x851c, + SCRATCH_UMSK = 0x8540, + SCRATCH_ADDR = 0x8544, + + CP_COHER_CNTL = 0x85f0, + DEST_BASE_0_ENA_bit = 1 << 0, + DEST_BASE_1_ENA_bit = 1 << 1, + SO0_DEST_BASE_ENA_bit = 1 << 2, + SO1_DEST_BASE_ENA_bit = 1 << 3, + SO2_DEST_BASE_ENA_bit = 1 << 4, + SO3_DEST_BASE_ENA_bit = 1 << 5, + CB0_DEST_BASE_ENA_bit = 1 << 6, + CB1_DEST_BASE_ENA_bit = 1 << 7, + CB2_DEST_BASE_ENA_bit = 1 << 8, + CB3_DEST_BASE_ENA_bit = 1 << 9, + CB4_DEST_BASE_ENA_bit = 1 << 10, + CB5_DEST_BASE_ENA_bit = 1 << 11, + CB6_DEST_BASE_ENA_bit = 1 << 12, + CB7_DEST_BASE_ENA_bit = 1 << 13, + DB_DEST_BASE_ENA_bit = 1 << 14, + CR_DEST_BASE_ENA_bit = 1 << 15, + TC_ACTION_ENA_bit = 1 << 23, + VC_ACTION_ENA_bit = 1 << 24, + CB_ACTION_ENA_bit = 1 << 25, + DB_ACTION_ENA_bit = 1 << 26, + SH_ACTION_ENA_bit = 1 << 27, + SMX_ACTION_ENA_bit = 1 << 28, + CR0_ACTION_ENA_bit = 1 << 29, + CR1_ACTION_ENA_bit = 1 << 30, + CR2_ACTION_ENA_bit = 1 << 31, + CP_COHER_SIZE = 0x85f4, + CP_COHER_BASE = 0x85f8, + CP_COHER_STATUS = 0x85fc, + MATCHING_GFX_CNTX_mask = 0xff << 0, + MATCHING_GFX_CNTX_shift = 0, + MATCHING_CR_CNTX_mask = 0xffff << 8, + MATCHING_CR_CNTX_shift = 8, + STATUS_bit = 1 << 31, + + CP_STALLED_STAT1 = 0x8674, + RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0, + RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1, + RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2, + RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3, + RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4, + RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5, + RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6, + RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7, + RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8, + RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9, + MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16, + MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17, + MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18, + RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24, + RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25, + RCIU_STALLED_ON_ME_READ_bit = 1 << 26, + RCIU_STALLED_ON_DMA_READ_bit = 1 << 27, + RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28, + CP_STALLED_STAT2 = 0x8678, + PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0, + PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1, + PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2, + PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3, + MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4, + ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8, + ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9, + CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10, + GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11, + ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12, + ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13, + ME_WAITING_DATA_FROM_PFP_bit = 1 << 14, + ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15, + RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16, + RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17, + EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18, + EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19, + EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20, + EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21, + SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22, + SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23, + PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24, + SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30, + SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31, + CP_BUSY_STAT = 0x867c, + REG_BUS_FIFO_BUSY_bit = 1 << 0, + RING_FETCHING_DATA_bit = 1 << 1, + INDR1_FETCHING_DATA_bit = 1 << 2, + INDR2_FETCHING_DATA_bit = 1 << 3, + STATE_FETCHING_DATA_bit = 1 << 4, + PRED_FETCHING_DATA_bit = 1 << 5, + COHER_CNTR_NEQ_ZERO_bit = 1 << 6, + PFP_PARSING_PACKETS_bit = 1 << 7, + ME_PARSING_PACKETS_bit = 1 << 8, + RCIU_PFP_BUSY_bit = 1 << 9, + RCIU_ME_BUSY_bit = 1 << 10, + OUTSTANDING_READ_TAGS_bit = 1 << 11, + SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12, + SEM_FAILED_AND_HOLDING_bit = 1 << 13, + SEM_POLLING_FOR_PASS_bit = 1 << 14, + _3D_BUSY_bit = 1 << 15, + _2D_BUSY_bit = 1 << 16, + CP_STAT = 0x8680, + CSF_RING_BUSY_bit = 1 << 0, + CSF_WPTR_POLL_BUSY_bit = 1 << 1, + CSF_INDIRECT1_BUSY_bit = 1 << 2, + CSF_INDIRECT2_BUSY_bit = 1 << 3, + CSF_STATE_BUSY_bit = 1 << 4, + CSF_PREDICATE_BUSY_bit = 1 << 5, + CSF_BUSY_bit = 1 << 6, + MIU_RDREQ_BUSY_bit = 1 << 7, + MIU_WRREQ_BUSY_bit = 1 << 8, + ROQ_RING_BUSY_bit = 1 << 9, + ROQ_INDIRECT1_BUSY_bit = 1 << 10, + ROQ_INDIRECT2_BUSY_bit = 1 << 11, + ROQ_STATE_BUSY_bit = 1 << 12, + ROQ_PREDICATE_BUSY_bit = 1 << 13, + ROQ_ALIGN_BUSY_bit = 1 << 14, + PFP_BUSY_bit = 1 << 15, + MEQ_BUSY_bit = 1 << 16, + ME_BUSY_bit = 1 << 17, + QUERY_BUSY_bit = 1 << 18, + SEMAPHORE_BUSY_bit = 1 << 19, + INTERRUPT_BUSY_bit = 1 << 20, + SURFACE_SYNC_BUSY_bit = 1 << 21, + DMA_BUSY_bit = 1 << 22, + RCIU_BUSY_bit = 1 << 23, + CP_STAT__CP_BUSY_bit = 1 << 31, + + CP_ME_CNTL = 0x86d8, + ME_STATMUX_mask = 0xff << 0, + ME_STATMUX_shift = 0, + ME_HALT_bit = 1 << 28, + CP_ME_STATUS = 0x86dc, + + CP_RB_RPTR = 0x8700, + RB_RPTR_mask = 0xfffff << 0, + RB_RPTR_shift = 0, + CP_RB_WPTR_DELAY = 0x8704, + PRE_WRITE_TIMER_mask = 0xfffffff << 0, + PRE_WRITE_TIMER_shift = 0, + PRE_WRITE_LIMIT_mask = 0x0f << 28, + PRE_WRITE_LIMIT_shift = 28, + + CP_ROQ_RB_STAT = 0x8780, + ROQ_RPTR_PRIMARY_mask = 0x3ff << 0, + ROQ_RPTR_PRIMARY_shift = 0, + ROQ_WPTR_PRIMARY_mask = 0x3ff << 16, + ROQ_WPTR_PRIMARY_shift = 16, + CP_ROQ_IB1_STAT = 0x8784, + ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0, + ROQ_RPTR_INDIRECT1_shift = 0, + ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16, + ROQ_WPTR_INDIRECT1_shift = 16, + CP_ROQ_IB2_STAT = 0x8788, + ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0, + ROQ_RPTR_INDIRECT2_shift = 0, + ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16, + ROQ_WPTR_INDIRECT2_shift = 16, + + CP_MEQ_STAT = 0x8794, + MEQ_RPTR_mask = 0x3ff << 0, + MEQ_RPTR_shift = 0, + MEQ_WPTR_mask = 0x3ff << 16, + MEQ_WPTR_shift = 16, + + CC_GC_SHADER_PIPE_CONFIG = 0x8950, + INACTIVE_QD_PIPES_mask = 0xff << 8, + INACTIVE_QD_PIPES_shift = 8, + R6XX_MAX_QD_PIPES = 8, + INACTIVE_SIMDS_mask = 0xff << 16, + INACTIVE_SIMDS_shift = 16, + R6XX_MAX_SIMDS = 8, + GC_USER_SHADER_PIPE_CONFIG = 0x8954, + + VC_ENHANCE = 0x9714, + DB_DEBUG = 0x9830, + PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31, + + DB_WATERMARKS = 0x00009838, + DEPTH_FREE_mask = 0x1f << 0, + DEPTH_FREE_shift = 0, + DEPTH_FLUSH_mask = 0x3f << 5, + DEPTH_FLUSH_shift = 5, + FORCE_SUMMARIZE_mask = 0x0f << 11, + FORCE_SUMMARIZE_shift = 11, + DEPTH_PENDING_FREE_mask = 0x1f << 15, + DEPTH_PENDING_FREE_shift = 15, + DEPTH_CACHELINE_FREE_mask = 0x1f << 20, + DEPTH_CACHELINE_FREE_shift = 20, + EARLY_Z_PANIC_DISABLE_bit = 1 << 25, + LATE_Z_PANIC_DISABLE_bit = 1 << 26, + RE_Z_PANIC_DISABLE_bit = 1 << 27, + DB_EXTRA_DEBUG_mask = 0x0f << 28, + DB_EXTRA_DEBUG_shift = 28, + + CP_RB_BASE = 0xc100, + CP_RB_CNTL = 0xc104, + RB_BUFSZ_mask = 0x3f << 0, + CP_RB_WPTR = 0xc114, + RB_WPTR_mask = 0xfffff << 0, + RB_WPTR_shift = 0, + CP_RB_RPTR_WR = 0xc108, + RB_RPTR_WR_mask = 0xfffff << 0, + RB_RPTR_WR_shift = 0, + + CP_INT_STATUS = 0xc128, + DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0, + ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1, + SEM_SIGNAL_INT_STAT_bit = 1 << 18, + CNTX_BUSY_INT_STAT_bit = 1 << 19, + CNTX_EMPTY_INT_STAT_bit = 1 << 20, + WAITMEM_SEM_INT_STAT_bit = 1 << 21, + PRIV_INSTR_INT_STAT_bit = 1 << 22, + PRIV_REG_INT_STAT_bit = 1 << 23, + OPCODE_ERROR_INT_STAT_bit = 1 << 24, + SCRATCH_INT_STAT_bit = 1 << 25, + TIME_STAMP_INT_STAT_bit = 1 << 26, + RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27, + DMA_INT_STAT_bit = 1 << 28, + IB2_INT_STAT_bit = 1 << 29, + IB1_INT_STAT_bit = 1 << 30, + RB_INT_STAT_bit = 1 << 31, + +// SX_ALPHA_TEST_CONTROL = 0x00028410, + ALPHA_FUNC__REF_NEVER = 0, + ALPHA_FUNC__REF_ALWAYS = 7, +// DB_SHADER_CONTROL = 0x0002880c, + Z_ORDER__EARLY_Z_THEN_LATE_Z = 2, +// PA_SU_SC_MODE_CNTL = 0x00028814, +// POLY_MODE_mask = 0x03 << 3, + POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE, +// POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, + POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES, + PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20, + DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */ +// DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, + DB_ALPHA_TO_MASK = 0x00028d44, + ALPHA_TO_MASK_ENABLE = 1 << 0, + ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, + ALPHA_TO_MASK_OFFSET0_shift = 8, + ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 8, + ALPHA_TO_MASK_OFFSET1_shift = 10, + ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 8, + ALPHA_TO_MASK_OFFSET2_shift = 12, + ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 8, + ALPHA_TO_MASK_OFFSET3_shift = 14, + +// SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, +// SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, + FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2, + FMT_16=5, FMT_16_FLOAT, FMT_8_8, + FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4, + FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16, + FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8, + FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10, + FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2, + FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16, + FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT, + FMT_1 = 37, FMT_GB_GR=39, + FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP, + FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32, + FMT_32_32_32_FLOAT=48, + +// High level register file lengths + SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */ + SQ_ALU_CONSTANT_ps_num = 256, + SQ_ALU_CONSTANT_vs_num = 256, + SQ_ALU_CONSTANT_all_num = 512, + SQ_ALU_CONSTANT_offset = 16, + SQ_ALU_CONSTANT_ps = 0, + SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num, + SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ + SQ_TEX_RESOURCE_ps_num = 160, + SQ_TEX_RESOURCE_vs_num = 160, + SQ_TEX_RESOURCE_fs_num = 16, + SQ_TEX_RESOURCE_gs_num = 160, + SQ_TEX_RESOURCE_all_num = 496, + SQ_TEX_RESOURCE_offset = 28, + SQ_TEX_RESOURCE_ps = 0, + SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num, + SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num, + SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num, + SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ + SQ_VTX_RESOURCE_ps_num = 160, + SQ_VTX_RESOURCE_vs_num = 160, + SQ_VTX_RESOURCE_fs_num = 16, + SQ_VTX_RESOURCE_gs_num = 160, + SQ_VTX_RESOURCE_all_num = 496, + SQ_VTX_RESOURCE_offset = 28, + SQ_VTX_RESOURCE_ps = 0, + SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num, + SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num, + SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num, + SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */ + SQ_TEX_SAMPLER_WORD_ps_num = 18, + SQ_TEX_SAMPLER_WORD_vs_num = 18, + SQ_TEX_SAMPLER_WORD_gs_num = 18, + SQ_TEX_SAMPLER_WORD_all_num = 54, + SQ_TEX_SAMPLER_WORD_offset = 12, + SQ_TEX_SAMPLER_WORD_ps = 0, + SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, + SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, + SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */ + SQ_LOOP_CONST_ps_num = 32, + SQ_LOOP_CONST_vs_num = 32, + SQ_LOOP_CONST_gs_num = 32, + SQ_LOOP_CONST_all_num = 96, + SQ_LOOP_CONST_offset = 4, + SQ_LOOP_CONST_ps = 0, + SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, + SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, + SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */ + SQ_BOOL_CONST_ps_num = 1, + SQ_BOOL_CONST_vs_num = 1, + SQ_BOOL_CONST_gs_num = 1, + SQ_BOOL_CONST_all_num = 3, + SQ_BOOL_CONST_offset = 4, + SQ_BOOL_CONST_ps = 0, + SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, + SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num, +}; + + +#endif diff --git a/driver/xf86-video-radeonhd/src/r600_reg_r7xx.h b/driver/xf86-video-radeonhd/src/r600_reg_r7xx.h new file mode 100644 index 000000000..f3e796281 --- /dev/null +++ b/driver/xf86-video-radeonhd/src/r600_reg_r7xx.h @@ -0,0 +1,149 @@ +/* + * RadeonHD R6xx, R7xx Register documentation + * + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2009 Matthias Hopf + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _R600_REG_R7xx_H_ +#define _R600_REG_R7xx_H_ + +/* + * Register update for R7xx chips + */ + +enum { + + /* R7XX_MC_VM_FB_LOCATION = 0x00002024, */ + +// GRBM_STATUS = 0x00008010, + R7XX_TA_BUSY_bit = 1 << 14, + + R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x00008d8c, + RING0_OFFSET_mask = 0xff << 0, + RING0_OFFSET_shift = 0, + ISOLATE_ES_ENABLE_bit = 1 << 12, + ISOLATE_GS_ENABLE_bit = 1 << 13, + VS_PC_LIMIT_ENABLE_bit = 1 << 14, + +// SQ_ALU_WORD0 = 0x00008dfc, +// SRC0_SEL_mask = 0x1ff << 0, +// SRC1_SEL_mask = 0x1ff << 13, + R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4, + R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5, + R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6, + R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7, +// INDEX_MODE_mask = 0x07 << 26, + R7xx_SQ_INDEX_GLOBAL = 0x05, + R7xx_SQ_INDEX_GLOBAL_AR_X = 0x06, + R6xx_SQ_ALU_WORD1_OP2 = 0x00008dfc, + R7xx_SQ_ALU_WORD1_OP2_V2 = 0x00008dfc, + R6xx_FOG_MERGE_bit = 1 << 5, + R6xx_OMOD_mask = 0x03 << 6, + R7xx_OMOD_mask = 0x03 << 5, + R6xx_OMOD_shift = 6, + R7xx_OMOD_shift = 5, + R6xx_SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8, + R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7, + R6xx_SQ_ALU_WORD1_OP2__ALU_INST_shift = 8, + R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7, + R7xx_SQ_OP2_INST_FREXP_64 = 0x07, + R7xx_SQ_OP2_INST_ADD_64 = 0x17, + R7xx_SQ_OP2_INST_MUL_64 = 0x1b, + R7xx_SQ_OP2_INST_FLT64_TO_FLT32 = 0x1c, + R7xx_SQ_OP2_INST_FLT32_TO_FLT64 = 0x1d, + R7xx_SQ_OP2_INST_LDEXP_64 = 0x7a, + R7xx_SQ_OP2_INST_FRACT_64 = 0x7b, + R7xx_SQ_OP2_INST_PRED_SETGT_64 = 0x7c, + R7xx_SQ_OP2_INST_PRED_SETE_64 = 0x7d, + R7xx_SQ_OP2_INST_PRED_SETGE_64 = 0x7e, +// SQ_ALU_WORD1_OP3 = 0x00008dfc, +// SRC2_SEL_mask = 0x1ff << 0, +// R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4, +// R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5, +// R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6, +// R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7, +// SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, + R7xx_SQ_OP3_INST_MULADD_64 = 0x08, + R7xx_SQ_OP3_INST_MULADD_64_M2 = 0x09, + R7xx_SQ_OP3_INST_MULADD_64_M4 = 0x0a, + R7xx_SQ_OP3_INST_MULADD_64_D2 = 0x0b, +// SQ_CF_ALU_WORD1 = 0x00008dfc, + R6xx_USES_WATERFALL_bit = 1 << 25, + R7xx_SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25, +// SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, +// ARRAY_BASE_mask = 0x1fff << 0, +// TYPE_mask = 0x03 << 13, +// SQ_EXPORT_PARAM = 0x02, +// X_UNUSED_FOR_SX_EXPORTS = 0x03, +// ELEM_SIZE_mask = 0x03 << 30, +// SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, +// SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23, + R7xx_SQ_CF_INST_MEM_EXPORT = 0x3a, +// SQ_CF_WORD1 = 0x00008dfc, +// SQ_CF_WORD1__COUNT_mask = 0x07 << 10, + R7xx_COUNT_3_bit = 1 << 19, +// SQ_CF_WORD1__CF_INST_mask = 0x7f << 23, + R7xx_SQ_CF_INST_END_PROGRAM = 0x19, + R7xx_SQ_CF_INST_WAIT_ACK = 0x1a, + R7xx_SQ_CF_INST_TEX_ACK = 0x1b, + R7xx_SQ_CF_INST_VTX_ACK = 0x1c, + R7xx_SQ_CF_INST_VTX_TC_ACK = 0x1d, +// SQ_VTX_WORD0 = 0x00008dfc, +// VTX_INST_mask = 0x1f << 0, + R7xx_SQ_VTX_INST_MEM = 0x02, +// SQ_VTX_WORD2 = 0x00008dfc, + R7xx_SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20, + +// SQ_TEX_WORD0 = 0x00008dfc, +// TEX_INST_mask = 0x1f << 0, + R7xx_X_MEMORY_READ = 0x02, + R7xx_SQ_TEX_INST_KEEP_GRADIENTS = 0x0a, + R7xx_X_FETCH4_LOAD4_INSTRUCTION_FOR_DX10_1 = 0x0f, + R7xx_SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24, + + R7xx_PA_SC_EDGERULE = 0x00028230, + R7xx_SPI_THREAD_GROUPING = 0x000286c8, + PS_GROUPING_mask = 0x1f << 0, + PS_GROUPING_shift = 0, + VS_GROUPING_mask = 0x1f << 8, + VS_GROUPING_shift = 8, + GS_GROUPING_mask = 0x1f << 16, + GS_GROUPING_shift = 16, + ES_GROUPING_mask = 0x1f << 24, + ES_GROUPING_shift = 24, + R7xx_CB_SHADER_CONTROL = 0x000287a0, + RT0_ENABLE_bit = 1 << 0, + RT1_ENABLE_bit = 1 << 1, + RT2_ENABLE_bit = 1 << 2, + RT3_ENABLE_bit = 1 << 3, + RT4_ENABLE_bit = 1 << 4, + RT5_ENABLE_bit = 1 << 5, + RT6_ENABLE_bit = 1 << 6, + RT7_ENABLE_bit = 1 << 7, +// DB_ALPHA_TO_MASK = 0x00028d44, + R7xx_OFFSET_ROUND_bit = 1 << 16, +// SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c, + R7xx_TRUNCATE_COORD_bit = 1 << 9, + R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10, + +} ; + +#endif /* _R600_REG_R7xx_H_ */ diff --git a/driver/xf86-video-radeonhd/src/r600_shader.c b/driver/xf86-video-radeonhd/src/r600_shader.c new file mode 100644 index 000000000..ab6e9b2fa --- /dev/null +++ b/driver/xf86-video-radeonhd/src/r600_shader.c @@ -0,0 +1,1848 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Author: Alex Deucher <alexander.deucher@amd.com> + * + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "xf86.h" + +#include "rhd.h" +#include "r600_shader.h" +#include "r600_reg.h" + +/* solid vs --------------------------------------- */ +int R600_solid_vs(enum RHD_CHIPSETS ChipSet, CARD32* shader) +{ + int i=0; + + /* 0 */ + shader[i++] = CF_DWORD0(ADDR(4)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(1), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_VTX), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 1 */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), + TYPE(SQ_EXPORT_POS), + RW_GPR(1), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(0)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(1), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 2 - always export a param whether it's used or not */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), + TYPE(SQ_EXPORT_PARAM), + RW_GPR(0), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(0)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(0), + END_OF_PROGRAM(1), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(0)); + /* 3 - padding */ + shader[i++] = 0x00000000; + shader[i++] = 0x00000000; + /* 4/5 */ + shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), + FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), + FETCH_WHOLE_QUAD(0), + BUFFER_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + SRC_SEL_X(SQ_SEL_X), + MEGA_FETCH_COUNT(8)); + shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), + DST_REL(0), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_0), + DST_SEL_W(SQ_SEL_1), + USE_CONST_FIELDS(0), + DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ + NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ + FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ + SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); + shader[i++] = VTX_DWORD2(OFFSET(0), + ENDIAN_SWAP(ENDIAN_NONE), + CONST_BUF_NO_STRIDE(0), + MEGA_FETCH(1)); + shader[i++] = VTX_DWORD_PAD; + + return i; +} + +/* solid ps --------------------------------------- */ +int R600_solid_ps(enum RHD_CHIPSETS ChipSet, CARD32* shader) +{ + int i=0; + + /* 0 */ + shader[i++] = CF_ALU_DWORD0(ADDR(2), + KCACHE_BANK0(0), + KCACHE_BANK1(0), + KCACHE_MODE0(SQ_CF_KCACHE_NOP)); + shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), + KCACHE_ADDR0(0), + KCACHE_ADDR1(0), + I_COUNT(4), + USES_WATERFALL(0), + CF_INST(SQ_CF_INST_ALU), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 1 */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), + TYPE(SQ_EXPORT_PIXEL), + RW_GPR(0), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(1)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(1), + END_OF_PROGRAM(1), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + + /* 2 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(256), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_X), + SRC0_NEG(0), + SRC1_SEL(0), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_X), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_AR_X), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_MOV), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_X), + CLAMP(1)); + /* 3 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(256), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Y), + SRC0_NEG(0), + SRC1_SEL(0), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Y), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_AR_X), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_MOV), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Y), + CLAMP(1)); + /* 4 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(256), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Z), + SRC0_NEG(0), + SRC1_SEL(0), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Z), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_AR_X), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_MOV), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Z), + CLAMP(1)); + /* 5 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(256), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_W), + SRC0_NEG(0), + SRC1_SEL(0), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_W), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_AR_X), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(1)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_MOV), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_W), + CLAMP(1)); + + return i; +} + +/* copy vs --------------------------------------- */ +int R600_copy_vs(enum RHD_CHIPSETS ChipSet, CARD32* shader) +{ + int i=0; + + /* 0 */ + shader[i++] = CF_DWORD0(ADDR(4)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(2), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_VTX), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 1 */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), + TYPE(SQ_EXPORT_POS), + RW_GPR(1), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(0)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 2 */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), + TYPE(SQ_EXPORT_PARAM), + RW_GPR(0), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(0)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(0), + END_OF_PROGRAM(1), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(0)); + /* 3 */ + shader[i++] = 0x00000000; + shader[i++] = 0x00000000; + /* 4/5 */ + shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), + FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), + FETCH_WHOLE_QUAD(0), + BUFFER_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + SRC_SEL_X(SQ_SEL_X), + MEGA_FETCH_COUNT(16)); + shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), + DST_REL(0), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_0), + DST_SEL_W(SQ_SEL_1), + USE_CONST_FIELDS(0), + DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ + NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ + FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ + SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); + shader[i++] = VTX_DWORD2(OFFSET(0), + ENDIAN_SWAP(ENDIAN_NONE), + CONST_BUF_NO_STRIDE(0), + MEGA_FETCH(1)); + shader[i++] = VTX_DWORD_PAD; + /* 6/7 */ + shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), + FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), + FETCH_WHOLE_QUAD(0), + BUFFER_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + SRC_SEL_X(SQ_SEL_X), + MEGA_FETCH_COUNT(8)); + shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), + DST_REL(0), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_0), + DST_SEL_W(SQ_SEL_1), + USE_CONST_FIELDS(0), + DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ + NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ + FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ + SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); + shader[i++] = VTX_DWORD2(OFFSET(8), + ENDIAN_SWAP(ENDIAN_NONE), + CONST_BUF_NO_STRIDE(0), + MEGA_FETCH(0)); + shader[i++] = VTX_DWORD_PAD; + + return i; +} + +/* copy ps --------------------------------------- */ +int R600_copy_ps(enum RHD_CHIPSETS ChipSet, CARD32* shader) +{ + int i=0; + + /* CF INST 0 */ + shader[i++] = CF_DWORD0(ADDR(2)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(1), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_TEX), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* CF INST 1 */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), + TYPE(SQ_EXPORT_PIXEL), + RW_GPR(0), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(1)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(1), + END_OF_PROGRAM(1), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* TEX INST 0 */ + shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), + BC_FRAC_MODE(0), + FETCH_WHOLE_QUAD(0), + RESOURCE_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(0), + DST_REL(ABSOLUTE), + DST_SEL_X(SQ_SEL_X), /* R */ + DST_SEL_Y(SQ_SEL_Y), /* G */ + DST_SEL_Z(SQ_SEL_Z), /* B */ + DST_SEL_W(SQ_SEL_W), /* A */ + LOD_BIAS(0), + COORD_TYPE_X(TEX_UNNORMALIZED), + COORD_TYPE_Y(TEX_UNNORMALIZED), + COORD_TYPE_Z(TEX_UNNORMALIZED), + COORD_TYPE_W(TEX_UNNORMALIZED)); + shader[i++] = TEX_DWORD2(OFFSET_X(0), + OFFSET_Y(0), + OFFSET_Z(0), + SAMPLER_ID(0), + SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_0), + SRC_SEL_W(SQ_SEL_1)); + shader[i++] = TEX_DWORD_PAD; + + return i; +} + +/* + * ; xv vertex shader + * 00 VTX: ADDR(4) CNT(2) + * 0 VFETCH R1.xy01, R0.x, fc0 MEGA(16) FORMAT(32_32_FLOAT) + * FORMAT_COMP(SIGNED) + * 1 VFETCH R0.xy01, R0.x, fc0 MINI(8) OFFSET(8) FORMAT(32_32_FLOAT) + * FORMAT_COMP(SIGNED) + * 01 EXP_DONE: POS0, R1 + * 02 EXP_DONE: PARAM0, R0 NO_BARRIER + * END_OF_PROGRAM + */ +int R600_xv_vs(enum RHD_CHIPSETS ChipSet, CARD32* shader) +{ + int i=0; + + /* 0 */ + shader[i++] = CF_DWORD0(ADDR(4)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(2), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_VTX), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 1 */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), + TYPE(SQ_EXPORT_POS), + RW_GPR(1), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(3)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(1), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 2 */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), + TYPE(SQ_EXPORT_PARAM), + RW_GPR(0), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(3)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(1), + END_OF_PROGRAM(1), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(0)); + shader[i++] = 0x00000000; + shader[i++] = 0x00000000; + /* 4/5 */ + shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), + FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), + FETCH_WHOLE_QUAD(0), + BUFFER_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + SRC_SEL_X(SQ_SEL_X), + MEGA_FETCH_COUNT(16)); + shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), + DST_REL(ABSOLUTE), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_0), + DST_SEL_W(SQ_SEL_1), + USE_CONST_FIELDS(0), + DATA_FORMAT(FMT_32_32_FLOAT), + NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), + FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), + SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); + shader[i++] = VTX_DWORD2(OFFSET(0), + ENDIAN_SWAP(ENDIAN_NONE), + CONST_BUF_NO_STRIDE(0), + MEGA_FETCH(1)); + shader[i++] = VTX_DWORD_PAD; + /* 6/7 */ + shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), + FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), + FETCH_WHOLE_QUAD(0), + BUFFER_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + SRC_SEL_X(SQ_SEL_X), + MEGA_FETCH_COUNT(8)); + shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), + DST_REL(ABSOLUTE), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_0), + DST_SEL_W(SQ_SEL_1), + USE_CONST_FIELDS(0), + DATA_FORMAT(FMT_32_32_FLOAT), + NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), + FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), + SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); + shader[i++] = VTX_DWORD2(OFFSET(8), + ENDIAN_SWAP(ENDIAN_NONE), + CONST_BUF_NO_STRIDE(0), + MEGA_FETCH(0)); + shader[i++] = VTX_DWORD_PAD; + + return i; +} + +/* + * ; xv ps planar + * 00 TEX: ADDR(20) CNT(3) NO_BARRIER + * 0 SAMPLE R1.x__1, R0.xy01, t0, s0 + * 1 SAMPLE R1.__x_, R0.xy01, t1, s1 + * 2 SAMPLE R1._x__, R0.xy01, t2, s2 + * 01 TEX: ADDR(28) CNT(2) NO_BARRIER + * 0 SAMPLE R1.x__1, R0.xy01, t0, s0 + * 1 SAMPLE R1._xy_, R0.xy01, t1, s1 + * 02 ALU: ADDR(4) CNT(16) + * 3 x: MULADD R1.x, R1.x, C3.x, C3.y CLAMP + * y: MULADD R1.y, R1.y, C3.z, C3.w + * z: MULADD R1.z, R1.z, C3.z, C3.w + * w: MOV R1.w, 0.0f + * 4 x: DOT4 R2.x, R1.x, C0.x CLAMP VEC_102 + * y: DOT4 ____, R1.y, C0.y CLAMP VEC_102 + * z: DOT4 ____, R1.z, C0.z CLAMP VEC_102 + * w: DOT4 ____, R1.w, C0.w CLAMP VEC_021 + * 5 x: DOT4 ____, R1.x, C1.x CLAMP VEC_102 + * y: DOT4 R2.y, R1.y, C1.y CLAMP VEC_102 + * z: DOT4 ____, R1.z, C1.z CLAMP VEC_102 + * w: DOT4 ____, R1.w, C1.w CLAMP VEC_021 + * 6 x: DOT4 ____, R1.x, C2.x CLAMP VEC_102 + * y: DOT4 ____, R1.y, C2.y CLAMP VEC_102 + * z: DOT4 R2.z, R1.z, C2.z CLAMP VEC_102 + * w: DOT4 ____, R1.w, C2.w CLAMP VEC_021 + * 03 EXP_DONE: PIX0, R2 + * END_OF_PROGRAM + */ +int R600_xv_ps(enum RHD_CHIPSETS ChipSet, CARD32* shader) +{ + int i = 0; + + /* 0 */ + shader[i++] = CF_DWORD0(ADDR(20)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_BOOL), + I_COUNT(0), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_CALL), + WHOLE_QUAD_MODE(0), + BARRIER(0)); + /* 1 */ + shader[i++] = CF_DWORD0(ADDR(28)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_NOT_BOOL), + I_COUNT(0), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_CALL), + WHOLE_QUAD_MODE(0), + BARRIER(0)); + /* 2 */ + shader[i++] = CF_ALU_DWORD0(ADDR(4), + KCACHE_BANK0(0), + KCACHE_BANK1(0), + KCACHE_MODE0(SQ_CF_KCACHE_NOP)); + shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), + KCACHE_ADDR0(0), + KCACHE_ADDR1(0), + I_COUNT(16), + USES_WATERFALL(0), + CF_INST(SQ_CF_INST_ALU), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 3 */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), + TYPE(SQ_EXPORT_PIXEL), + RW_GPR(2), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(3)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(1), + END_OF_PROGRAM(1), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 4 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_X), + SRC0_NEG(0), + SRC1_SEL(259), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_X), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(259), + SRC2_REL(ABSOLUTE), + SRC2_ELEM(ELEM_Y), + SRC2_NEG(0), + ALU_INST(SQ_OP3_INST_MULADD), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(1), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_X), + CLAMP(1)); + /* 5 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Y), + SRC0_NEG(0), + SRC1_SEL(259), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Z), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(259), + SRC2_REL(ABSOLUTE), + SRC2_ELEM(ELEM_W), + SRC2_NEG(0), + ALU_INST(SQ_OP3_INST_MULADD), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(1), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Y), + CLAMP(0)); + /* 6 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Z), + SRC0_NEG(0), + SRC1_SEL(259), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Z), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(259), + SRC2_REL(ABSOLUTE), + SRC2_ELEM(ELEM_W), + SRC2_NEG(0), + ALU_INST(SQ_OP3_INST_MULADD), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(1), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Z), + CLAMP(0)); + /* 7 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_X), + SRC0_NEG(0), + SRC1_SEL(SQ_ALU_SRC_0), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_X), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(1)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_MOV), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(1), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_W), + CLAMP(0)); + /* 8 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_X), + SRC0_NEG(0), + SRC1_SEL(256), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_X), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_102), + DST_GPR(2), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_X), + CLAMP(1)); + /* 9 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Y), + SRC0_NEG(0), + SRC1_SEL(256), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Y), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(0), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_102), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Y), + CLAMP(1)); + /* 10 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Z), + SRC0_NEG(0), + SRC1_SEL(256), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Z), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(0), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_102), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Z), + CLAMP(1)); + /* 11 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_W), + SRC0_NEG(0), + SRC1_SEL(256), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_W), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(1)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(0), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_021), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_W), + CLAMP(1)); + /* 12 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_X), + SRC0_NEG(0), + SRC1_SEL(257), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_X), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(0), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_102), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_X), + CLAMP(1)); + /* 13 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Y), + SRC0_NEG(0), + SRC1_SEL(257), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Y), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_102), + DST_GPR(2), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Y), + CLAMP(1)); + /* 14 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Z), + SRC0_NEG(0), + SRC1_SEL(257), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Z), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(0), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_102), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Z), + CLAMP(1)); + /* 15 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_W), + SRC0_NEG(0), + SRC1_SEL(257), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_W), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(1)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(0), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_021), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_W), + CLAMP(1)); + /* 16 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_X), + SRC0_NEG(0), + SRC1_SEL(258), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_X), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(0), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_102), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_X), + CLAMP(1)); + /* 17 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Y), + SRC0_NEG(0), + SRC1_SEL(258), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Y), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(0), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_102), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Y), + CLAMP(1)); + /* 18 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Z), + SRC0_NEG(0), + SRC1_SEL(258), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Z), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_102), + DST_GPR(2), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Z), + CLAMP(1)); + /* 19 */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_W), + SRC0_NEG(0), + SRC1_SEL(258), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_W), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(1)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(0), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_DOT4), + BANK_SWIZZLE(SQ_ALU_VEC_021), + DST_GPR(0), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_W), + CLAMP(1)); + /* 20 */ + shader[i++] = CF_DWORD0(ADDR(22)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(3), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_TEX), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 21 */ + shader[i++] = CF_DWORD0(ADDR(0)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(0), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_RETURN), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 22/23 */ + shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), + BC_FRAC_MODE(0), + FETCH_WHOLE_QUAD(0), + RESOURCE_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(1), + DST_REL(ABSOLUTE), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_MASK), + DST_SEL_Z(SQ_SEL_MASK), + DST_SEL_W(SQ_SEL_1), + LOD_BIAS(0), + COORD_TYPE_X(TEX_NORMALIZED), + COORD_TYPE_Y(TEX_NORMALIZED), + COORD_TYPE_Z(TEX_NORMALIZED), + COORD_TYPE_W(TEX_NORMALIZED)); + shader[i++] = TEX_DWORD2(OFFSET_X(0), + OFFSET_Y(0), + OFFSET_Z(0), + SAMPLER_ID(0), + SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_0), + SRC_SEL_W(SQ_SEL_1)); + shader[i++] = TEX_DWORD_PAD; + /* 24/25 */ + shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), + BC_FRAC_MODE(0), + FETCH_WHOLE_QUAD(0), + RESOURCE_ID(1), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(1), + DST_REL(ABSOLUTE), + DST_SEL_X(SQ_SEL_MASK), + DST_SEL_Y(SQ_SEL_MASK), + DST_SEL_Z(SQ_SEL_X), + DST_SEL_W(SQ_SEL_MASK), + LOD_BIAS(0), + COORD_TYPE_X(TEX_NORMALIZED), + COORD_TYPE_Y(TEX_NORMALIZED), + COORD_TYPE_Z(TEX_NORMALIZED), + COORD_TYPE_W(TEX_NORMALIZED)); + shader[i++] = TEX_DWORD2(OFFSET_X(0), + OFFSET_Y(0), + OFFSET_Z(0), + SAMPLER_ID(1), + SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_0), + SRC_SEL_W(SQ_SEL_1)); + shader[i++] = TEX_DWORD_PAD; + /* 26/27 */ + shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), + BC_FRAC_MODE(0), + FETCH_WHOLE_QUAD(0), + RESOURCE_ID(2), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(1), + DST_REL(ABSOLUTE), + DST_SEL_X(SQ_SEL_MASK), + DST_SEL_Y(SQ_SEL_X), + DST_SEL_Z(SQ_SEL_MASK), + DST_SEL_W(SQ_SEL_MASK), + LOD_BIAS(0), + COORD_TYPE_X(TEX_NORMALIZED), + COORD_TYPE_Y(TEX_NORMALIZED), + COORD_TYPE_Z(TEX_NORMALIZED), + COORD_TYPE_W(TEX_NORMALIZED)); + shader[i++] = TEX_DWORD2(OFFSET_X(0), + OFFSET_Y(0), + OFFSET_Z(0), + SAMPLER_ID(2), + SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_0), + SRC_SEL_W(SQ_SEL_1)); + shader[i++] = TEX_DWORD_PAD; + /* 28 */ + shader[i++] = CF_DWORD0(ADDR(30)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(2), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_TEX), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 29 */ + shader[i++] = CF_DWORD0(ADDR(0)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(0), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_RETURN), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 30/31 */ + shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), + BC_FRAC_MODE(0), + FETCH_WHOLE_QUAD(0), + RESOURCE_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(1), + DST_REL(ABSOLUTE), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_MASK), + DST_SEL_Z(SQ_SEL_MASK), + DST_SEL_W(SQ_SEL_1), + LOD_BIAS(0), + COORD_TYPE_X(TEX_NORMALIZED), + COORD_TYPE_Y(TEX_NORMALIZED), + COORD_TYPE_Z(TEX_NORMALIZED), + COORD_TYPE_W(TEX_NORMALIZED)); + shader[i++] = TEX_DWORD2(OFFSET_X(0), + OFFSET_Y(0), + OFFSET_Z(0), + SAMPLER_ID(0), + SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_0), + SRC_SEL_W(SQ_SEL_1)); + shader[i++] = TEX_DWORD_PAD; + /* 32/33 */ + shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), + BC_FRAC_MODE(0), + FETCH_WHOLE_QUAD(0), + RESOURCE_ID(1), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(1), + DST_REL(ABSOLUTE), + DST_SEL_X(SQ_SEL_MASK), + DST_SEL_Y(SQ_SEL_X), + DST_SEL_Z(SQ_SEL_Y), + DST_SEL_W(SQ_SEL_MASK), + LOD_BIAS(0), + COORD_TYPE_X(TEX_NORMALIZED), + COORD_TYPE_Y(TEX_NORMALIZED), + COORD_TYPE_Z(TEX_NORMALIZED), + COORD_TYPE_W(TEX_NORMALIZED)); + shader[i++] = TEX_DWORD2(OFFSET_X(0), + OFFSET_Y(0), + OFFSET_Z(0), + SAMPLER_ID(1), + SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_0), + SRC_SEL_W(SQ_SEL_1)); + shader[i++] = TEX_DWORD_PAD; + + return i; +} + +/* comp mask ps --------------------------------------- */ +int R600_comp_mask_ps(enum RHD_CHIPSETS ChipSet, CARD32* shader) +{ + int i=0; + + /* 0 */ + shader[i++] = CF_DWORD0(ADDR(8)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(2), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_TEX), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + + /* 1 */ + shader[i++] = CF_ALU_DWORD0(ADDR(3), + KCACHE_BANK0(0), + KCACHE_BANK1(0), + KCACHE_MODE0(SQ_CF_KCACHE_NOP)); + shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), + KCACHE_ADDR0(0), + KCACHE_ADDR1(0), + I_COUNT(4), + USES_WATERFALL(0), + CF_INST(SQ_CF_INST_ALU), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + + /* 2 */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), + TYPE(SQ_EXPORT_PIXEL), + RW_GPR(2), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(1)); + + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(1), + END_OF_PROGRAM(1), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + + /* 3 - alu 0 */ + /* MUL gpr[2].x gpr[1].x gpr[0].x */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_X), + SRC0_NEG(0), + SRC1_SEL(0), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_X), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_MUL), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(2), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_X), + CLAMP(1)); + /* 4 - alu 1 */ + /* MUL gpr[2].y gpr[1].y gpr[0].y */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Y), + SRC0_NEG(0), + SRC1_SEL(0), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Y), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_MUL), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(2), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Y), + CLAMP(1)); + /* 5 - alu 2 */ + /* MUL gpr[2].z gpr[1].z gpr[0].z */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_Z), + SRC0_NEG(0), + SRC1_SEL(0), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_Z), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(0)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_MUL), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(2), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_Z), + CLAMP(1)); + /* 6 - alu 3 */ + /* MUL gpr[2].w gpr[1].w gpr[0].w */ + shader[i++] = ALU_DWORD0(SRC0_SEL(1), + SRC0_REL(ABSOLUTE), + SRC0_ELEM(ELEM_W), + SRC0_NEG(0), + SRC1_SEL(0), + SRC1_REL(ABSOLUTE), + SRC1_ELEM(ELEM_W), + SRC1_NEG(0), + INDEX_MODE(SQ_INDEX_LOOP), + PRED_SEL(SQ_PRED_SEL_OFF), + LAST(1)); + shader[i++] = ALU_DWORD1_OP2(ChipSet, + SRC0_ABS(0), + SRC1_ABS(0), + UPDATE_EXECUTE_MASK(0), + UPDATE_PRED(0), + WRITE_MASK(1), + FOG_MERGE(0), + OMOD(SQ_ALU_OMOD_OFF), + ALU_INST(SQ_OP2_INST_MUL), + BANK_SWIZZLE(SQ_ALU_VEC_012), + DST_GPR(2), + DST_REL(ABSOLUTE), + DST_ELEM(ELEM_W), + CLAMP(1)); + /* 7 */ + shader[i++] = 0x00000000; + shader[i++] = 0x00000000; + + /* 8/9 - src */ + shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), + BC_FRAC_MODE(0), + FETCH_WHOLE_QUAD(0), + RESOURCE_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(0), + DST_REL(ABSOLUTE), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_Z), + DST_SEL_W(SQ_SEL_W), + LOD_BIAS(0), + COORD_TYPE_X(TEX_NORMALIZED), + COORD_TYPE_Y(TEX_NORMALIZED), + COORD_TYPE_Z(TEX_NORMALIZED), + COORD_TYPE_W(TEX_NORMALIZED)); + shader[i++] = TEX_DWORD2(OFFSET_X(0), + OFFSET_Y(0), + OFFSET_Z(0), + SAMPLER_ID(0), + SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_0), + SRC_SEL_W(SQ_SEL_1)); + shader[i++] = TEX_DWORD_PAD; + /* 10/11 - mask */ + shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), + BC_FRAC_MODE(0), + FETCH_WHOLE_QUAD(0), + RESOURCE_ID(1), + SRC_GPR(1), + SRC_REL(ABSOLUTE), + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(1), + DST_REL(ABSOLUTE), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_Z), + DST_SEL_W(SQ_SEL_W), + LOD_BIAS(0), + COORD_TYPE_X(TEX_NORMALIZED), + COORD_TYPE_Y(TEX_NORMALIZED), + COORD_TYPE_Z(TEX_NORMALIZED), + COORD_TYPE_W(TEX_NORMALIZED)); + shader[i++] = TEX_DWORD2(OFFSET_X(0), + OFFSET_Y(0), + OFFSET_Z(0), + SAMPLER_ID(1), + SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_0), + SRC_SEL_W(SQ_SEL_1)); + shader[i++] = TEX_DWORD_PAD; + + return i; +} + +/* comp vs --------------------------------------- */ +int R600_comp_vs(enum RHD_CHIPSETS ChipSet, CARD32* shader) +{ + int i = 0; + + /* 0 */ + shader[i++] = CF_DWORD0(ADDR(3)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_BOOL), + I_COUNT(0), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_CALL), + WHOLE_QUAD_MODE(0), + BARRIER(0)); + /* 1 */ + shader[i++] = CF_DWORD0(ADDR(14)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_NOT_BOOL), + I_COUNT(0), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_CALL), + WHOLE_QUAD_MODE(0), + BARRIER(0)); + /* 2 */ + shader[i++] = CF_DWORD0(0); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(0), + CALL_COUNT(0), + END_OF_PROGRAM(1), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_NOP), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 3 - mask sub */ + shader[i++] = CF_DWORD0(ADDR(8)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(3), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_VTX), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 4 - dst */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), + TYPE(SQ_EXPORT_POS), + RW_GPR(2), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(0)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(1), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 5 - src */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), + TYPE(SQ_EXPORT_PARAM), + RW_GPR(1), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(0)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(1), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT), + WHOLE_QUAD_MODE(0), + BARRIER(0)); + /* 6 - mask */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(1), + TYPE(SQ_EXPORT_PARAM), + RW_GPR(0), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(0)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(1), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(0)); + /* 7 */ + shader[i++] = CF_DWORD0(ADDR(0)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(0), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_RETURN), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 8/9 - dst */ + shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), + FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), + FETCH_WHOLE_QUAD(0), + BUFFER_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + SRC_SEL_X(SQ_SEL_X), + MEGA_FETCH_COUNT(24)); + shader[i++] = VTX_DWORD1_GPR(DST_GPR(2), + DST_REL(0), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_0), + DST_SEL_W(SQ_SEL_1), + USE_CONST_FIELDS(0), + DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ + NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ + FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ + SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); + shader[i++] = VTX_DWORD2(OFFSET(0), + ENDIAN_SWAP(ENDIAN_NONE), + CONST_BUF_NO_STRIDE(0), + MEGA_FETCH(1)); + shader[i++] = VTX_DWORD_PAD; + /* 10/11 - src */ + shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), + FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), + FETCH_WHOLE_QUAD(0), + BUFFER_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + SRC_SEL_X(SQ_SEL_X), + MEGA_FETCH_COUNT(8)); + shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), + DST_REL(0), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_0), + DST_SEL_W(SQ_SEL_1), + USE_CONST_FIELDS(0), + DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ + NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ + FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ + SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); + shader[i++] = VTX_DWORD2(OFFSET(8), + ENDIAN_SWAP(ENDIAN_NONE), + CONST_BUF_NO_STRIDE(0), + MEGA_FETCH(0)); + shader[i++] = VTX_DWORD_PAD; + /* 12/13 - mask */ + shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), + FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), + FETCH_WHOLE_QUAD(0), + BUFFER_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + SRC_SEL_X(SQ_SEL_X), + MEGA_FETCH_COUNT(8)); + shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), + DST_REL(0), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_0), + DST_SEL_W(SQ_SEL_1), + USE_CONST_FIELDS(0), + DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ + NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ + FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ + SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); + shader[i++] = VTX_DWORD2(OFFSET(16), + ENDIAN_SWAP(ENDIAN_NONE), + CONST_BUF_NO_STRIDE(0), + MEGA_FETCH(0)); + shader[i++] = VTX_DWORD_PAD; + + /* 14 - non-mask sub */ + shader[i++] = CF_DWORD0(ADDR(18)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(2), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_VTX), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 15 - dst */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0), + TYPE(SQ_EXPORT_POS), + RW_GPR(1), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(0)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 16 - src */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0), + TYPE(SQ_EXPORT_PARAM), + RW_GPR(0), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(0)); + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(0)); + /* 17 */ + shader[i++] = CF_DWORD0(ADDR(0)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(0), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_RETURN), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 18/19 - dst */ + shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), + FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), + FETCH_WHOLE_QUAD(0), + BUFFER_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + SRC_SEL_X(SQ_SEL_X), + MEGA_FETCH_COUNT(16)); + shader[i++] = VTX_DWORD1_GPR(DST_GPR(1), + DST_REL(0), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_0), + DST_SEL_W(SQ_SEL_1), + USE_CONST_FIELDS(0), + DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ + NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ + FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ + SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); + shader[i++] = VTX_DWORD2(OFFSET(0), + ENDIAN_SWAP(ENDIAN_NONE), + CONST_BUF_NO_STRIDE(0), + MEGA_FETCH(1)); + shader[i++] = VTX_DWORD_PAD; + /* 20/21 - src */ + shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH), + FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA), + FETCH_WHOLE_QUAD(0), + BUFFER_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + SRC_SEL_X(SQ_SEL_X), + MEGA_FETCH_COUNT(8)); + shader[i++] = VTX_DWORD1_GPR(DST_GPR(0), + DST_REL(0), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_0), + DST_SEL_W(SQ_SEL_1), + USE_CONST_FIELDS(0), + DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */ + NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */ + FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */ + SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); + shader[i++] = VTX_DWORD2(OFFSET(8), + ENDIAN_SWAP(ENDIAN_NONE), + CONST_BUF_NO_STRIDE(0), + MEGA_FETCH(0)); + shader[i++] = VTX_DWORD_PAD; + + return i; +} + +/* comp ps --------------------------------------- */ +int R600_comp_ps(enum RHD_CHIPSETS ChipSet, CARD32* shader) +{ + int i=0; + + /* 0 */ + shader[i++] = CF_DWORD0(ADDR(2)); + shader[i++] = CF_DWORD1(POP_COUNT(0), + CF_CONST(0), + COND(SQ_CF_COND_ACTIVE), + I_COUNT(1), + CALL_COUNT(0), + END_OF_PROGRAM(0), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_TEX), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + /* 1 */ + shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), + TYPE(SQ_EXPORT_PIXEL), + RW_GPR(0), + RW_REL(ABSOLUTE), + INDEX_GPR(0), + ELEM_SIZE(1)); + + shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_Z), + SRC_SEL_W(SQ_SEL_W), + R6xx_ELEM_LOOP(0), + BURST_COUNT(1), + END_OF_PROGRAM(1), + VALID_PIXEL_MODE(0), + CF_INST(SQ_CF_INST_EXPORT_DONE), + WHOLE_QUAD_MODE(0), + BARRIER(1)); + + + /* 2/3 - src */ + shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), + BC_FRAC_MODE(0), + FETCH_WHOLE_QUAD(0), + RESOURCE_ID(0), + SRC_GPR(0), + SRC_REL(ABSOLUTE), + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(0), + DST_REL(ABSOLUTE), + DST_SEL_X(SQ_SEL_X), + DST_SEL_Y(SQ_SEL_Y), + DST_SEL_Z(SQ_SEL_Z), + DST_SEL_W(SQ_SEL_W), + LOD_BIAS(0), + COORD_TYPE_X(TEX_NORMALIZED), + COORD_TYPE_Y(TEX_NORMALIZED), + COORD_TYPE_Z(TEX_NORMALIZED), + COORD_TYPE_W(TEX_NORMALIZED)); + shader[i++] = TEX_DWORD2(OFFSET_X(0), + OFFSET_Y(0), + OFFSET_Z(0), + SAMPLER_ID(0), + SRC_SEL_X(SQ_SEL_X), + SRC_SEL_Y(SQ_SEL_Y), + SRC_SEL_Z(SQ_SEL_0), + SRC_SEL_W(SQ_SEL_1)); + shader[i++] = TEX_DWORD_PAD; + + return i; +} diff --git a/driver/xf86-video-radeonhd/src/r600_shader.h b/driver/xf86-video-radeonhd/src/r600_shader.h new file mode 100644 index 000000000..0ff8671f5 --- /dev/null +++ b/driver/xf86-video-radeonhd/src/r600_shader.h @@ -0,0 +1,359 @@ +/* + * RadeonHD R6xx, R7xx DRI driver + * + * Copyright (C) 2008-2009 Alexander Deucher + * Copyright (C) 2008-2009 Matthias Hopf + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Shader macros + */ + +#ifndef __SHADER_H__ +#define __SHADER_H__ + + +/* Restrictions of ALU instructions + * order of scalar ops is always x,y,z,w,t(rans), last to be indicated by last==1. + * max of 3 different src GPRs per instr. + * max of 4 different cfile constant components per instr. + * max of 2 (different) constants (any type) for t. + * bank swizzle (see below). + * GPR write stalls read of same register. Auto-replaced by PV/PS, NOP needed if registers are relative to + * different indices (gpr,loop,nothing). + * may use constant registers or constant cache, but not both. + */ + +/* Bank_swizzle: (pp. 297ff) + * Only one of each x,y,z,w GPR component can be loaded per cycle (3 cycles per instr, called 0-2). + * per scalar instruction bank_swizzle can select which cycle each operand comes from. e.g.: + * SRC0 SRC1 SRC2 SWIZZLE cycle0 cycle1 cycle2 + * 1.x 2.x 012 1.x 2.x - + * 3.x 1.y 201 1.y - 3.x + * 2.x 1.y 102 (1.y) (2.x) - + * If data is read in a cycle, multiple scalar instructions can reference it. + * Special case: square() - i.e. same component in src0+src1 doesn't need read port -> ignores swizzle for src1. + * No restrictions for constants or PV/PS. + * t can load multiple components in a single cycle slot, but has to share cycles with xyzw. + * t with single constant may not load GPRs or PV/PS in cycle 0 (carefull with ALU_TRANS_210). + * t with two constants may only load GPRs or PV/PS in cycle 2. + */ + + +/* Oder of instructions: All CF, All ALU, All Tex/Vtx fetches */ + + +// CF insts +// addr +#define ADDR(x) (x) +// pc +#define POP_COUNT(x) (x) +// const +#define CF_CONST(x) (x) +// cond +#define COND(x) (x) // SQ_COND_* +// count +#define I_COUNT(x) ((x) ? ((x) - 1) : 0) +//r7xx +#define COUNT_3(x) (x) +// call count +#define CALL_COUNT(x) (x) +// eop +#define END_OF_PROGRAM(x) (x) +// vpm +#define VALID_PIXEL_MODE(x) (x) +// cf inst +#define CF_INST(x) (x) // SQ_CF_INST_* + +// wqm +#define WHOLE_QUAD_MODE(x) (x) +// barrier +#define BARRIER(x) (x) +//kb0 +#define KCACHE_BANK0(x) (x) +//kb1 +#define KCACHE_BANK1(x) (x) +// km0/1 +#define KCACHE_MODE0(x) (x) +#define KCACHE_MODE1(x) (x) // SQ_CF_KCACHE_* +// +#define KCACHE_ADDR0(x) (x) +#define KCACHE_ADDR1(x) (x) +// uw +#define USES_WATERFALL(x) (x) + +#define ARRAY_BASE(x) (x) +// export pixel +#define CF_PIXEL_MRT0 0 +#define CF_PIXEL_MRT1 1 +#define CF_PIXEL_MRT2 2 +#define CF_PIXEL_MRT3 3 +#define CF_PIXEL_MRT4 4 +#define CF_PIXEL_MRT5 5 +#define CF_PIXEL_MRT6 6 +#define CF_PIXEL_MRT7 7 +// *_FOG: r6xx only +#define CF_PIXEL_MRT0_FOG 16 +#define CF_PIXEL_MRT1_FOG 17 +#define CF_PIXEL_MRT2_FOG 18 +#define CF_PIXEL_MRT3_FOG 19 +#define CF_PIXEL_MRT4_FOG 20 +#define CF_PIXEL_MRT5_FOG 21 +#define CF_PIXEL_MRT6_FOG 22 +#define CF_PIXEL_MRT7_FOG 23 +#define CF_PIXEL_Z 61 +// export pos +#define CF_POS0 60 +#define CF_POS1 61 +#define CF_POS2 62 +#define CF_POS3 63 +// export param +// 0...31 +#define TYPE(x) (x) // SQ_EXPORT_* +#if 0 +// type export +#define SQ_EXPORT_PIXEL 0 +#define SQ_EXPORT_POS 1 +#define SQ_EXPORT_PARAM 2 +// reserved 3 +// type mem +#define SQ_EXPORT_WRITE 0 +#define SQ_EXPORT_WRITE_IND 1 +#define SQ_EXPORT_WRITE_ACK 2 +#define SQ_EXPORT_WRITE_IND_ACK 3 +#endif + +#define RW_GPR(x) (x) +#define RW_REL(x) (x) +#define ABSOLUTE 0 +#define RELATIVE 1 +#define INDEX_GPR(x) (x) +#define ELEM_SIZE(x) (x ? (x - 1) : 0) +#define COMP_MASK(x) (x) +#define R6xx_ELEM_LOOP(x) (x) +#define BURST_COUNT(x) (x ? (x - 1) : 0) + +// swiz +#define SRC_SEL_X(x) (x) // SQ_SEL_* each +#define SRC_SEL_Y(x) (x) +#define SRC_SEL_Z(x) (x) +#define SRC_SEL_W(x) (x) + +#define CF_DWORD0(addr) (addr) +// R7xx has another entry (COUNT3), but that is only used for adding a bit to count. +// We allow one more bit for count in the argument of the macro on R7xx instead. +// R6xx: [0,7] R7xx: [1,16] +#define CF_DWORD1(pc, cf_const, cond, count, call_count, eop, vpm, cf_inst, wqm, b) \ + (((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | (((count) & 7) << 10) | (((count) >> 3) << 19) | \ + ((call_count) << 13) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)) + +#define CF_ALU_DWORD0(addr, kb0, kb1, km0) (((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30)) +#define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, uw, cf_inst, wqm, b) \ + (((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \ + ((count) << 18) | ((uw) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31)) + +#define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \ + (((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | ((index_gpr) << 23) | \ + ((es) << 30)) +// R7xx apparently doesn't have the ELEM_LOOP entry any more +// We still expose it, but ELEM_LOOP is explicitely R6xx now. +// TODO: is this just forgotten in the docs, or really not available any more? +#define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \ + (((array_size) << 0) | ((comp_mask) << 12) | ((el) << 16) | ((bc) << 17) | \ + ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)) +#define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, el, bc, eop, vpm, cf_inst, wqm, b) \ + (((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | ((el) << 16) | \ + ((bc) << 17) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | \ + ((wqm) << 30) | ((b) << 31)) + +// ALU clause insts +#define SRC0_SEL(x) (x) +#define SRC1_SEL(x) (x) +#define SRC2_SEL(x) (x) +// src[0-2]_sel +// 0-127 GPR +// 128-159 kcache constants bank 0 +// 160-191 kcache constants bank 1 +// 248-255 special SQ_ALU_SRC_* (0, 1, etc.) + +#define SRC0_REL(x) (x) +#define SRC1_REL(x) (x) +#define SRC2_REL(x) (x) +// elem +#define SRC0_ELEM(x) (x) +#define SRC1_ELEM(x) (x) +#define SRC2_ELEM(x) (x) +#define ELEM_X 0 +#define ELEM_Y 1 +#define ELEM_Z 2 +#define ELEM_W 3 +// neg +#define SRC0_NEG(x) (x) +#define SRC1_NEG(x) (x) +#define SRC2_NEG(x) (x) +// im +#define INDEX_MODE(x) (x) // SQ_INDEX_* +// ps +#define PRED_SEL(x) (x) // SQ_PRED_SEL_* +// last +#define LAST(x) (x) +// abs +#define SRC0_ABS(x) (x) +#define SRC1_ABS(x) (x) +// uem +#define UPDATE_EXECUTE_MASK(x) (x) +// up +#define UPDATE_PRED(x) (x) +// wm +#define WRITE_MASK(x) (x) +// fm +#define FOG_MERGE(x) (x) +// omod +#define OMOD(x) (x) // SQ_ALU_OMOD_* +// alu inst +#define ALU_INST(x) (x) // SQ_ALU_INST_* +//bs +#define BANK_SWIZZLE(x) (x) // SQ_ALU_VEC_* +#define DST_GPR(x) (x) +#define DST_REL(x) (x) +#define DST_ELEM(x) (x) +#define CLAMP(x) (x) + +#define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \ + (((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \ + ((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \ + ((im) << 26) | ((ps) << 29) | ((last) << 31)) +// R7xx has alu_inst at a different slot, and no fog merge any more (no fix function fog any more) +#define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ + (((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ + ((fm) << 5) | ((omod) << 6) | ((alu_inst) << 8) | ((bs) << 18) | ((dst_gpr) << 21) | \ + ((dr) << 28) | ((de) << 29) | ((clamp) << 31)) +#define R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ + (((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ + ((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \ + ((dr) << 28) | ((de) << 29) | ((clamp) << 31)) +// This is a general chipset macro, but due to selection by chipid typically not usable in static arrays +// Fog is NOT USED on R7xx, even if specified. +#define ALU_DWORD1_OP2(chipid, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ + ((chipid) < RHD_RV770 ? \ + R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \ + R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp)) +#define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \ + (((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \ + ((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \ + ((de) << 29) | ((clamp) << 31)) + +// VTX clause insts +// vxt insts +#define VTX_INST(x) (x) // SQ_VTX_INST_* + +// fetch type +#define FETCH_TYPE(x) (x) // SQ_VTX_FETCH_* + +#define FETCH_WHOLE_QUAD(x) (x) +#define BUFFER_ID(x) (x) +#define SRC_GPR(x) (x) +#define SRC_REL(x) (x) +#define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0) + +#define SEMANTIC_ID(x) (x) +#define DST_SEL_X(x) (x) +#define DST_SEL_Y(x) (x) +#define DST_SEL_Z(x) (x) +#define DST_SEL_W(x) (x) +#define USE_CONST_FIELDS(x) (x) +#define DATA_FORMAT(x) (x) +// num format +#define NUM_FORMAT_ALL(x) (x) // SQ_NUM_FORMAT_* +// format comp +#define FORMAT_COMP_ALL(x) (x) // SQ_FORMAT_COMP_* +// sma +#define SRF_MODE_ALL(x) (x) +#define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0 +#define SRF_MODE_NO_ZERO 1 +#define OFFSET(x) (x) +// endian swap +#define ENDIAN_SWAP(x) (x) // SQ_ENDIAN_* +#define CONST_BUF_NO_STRIDE(x) (x) +// mf +#define MEGA_FETCH(x) (x) + +#define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \ + (((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \ + ((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26)) +#define VTX_DWORD1_SEM(semantic_id, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ + (((semantic_id) << 0) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ + ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)) +#define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ + (((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ + ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)) +#define VTX_DWORD2(offset, es, cbns, mf) \ + (((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19)) +#define VTX_DWORD_PAD 0x00000000 + +// TEX clause insts +// tex insts +#define TEX_INST(x) (x) // SQ_TEX_INST_* + +#define BC_FRAC_MODE(x) (x) +#define FETCH_WHOLE_QUAD(x) (x) +#define RESOURCE_ID(x) (x) +#define R7xx_ALT_CONST(x) (x) + +#define LOD_BIAS(x) (x) +//ct +#define COORD_TYPE_X(x) (x) +#define COORD_TYPE_Y(x) (x) +#define COORD_TYPE_Z(x) (x) +#define COORD_TYPE_W(x) (x) +#define TEX_UNNORMALIZED 0 +#define TEX_NORMALIZED 1 +#define OFFSET_X(x) (((int)(x) * 2) & 0x1f) /* 4:1-bits 2's-complement fixed-point: [-8.0..7.5] */ +#define OFFSET_Y(x) (((int)(x) * 2) & 0x1f) +#define OFFSET_Z(x) (((int)(x) * 2) & 0x1f) +#define SAMPLER_ID(x) (x) + +// R7xx has an additional parameter ALT_CONST. We always expose it, but ALT_CONST is R7xx only +#define TEX_DWORD0(tex_inst, bfm, fwq, resource_id, src_gpr, sr, ac) \ + (((tex_inst) << 0) | ((bfm) << 5) | ((fwq) << 7) | ((resource_id) << 8) | \ + ((src_gpr) << 16) | ((sr) << 23) | ((ac) << 24)) +#define TEX_DWORD1(dst_gpr, dr, dsx, dsy, dsz, dsw, lod_bias, ctx, cty, ctz, ctw) \ + (((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ + ((lod_bias) << 21) | ((ctx) << 28) | ((cty) << 29) | ((ctz) << 30) | ((ctw) << 31)) +#define TEX_DWORD2(offset_x, offset_y, offset_z, sampler_id, ssx, ssy, ssz, ssw) \ + (((offset_x) << 0) | ((offset_y) << 5) | ((offset_z) << 10) | ((sampler_id) << 15) | \ + ((ssx) << 20) | ((ssy) << 23) | ((ssz) << 26) | ((ssw) << 29)) +#define TEX_DWORD_PAD 0x00000000 + + +#endif + +extern int R600_solid_vs(enum RHD_CHIPSETS ChipSet, CARD32* vs); +extern int R600_solid_ps(enum RHD_CHIPSETS ChipSet, CARD32* ps); + +extern int R600_copy_vs(enum RHD_CHIPSETS ChipSet, CARD32* vs); +extern int R600_copy_ps(enum RHD_CHIPSETS ChipSet, CARD32* ps); + +extern int R600_xv_vs(enum RHD_CHIPSETS ChipSet, CARD32* shader); +extern int R600_xv_ps(enum RHD_CHIPSETS ChipSet, CARD32* shader); + +extern int R600_comp_vs(enum RHD_CHIPSETS ChipSet, CARD32* vs); +extern int R600_comp_mask_ps(enum RHD_CHIPSETS ChipSet, CARD32* ps); +extern int R600_comp_ps(enum RHD_CHIPSETS ChipSet, CARD32* ps); diff --git a/driver/xf86-video-radeonhd/src/r600_state.h b/driver/xf86-video-radeonhd/src/r600_state.h new file mode 100644 index 000000000..77b852f31 --- /dev/null +++ b/driver/xf86-video-radeonhd/src/r600_state.h @@ -0,0 +1,293 @@ +#ifndef __R600_STATE_H__ +#define __R600_STATE_H__ + +#include "xf86drm.h" + +typedef int bool_t; + +/* seriously ?! @#$%% */ +# define uint32_t CARD32 +# define uint64_t CARD64 + +#define CLEAR(x) memset (&x, 0, sizeof(x)) + +/* Sequencer / thread handling */ +typedef struct { + int ps_prio; + int vs_prio; + int gs_prio; + int es_prio; + int num_ps_gprs; + int num_vs_gprs; + int num_gs_gprs; + int num_es_gprs; + int num_temp_gprs; + int num_ps_threads; + int num_vs_threads; + int num_gs_threads; + int num_es_threads; + int num_ps_stack_entries; + int num_vs_stack_entries; + int num_gs_stack_entries; + int num_es_stack_entries; +} sq_config_t; + +/* Color buffer / render target */ +typedef struct { + int id; + int w; + int h; + uint64_t base; + int format; + int endian; + int array_mode; // tiling + int number_type; + int read_size; + int comp_swap; + int tile_mode; + int blend_clamp; + int clear_color; + int blend_bypass; + int blend_float32; + int simple_float; + int round_mode; + int tile_compact; + int source_format; +} cb_config_t; + +/* Depth buffer */ +typedef struct { + int w; + int h; + uint64_t base; + int format; + int read_size; + int array_mode; // tiling + int tile_surface_en; + int tile_compact; + int zrange_precision; +} db_config_t; + +/* Shader */ +typedef struct { + uint64_t shader_addr; + int num_gprs; + int stack_size; + int dx10_clamp; + int prime_cache_pgm_en; + int prime_cache_on_draw; + int fetch_cache_lines; + int prime_cache_en; + int prime_cache_on_const; + int clamp_consts; + int export_mode; + int uncached_first_inst; +} shader_config_t; + +/* Vertex buffer / vtx resource */ +typedef struct { + int id; + uint64_t vb_addr; + uint32_t vtx_num_entries; + uint32_t vtx_size_dw; + int clamp_x; + int format; + int num_format_all; + int format_comp_all; + int srf_mode_all; + int endian; + int mem_req_size; +} vtx_resource_t; + +/* Texture resource */ +typedef struct { + int id; + int w; + int h; + int pitch; + int depth; + int dim; + int tile_mode; + int tile_type; + int format; + uint64_t base; + uint64_t mip_base; + int format_comp_x; + int format_comp_y; + int format_comp_z; + int format_comp_w; + int num_format_all; + int srf_mode_all; + int force_degamma; + int endian; + int request_size; + int dst_sel_x; + int dst_sel_y; + int dst_sel_z; + int dst_sel_w; + int base_level; + int last_level; + int base_array; + int last_array; + int mpeg_clamp; + int perf_modulation; + int interlaced; +} tex_resource_t; + +/* Texture sampler */ +typedef struct { + int id; + /* Clamping */ + int clamp_x, clamp_y, clamp_z; + int border_color; + /* Filtering */ + int xy_mag_filter, xy_min_filter; + int z_filter; + int mip_filter; + bool_t high_precision_filter; /* ? */ + int perf_mip; /* ? 0-7 */ + int perf_z; /* ? 3 */ + /* LoD selection */ + int min_lod, max_lod; /* 0-0x3ff */ + int lod_bias; /* 0-0xfff (signed?) */ + int lod_bias2; /* ? 0-0xfff (signed?) */ + bool_t lod_uses_minor_axis; /* ? */ + /* Other stuff */ + bool_t point_sampling_clamp; /* ? */ + bool_t tex_array_override; /* ? */ + bool_t mc_coord_truncate; /* ? */ + bool_t force_degamma; /* ? */ + bool_t fetch_4; /* ? */ + bool_t sample_is_pcf; /* ? */ + bool_t type; /* ? */ + int depth_compare; /* only depth textures? */ + int chroma_key; +} tex_sampler_t; + +/* Draw command */ +typedef struct { + uint32_t prim_type; + uint32_t vgt_draw_initiator; + uint32_t index_type; + uint32_t num_instances; + uint32_t num_indices; +} draw_config_t; + + /* CP packet types */ +#define RADEON_CP_PACKET0 0x00000000 +#define RADEON_CP_PACKET1 0x40000000 +#define RADEON_CP_PACKET2 0x80000000 +#define RADEON_CP_PACKET3 0xC0000000 + +#define RADEON_TIMEOUT 2000000 + +#define E32(ib, dword) \ +do { \ + uint32_t *ib_head = (pointer)(char*)(ib)->address; \ + ib_head[(ib)->used >> 2] = (dword); \ + (ib)->used += 4; \ +} while (0) + +#define EFLOAT(ib, val) \ +do { \ + union { float f; uint32_t d; } a; \ + a.f = (val); \ + E32((ib), a.d); \ +} while (0) + +#define PACK3(ib, cmd, num) \ +do { \ + E32((ib), RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \ +} while (0) + +/* write num registers, start at reg */ +/* If register falls in a special area, special commands are issued */ +#define PACK0(ib, reg, num) \ +do { \ + if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \ + PACK3((ib), IT_SET_CONFIG_REG, (num) + 1); \ + E32(ib, ((reg) - SET_CONFIG_REG_offset) >> 2); \ + } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \ + PACK3((ib), IT_SET_CONTEXT_REG, (num) + 1); \ + E32(ib, ((reg) - 0x28000) >> 2); \ + } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \ + PACK3((ib), IT_SET_ALU_CONST, (num) + 1); \ + E32(ib, ((reg) - SET_ALU_CONST_offset) >> 2); \ + } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \ + PACK3((ib), IT_SET_RESOURCE, num + 1); \ + E32((ib), ((reg) - SET_RESOURCE_offset) >> 2); \ + } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \ + PACK3((ib), IT_SET_SAMPLER, (num) + 1); \ + E32((ib), (reg - SET_SAMPLER_offset) >> 2); \ + } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \ + PACK3((ib), IT_SET_CTL_CONST, (num) + 1); \ + E32((ib), ((reg) - SET_CTL_CONST_offset) >> 2); \ + } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \ + PACK3((ib), IT_SET_LOOP_CONST, (num) + 1); \ + E32((ib), ((reg) - SET_LOOP_CONST_offset) >> 2); \ + } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \ + PACK3((ib), IT_SET_BOOL_CONST, (num) + 1); \ + E32((ib), ((reg) - SET_BOOL_CONST_offset) >> 2); \ + } else { \ + E32((ib), CP_PACKET0 ((reg), (num))); \ + } \ +} while (0) + +/* write a single register */ +#define EREG(ib, reg, val) \ +do { \ + PACK0((ib), (reg), 1); \ + E32((ib), (val)); \ +} while (0) + +void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib); +void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib); + +uint64_t +upload (ScrnInfoPtr pScrn, void *shader, int size, int offset); +void +wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib); +void +wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib); +void +wait_vline_range(ScrnInfoPtr pScrn, drmBufPtr ib, int crtc, int start, int stop); +void +start_3d(ScrnInfoPtr pScrn, drmBufPtr ib); +void +set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf); +void +cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr); +void +fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf); +void +vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf); +void +ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf); +void +set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf); +void +set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val); +void +set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res); +void +set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res); +void +set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s); +void +set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2); +void +set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2); +void +set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2); +void +set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2); +void +set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2); +void +set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib); +void +draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices); +void +draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf); + +#endif diff --git a/driver/xf86-video-radeonhd/src/r600_textured_videofuncs.c b/driver/xf86-video-radeonhd/src/r600_textured_videofuncs.c new file mode 100644 index 000000000..96f5885f5 --- /dev/null +++ b/driver/xf86-video-radeonhd/src/r600_textured_videofuncs.c @@ -0,0 +1,531 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Author: Alex Deucher <alexander.deucher@amd.com> + * + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "xf86.h" + +#include "exa.h" + +#include "rhd.h" +#include "rhd_cs.h" +#include "r6xx_accel.h" +#include "r600_shader.h" +#include "r600_reg.h" +#include "r600_state.h" + +#include "rhd_video.h" + +#include <X11/extensions/Xv.h> +#include "fourcc.h" + +# ifdef DAMAGE +# include "damage.h" +# endif + +/* seriously ?! @#$%% */ +# define uint32_t CARD32 +# define uint64_t CARD64 + +static void +R600DoneTexturedVideo(ScrnInfoPtr pScrn) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + draw_config_t draw_conf; + vtx_resource_t vtx_res; + + CLEAR (draw_conf); + CLEAR (vtx_res); + + if (accel_state->vb_index == 0) { + R600IBDiscard(pScrn, accel_state->ib); + return; + } + + accel_state->vb_mc_addr = RHDDRIGetIntGARTLocation(pScrn) + + (accel_state->ib->idx * accel_state->ib->total) + (accel_state->ib->total / 2); + accel_state->vb_size = accel_state->vb_index * 16; + + /* flush vertex cache */ + if ((rhdPtr->ChipSet == RHD_RV610) || + (rhdPtr->ChipSet == RHD_RV620) || + (rhdPtr->ChipSet == RHD_M72) || + (rhdPtr->ChipSet == RHD_M74) || + (rhdPtr->ChipSet == RHD_M82) || + (rhdPtr->ChipSet == RHD_RS780) || + (rhdPtr->ChipSet == RHD_RV710)) + cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, + accel_state->vb_size, accel_state->vb_mc_addr); + else + cp_set_surface_sync(pScrn, accel_state->ib, VC_ACTION_ENA_bit, + accel_state->vb_size, accel_state->vb_mc_addr); + + /* Vertex buffer setup */ + vtx_res.id = SQ_VTX_RESOURCE_vs; + vtx_res.vtx_size_dw = 16 / 4; + vtx_res.vtx_num_entries = accel_state->vb_size / 4; + vtx_res.mem_req_size = 1; + vtx_res.vb_addr = accel_state->vb_mc_addr; + set_vtx_resource (pScrn, accel_state->ib, &vtx_res); + + draw_conf.prim_type = DI_PT_RECTLIST; + draw_conf.vgt_draw_initiator = DI_SRC_SEL_AUTO_INDEX; + draw_conf.num_instances = 1; + draw_conf.num_indices = vtx_res.vtx_num_entries / vtx_res.vtx_size_dw; + draw_conf.index_type = DI_INDEX_SIZE_16_BIT; + + draw_auto(pScrn, accel_state->ib, &draw_conf); + + wait_3d_idle_clean(pScrn, accel_state->ib); + + /* sync destination surface */ + cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit), + accel_state->dst_size, accel_state->dst_mc_addr); + + R600CPFlushIndirect(pScrn, accel_state->ib); +} + +void +R600DisplayTexturedVideo(ScrnInfoPtr pScrn, struct RHDPortPriv *pPriv) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + PixmapPtr pPixmap = pPriv->pPixmap; + BoxPtr pBox = REGION_RECTS(&pPriv->clip); + int nBox = REGION_NUM_RECTS(&pPriv->clip); + int dstxoff, dstyoff; + cb_config_t cb_conf; + tex_resource_t tex_res; + tex_sampler_t tex_samp; + shader_config_t vs_conf, ps_conf; + int uv_offset; + + static float ps_alu_consts[] = { + 1.0, 0.0, 1.4020, 0, // r - c[0] + 1.0, -0.34414, -0.71414, 0, // g - c[1] + 1.0, 1.7720, 0.0, 0, // b - c[2] + /* Constants for undoing Y'CbCr scaling + * - Y' is scaled from 16:235 + * - Cb/Cr are scaled from 16:240 + * Unscaled value N' = N * N_mul + N_shift (N' in range [-0.5, 0.5]) + * Vector is [Y_mul, Y_shfit, C_mul, C_shift] + */ + 256.0/219.0, -16.0/219.0, 256.0/224.0, -128.0/224.0, + }; + + CLEAR (cb_conf); + CLEAR (tex_res); + CLEAR (tex_samp); + CLEAR (vs_conf); + CLEAR (ps_conf); + + accel_state->dst_pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8); + accel_state->src_pitch[0] = pPriv->BufferPitch; + + // bad pitch + if (accel_state->src_pitch[0] & 7) + return; + if (accel_state->dst_pitch & 7) + return; + +#ifdef COMPOSITE + dstxoff = -pPixmap->screen_x + pPixmap->drawable.x; + dstyoff = -pPixmap->screen_y + pPixmap->drawable.y; +#else + dstxoff = 0; + dstyoff = 0; +#endif + + accel_state->ib = RHDDRMCPBuffer(pScrn->scrnIndex); + + /* Init */ + start_3d(pScrn, accel_state->ib); + + //cp_set_surface_sync(pScrn, accel_state->ib); + + set_default_state(pScrn, accel_state->ib); + + /* Scissor / viewport */ + EREG(accel_state->ib, PA_CL_VTE_CNTL, VTX_XY_FMT_bit); + EREG(accel_state->ib, PA_CL_CLIP_CNTL, CLIP_DISABLE_bit); + + accel_state->vs_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset + + accel_state->xv_vs_offset; + + accel_state->ps_mc_addr = rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart + accel_state->shaders->offset + + accel_state->xv_ps_offset; + + switch(pPriv->id) { + case FOURCC_YV12: + case FOURCC_I420: + set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0)); + break; + case FOURCC_UYVY: + case FOURCC_YUY2: + default: + set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0)); + break; + } + + accel_state->vs_size = 512; + accel_state->ps_size = 512; + + /* Shader */ + + /* flush SQ cache */ + cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit, + accel_state->vs_size, accel_state->vs_mc_addr); + + vs_conf.shader_addr = accel_state->vs_mc_addr; + vs_conf.num_gprs = 2; + vs_conf.stack_size = 0; + vs_setup (pScrn, accel_state->ib, &vs_conf); + + /* flush SQ cache */ + cp_set_surface_sync(pScrn, accel_state->ib, SH_ACTION_ENA_bit, + accel_state->ps_size, accel_state->ps_mc_addr); + + ps_conf.shader_addr = accel_state->ps_mc_addr; + ps_conf.num_gprs = 3; + ps_conf.stack_size = 1; + ps_conf.uncached_first_inst = 1; + ps_conf.clamp_consts = 0; + ps_conf.export_mode = 2; + ps_setup (pScrn, accel_state->ib, &ps_conf); + + // PS alu constants + set_alu_consts(pScrn, accel_state->ib, 0, sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); + + /* Texture */ + switch(pPriv->id) { + case FOURCC_YV12: + case FOURCC_I420: + accel_state->src_mc_addr[0] = pPriv->BufferOffset + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + accel_state->src_size[0] = accel_state->src_pitch[0] * pPriv->h; + + /* flush texture cache */ + cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0], + accel_state->src_mc_addr[0]); + + // Y texture + tex_res.id = 0; + tex_res.w = pPriv->w; + tex_res.h = pPriv->h; + tex_res.pitch = accel_state->src_pitch[0]; + tex_res.depth = 0; + tex_res.dim = SQ_TEX_DIM_2D; + tex_res.base = accel_state->src_mc_addr[0]; + tex_res.mip_base = accel_state->src_mc_addr[0]; + + tex_res.format = FMT_8; + tex_res.dst_sel_x = SQ_SEL_X; //Y + tex_res.dst_sel_y = SQ_SEL_1; + tex_res.dst_sel_z = SQ_SEL_1; + tex_res.dst_sel_w = SQ_SEL_1; + + tex_res.request_size = 1; + tex_res.base_level = 0; + tex_res.last_level = 0; + tex_res.perf_modulation = 0; + tex_res.interlaced = 0; + set_tex_resource (pScrn, accel_state->ib, &tex_res); + + // Y sampler + tex_samp.id = 0; + tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; + tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; + tex_samp.clamp_z = SQ_TEX_WRAP; + + + // UV texture + uv_offset = accel_state->src_pitch[0] * pPriv->h; + uv_offset = (uv_offset + 255) & ~255; + + cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, + accel_state->src_size[0] / 4, + accel_state->src_mc_addr[0] + uv_offset); + + tex_res.id = 1; + tex_res.format = FMT_8; + tex_res.w = pPriv->w >> 1; + tex_res.h = pPriv->h >> 1; + tex_res.pitch = accel_state->src_pitch[0] >> 1; + tex_res.dst_sel_x = SQ_SEL_X; //V or U + tex_res.dst_sel_y = SQ_SEL_1; + tex_res.dst_sel_z = SQ_SEL_1; + tex_res.dst_sel_w = SQ_SEL_1; + tex_res.interlaced = 0; + // XXX tex bases need to be 256B aligned + tex_res.base = accel_state->src_mc_addr[0] + uv_offset; + tex_res.mip_base = accel_state->src_mc_addr[0] + uv_offset; + set_tex_resource (pScrn, accel_state->ib, &tex_res); + + // xxx: switch to bicubic + tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; + tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; + + tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; + tex_samp.mip_filter = 0; /* no mipmap */ + set_tex_sampler (pScrn, accel_state->ib, &tex_samp); + + // UV sampler + tex_samp.id = 1; + set_tex_sampler (pScrn, accel_state->ib, &tex_samp); + + // UV texture + uv_offset += ((accel_state->src_pitch[0] >> 1) * (pPriv->h >> 1)); + uv_offset = (uv_offset + 255) & ~255; + + cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, + accel_state->src_size[0] / 4, + accel_state->src_mc_addr[0] + uv_offset); + + tex_res.id = 2; + tex_res.format = FMT_8; + tex_res.w = pPriv->w >> 1; + tex_res.h = pPriv->h >> 1; + tex_res.pitch = accel_state->src_pitch[0] >> 1; + tex_res.dst_sel_x = SQ_SEL_X; //V or U + tex_res.dst_sel_y = SQ_SEL_1; + tex_res.dst_sel_z = SQ_SEL_1; + tex_res.dst_sel_w = SQ_SEL_1; + tex_res.interlaced = 0; + // XXX tex bases need to be 256B aligned + tex_res.base = accel_state->src_mc_addr[0] + uv_offset; + tex_res.mip_base = accel_state->src_mc_addr[0] + uv_offset; + set_tex_resource (pScrn, accel_state->ib, &tex_res); + + // xxx: switch to bicubic + tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; + tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; + + tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; + tex_samp.mip_filter = 0; /* no mipmap */ + set_tex_sampler (pScrn, accel_state->ib, &tex_samp); + + // UV sampler + tex_samp.id = 2; + set_tex_sampler (pScrn, accel_state->ib, &tex_samp); + break; + case FOURCC_UYVY: + case FOURCC_YUY2: + default: + accel_state->src_mc_addr[0] = pPriv->BufferOffset + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + accel_state->src_size[0] = accel_state->src_pitch[0] * pPriv->h; + + /* flush texture cache */ + cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0], + accel_state->src_mc_addr[0]); + + // Y texture + tex_res.id = 0; + tex_res.w = pPriv->w; + tex_res.h = pPriv->h; + tex_res.pitch = accel_state->src_pitch[0] >> 1; + tex_res.depth = 0; + tex_res.dim = SQ_TEX_DIM_2D; + tex_res.base = accel_state->src_mc_addr[0]; + tex_res.mip_base = accel_state->src_mc_addr[0]; + + tex_res.format = FMT_8_8; + if (pPriv->id == FOURCC_UYVY) + tex_res.dst_sel_x = SQ_SEL_Y; //Y + else + tex_res.dst_sel_x = SQ_SEL_X; //Y + tex_res.dst_sel_y = SQ_SEL_1; + tex_res.dst_sel_z = SQ_SEL_1; + tex_res.dst_sel_w = SQ_SEL_1; + + tex_res.request_size = 1; + tex_res.base_level = 0; + tex_res.last_level = 0; + tex_res.perf_modulation = 0; + tex_res.interlaced = 0; + set_tex_resource (pScrn, accel_state->ib, &tex_res); + + // Y sampler + tex_samp.id = 0; + tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; + tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; + tex_samp.clamp_z = SQ_TEX_WRAP; + + + // UV texture + tex_res.id = 1; + tex_res.format = FMT_8_8_8_8; + tex_res.w = pPriv->w >> 1; + tex_res.h = pPriv->h; + tex_res.pitch = accel_state->src_pitch[0] >> 2; + if (pPriv->id == FOURCC_UYVY) { + tex_res.dst_sel_x = SQ_SEL_X; //V + tex_res.dst_sel_y = SQ_SEL_Z; //U + } else { + tex_res.dst_sel_x = SQ_SEL_Y; //V + tex_res.dst_sel_y = SQ_SEL_W; //U + } + tex_res.dst_sel_z = SQ_SEL_1; + tex_res.dst_sel_w = SQ_SEL_1; + tex_res.interlaced = 0; + // XXX tex bases need to be 256B aligned + tex_res.base = accel_state->src_mc_addr[0]; + tex_res.mip_base = accel_state->src_mc_addr[0]; + set_tex_resource (pScrn, accel_state->ib, &tex_res); + + // xxx: switch to bicubic + tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; + tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; + + tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; + tex_samp.mip_filter = 0; /* no mipmap */ + set_tex_sampler (pScrn, accel_state->ib, &tex_samp); + + // UV sampler + tex_samp.id = 1; + set_tex_sampler (pScrn, accel_state->ib, &tex_samp); + break; + } + + /* Render setup */ + EREG(accel_state->ib, CB_SHADER_MASK, (0x0f << OUTPUT0_ENABLE_shift)); + EREG(accel_state->ib, R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit)); + EREG(accel_state->ib, CB_COLOR_CONTROL, (0xcc << ROP3_shift)); /* copy */ + + cb_conf.id = 0; + + accel_state->dst_mc_addr = exaGetPixmapOffset(pPixmap) + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart; + + cb_conf.w = accel_state->dst_pitch; + cb_conf.h = pPixmap->drawable.height; + cb_conf.base = accel_state->dst_mc_addr; + + switch (pPixmap->drawable.bitsPerPixel) { + case 16: + if (pPixmap->drawable.depth == 15) { + cb_conf.format = COLOR_1_5_5_5; + cb_conf.comp_swap = 1; //ARGB + } else { + cb_conf.format = COLOR_5_6_5; + cb_conf.comp_swap = 2; //RGB + } + break; + case 32: + cb_conf.format = COLOR_8_8_8_8; + cb_conf.comp_swap = 1; //ARGB + break; + default: + return; + } + + cb_conf.source_format = 1; + cb_conf.blend_clamp = 1; + set_render_target(pScrn, accel_state->ib, &cb_conf); + + EREG(accel_state->ib, PA_SU_SC_MODE_CNTL, (FACE_bit | + (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) | + (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift))); + EREG(accel_state->ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */ + DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */ + + /* Interpolator setup */ + // export tex coords from VS + EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift)); + EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift)); + + /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x + * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */ + EREG(accel_state->ib, SPI_PS_IN_CONTROL_0, ((1 << NUM_INTERP_shift))); + EREG(accel_state->ib, SPI_PS_IN_CONTROL_1, 0); + EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 <<2), ((0 << SEMANTIC_shift) | + (0x03 << DEFAULT_VAL_shift) | + SEL_CENTROID_bit)); + EREG(accel_state->ib, SPI_INTERP_CONTROL_0, 0); + + if (exaGetPixmapOffset(pPixmap) == 0) + wait_vline_range( + pScrn, + accel_state->ib, + 0 /* TODO */, + dstyoff + pPriv->drw_y, + dstyoff + pPriv->drw_y + pPriv->dst_h - 1 + ); + + accel_state->vb_index = 0; + + while (nBox--) { + int srcX, srcY, srcw, srch; + int dstX, dstY, dstw, dsth; + float *vb; + + if (((accel_state->vb_index + 3) * 16) > (accel_state->ib->total / 2)) { + R600DoneTexturedVideo(pScrn); + accel_state->vb_index = 0; + accel_state->ib = RHDDRMCPBuffer(pScrn->scrnIndex); + } + + vb = (pointer)((char*)accel_state->ib->address + + (accel_state->ib->total / 2) + + accel_state->vb_index * 16); + + dstX = pBox->x1 + dstxoff; + dstY = pBox->y1 + dstyoff; + dstw = pBox->x2 - pBox->x1; + dsth = pBox->y2 - pBox->y1; + + srcX = ((pBox->x1 - pPriv->drw_x) * + pPriv->src_w) / pPriv->dst_w; + srcY = ((pBox->y1 - pPriv->drw_y) * + pPriv->src_h) / pPriv->dst_h; + + srcw = (pPriv->src_w * dstw) / pPriv->dst_w; + srch = (pPriv->src_h * dsth) / pPriv->dst_h; + + vb[0] = (float)dstX; + vb[1] = (float)dstY; + vb[2] = (float)srcX / pPriv->w; + vb[3] = (float)srcY / pPriv->h; + + vb[4] = (float)dstX; + vb[5] = (float)(dstY + dsth); + vb[6] = (float)srcX / pPriv->w; + vb[7] = (float)(srcY + srch) / pPriv->h; + + vb[8] = (float)(dstX + dstw); + vb[9] = (float)(dstY + dsth); + vb[10] = (float)(srcX + srcw) / pPriv->w; + vb[11] = (float)(srcY + srch) / pPriv->h; + + accel_state->vb_index += 3; + + pBox++; + } + + R600DoneTexturedVideo(pScrn); + + DamageDamageRegion(pPriv->pDraw, &pPriv->clip); +} diff --git a/driver/xf86-video-radeonhd/src/r6xx_accel.c b/driver/xf86-video-radeonhd/src/r6xx_accel.c new file mode 100644 index 000000000..ae9a15c7c --- /dev/null +++ b/driver/xf86-video-radeonhd/src/r6xx_accel.c @@ -0,0 +1,1233 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: Alex Deucher <alexander.deucher@amd.com> + * Matthias Hopf <mhopf@suse.de> + */ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "xf86.h" + +#include <errno.h> + +/* for usleep */ +#if HAVE_XF86_ANSIC_H +# include "xf86_ansic.h" +#else +# include <unistd.h> +#endif + +#include "rhd.h" +#include "rhd_regs.h" +#include "rhd_crtc.h" +#include "rhd_cs.h" +#include "r6xx_accel.h" +#include "r600_shader.h" +#include "r600_reg.h" +#include "r600_state.h" + +#include "xf86drm.h" +/* Workaround for header mismatches */ +#ifndef DEPRECATED +# define DEPRECATED __attribute__ ((deprecated)) +# define __user +#endif +#include "radeon_drm.h" + + +/* seriously ?! @#$%% */ +# define uint32_t CARD32 +# define uint64_t CARD64 + + +/* Flush the indirect buffer to the kernel for submission to the card */ +void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib) +{ +// RHDPtr rhdPtr = RHDPTR(pScrn); + drmBufPtr buffer = ib; + int start = 0; + drm_radeon_indirect_t indirect; + int drmFD = RHDDRMFDGet(pScrn->scrnIndex); + + if (!buffer) return; + + //xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Flushing buffer %d\n", + // buffer->idx); + + while (buffer->used & 0x3c){ + E32(buffer, CP_PACKET2()); /* fill up to multiple of 16 dwords */ + } + + //ErrorF("buffer bytes: %d\n", buffer->used); + + indirect.idx = buffer->idx; + indirect.start = start; + indirect.end = buffer->used; + indirect.discard = 1; + + drmCommandWriteRead(drmFD, DRM_RADEON_INDIRECT, + &indirect, sizeof(drm_radeon_indirect_t)); + +} + +void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib) +{ + if (!ib) return; + + ib->used = 0; + R600CPFlushIndirect(pScrn, ib); +} + +void +wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib) +{ +// RHDPtr rhdPtr = RHDPTR(pScrn); + + //flush caches, don't generate timestamp + PACK3(ib, IT_EVENT_WRITE, 1); + E32(ib, CACHE_FLUSH_AND_INV_EVENT); + // wait for 3D idle clean + EREG(ib, WAIT_UNTIL, (WAIT_3D_IDLE_bit | + WAIT_3D_IDLECLEAN_bit)); +} + +void +wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib) +{ +// RHDPtr rhdPtr = RHDPTR(pScrn); + + EREG(ib, WAIT_UNTIL, WAIT_3D_IDLE_bit); + +} + +/* + * inserts a wait for vline in the command stream + */ +void +wait_vline_range(ScrnInfoPtr pScrn, drmBufPtr ib, int crtc, int start, int stop) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + struct rhdCrtc *rhdCrtc; + + if ((crtc < 0) || (crtc > 1)) + return; + + rhdCrtc = rhdPtr->Crtc[crtc]; + if(!rhdCrtc || !rhdCrtc->CurrentMode) + return; + + start = max(start, 0); + stop = min(stop, rhdCrtc->CurrentMode->VDisplay-1); + +#if 0 + ErrorF("wait_vline_range: start %d stop %d\n", start, stop); +#endif + + if (stop <= start) + return; + + /* set the VLINE range */ + if(crtc == 0) + EREG(ib, D1MODE_VLINE_START_END, start | (stop << 16)); + else + EREG(ib, D2MODE_VLINE_START_END, start | (stop << 16)); + + /* tell the CP to poll the VLINE state register */ + PACK3(ib, IT_WAIT_REG_MEM, 6); + E32(ib, WAIT_REG | WAIT_EQ); + if(crtc == 0) + E32(ib, D1MODE_VLINE_STATUS >> 2); + else + E32(ib, D2MODE_VLINE_STATUS >> 2); + E32(ib, 0); + E32(ib, 0); // Ref value + E32(ib, 0x1000); // Mask + E32(ib, 10); // Wait interval +} + +static void +reset_cb(ScrnInfoPtr pScrn, drmBufPtr ib) +{ + int i; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + PACK0(ib, CB_COLOR0_INFO, 8); + for (i = 0; i < 8; i++) + E32(ib, 0); +} + +static void +reset_td_samplers(ScrnInfoPtr pScrn, drmBufPtr ib) +{ + int i; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + wait_3d_idle(pScrn, ib); + + PACK0(ib, TD_PS_SAMPLER0_BORDER_RED, 4*TD_PS_SAMPLER0_BORDER_RED_num); + for (i = 0; i < 4*TD_PS_SAMPLER0_BORDER_RED_num; i++) + E32(ib, 0); + PACK0(ib, TD_VS_SAMPLER0_BORDER_RED, 4*TD_VS_SAMPLER0_BORDER_RED_num); + for (i = 0; i < 4*TD_VS_SAMPLER0_BORDER_RED_num; i++) + E32(ib, 0); + + wait_3d_idle(pScrn, ib); +} + +static void +reset_sampler_const (ScrnInfoPtr pScrn, drmBufPtr ib) +{ + int i; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + for (i = 0; i < SQ_TEX_SAMPLER_WORD_all_num; i++) { + PACK0 (ib, SQ_TEX_SAMPLER_WORD + i * SQ_TEX_SAMPLER_WORD_offset, 3); + E32 (ib, SQ_TEX_DEPTH_COMPARE_LESSEQUAL << DEPTH_COMPARE_FUNCTION_shift); + E32 (ib, MAX_LOD_mask); + E32 (ib, 0); + } +} + +static void +reset_dx9_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib) +{ + int i; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + const int count = SQ_ALU_CONSTANT_all_num * (SQ_ALU_CONSTANT_offset >> 2); + + PACK0(ib, SQ_ALU_CONSTANT, count); + for (i = 0; i < count; i++) + EFLOAT(ib, 0.0); +} + +static void +reset_bool_loop_const(ScrnInfoPtr pScrn, drmBufPtr ib) +{ + int i; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + PACK0(ib, SQ_BOOL_CONST, SQ_BOOL_CONST_all_num); + for (i = 0; i < SQ_BOOL_CONST_all_num; i++) + E32(ib, 0); + + PACK0(ib, SQ_LOOP_CONST, SQ_LOOP_CONST_all_num); + + for (i = 0; i < SQ_LOOP_CONST_all_num; i++) + E32(ib, 0); + +} + +void +start_3d(ScrnInfoPtr pScrn, drmBufPtr ib) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + + if (rhdPtr->ChipSet < RHD_RV770) { + PACK3(ib, IT_START_3D_CMDBUF, 1); + E32(ib, 0); + } + + PACK3(ib, IT_CONTEXT_CONTROL, 2); + E32(ib, 0x80000000); + E32(ib, 0x80000000); + + wait_3d_idle_clean (pScrn, ib); +} + +/* + * Setup of functional groups + */ + +// asic stack/thread/gpr limits - need to query the drm +static void +sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf) +{ + uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; + uint32_t sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; + RHDPtr rhdPtr = RHDPTR(pScrn); + + if ((rhdPtr->ChipSet == RHD_RV610) || + (rhdPtr->ChipSet == RHD_RV620) || + (rhdPtr->ChipSet == RHD_M72) || + (rhdPtr->ChipSet == RHD_M74) || + (rhdPtr->ChipSet == RHD_M82) || + (rhdPtr->ChipSet == RHD_RS780) || + (rhdPtr->ChipSet == RHD_RV710)) + sq_config = 0; // no VC + else + sq_config = VC_ENABLE_bit; + + sq_config |= (DX9_CONSTS_bit | + ALU_INST_PREFER_VECTOR_bit | + (sq_conf->ps_prio << PS_PRIO_shift) | + (sq_conf->vs_prio << VS_PRIO_shift) | + (sq_conf->gs_prio << GS_PRIO_shift) | + (sq_conf->es_prio << ES_PRIO_shift)); + + sq_gpr_resource_mgmt_1 = ((sq_conf->num_ps_gprs << NUM_PS_GPRS_shift) | + (sq_conf->num_vs_gprs << NUM_VS_GPRS_shift) | + (sq_conf->num_temp_gprs << NUM_CLAUSE_TEMP_GPRS_shift)); + sq_gpr_resource_mgmt_2 = ((sq_conf->num_gs_gprs << NUM_GS_GPRS_shift) | + (sq_conf->num_es_gprs << NUM_ES_GPRS_shift)); + + sq_thread_resource_mgmt = ((sq_conf->num_ps_threads << NUM_PS_THREADS_shift) | + (sq_conf->num_vs_threads << NUM_VS_THREADS_shift) | + (sq_conf->num_gs_threads << NUM_GS_THREADS_shift) | + (sq_conf->num_es_threads << NUM_ES_THREADS_shift)); + + sq_stack_resource_mgmt_1 = ((sq_conf->num_ps_stack_entries << NUM_PS_STACK_ENTRIES_shift) | + (sq_conf->num_vs_stack_entries << NUM_VS_STACK_ENTRIES_shift)); + + sq_stack_resource_mgmt_2 = ((sq_conf->num_gs_stack_entries << NUM_GS_STACK_ENTRIES_shift) | + (sq_conf->num_es_stack_entries << NUM_ES_STACK_ENTRIES_shift)); + + PACK0(ib, SQ_CONFIG, 6); + E32(ib, sq_config); + E32(ib, sq_gpr_resource_mgmt_1); + E32(ib, sq_gpr_resource_mgmt_2); + E32(ib, sq_thread_resource_mgmt); + E32(ib, sq_stack_resource_mgmt_1); + E32(ib, sq_stack_resource_mgmt_2); + +} + +void +set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf) +{ + uint32_t cb_color_info; + int pitch, slice, h; + RHDPtr rhdPtr = RHDPTR(pScrn); + + cb_color_info = ((cb_conf->endian << ENDIAN_shift) | + (cb_conf->format << CB_COLOR0_INFO__FORMAT_shift) | + (cb_conf->array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) | + (cb_conf->number_type << NUMBER_TYPE_shift) | + (cb_conf->comp_swap << COMP_SWAP_shift) | + (cb_conf->tile_mode << CB_COLOR0_INFO__TILE_MODE_shift)); + if (cb_conf->read_size) + cb_color_info |= CB_COLOR0_INFO__READ_SIZE_bit; + if (cb_conf->blend_clamp) + cb_color_info |= BLEND_CLAMP_bit; + if (cb_conf->clear_color) + cb_color_info |= CLEAR_COLOR_bit; + if (cb_conf->blend_bypass) + cb_color_info |= BLEND_BYPASS_bit; + if (cb_conf->blend_float32) + cb_color_info |= BLEND_FLOAT32_bit; + if (cb_conf->simple_float) + cb_color_info |= SIMPLE_FLOAT_bit; + if (cb_conf->round_mode) + cb_color_info |= CB_COLOR0_INFO__ROUND_MODE_bit; + if (cb_conf->tile_compact) + cb_color_info |= TILE_COMPACT_bit; + if (cb_conf->source_format) + cb_color_info |= SOURCE_FORMAT_bit; + + pitch = (cb_conf->w / 8) - 1; + h = (cb_conf->h + 7) & ~7; + slice = ((cb_conf->w * h) / 64) - 1; + + EREG(ib, (CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8)); + + // rv6xx workaround + if ((rhdPtr->ChipSet > RHD_R600) && + (rhdPtr->ChipSet < RHD_RV770)) { + PACK3(ib, IT_SURFACE_BASE_UPDATE, 1); + E32(ib, (2 << cb_conf->id)); + } + + // pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib + EREG(ib, (CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << PITCH_TILE_MAX_shift) | + (slice << SLICE_TILE_MAX_shift))); + EREG(ib, (CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0 << SLICE_START_shift) | + (0 << SLICE_MAX_shift))); + EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info); + EREG(ib, (CB_COLOR0_TILE + (4 * cb_conf->id)), (0 >> 8)); // CMASK per-tile data base/256 + EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256 + EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0 << CMASK_BLOCK_MAX_shift) | + (0 << FMASK_TILE_MAX_shift))); +} + +void +cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr) +{ +// RHDPtr rhdPtr = RHDPTR(pScrn); + + uint32_t cp_coher_size; + if (size == 0xffffffff) + cp_coher_size = 0xffffffff; + else + cp_coher_size = ((size + 255) >> 8); + + PACK3(ib, IT_SURFACE_SYNC, 4); + E32(ib, sync_type); + E32(ib, cp_coher_size); + E32(ib, (mc_addr >> 8)); + E32(ib, 10); /* poll interval */ +} + +void +fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf) +{ + uint32_t sq_pgm_resources; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + sq_pgm_resources = ((fs_conf->num_gprs << NUM_GPRS_shift) | + (fs_conf->stack_size << STACK_SIZE_shift)); + + if (fs_conf->dx10_clamp) + sq_pgm_resources |= SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit; + + EREG(ib, SQ_PGM_START_FS, fs_conf->shader_addr >> 8); + EREG(ib, SQ_PGM_RESOURCES_FS, sq_pgm_resources); + EREG(ib, SQ_PGM_CF_OFFSET_FS, 0); +} + +void +vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf) +{ + uint32_t sq_pgm_resources; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + sq_pgm_resources = ((vs_conf->num_gprs << NUM_GPRS_shift) | + (vs_conf->stack_size << STACK_SIZE_shift)); + + if (vs_conf->dx10_clamp) + sq_pgm_resources |= SQ_PGM_RESOURCES_VS__DX10_CLAMP_bit; + if (vs_conf->fetch_cache_lines) + sq_pgm_resources |= (vs_conf->fetch_cache_lines << FETCH_CACHE_LINES_shift); + if (vs_conf->uncached_first_inst) + sq_pgm_resources |= UNCACHED_FIRST_INST_bit; + + EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8); + EREG(ib, SQ_PGM_RESOURCES_VS, sq_pgm_resources); + EREG(ib, SQ_PGM_CF_OFFSET_VS, 0); +} + +void +ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf) +{ + uint32_t sq_pgm_resources; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + sq_pgm_resources = ((ps_conf->num_gprs << NUM_GPRS_shift) | + (ps_conf->stack_size << STACK_SIZE_shift)); + + if (ps_conf->dx10_clamp) + sq_pgm_resources |= SQ_PGM_RESOURCES_PS__DX10_CLAMP_bit; + if (ps_conf->fetch_cache_lines) + sq_pgm_resources |= (ps_conf->fetch_cache_lines << FETCH_CACHE_LINES_shift); + if (ps_conf->uncached_first_inst) + sq_pgm_resources |= UNCACHED_FIRST_INST_bit; + if (ps_conf->clamp_consts) + sq_pgm_resources |= CLAMP_CONSTS_bit; + + EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8); + EREG(ib, SQ_PGM_RESOURCES_PS, sq_pgm_resources); + EREG(ib, SQ_PGM_EXPORTS_PS, ps_conf->export_mode); + EREG(ib, SQ_PGM_CF_OFFSET_PS, 0); +} + +void +set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf) +{ + int i; + const int countreg = count * (SQ_ALU_CONSTANT_offset >> 2); +// RHDPtr rhdPtr = RHDPTR(pScrn); + + PACK0(ib, SQ_ALU_CONSTANT + offset * SQ_ALU_CONSTANT_offset, countreg); + for (i = 0; i < countreg; i++) + EFLOAT(ib, const_buf[i]); +} + +void +set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val) +{ + /* bool register order is: ps, vs, gs; one register each + * 1 bits per bool; 32 bools each for ps, vs, gs. + */ + EREG(ib, SQ_BOOL_CONST + offset * SQ_BOOL_CONST_offset, val); +} + +void +set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res) +{ + uint32_t sq_vtx_constant_word2; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + sq_vtx_constant_word2 = ((((res->vb_addr) >> 32) & BASE_ADDRESS_HI_mask) | + ((res->vtx_size_dw << 2) << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift) | + (res->format << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift) | + (res->num_format_all << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift) | + (res->endian << SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift)); + if (res->clamp_x) + sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit; + + if (res->format_comp_all) + sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; + + if (res->srf_mode_all) + sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit; + + PACK0(ib, SQ_VTX_RESOURCE + res->id * SQ_VTX_RESOURCE_offset, 7); + E32(ib, res->vb_addr & 0xffffffff); // 0: BASE_ADDRESS + E32(ib, (res->vtx_num_entries << 2) - 1); // 1: SIZE + E32(ib, sq_vtx_constant_word2); // 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN + E32(ib, res->mem_req_size << MEM_REQUEST_SIZE_shift); // 3: MEM_REQUEST_SIZE ?!? + E32(ib, 0); // 4: n/a + E32(ib, 0); // 5: n/a + E32(ib, SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD6_0__TYPE_shift); // 6: TYPE +} + +void +set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res) +{ + uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; + uint32_t sq_tex_resource_word5, sq_tex_resource_word6; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + sq_tex_resource_word0 = ((tex_res->dim << DIM_shift) | + (tex_res->tile_mode << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift)); + + if (tex_res->w) + sq_tex_resource_word0 |= (((((tex_res->pitch + 7) >> 3) - 1) << PITCH_shift) | + ((tex_res->w - 1) << TEX_WIDTH_shift)); + + if (tex_res->tile_type) + sq_tex_resource_word0 |= TILE_TYPE_bit; + + sq_tex_resource_word1 = (tex_res->format << SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift); + + if (tex_res->h) + sq_tex_resource_word1 |= ((tex_res->h - 1) << TEX_HEIGHT_shift); + if (tex_res->depth) + sq_tex_resource_word1 |= ((tex_res->depth - 1) << TEX_DEPTH_shift); + + sq_tex_resource_word4 = ((tex_res->format_comp_x << FORMAT_COMP_X_shift) | + (tex_res->format_comp_y << FORMAT_COMP_Y_shift) | + (tex_res->format_comp_z << FORMAT_COMP_Z_shift) | + (tex_res->format_comp_w << FORMAT_COMP_W_shift) | + (tex_res->num_format_all << SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift) | + (tex_res->endian << SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift) | + (tex_res->request_size << REQUEST_SIZE_shift) | + (tex_res->dst_sel_x << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) | + (tex_res->dst_sel_y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) | + (tex_res->dst_sel_z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) | + (tex_res->dst_sel_w << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift) | + (tex_res->base_level << BASE_LEVEL_shift)); + + if (tex_res->srf_mode_all) + sq_tex_resource_word4 |= SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit; + if (tex_res->force_degamma) + sq_tex_resource_word4 |= SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit; + + sq_tex_resource_word5 = ((tex_res->last_level << LAST_LEVEL_shift) | + (tex_res->base_array << BASE_ARRAY_shift) | + (tex_res->last_array << LAST_ARRAY_shift)); + + sq_tex_resource_word6 = ((tex_res->mpeg_clamp << MPEG_CLAMP_shift) | + (tex_res->perf_modulation << PERF_MODULATION_shift) | + (SQ_TEX_VTX_VALID_TEXTURE << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift)); + + if (tex_res->interlaced) + sq_tex_resource_word6 |= INTERLACED_bit; + + PACK0(ib, SQ_TEX_RESOURCE + tex_res->id * SQ_TEX_RESOURCE_offset, 7); + E32(ib, sq_tex_resource_word0); + E32(ib, sq_tex_resource_word1); + E32(ib, ((tex_res->base) >> 8)); + E32(ib, ((tex_res->mip_base) >> 8)); + E32(ib, sq_tex_resource_word4); + E32(ib, sq_tex_resource_word5); + E32(ib, sq_tex_resource_word6); +} + +void +set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s) +{ + uint32_t sq_tex_sampler_word0, sq_tex_sampler_word1, sq_tex_sampler_word2; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + sq_tex_sampler_word0 = ((s->clamp_x << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift) | + (s->clamp_y << CLAMP_Y_shift) | + (s->clamp_z << CLAMP_Z_shift) | + (s->xy_mag_filter << XY_MAG_FILTER_shift) | + (s->xy_min_filter << XY_MIN_FILTER_shift) | + (s->z_filter << Z_FILTER_shift) | + (s->mip_filter << MIP_FILTER_shift) | + (s->border_color << BORDER_COLOR_TYPE_shift) | + (s->depth_compare << DEPTH_COMPARE_FUNCTION_shift) | + (s->chroma_key << CHROMA_KEY_shift)); + if (s->point_sampling_clamp) + sq_tex_sampler_word0 |= POINT_SAMPLING_CLAMP_bit; + if (s->tex_array_override) + sq_tex_sampler_word0 |= TEX_ARRAY_OVERRIDE_bit; + if (s->lod_uses_minor_axis) + sq_tex_sampler_word0 |= LOD_USES_MINOR_AXIS_bit; + + sq_tex_sampler_word1 = ((s->min_lod << MIN_LOD_shift) | + (s->max_lod << MAX_LOD_shift) | + (s->lod_bias << SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift)); + + sq_tex_sampler_word2 = ((s->lod_bias2 << LOD_BIAS_SEC_shift) | + (s->perf_mip << PERF_MIP_shift) | + (s->perf_z << PERF_Z_shift)); + if (s->mc_coord_truncate) + sq_tex_sampler_word2 |= MC_COORD_TRUNCATE_bit; + if (s->force_degamma) + sq_tex_sampler_word2 |= SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit; + if (s->high_precision_filter) + sq_tex_sampler_word2 |= HIGH_PRECISION_FILTER_bit; + if (s->fetch_4) + sq_tex_sampler_word2 |= FETCH_4_bit; + if (s->sample_is_pcf) + sq_tex_sampler_word2 |= SAMPLE_IS_PCF_bit; + if (s->type) + sq_tex_sampler_word2 |= SQ_TEX_SAMPLER_WORD2_0__TYPE_bit; + + PACK0(ib, SQ_TEX_SAMPLER_WORD + s->id * SQ_TEX_SAMPLER_WORD_offset, 3); + E32(ib, sq_tex_sampler_word0); + E32(ib, sq_tex_sampler_word1); + E32(ib, sq_tex_sampler_word2); +} + +//XXX deal with clip offsets in clip setup +void +set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2) +{ +// RHDPtr rhdPtr = RHDPTR(pScrn); + + EREG(ib, PA_SC_SCREEN_SCISSOR_TL, ((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) | + (y1 << PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift))); + EREG(ib, PA_SC_SCREEN_SCISSOR_BR, ((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) | + (y2 << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift))); +} + +void +set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2) +{ +// RHDPtr rhdPtr = RHDPTR(pScrn); + + EREG(ib, PA_SC_VPORT_SCISSOR_0_TL + + id * PA_SC_VPORT_SCISSOR_0_TL_offset, ((x1 << PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift) | + (y1 << PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift) | + WINDOW_OFFSET_DISABLE_bit)); + EREG(ib, PA_SC_VPORT_SCISSOR_0_BR + + id * PA_SC_VPORT_SCISSOR_0_BR_offset, ((x2 << PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift) | + (y2 << PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift))); +} + +void +set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2) +{ +// RHDPtr rhdPtr = RHDPTR(pScrn); + + EREG(ib, PA_SC_GENERIC_SCISSOR_TL, ((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) | + (y1 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift) | + WINDOW_OFFSET_DISABLE_bit)); + EREG(ib, PA_SC_GENERIC_SCISSOR_BR, ((x2 << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) | + (y2 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift))); +} + +void +set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2) +{ +// RHDPtr rhdPtr = RHDPTR(pScrn); + + EREG(ib, PA_SC_WINDOW_SCISSOR_TL, ((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) | + (y1 << PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift) | + WINDOW_OFFSET_DISABLE_bit)); + EREG(ib, PA_SC_WINDOW_SCISSOR_BR, ((x2 << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) | + (y2 << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift))); +} + +void +set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2) +{ +// RHDPtr rhdPtr = RHDPTR(pScrn); + + EREG(ib, PA_SC_CLIPRECT_0_TL + + id * PA_SC_CLIPRECT_0_TL_offset, ((x1 << PA_SC_CLIPRECT_0_TL__TL_X_shift) | + (y1 << PA_SC_CLIPRECT_0_TL__TL_Y_shift))); + EREG(ib, PA_SC_CLIPRECT_0_BR + + id * PA_SC_CLIPRECT_0_BR_offset, ((x2 << PA_SC_CLIPRECT_0_BR__BR_X_shift) | + (y2 << PA_SC_CLIPRECT_0_BR__BR_Y_shift))); +} + +/* + * Setup of default state + */ + +void +set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib) +{ + tex_resource_t tex_res; + shader_config_t fs_conf; + sq_config_t sq_conf; + int i; +// uint32_t reg; + RHDPtr rhdPtr = RHDPTR(pScrn); + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + + memset(&tex_res, 0, sizeof(tex_resource_t)); + memset(&fs_conf, 0, sizeof(shader_config_t)); + +#if 1 + if (accel_state->XHas3DEngineState) + return; +#endif + + accel_state->XHas3DEngineState = TRUE; + + wait_3d_idle(pScrn, ib); + + // ASIC specific setup, see drm + if (rhdPtr->ChipSet < RHD_RV770) { + EREG(ib, TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) | + (28 << TD_FIFO_CREDIT_shift))); + EREG(ib, VC_ENHANCE, 0); + EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); + EREG(ib, DB_DEBUG, 0x82000000); /* ? */ + EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) | + (16 << DEPTH_FLUSH_shift) | + (0 << FORCE_SUMMARIZE_shift) | + (4 << DEPTH_PENDING_FREE_shift) | + (16 << DEPTH_CACHELINE_FREE_shift) | + 0)); + } else { + EREG(ib, TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) | + (28 << TD_FIFO_CREDIT_shift))); + EREG(ib, VC_ENHANCE, 0); + EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit); + EREG(ib, DB_DEBUG, 0); + EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) | + (16 << DEPTH_FLUSH_shift) | + (0 << FORCE_SUMMARIZE_shift) | + (4 << DEPTH_PENDING_FREE_shift) | + (4 << DEPTH_CACHELINE_FREE_shift) | + 0)); + } + + reset_td_samplers(pScrn, ib); + reset_dx9_alu_consts(pScrn, ib); + reset_bool_loop_const (pScrn, ib); + reset_sampler_const (pScrn, ib); + + // SQ + sq_conf.ps_prio = 0; + sq_conf.vs_prio = 1; + sq_conf.gs_prio = 2; + sq_conf.es_prio = 3; + // need to set stack/thread/gpr limits based on the asic + // for now just set them low enough so any card will work + // see r600_cp.c in the drm + switch (rhdPtr->ChipSet) { + case RHD_R600: + sq_conf.num_ps_gprs = 192; + sq_conf.num_vs_gprs = 56; + sq_conf.num_temp_gprs = 4; + sq_conf.num_gs_gprs = 0; + sq_conf.num_es_gprs = 0; + sq_conf.num_ps_threads = 136; + sq_conf.num_vs_threads = 48; + sq_conf.num_gs_threads = 4; + sq_conf.num_es_threads = 4; + sq_conf.num_ps_stack_entries = 128; + sq_conf.num_vs_stack_entries = 128; + sq_conf.num_gs_stack_entries = 0; + sq_conf.num_es_stack_entries = 0; + break; + case RHD_RV630: + case RHD_M76: + case RHD_RV635: + case RHD_M86: + sq_conf.num_ps_gprs = 84; + sq_conf.num_vs_gprs = 36; + sq_conf.num_temp_gprs = 4; + sq_conf.num_gs_gprs = 0; + sq_conf.num_es_gprs = 0; + sq_conf.num_ps_threads = 144; + sq_conf.num_vs_threads = 40; + sq_conf.num_gs_threads = 4; + sq_conf.num_es_threads = 4; + sq_conf.num_ps_stack_entries = 40; + sq_conf.num_vs_stack_entries = 40; + sq_conf.num_gs_stack_entries = 32; + sq_conf.num_es_stack_entries = 16; + break; + case RHD_RV610: + case RHD_M74: + case RHD_M72: + case RHD_M82: + case RHD_RV620: + case RHD_RS780: + default: + sq_conf.num_ps_gprs = 84; + sq_conf.num_vs_gprs = 36; + sq_conf.num_temp_gprs = 4; + sq_conf.num_gs_gprs = 0; + sq_conf.num_es_gprs = 0; + sq_conf.num_ps_threads = 136; + sq_conf.num_vs_threads = 48; + sq_conf.num_gs_threads = 4; + sq_conf.num_es_threads = 4; + sq_conf.num_ps_stack_entries = 40; + sq_conf.num_vs_stack_entries = 40; + sq_conf.num_gs_stack_entries = 32; + sq_conf.num_es_stack_entries = 16; + break; + case RHD_RV670: + case RHD_R680: + sq_conf.num_ps_gprs = 144; + sq_conf.num_vs_gprs = 40; + sq_conf.num_temp_gprs = 4; + sq_conf.num_gs_gprs = 0; + sq_conf.num_es_gprs = 0; + sq_conf.num_ps_threads = 136; + sq_conf.num_vs_threads = 48; + sq_conf.num_gs_threads = 4; + sq_conf.num_es_threads = 4; + sq_conf.num_ps_stack_entries = 40; + sq_conf.num_vs_stack_entries = 40; + sq_conf.num_gs_stack_entries = 32; + sq_conf.num_es_stack_entries = 16; + break; + case RHD_RV770: + case RHD_M98: + sq_conf.num_ps_gprs = 192; + sq_conf.num_vs_gprs = 56; + sq_conf.num_temp_gprs = 4; + sq_conf.num_gs_gprs = 0; + sq_conf.num_es_gprs = 0; + sq_conf.num_ps_threads = 188; + sq_conf.num_vs_threads = 60; + sq_conf.num_gs_threads = 0; + sq_conf.num_es_threads = 0; + sq_conf.num_ps_stack_entries = 256; + sq_conf.num_vs_stack_entries = 256; + sq_conf.num_gs_stack_entries = 0; + sq_conf.num_es_stack_entries = 0; + break; + case RHD_RV730: + case RHD_M96: + sq_conf.num_ps_gprs = 84; + sq_conf.num_vs_gprs = 36; + sq_conf.num_temp_gprs = 4; + sq_conf.num_gs_gprs = 0; + sq_conf.num_es_gprs = 0; + sq_conf.num_ps_threads = 188; + sq_conf.num_vs_threads = 60; + sq_conf.num_gs_threads = 0; + sq_conf.num_es_threads = 0; + sq_conf.num_ps_stack_entries = 128; + sq_conf.num_vs_stack_entries = 128; + sq_conf.num_gs_stack_entries = 0; + sq_conf.num_es_stack_entries = 0; + break; + case RHD_RV710: + sq_conf.num_ps_gprs = 192; + sq_conf.num_vs_gprs = 56; + sq_conf.num_temp_gprs = 4; + sq_conf.num_gs_gprs = 0; + sq_conf.num_es_gprs = 0; + sq_conf.num_ps_threads = 144; + sq_conf.num_vs_threads = 48; + sq_conf.num_gs_threads = 0; + sq_conf.num_es_threads = 0; + sq_conf.num_ps_stack_entries = 128; + sq_conf.num_vs_stack_entries = 128; + sq_conf.num_gs_stack_entries = 0; + sq_conf.num_es_stack_entries = 0; + break; + } + + sq_setup(pScrn, ib, &sq_conf); + + EREG(ib, SQ_VTX_BASE_VTX_LOC, 0); + EREG(ib, SQ_VTX_START_INST_LOC, 0); + + PACK0(ib, SQ_ESGS_RING_ITEMSIZE, 9); + E32(ib, 0); // SQ_ESGS_RING_ITEMSIZE + E32(ib, 0); // SQ_GSVS_RING_ITEMSIZE + E32(ib, 0); // SQ_ESTMP_RING_ITEMSIZE + E32(ib, 0); // SQ_GSTMP_RING_ITEMSIZE + E32(ib, 0); // SQ_VSTMP_RING_ITEMSIZE + E32(ib, 0); // SQ_PSTMP_RING_ITEMSIZE + E32(ib, 0); // SQ_FBUF_RING_ITEMSIZE + E32(ib, 0); // SQ_REDUC_RING_ITEMSIZE + E32(ib, 0); // SQ_GS_VERT_ITEMSIZE + + // DB + EREG(ib, DB_DEPTH_INFO, 0); + EREG(ib, DB_STENCIL_CLEAR, 0); + EREG(ib, DB_DEPTH_CLEAR, 0); + EREG(ib, DB_STENCILREFMASK, 0); + EREG(ib, DB_STENCILREFMASK_BF, 0); + EREG(ib, DB_DEPTH_CONTROL, 0); + EREG(ib, DB_RENDER_CONTROL, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); + if (rhdPtr->ChipSet < RHD_RV770) + EREG(ib, DB_RENDER_OVERRIDE, FORCE_SHADER_Z_ORDER_bit); + else + EREG(ib, DB_RENDER_OVERRIDE, 0); + EREG(ib, DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) | + (2 << ALPHA_TO_MASK_OFFSET1_shift) | + (2 << ALPHA_TO_MASK_OFFSET2_shift) | + (2 << ALPHA_TO_MASK_OFFSET3_shift))); + + // SX + EREG(ib, SX_ALPHA_TEST_CONTROL, 0); + EREG(ib, SX_ALPHA_REF, 0); + + // CB + reset_cb(pScrn, ib); + + PACK0(ib, CB_BLEND_RED, 4); + E32(ib, 0x00000000); + E32(ib, 0x00000000); + E32(ib, 0x00000000); + E32(ib, 0x00000000); + + /* CB_COLOR_CONTROL.PER_MRT_BLEND is off */ + // RV6xx+ have per-MRT blend + if (rhdPtr->ChipSet > RHD_R600) { + PACK0(ib, CB_BLEND0_CONTROL, CB_BLEND0_CONTROL_num); + for (i = 0; i < CB_BLEND0_CONTROL_num; i++) + E32(ib, 0); + } + + EREG(ib, CB_BLEND_CONTROL, 0); + + if (rhdPtr->ChipSet < RHD_RV770) { + PACK0(ib, CB_FOG_RED, 3); + E32(ib, 0x00000000); + E32(ib, 0x00000000); + E32(ib, 0x00000000); + } + + EREG(ib, CB_COLOR_CONTROL, 0); + PACK0(ib, CB_CLRCMP_CONTROL, 4); + E32(ib, 1 << CLRCMP_FCN_SEL_shift); // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC + E32(ib, 0); // CB_CLRCMP_SRC + E32(ib, 0); // CB_CLRCMP_DST + E32(ib, 0); // CB_CLRCMP_MSK + + + if (rhdPtr->ChipSet < RHD_RV770) { + PACK0(ib, CB_CLEAR_RED, 4); + EFLOAT(ib, 1.0); /* WTF? */ + EFLOAT(ib, 0.0); + EFLOAT(ib, 1.0); + EFLOAT(ib, 1.0); + } + EREG(ib, CB_TARGET_MASK, (0x0f << TARGET0_ENABLE_shift)); + + // SC + set_generic_scissor(pScrn, ib, 0, 0, 8192, 8192); + set_screen_scissor (pScrn, ib, 0, 0, 8192, 8192); + EREG(ib, PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) | + (0 << WINDOW_Y_OFFSET_shift))); + set_window_scissor (pScrn, ib, 0, 0, 8192, 8192); + + EREG(ib, PA_SC_CLIPRECT_RULE, CLIP_RULE_mask); + + /* clip boolean is set to always visible -> doesn't matter */ + for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++) + set_clip_rect (pScrn, ib, i, 0, 0, 8192, 8192); + + if (rhdPtr->ChipSet < RHD_RV770) + EREG(ib, R7xx_PA_SC_EDGERULE, 0x00000000); + else + EREG(ib, R7xx_PA_SC_EDGERULE, 0xAAAAAAAA); /* ? */ + + for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++) { + set_vport_scissor (pScrn, ib, i, 0, 0, 8192, 8192); + PACK0(ib, PA_SC_VPORT_ZMIN_0 + i * PA_SC_VPORT_ZMIN_0_offset, 2); + EFLOAT(ib, 0.0); + EFLOAT(ib, 1.0); + } + + if (rhdPtr->ChipSet < RHD_RV770) + EREG(ib, PA_SC_MODE_CNTL, (WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit)); + else + EREG(ib, PA_SC_MODE_CNTL, (FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit | + 0x00500000)); /* ? */ + + EREG(ib, PA_SC_LINE_CNTL, 0); + EREG(ib, PA_SC_AA_CONFIG, 0); + EREG(ib, PA_SC_AA_MASK, 0xFFFFFFFF); + + //XXX: double check this + if (rhdPtr->ChipSet > RHD_R600) { + EREG(ib, PA_SC_AA_SAMPLE_LOCS_MCTX, 0); + EREG(ib, PA_SC_AA_SAMPLE_LOCS_8S_WD1_M, 0); + } + + EREG(ib, PA_SC_LINE_STIPPLE, 0); + EREG(ib, PA_SC_MPASS_PS_CNTL, 0); + + // CL + PACK0(ib, PA_CL_VPORT_XSCALE_0, 6); + EFLOAT(ib, 0.0f); // PA_CL_VPORT_XSCALE + EFLOAT(ib, 0.0f); // PA_CL_VPORT_XOFFSET + EFLOAT(ib, 0.0f); // PA_CL_VPORT_YSCALE + EFLOAT(ib, 0.0f); // PA_CL_VPORT_YOFFSET + EFLOAT(ib, 0.0f); // PA_CL_VPORT_ZSCALE + EFLOAT(ib, 0.0f); // PA_CL_VPORT_ZOFFSET + EREG(ib, PA_CL_CLIP_CNTL, (CLIP_DISABLE_bit | DX_CLIP_SPACE_DEF_bit)); + EREG(ib, PA_CL_VTE_CNTL, 0); + EREG(ib, PA_CL_VS_OUT_CNTL, 0); + EREG(ib, PA_CL_NANINF_CNTL, 0); + PACK0(ib, PA_CL_GB_VERT_CLIP_ADJ, 4); + EFLOAT(ib, 1.0); // PA_CL_GB_VERT_CLIP_ADJ + EFLOAT(ib, 1.0); // PA_CL_GB_VERT_DISC_ADJ + EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_CLIP_ADJ + EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_DISC_ADJ + + /* user clipping planes are disabled by default */ + PACK0(ib, PA_CL_UCP_0_X, 24); + for (i = 0; i < 24; i++) + EFLOAT(ib, 0.0); + + // SU + EREG(ib, PA_SU_SC_MODE_CNTL, FACE_bit); + EREG(ib, PA_SU_POINT_SIZE, 0); + EREG(ib, PA_SU_POINT_MINMAX, 0); + EREG(ib, PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0); + EREG(ib, PA_SU_POLY_OFFSET_BACK_SCALE, 0); + EREG(ib, PA_SU_POLY_OFFSET_FRONT_SCALE, 0); + EREG(ib, PA_SU_POLY_OFFSET_BACK_OFFSET, 0); + EREG(ib, PA_SU_POLY_OFFSET_FRONT_OFFSET, 0); + + EREG(ib, PA_SU_LINE_CNTL, (8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ + EREG(ib, PA_SU_VTX_CNTL, ((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | + (5 << QUANT_MODE_shift))); /* Round to Even, fixed point 1/256 */ + EREG(ib, PA_SU_POLY_OFFSET_CLAMP, 0); + + // SPI + if (rhdPtr->ChipSet < RHD_RV770) + EREG(ib, R7xx_SPI_THREAD_GROUPING, 0); + else + EREG(ib, R7xx_SPI_THREAD_GROUPING, (1 << PS_GROUPING_shift)); + + EREG(ib, SPI_INTERP_CONTROL_0, ((2 << PNT_SPRITE_OVRD_X_shift) | + (3 << PNT_SPRITE_OVRD_Y_shift) | + (0 << PNT_SPRITE_OVRD_Z_shift) | + (1 << PNT_SPRITE_OVRD_W_shift))); /* s,t,0,1 */ + EREG(ib, SPI_INPUT_Z, 0); + EREG(ib, SPI_FOG_CNTL, 0); + EREG(ib, SPI_FOG_FUNC_SCALE, 0); + EREG(ib, SPI_FOG_FUNC_BIAS, 0); + + PACK0(ib, SPI_VS_OUT_ID_0, SPI_VS_OUT_ID_0_num); + for (i = 0; i < SPI_VS_OUT_ID_0_num; i++) /* identity mapping */ + E32(ib, 0x03020100 + i*0x04040404); + EREG(ib, SPI_VS_OUT_CONFIG, 0); + + // clear FS + fs_setup(pScrn, ib, &fs_conf); + + // VGT + EREG(ib, VGT_MAX_VTX_INDX, 2048); /* XXX set to a reasonably large number of indices */ + EREG(ib, VGT_MIN_VTX_INDX, 0); + EREG(ib, VGT_INDX_OFFSET, 0); + EREG(ib, VGT_INSTANCE_STEP_RATE_0, 0); + EREG(ib, VGT_INSTANCE_STEP_RATE_1, 0); + + EREG(ib, VGT_MULTI_PRIM_IB_RESET_INDX, 0); + EREG(ib, VGT_OUTPUT_PATH_CNTL, 0); + EREG(ib, VGT_GS_MODE, 0); + EREG(ib, VGT_HOS_CNTL, 0); + EREG(ib, VGT_HOS_MAX_TESS_LEVEL, 0); + EREG(ib, VGT_HOS_MIN_TESS_LEVEL, 0); + EREG(ib, VGT_HOS_REUSE_DEPTH, 0); + EREG(ib, VGT_GROUP_PRIM_TYPE, 0); + EREG(ib, VGT_GROUP_FIRST_DECR, 0); + EREG(ib, VGT_GROUP_DECR, 0); + EREG(ib, VGT_GROUP_VECT_0_CNTL, 0); + EREG(ib, VGT_GROUP_VECT_1_CNTL, 0); + EREG(ib, VGT_GROUP_VECT_0_FMT_CNTL, 0); + EREG(ib, VGT_GROUP_VECT_1_FMT_CNTL, 0); + EREG(ib, VGT_PRIMITIVEID_EN, 0); + EREG(ib, VGT_MULTI_PRIM_IB_RESET_EN, 0); + EREG(ib, VGT_STRMOUT_EN, 0); + EREG(ib, VGT_REUSE_OFF, 0); + EREG(ib, VGT_VTX_CNT_EN, 0); + EREG(ib, VGT_STRMOUT_BUFFER_EN, 0); + + // clear tex resources - PS + for (i = 0; i < 16; i++) { + tex_res.id = i; + set_tex_resource(pScrn, ib, &tex_res); + } + + // clear tex resources - VS + for (i = 160; i < 164; i++) { + tex_res.id = i; + set_tex_resource(pScrn, ib, &tex_res); + } + + // clear tex resources - FS + for (i = 320; i < 335; i++) { + tex_res.id = i; + set_tex_resource(pScrn, ib, &tex_res); + } + +} + + +/* + * Commands + */ + +void +draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices) +{ + uint32_t i, count; +// RHDPtr rhdPtr = RHDPTR(pScrn); + + EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type); + PACK3(ib, IT_INDEX_TYPE, 1); + E32(ib, draw_conf->index_type); + PACK3(ib, IT_NUM_INSTANCES, 1); + E32(ib, draw_conf->num_instances); + + // calculate num of packets + count = 2; + if (draw_conf->index_type == DI_INDEX_SIZE_16_BIT) + count += (draw_conf->num_indices + 1) / 2; + else + count += draw_conf->num_indices; + + PACK3(ib, IT_DRAW_INDEX_IMMD, count); + E32(ib, draw_conf->num_indices); + E32(ib, draw_conf->vgt_draw_initiator); + + if (draw_conf->index_type == DI_INDEX_SIZE_16_BIT) { + for (i = 0; i < draw_conf->num_indices; i += 2) { + if ((i + 1) == draw_conf->num_indices) + E32(ib, indices[i]); + else + E32(ib, (indices[i] | (indices[i + 1] << 16))); + } + } else { + for (i = 0; i < draw_conf->num_indices; i++) + E32(ib, indices[i]); + } +} + +void +draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf) +{ +// RHDPtr rhdPtr = RHDPTR(pScrn); + + EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type); + PACK3(ib, IT_INDEX_TYPE, 1); + E32(ib, draw_conf->index_type); + PACK3(ib, IT_NUM_INSTANCES, 1); + E32(ib, draw_conf->num_instances); + PACK3(ib, IT_DRAW_INDEX_AUTO, 2); + E32(ib, draw_conf->num_indices); + E32(ib, draw_conf->vgt_draw_initiator); +} + +#define R6XX_LOOP_COUNT 2000000 + +static Bool +R6xxIdleLocal(int scrnIndex) +{ + ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; + RHDPtr rhdPtr = RHDPTR(pScrn); + int i; + + /* wait for fifo to clear */ + for (i = 0; i < R6XX_LOOP_COUNT; i++) { + if (rhdPtr->ChipSet >= RHD_RV770) { + if (8 == (RHDRegRead(pScrn, GRBM_STATUS) & R700_CMDFIFO_AVAIL_mask)) + break; + } else { + if (16 == (RHDRegRead(pScrn, GRBM_STATUS) & R600_CMDFIFO_AVAIL_mask)) + break; + } + } + + if (i == R6XX_LOOP_COUNT) { + xf86DrvMsg(scrnIndex, X_ERROR, "%s: FIFO Timeout 0x%08X.\n", __func__, + (unsigned int) RHDRegRead(pScrn, GRBM_STATUS)); + return FALSE; + } + + /* wait for engine to go idle */ + for (i = 0; i < R6XX_LOOP_COUNT; i++) + if (!(RHDRegRead(pScrn, GRBM_STATUS) & GUI_ACTIVE_bit)) + break; + + if (i == R6XX_LOOP_COUNT) { + xf86DrvMsg(scrnIndex, X_ERROR, "%s: Idle Timeout 0x%08X.\n", __func__, + (unsigned int) RHDRegRead(pScrn, GRBM_STATUS)); + return FALSE; + } + + return TRUE; +} + +static void +R6xxEngineReset(ScrnInfoPtr pScrn) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + uint32_t cp_ptr, cp_me_cntl, cp_rb_cntl; + + xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, "%s!!!!!\n", __func__); + + cp_ptr = RHDRegRead(pScrn, CP_RB_WPTR); + + cp_me_cntl = RHDRegRead(pScrn, CP_ME_CNTL); + RHDRegWrite(pScrn, CP_ME_CNTL, 0x10000000); + + RHDRegWrite(pScrn, GRBM_SOFT_RESET, 0x7fff); + RHDRegRead(pScrn, GRBM_SOFT_RESET); + usleep (50); + RHDRegWrite(pScrn, GRBM_SOFT_RESET, 0); + RHDRegRead(pScrn, GRBM_SOFT_RESET); + + RHDRegWrite(pScrn, CP_RB_WPTR_DELAY, 0); + cp_rb_cntl = RHDRegRead(pScrn, CP_RB_CNTL); + RHDRegWrite(pScrn, CP_RB_CNTL, 0x80000000); + + RHDRegWrite(pScrn, CP_RB_RPTR_WR, cp_ptr); + RHDRegWrite(pScrn, CP_RB_WPTR, cp_ptr); + RHDRegWrite(pScrn, CP_RB_CNTL, cp_rb_cntl); + RHDRegWrite(pScrn, CP_ME_CNTL, cp_me_cntl); + + if (rhdPtr->TwoDPrivate) + ((struct r6xx_accel_state *) rhdPtr->TwoDPrivate)->XHas3DEngineState = FALSE; + +} + +void +R6xxIdle(ScrnInfoPtr pScrn) +{ + if (!R6xxIdleLocal(pScrn->scrnIndex)) + R6xxEngineReset(pScrn); +} diff --git a/driver/xf86-video-radeonhd/src/r6xx_accel.h b/driver/xf86-video-radeonhd/src/r6xx_accel.h new file mode 100644 index 000000000..b86f9b3f0 --- /dev/null +++ b/driver/xf86-video-radeonhd/src/r6xx_accel.h @@ -0,0 +1,89 @@ + +#include "exa.h" + +#include "xf86drm.h" + +/* seriously ?! @#$%% */ +# define uint32_t CARD32 +# define uint64_t CARD64 + +/* r600_exa.c */ +Bool R6xxEXAInit(ScrnInfoPtr pScrn, ScreenPtr pScreen); +void R6xxEXACloseScreen(ScreenPtr pScreen); +void R6xxEXADestroy(ScrnInfoPtr pScrn); + +void R6xxCacheFlush(struct RhdCS *CS); +void R6xxEngineWaitIdleFull(struct RhdCS *CS); + +extern unsigned int +RHDDRIGetIntGARTLocation(ScrnInfoPtr pScrn); + +extern PixmapPtr +RADEONGetDrawablePixmap(DrawablePtr pDrawable); + +/* r6xx_accel.c */ +void +R6xxIdle(ScrnInfoPtr pScrn); + +Bool +R600LoadShaders(ScrnInfoPtr pScrn); + +struct r6xx_accel_state { + Bool XHas3DEngineState; + + int exaSyncMarker; + int exaMarkerSynced; + + drmBufPtr ib; + int vb_index; + + // shader storage + ExaOffscreenArea *shaders; + uint32_t solid_vs_offset; + uint32_t solid_ps_offset; + uint32_t copy_vs_offset; + uint32_t copy_ps_offset; + uint32_t comp_vs_offset; + uint32_t comp_ps_offset; + uint32_t comp_mask_ps_offset; + uint32_t xv_vs_offset; + uint32_t xv_ps_offset; + + //size/addr stuff + uint32_t src_size[2]; + uint64_t src_mc_addr[2]; + uint32_t src_pitch[2]; + uint32_t src_width[2]; + uint32_t src_height[2]; + uint32_t src_bpp[2]; + uint32_t dst_size; + uint64_t dst_mc_addr; + uint32_t dst_pitch; + uint32_t dst_height; + uint32_t dst_bpp; + uint32_t vs_size; + uint64_t vs_mc_addr; + uint32_t ps_size; + uint64_t ps_mc_addr; + uint32_t vb_size; + uint64_t vb_mc_addr; + + // UTS/DFS + drmBufPtr scratch; + + // copy + ExaOffscreenArea *copy_area; + Bool same_surface; + int rop; + uint32_t planemask; + + //comp + unsigned short texW[2]; + unsigned short texH[2]; + Bool is_transform[2]; + struct _PictTransform *transform[2]; + Bool has_mask; + Bool component_alpha; + Bool src_alpha; +}; + diff --git a/driver/xf86-video-radeonhd/src/radeon_exa_render.c b/driver/xf86-video-radeonhd/src/radeon_exa_render.c index 6d25446bb..ef0f810e4 100644 --- a/driver/xf86-video-radeonhd/src/radeon_exa_render.c +++ b/driver/xf86-video-radeonhd/src/radeon_exa_render.c @@ -422,7 +422,7 @@ static Bool RADEONSetupSourceTile(PicturePtr pPict, return TRUE; } -static PixmapPtr +PixmapPtr RADEONGetDrawablePixmap(DrawablePtr pDrawable) { if (pDrawable->type == DRAWABLE_WINDOW) diff --git a/driver/xf86-video-radeonhd/src/rhd.h b/driver/xf86-video-radeonhd/src/rhd.h index 130877f65..e58689cdb 100644 --- a/driver/xf86-video-radeonhd/src/rhd.h +++ b/driver/xf86-video-radeonhd/src/rhd.h @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. @@ -30,6 +30,8 @@ # error "config.h missing!" # endif +#include <compiler.h> + #define RHD_MAJOR_VERSION (PACKAGE_VERSION_MAJOR) #define RHD_MINOR_VERSION (PACKAGE_VERSION_MINOR) #define RHD_PATCHLEVEL (PACKAGE_VERSION_PATCHLEVEL) @@ -44,7 +46,6 @@ #define RHD_NAME "RADEONHD" #define RHD_DRIVER_NAME "radeonhd" - enum RHD_CHIPSETS { RHD_UNKNOWN = 0, /* R500 */ @@ -89,6 +90,7 @@ enum RHD_CHIPSETS { RHD_RV635, RHD_M86, RHD_RS780, + RHD_RS880, RHD_RV770, RHD_R700, RHD_M98, @@ -123,7 +125,8 @@ enum RHD_TV_MODE { enum rhdPropertyAction { rhdPropertyCheck, rhdPropertyGet, - rhdPropertySet + rhdPropertySet, + rhdPropertyCommit }; union rhdPropertyData @@ -160,6 +163,13 @@ union rhdPropertyData typedef struct pci_device *pciVideoPtr; #endif +#ifndef NO_ASSERT +enum debugFlags { + VGA_SETUP, + MC_SETUP +}; +#endif + enum rhdCardType { RHD_CARD_NONE, RHD_CARD_AGP, @@ -191,10 +201,11 @@ typedef struct RHDOpt { /* Some more intelligent handling of chosing which acceleration to use */ enum AccelMethod { RHD_ACCEL_NONE = 0, /* ultra slow, but might be desired for debugging. */ - RHD_ACCEL_SHADOWFB = 1, /* cache in main ram. */ - RHD_ACCEL_XAA = 2, /* "old" X acceleration architecture. */ - RHD_ACCEL_EXA = 3, /* not done yet. */ - RHD_ACCEL_DEFAULT = 4 /* keep as highest. */ + RHD_ACCEL_FORCE_SHADOWFB = 1, /* shadowfb even with dri enabled. Known to have damage issues. */ + RHD_ACCEL_SHADOWFB = 2, /* cache in main ram. */ + RHD_ACCEL_XAA = 3, /* "old" X acceleration architecture. */ + RHD_ACCEL_EXA = 4, /* not done yet. */ + RHD_ACCEL_DEFAULT = 5 /* keep as highest. */ }; typedef struct RHDRec { @@ -235,6 +246,7 @@ typedef struct RHDRec { pointer FbBase; /* map base of fb */ unsigned int FbPhysAddress; /* card PCI BAR address of FB */ unsigned int FbIntAddress; /* card internal address of FB */ + CARD32 FbIntSize; /* card internal FB aperture size */ unsigned int FbPCIAddress; /* physical address of FB */ Bool directRenderingEnabled; @@ -325,6 +337,12 @@ typedef struct RHDRec { CARD32 UseAtomFlags; struct rhdOutput *DigEncoderOutput[2]; +# define RHD_CHECKDEBUGFLAG(rhdPtr, FLAG) (rhdPtr->DebugFlags & (1 << FLAG)) +#ifndef NO_ASSERT +# define RHD_SETDEBUGFLAG(rhdPtr, FLAG) (rhdPtr->DebugFlags |= (1 << FLAG)) +# define RHD_UNSETDEBUGFLAG(rhdPtr, FLAG) (rhdPtr->DebugFlags &= ~((CARD32)1 << FLAG)) + CARD32 DebugFlags; +#endif } RHDRec, *RHDPtr; #define RHDPTR(p) ((RHDPtr)((p)->driverPrivate)) @@ -360,12 +378,17 @@ extern Bool RHDScalePolicy(struct rhdMonitor *Monitor, struct rhdConnector *Conn extern void RHDPrepareMode(RHDPtr rhdPtr); extern Bool RHDUseAtom(RHDPtr rhdPtr, enum RHD_CHIPSETS *BlackList, enum atomSubSystem subsys); -extern CARD32 _RHDRegRead(int scrnIndex, CARD16 offset); -#define RHDRegRead(ptr, offset) _RHDRegRead((ptr)->scrnIndex, (offset)) -extern void _RHDRegWrite(int scrnIndex, CARD16 offset, CARD32 value); -#define RHDRegWrite(ptr, offset, value) _RHDRegWrite((ptr)->scrnIndex, (offset), (value)) -extern void _RHDRegMask(int scrnIndex, CARD16 offset, CARD32 value, CARD32 mask); -#define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->scrnIndex, (offset), (value), (mask)) +#define RHDRegRead(ptr, offset) MMIO_IN32(RHDPTRI(ptr)->MMIOBase, offset) +#define RHDRegWrite(ptr, offset, value) MMIO_OUT32(RHDPTRI(ptr)->MMIOBase, offset, value) +#define RHDRegMask(ptr, offset, value, mask) \ +do { \ + CARD32 tmp; \ + tmp = RHDRegRead((ptr), (offset)); \ + tmp &= ~(mask); \ + tmp |= ((value) & (mask)); \ + RHDRegWrite((ptr), (offset), tmp); \ +} while(0) + extern CARD32 _RHDReadMC(int scrnIndex, CARD32 addr); #define RHDReadMC(ptr,addr) _RHDReadMC((ptr)->scrnIndex,(addr)) extern void _RHDWriteMC(int scrnIndex, CARD32 addr, CARD32 data); diff --git a/driver/xf86-video-radeonhd/src/rhd_atombios.c b/driver/xf86-video-radeonhd/src/rhd_atombios.c index 208f86885..a285e48bb 100644 --- a/driver/xf86-video-radeonhd/src/rhd_atombios.c +++ b/driver/xf86-video-radeonhd/src/rhd_atombios.c @@ -1,6 +1,6 @@ /* * Copyright 2007, 2008 Egbert Eich <eich@novell.com> - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. * @@ -1550,7 +1550,7 @@ rhdAtomEncoderControl(atomBiosHandlePtr handle, enum atomEncoder EncoderId, lvds->ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_EN; break; } - switch (Config->u.lvds2.SpatialDither) + if (Config->u.lvds2.SpatialDither) lvds->ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_EN; } diff --git a/driver/xf86-video-radeonhd/src/rhd_atombios.h b/driver/xf86-video-radeonhd/src/rhd_atombios.h index e960db3c7..56e4a3936 100644 --- a/driver/xf86-video-radeonhd/src/rhd_atombios.h +++ b/driver/xf86-video-radeonhd/src/rhd_atombios.h @@ -1,6 +1,6 @@ /* * Copyright 2007, 2008 Egbert Eich <eich@novell.com> - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. * diff --git a/driver/xf86-video-radeonhd/src/rhd_atomcrtc.c b/driver/xf86-video-radeonhd/src/rhd_atomcrtc.c index 7e27df7ee..72b3d8de7 100644 --- a/driver/xf86-video-radeonhd/src/rhd_atomcrtc.c +++ b/driver/xf86-video-radeonhd/src/rhd_atomcrtc.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. @@ -141,8 +141,8 @@ rhdAtomScaleSet(struct rhdCrtc *Crtc, enum rhdCrtcScaleType Type, data.Address = NULL; RHDAtomBiosFunc(rhdPtr->scrnIndex, rhdPtr->atomBIOS, ATOM_SET_REGISTER_LIST_LOCATION, &data); - RHDTuneMCAccessForDisplay(rhdPtr, Crtc->Id, Mode, - ScaledToMode ? ScaledToMode : Mode); + RHDMCTuneAccessForDisplay(rhdPtr, Crtc->Id, Mode, + ScaledToMode ? ScaledToMode : Mode); } /* @@ -256,7 +256,7 @@ rhdAtomModeSet(struct rhdCrtc *Crtc, DisplayModePtr Mode) /* * */ -static void +static Bool rhdAtomCrtcPower(struct rhdCrtc *Crtc, int Power) { RHDPtr rhdPtr = RHDPTRI(Crtc); @@ -294,6 +294,13 @@ rhdAtomCrtcPower(struct rhdCrtc *Crtc, int Power) } data.Address = NULL; RHDAtomBiosFunc(Crtc->scrnIndex, rhdPtr->atomBIOS, ATOM_SET_REGISTER_LIST_LOCATION, &data); + + /* + * we always claim we succeeded here, after all, we know, AtomBIOS knows + * how to do things, right? + * Err, no, when we use AtomBIOS we should not have a clue how to find out. + */ + return TRUE; } /* diff --git a/driver/xf86-video-radeonhd/src/rhd_atomout.c b/driver/xf86-video-radeonhd/src/rhd_atomout.c index 5d6a66a8d..1d1662ac9 100644 --- a/driver/xf86-video-radeonhd/src/rhd_atomout.c +++ b/driver/xf86-video-radeonhd/src/rhd_atomout.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. @@ -278,13 +278,14 @@ atomSetBacklightFromBIOSScratch(struct rhdOutput *Output) * */ static void -atomSetBacklight(struct rhdOutput *Output, int value) +atomSetBacklight(struct rhdOutput *Output) { RHDPtr rhdPtr = RHDPTRI(Output); + struct rhdAtomOutputPrivate *Private = (struct rhdAtomOutputPrivate *) Output->Private; RHDFUNC(Output); - RHDAtomBIOSScratchBlLevel(rhdPtr, rhdBIOSScratchBlSet, &value); + RHDAtomBIOSScratchBlLevel(rhdPtr, rhdBIOSScratchBlSet, &Private->BlLevel); atomSetBacklightFromBIOSScratch(Output); } @@ -352,6 +353,63 @@ rhdAtomOutputSet(struct rhdOutput *Output, DisplayModePtr Mode) /* * */ +static Bool +atomIsHdmiEnabled(struct rhdOutput *Output) +{ + struct rhdAtomOutputPrivate *Private = (struct rhdAtomOutputPrivate *) Output->Private; + switch(Output->Id) { + case RHD_OUTPUT_TMDSA: + case RHD_OUTPUT_LVTMA: + return Private->EncoderConfig.u.lvds2.Hdmi; + + case RHD_OUTPUT_UNIPHYA: + case RHD_OUTPUT_UNIPHYB: + case RHD_OUTPUT_UNIPHYC: + case RHD_OUTPUT_UNIPHYD: + case RHD_OUTPUT_UNIPHYE: + case RHD_OUTPUT_UNIPHYF: + case RHD_OUTPUT_KLDSKP_LVTMA: + return Private->TransmitterConfig.Mode == atomHDMI && + Private->EncoderConfig.u.dig.EncoderMode == atomHDMI; + + default: + return FALSE; + } +} + +/* + * + */ +static void +atomSetHdmiEnabled(struct rhdOutput *Output, Bool value) +{ + struct rhdAtomOutputPrivate *Private = (struct rhdAtomOutputPrivate *) Output->Private; + switch(Output->Id) { + case RHD_OUTPUT_TMDSA: + case RHD_OUTPUT_LVTMA: + Private->EncoderConfig.u.lvds2.Hdmi = value; + break; + + case RHD_OUTPUT_UNIPHYA: + case RHD_OUTPUT_UNIPHYB: + case RHD_OUTPUT_UNIPHYC: + case RHD_OUTPUT_UNIPHYD: + case RHD_OUTPUT_UNIPHYE: + case RHD_OUTPUT_UNIPHYF: + case RHD_OUTPUT_KLDSKP_LVTMA: + Private->TransmitterConfig.Mode = + Private->EncoderConfig.u.dig.EncoderMode = + value ? atomHDMI : atomDVI; + break; + + default: + break; + } +} + +/* + * + */ static inline void rhdAtomOutputPower(struct rhdOutput *Output, int Power) { @@ -359,39 +417,9 @@ rhdAtomOutputPower(struct rhdOutput *Output, int Power) struct rhdAtomOutputPrivate *Private = (struct rhdAtomOutputPrivate *) Output->Private; struct atomEncoderConfig *EncoderConfig = &Private->EncoderConfig; union AtomBiosArg data; - Bool enableHDMI = FALSE; RHDFUNC(Output); - if(Output->Connector != NULL) { - enableHDMI = RHDConnectorEnableHDMI(Output->Connector); - switch(Output->Id) { - case RHD_OUTPUT_TMDSA: - case RHD_OUTPUT_LVTMA: - if(enableHDMI && !Private->EncoderConfig.u.lvds2.Hdmi) - Private->EncoderConfig.u.lvds2.Hdmi = TRUE; - else if(!enableHDMI && Private->EncoderConfig.u.lvds2.Hdmi) - Private->EncoderConfig.u.lvds2.Hdmi = FALSE; - break; - - case RHD_OUTPUT_UNIPHYA: - case RHD_OUTPUT_UNIPHYB: - case RHD_OUTPUT_KLDSKP_LVTMA: - if(enableHDMI && Private->TransmitterConfig.Mode == atomDVI) { - Private->TransmitterConfig.Mode = atomHDMI; - Private->EncoderConfig.u.dig.EncoderMode = atomHDMI; - - } else if(!enableHDMI && Private->TransmitterConfig.Mode == atomHDMI) { - Private->TransmitterConfig.Mode = atomDVI; - Private->EncoderConfig.u.dig.EncoderMode = atomDVI; - } - break; - - default: - break; - } - } - data.Address = &Private->Save; RHDAtomBiosFunc(Output->scrnIndex, rhdPtr->atomBIOS, ATOM_SET_REGISTER_LIST_LOCATION, &data); @@ -423,7 +451,7 @@ rhdAtomOutputPower(struct rhdOutput *Output, int Power) ERROR_MSG("rhdAtomOutputControl(atomOutputEnable)"); break; } - RHDHdmiEnable(Private->Hdmi, enableHDMI); + RHDHdmiEnable(Private->Hdmi, atomIsHdmiEnabled(Output)); break; case RHD_POWER_RESET: RHDDebug(Output->scrnIndex, "RHD_POWER_RESET\n"); @@ -518,9 +546,6 @@ rhdAtomOutputModeValid(struct rhdOutput *Output, DisplayModePtr Mode) RHDFUNC(Output); - if (Mode->Flags & V_INTERLACE) - return MODE_NO_INTERLACE; - if (Mode->Clock < 25000) return MODE_CLOCK_LOW; @@ -656,7 +681,16 @@ atomLVDSPropertyControl(struct rhdOutput *Output, return FALSE; switch (Property) { case RHD_OUTPUT_BACKLIGHT: - atomSetBacklight(Output, val->integer); + Private->BlLevel = val->integer; + return TRUE; + default: + return FALSE; + } + break; + case rhdPropertyCommit: + switch (Property) { + case RHD_OUTPUT_BACKLIGHT: + atomSetBacklight(Output); return TRUE; default: return FALSE; @@ -678,17 +712,21 @@ atomTMDSPropertyControl(struct rhdOutput *Output, RHDFUNC(Output); switch (Action) { case rhdPropertyCheck: - switch (Property) { - case RHD_OUTPUT_COHERENT: + switch (Property) { + case RHD_OUTPUT_COHERENT: + case RHD_OUTPUT_HDMI: return TRUE; - default: - return FALSE; - } + default: + return FALSE; + } case rhdPropertyGet: switch (Property) { case RHD_OUTPUT_COHERENT: val->Bool = Private->Coherent; return TRUE; + case RHD_OUTPUT_HDMI: + val->Bool = atomIsHdmiEnabled(Output); + return TRUE; default: return FALSE; } @@ -697,6 +735,18 @@ atomTMDSPropertyControl(struct rhdOutput *Output, switch (Property) { case RHD_OUTPUT_COHERENT: Private->Coherent = val->Bool; + break; + case RHD_OUTPUT_HDMI: + atomSetHdmiEnabled(Output, val->Bool); + break; + default: + return FALSE; + } + break; + case rhdPropertyCommit: + switch (Property) { + case RHD_OUTPUT_COHERENT: + case RHD_OUTPUT_HDMI: Output->Mode(Output, Private->Mode); Output->Power(Output, RHD_POWER_ON); break; @@ -1004,23 +1054,9 @@ RHDAtomOutputInit(RHDPtr rhdPtr, rhdConnectorType ConnectorType, LVDSInfoRetrieve(rhdPtr, Private); Private->Hdmi = NULL; } else { - int from = X_CONFIG; TransmitterConfig->Mode = EncoderConfig->u.dig.EncoderMode = atomDVI; TMDSInfoRetrieve(rhdPtr, Private); - switch (RhdParseBooleanOption(&rhdPtr->coherent, Output->Name)) { - case RHD_OPTION_NOT_SET: - case RHD_OPTION_DEFAULT: - from = X_DEFAULT; - Private->Coherent = FALSE; - break; - case RHD_OPTION_ON: - Private->Coherent = TRUE; - break; - case RHD_OPTION_OFF: - Private->Coherent = FALSE; - break; - } - xf86DrvMsg(rhdPtr->scrnIndex,from,"Setting %s to %scoherent\n",Output->Name,Private->Coherent ? "" : "in"); + Private->Coherent = FALSE; Private->Hdmi = RHDHdmiInit(rhdPtr, Output); } break; diff --git a/driver/xf86-video-radeonhd/src/rhd_atomout.h b/driver/xf86-video-radeonhd/src/rhd_atomout.h index c2bef4af3..e84e1e4ca 100644 --- a/driver/xf86-video-radeonhd/src/rhd_atomout.h +++ b/driver/xf86-video-radeonhd/src/rhd_atomout.h @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_atompll.c b/driver/xf86-video-radeonhd/src/rhd_atompll.c index 1d459848b..9caedb273 100644 --- a/driver/xf86-video-radeonhd/src/rhd_atompll.c +++ b/driver/xf86-video-radeonhd/src/rhd_atompll.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_atomwrapper.c b/driver/xf86-video-radeonhd/src/rhd_atomwrapper.c index be26375ef..643b7b1a7 100644 --- a/driver/xf86-video-radeonhd/src/rhd_atomwrapper.c +++ b/driver/xf86-video-radeonhd/src/rhd_atomwrapper.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_atomwrapper.h b/driver/xf86-video-radeonhd/src/rhd_atomwrapper.h index 1e7cc773f..53ea529c6 100644 --- a/driver/xf86-video-radeonhd/src/rhd_atomwrapper.h +++ b/driver/xf86-video-radeonhd/src/rhd_atomwrapper.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_audio.c b/driver/xf86-video-radeonhd/src/rhd_audio.c index 0709c7672..8d8a7d14e 100644 --- a/driver/xf86-video-radeonhd/src/rhd_audio.c +++ b/driver/xf86-video-radeonhd/src/rhd_audio.c @@ -1,6 +1,6 @@ /* * Copyright 2008 Christian König <deathsimple@vodafone.de> - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. @@ -165,7 +165,7 @@ RHDAudioInit(RHDPtr rhdPtr) { RHDFUNC(rhdPtr); - if (rhdPtr->ChipSet >= RHD_R600) { + if (rhdPtr->ChipSet >= RHD_RS600) { struct rhdAudio *Audio = (struct rhdAudio *) xnfcalloc(sizeof(struct rhdAudio), 1); Audio->scrnIndex = rhdPtr->scrnIndex; diff --git a/driver/xf86-video-radeonhd/src/rhd_audio.h b/driver/xf86-video-radeonhd/src/rhd_audio.h index a5f1314eb..d74016c4e 100644 --- a/driver/xf86-video-radeonhd/src/rhd_audio.h +++ b/driver/xf86-video-radeonhd/src/rhd_audio.h @@ -1,6 +1,6 @@ /* * Copyright 2008 Christian König <deathsimple@vodafone.de> - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_biosscratch.c b/driver/xf86-video-radeonhd/src/rhd_biosscratch.c index fd09fb61a..d2a905c32 100644 --- a/driver/xf86-video-radeonhd/src/rhd_biosscratch.c +++ b/driver/xf86-video-radeonhd/src/rhd_biosscratch.c @@ -1,6 +1,6 @@ /* * Copyright 2007, 2008 Egbert Eich <eich@novell.com> - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. * diff --git a/driver/xf86-video-radeonhd/src/rhd_biosscratch.h b/driver/xf86-video-radeonhd/src/rhd_biosscratch.h index f506e3dd6..17d452e3b 100644 --- a/driver/xf86-video-radeonhd/src/rhd_biosscratch.h +++ b/driver/xf86-video-radeonhd/src/rhd_biosscratch.h @@ -1,6 +1,6 @@ /* * Copyright 2007, 2008 Egbert Eich <eich@novell.com> - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. * diff --git a/driver/xf86-video-radeonhd/src/rhd_card.h b/driver/xf86-video-radeonhd/src/rhd_card.h index 682f3a758..d85493190 100644 --- a/driver/xf86-video-radeonhd/src/rhd_card.h +++ b/driver/xf86-video-radeonhd/src/rhd_card.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_connector.c b/driver/xf86-video-radeonhd/src/rhd_connector.c index d05eaf209..27ecdafbf 100644 --- a/driver/xf86-video-radeonhd/src/rhd_connector.c +++ b/driver/xf86-video-radeonhd/src/rhd_connector.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_connector.h b/driver/xf86-video-radeonhd/src/rhd_connector.h index 23967bac7..07a8564f3 100644 --- a/driver/xf86-video-radeonhd/src/rhd_connector.h +++ b/driver/xf86-video-radeonhd/src/rhd_connector.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_crtc.c b/driver/xf86-video-radeonhd/src/rhd_crtc.c index 62ee54126..ea0728cff 100644 --- a/driver/xf86-video-radeonhd/src/rhd_crtc.c +++ b/driver/xf86-video-radeonhd/src/rhd_crtc.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. @@ -536,6 +536,7 @@ DxModeRestore(struct rhdCrtc *Crtc) { struct rhdCrtcModePrivate *ModePriv = Crtc->ModePriv; CARD32 RegOff; + RHDPtr rhdPtr = RHDPTRI(Crtc); if (!ModePriv) { xf86DrvMsg(Crtc->scrnIndex, X_ERROR, "%s: no registers stored!\n", @@ -580,6 +581,10 @@ DxModeRestore(struct rhdCrtc *Crtc) * timing can be set to 0. This doesn't always restore properly... * Workaround is to set a valid sync length for a bit so VGA can * latch in. */ + + /* Make sure VGA is restored already */ + ASSERT(!RHD_CHECKDEBUGFLAG(rhdPtr, VGA_SETUP)); + if (!ModePriv->StoreCrtcVSyncA && (ModePriv->StoreCrtcControl & 0x00000001)) { RHDRegWrite(Crtc, RegOff + D1CRTC_V_SYNC_A, 0x00040000); usleep(300000); /* seems a reliable timeout here */ @@ -781,8 +786,8 @@ DxScaleSet(struct rhdCrtc *Crtc, enum rhdCrtcScaleType Type, RHDRegWrite(Crtc, RegOff + D1SCL_DITHER, 0x00001010); break; } - RHDTuneMCAccessForDisplay(rhdPtr, Crtc->Id, Mode, - ScaledToMode ? ScaledToMode : Mode); + RHDMCTuneAccessForDisplay(rhdPtr, Crtc->Id, Mode, + ScaledToMode ? ScaledToMode : Mode); } /* @@ -1007,7 +1012,7 @@ D2ViewPortStart(struct rhdCrtc *Crtc, CARD16 X, CARD16 Y) /* * */ -static void +static Bool D1CRTCDisable(struct rhdCrtc *Crtc) { if (RHDRegRead(Crtc, D1CRTC_CONTROL) & 0x00000001) { @@ -1021,18 +1026,20 @@ D1CRTCDisable(struct rhdCrtc *Crtc) if (!(RHDRegRead(Crtc, D1CRTC_CONTROL) & 0x00010000)) { RHDDebug(Crtc->scrnIndex, "%s: %d loops\n", __func__, i); RHDRegMask(Crtc, D1CRTC_CONTROL, Control, 0x00000300); - return; + return TRUE; } xf86DrvMsg(Crtc->scrnIndex, X_ERROR, "%s: Failed to Unsync %s\n", __func__, Crtc->Name); RHDRegMask(Crtc, D1CRTC_CONTROL, Control, 0x00000300); + return FALSE; } + return TRUE; } /* * */ -static void +static Bool D2CRTCDisable(struct rhdCrtc *Crtc) { if (RHDRegRead(Crtc, D2CRTC_CONTROL) & 0x00000001) { @@ -1046,20 +1053,23 @@ D2CRTCDisable(struct rhdCrtc *Crtc) if (!(RHDRegRead(Crtc, D2CRTC_CONTROL) & 0x00010000)) { RHDDebug(Crtc->scrnIndex, "%s: %d loops\n", __func__, i); RHDRegMask(Crtc, D2CRTC_CONTROL, Control, 0x00000300); - return; + return TRUE; } xf86DrvMsg(Crtc->scrnIndex, X_ERROR, "%s: Failed to Unsync %s\n", __func__, Crtc->Name); RHDRegMask(Crtc, D2CRTC_CONTROL, Control, 0x00000300); + return FALSE; } + return TRUE; } /* * */ -static void +static Bool D1Power(struct rhdCrtc *Crtc, int Power) { + Bool ret; RHDFUNC(Crtc); switch (Power) { @@ -1068,26 +1078,26 @@ D1Power(struct rhdCrtc *Crtc, int Power) usleep(2); RHDRegMask(Crtc, D1CRTC_CONTROL, 0, 0x01000000); /* enable read requests */ RHDRegMask(Crtc, D1CRTC_CONTROL, 1, 1); - return; + return TRUE; case RHD_POWER_RESET: RHDRegMask(Crtc, D1CRTC_CONTROL, 0x01000000, 0x01000000); /* disable read requests */ - D1CRTCDisable(Crtc); - return; + return D1CRTCDisable(Crtc); case RHD_POWER_SHUTDOWN: default: RHDRegMask(Crtc, D1CRTC_CONTROL, 0x01000000, 0x01000000); /* disable read requests */ - D1CRTCDisable(Crtc); + ret = D1CRTCDisable(Crtc); RHDRegMask(Crtc, D1GRPH_ENABLE, 0, 0x00000001); - return; + return ret; } } /* * */ -static void +static Bool D2Power(struct rhdCrtc *Crtc, int Power) { + Bool ret; RHDFUNC(Crtc); switch (Power) { @@ -1096,17 +1106,16 @@ D2Power(struct rhdCrtc *Crtc, int Power) usleep(2); RHDRegMask(Crtc, D2CRTC_CONTROL, 0, 0x01000000); /* enable read requests */ RHDRegMask(Crtc, D2CRTC_CONTROL, 1, 1); - return; + return TRUE; case RHD_POWER_RESET: RHDRegMask(Crtc, D2CRTC_CONTROL, 0x01000000, 0x01000000); /* disable read requests */ - D2CRTCDisable(Crtc); - return; + return D2CRTCDisable(Crtc); case RHD_POWER_SHUTDOWN: default: RHDRegMask(Crtc, D2CRTC_CONTROL, 0x01000000, 0x01000000); /* disable read requests */ - D2CRTCDisable(Crtc); + ret = D2CRTCDisable(Crtc); RHDRegMask(Crtc, D2GRPH_ENABLE, 0, 0x00000001); - return; + return ret; } } diff --git a/driver/xf86-video-radeonhd/src/rhd_crtc.h b/driver/xf86-video-radeonhd/src/rhd_crtc.h index 8f58c13a8..af3916af0 100644 --- a/driver/xf86-video-radeonhd/src/rhd_crtc.h +++ b/driver/xf86-video-radeonhd/src/rhd_crtc.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2004-2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * @@ -108,7 +108,7 @@ struct rhdCrtc { void (*LUTRestore) (struct rhdCrtc *Crtc); void (*LUTDestroy) (struct rhdCrtc *Crtc); - void (*Power) (struct rhdCrtc *Crtc, int Power); + Bool (*Power) (struct rhdCrtc *Crtc, int Power); void (*Blank) (struct rhdCrtc *Crtc, Bool Blank); }; diff --git a/driver/xf86-video-radeonhd/src/rhd_cs.c b/driver/xf86-video-radeonhd/src/rhd_cs.c index 256c1ae32..5e9fa0237 100644 --- a/driver/xf86-video-radeonhd/src/rhd_cs.c +++ b/driver/xf86-video-radeonhd/src/rhd_cs.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2008 Egbert Eich <eich@novell.com> * @@ -31,6 +31,8 @@ #include "xf86.h" +#include <compiler.h> + #include "rhd.h" #include "rhd_cs.h" #include "r5xx_regs.h" @@ -50,8 +52,8 @@ /* First... provide some macro's for accessing the registers, which will somewhat speed up things */ -#define CSMMIORegRead(Reg) (*(volatile CARD32 *) (MMIOBase + (Reg))) -#define CSMMIORegWrite(Reg, Value) (*(volatile CARD32 *) (MMIOBase + (Reg))) = (Value) +#define CSMMIORegRead(Reg) MMIO_IN32(MMIOBase, (Reg)) +#define CSMMIORegWrite(Reg, Value) MMIO_OUT32(MMIOBase, (Reg), (Value)) static void CSMMIORBBMStuff(struct RhdCS *CS) @@ -210,12 +212,21 @@ struct RhdDRMCP { static void DRMCPFlush(struct RhdCS *CS) { + RHDPtr rhdPtr = RHDPTRI(CS); struct RhdDRMCP *CP = CS->Private; struct drm_radeon_indirect indirect; if (!CP->DrmBuffer) return; + if (rhdPtr->ChipSet >= RHD_R600) { + while ((CS->Wptr * 4) & 0x3c) { + RHDCSGrab(CS, 1); + RHDCSWrite(CS, CP_PACKET2()); + RHDCSAdvance(CS); + } + } + indirect.idx = CP->DrmBuffer->idx; indirect.start = CS->Flushed * 4; indirect.end = CS->Wptr * 4; @@ -228,6 +239,7 @@ DRMCPFlush(struct RhdCS *CS) if (CS->Wptr & 1) CS->Wptr++; + CS->Flushed = CS->Wptr; #ifdef RHD_CS_DEBUG CS->Grabbed = 0; @@ -240,9 +252,18 @@ DRMCPFlush(struct RhdCS *CS) static void DRMCPBufferDiscard(struct RhdCS *CS) { + RHDPtr rhdPtr = RHDPTRI(CS); struct RhdDRMCP *CP = CS->Private; struct drm_radeon_indirect indirect; + if (rhdPtr->ChipSet >= RHD_R600) { + while ((CS->Wptr * 4) & 0x3c){ + RHDCSGrab(CS, 1); + RHDCSWrite(CS, CP_PACKET2()); + RHDCSAdvance(CS); + } + } + indirect.idx = CP->DrmBuffer->idx; indirect.start = CS->Flushed * 4; indirect.end = CS->Wptr * 4; diff --git a/driver/xf86-video-radeonhd/src/rhd_cs.h b/driver/xf86-video-radeonhd/src/rhd_cs.h index 7cf628f2b..f565d67df 100644 --- a/driver/xf86-video-radeonhd/src/rhd_cs.h +++ b/driver/xf86-video-radeonhd/src/rhd_cs.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2008 Egbert Eich <eich@novell.com> * diff --git a/driver/xf86-video-radeonhd/src/rhd_cursor.c b/driver/xf86-video-radeonhd/src/rhd_cursor.c index c967bbfa6..eff990bba 100644 --- a/driver/xf86-video-radeonhd/src/rhd_cursor.c +++ b/driver/xf86-video-radeonhd/src/rhd_cursor.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. @@ -220,10 +220,16 @@ displayCursor(struct rhdCrtc *Crtc) * hotspot support for that. Cannot exceed width, but cursor is * not visible in this case. */ + /* xorg bug#13405: Cursor corruptions + * With both CRTC enabled but HW cursor active only on one, the reported + * corruption is seen. If HW cursor for both CRTC is forced to stay on, then no + * corruption occurs. */ +#if 0 if (Cursor->X >= Crtc->X - Cursor->Width && Cursor->X < Crtc->X + Crtc->Width && Cursor->Y >= Crtc->Y - Cursor->Height && Cursor->Y < Crtc->Y + Crtc->Height) { +#endif int X, Y, HotX, HotY; X = Cursor->X >= 0 ? Cursor->X : 0; @@ -233,8 +239,10 @@ displayCursor(struct rhdCrtc *Crtc) enableCursor(Cursor, TRUE); setCursorPos(Cursor, X, Y, HotX, HotY); +#if 0 } else enableCursor(Cursor, FALSE); +#endif } /* diff --git a/driver/xf86-video-radeonhd/src/rhd_cursor.h b/driver/xf86-video-radeonhd/src/rhd_cursor.h index 42a566eab..a2347d753 100644 --- a/driver/xf86-video-radeonhd/src/rhd_cursor.h +++ b/driver/xf86-video-radeonhd/src/rhd_cursor.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_dac.c b/driver/xf86-video-radeonhd/src/rhd_dac.c index f253e100e..30e699fab 100644 --- a/driver/xf86-video-radeonhd/src/rhd_dac.c +++ b/driver/xf86-video-radeonhd/src/rhd_dac.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_ddia.c b/driver/xf86-video-radeonhd/src/rhd_ddia.c index 2dbc0a926..effd0b7a2 100644 --- a/driver/xf86-video-radeonhd/src/rhd_ddia.c +++ b/driver/xf86-video-radeonhd/src/rhd_ddia.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_dig.c b/driver/xf86-video-radeonhd/src/rhd_dig.c index 3fe247a8d..6cc5521fa 100644 --- a/driver/xf86-video-radeonhd/src/rhd_dig.c +++ b/driver/xf86-video-radeonhd/src/rhd_dig.c @@ -1,8 +1,8 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> - * Copyright 2007, 2008 Egbert Eich <eich@novell.com> - * Copyright 2007, 2008 Advanced Micro Devices, Inc. + * Copyright 2007-2009 Luc Verhaegen <libv@exsuse.de> + * Copyright 2007-2009 Matthias Hopf <mhopf@novell.com> + * Copyright 2007-2009 Egbert Eich <eich@novell.com> + * Copyright 2007-2009 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -151,9 +151,6 @@ LVTMATransmitterModeValid(struct rhdOutput *Output, DisplayModePtr Mode) { RHDFUNC(Output); - if (Mode->Flags & V_INTERLACE) - return MODE_NO_INTERLACE; - if (Output->Connector->Type == RHD_CONNECTOR_DVI_SINGLE && Mode->SynthClock > 165000) return MODE_CLOCK_HIGH; @@ -162,14 +159,13 @@ LVTMATransmitterModeValid(struct rhdOutput *Output, DisplayModePtr Mode) } static void -LVDSSetBacklight(struct rhdOutput *Output, int level) +LVDSSetBacklight(struct rhdOutput *Output) { struct DIGPrivate *Private = (struct DIGPrivate *) Output->Private; + int level = Private->BlLevel; RHDFUNC(Output); - Private->BlLevel = level; - RHDRegMask(Output, RV620_LVTMA_PWRSEQ_REF_DIV, 0x144 << LVTMA_BL_MOD_REF_DI_SHIFT, 0x7ff << LVTMA_BL_MOD_REF_DI_SHIFT); @@ -215,7 +211,16 @@ LVDSTransmitterPropertyControl(struct rhdOutput *Output, return FALSE; switch (Property) { case RHD_OUTPUT_BACKLIGHT: - LVDSSetBacklight(Output, val->integer); + Private->BlLevel = val->integer; + return TRUE; + default: + return FALSE; + } + break; + case rhdPropertyCommit: + switch (Property) { + case RHD_OUTPUT_BACKLIGHT: + LVDSSetBacklight(Output); return TRUE; default: return FALSE; @@ -237,17 +242,21 @@ TMDSTransmitterPropertyControl(struct rhdOutput *Output, RHDFUNC(Output); switch (Action) { case rhdPropertyCheck: - switch (Property) { - case RHD_OUTPUT_COHERENT: + switch (Property) { + case RHD_OUTPUT_COHERENT: + case RHD_OUTPUT_HDMI: return TRUE; - default: - return FALSE; - } + default: + return FALSE; + } case rhdPropertyGet: switch (Property) { case RHD_OUTPUT_COHERENT: val->Bool = Private->Coherent; return TRUE; + case RHD_OUTPUT_HDMI: + val->Bool = Private->EncoderMode == TMDS_HDMI; + return TRUE; default: return FALSE; } @@ -256,6 +265,18 @@ TMDSTransmitterPropertyControl(struct rhdOutput *Output, switch (Property) { case RHD_OUTPUT_COHERENT: Private->Coherent = val->Bool; + break; + case RHD_OUTPUT_HDMI: + Private->EncoderMode = val->Bool ? TMDS_HDMI : TMDS_DVI; + break; + default: + return FALSE; + } + break; + case rhdPropertyCommit: + switch (Property) { + case RHD_OUTPUT_COHERENT: + case RHD_OUTPUT_HDMI: Output->Mode(Output, Private->Mode); Output->Power(Output, RHD_POWER_ON); break; @@ -274,11 +295,11 @@ static void LVTMATransmitterSet(struct rhdOutput *Output, struct rhdCrtc *Crtc, DisplayModePtr Mode) { struct DIGPrivate *Private = (struct DIGPrivate *)Output->Private; - CARD32 value = 0; #ifdef ATOM_BIOS + CARD32 value = 0; AtomBiosArgRec data; -#endif RHDPtr rhdPtr = RHDPTRI(Output); +#endif Bool doCoherent = Private->Coherent; RHDFUNC(Output); @@ -729,6 +750,55 @@ LVTMATransmitterDestroy(struct rhdOutput *Output) xfree(digPrivate->Transmitter.Private); } +/* + * + */ +void +rhdPrintDigDebug(RHDPtr rhdPtr, const char *name) +{ + xf86DrvMsgVerb(rhdPtr->scrnIndex, X_INFO, 7, "%s: DIGn_CNTL: n=1: 0x%x n=2: 0x%x\n", + name, (unsigned int) RHDRegRead(rhdPtr, RV620_DIG1_CNTL), + (unsigned int) RHDRegRead(rhdPtr, DIG2_OFFSET + RV620_DIG1_CNTL)); +} + +/* + * + */ +static CARD32 +digProbeEncoder(struct rhdOutput *Output) +{ + if (Output->Id == RHD_OUTPUT_KLDSKP_LVTMA) { + return ENCODER_DIG2; + } else { + Bool swap = (RHDRegRead(Output, RV620_DCIO_LINK_STEER_CNTL) + & RV62_LINK_STEER_SWAP) == RV62_LINK_STEER_SWAP; + + switch (Output->Id) { + case RHD_OUTPUT_UNIPHYA: + if (swap) { + RHDDebug(Output->scrnIndex, "%s: detected ENCODER_DIG2 for UNIPHYA\n",__func__); + return ENCODER_DIG2; + } else { + RHDDebug(Output->scrnIndex, "%s: detected ENCODER_DIG1 for UNIPHYA\n",__func__); + return ENCODER_DIG1; + } + break; + case RHD_OUTPUT_UNIPHYB: + if (swap) { + RHDDebug(Output->scrnIndex, "%s: detected ENCODER_DIG1 for UNIPHYB\n",__func__); + return ENCODER_DIG1; + } else { + RHDDebug(Output->scrnIndex, "%s: detected ENCODER_DIG2 for UNIPHYB\n",__func__); + return ENCODER_DIG2; + } + break; + default: + return ENCODER_NONE; /* should not get here */ + } + } + return ENCODER_NONE; +} + #if defined(ATOM_BIOS) && defined(ATOM_BIOS_PARSER) struct ATOMTransmitterPrivate @@ -756,17 +826,6 @@ ATOMTransmitterModeValid(struct rhdOutput *Output, DisplayModePtr Mode) /* * */ -void -rhdPrintDigDebug(RHDPtr rhdPtr, const char *name) -{ - xf86DrvMsgVerb(rhdPtr->scrnIndex, X_INFO, 7, "%s: DIGn_CNTL: n=1: 0x%x n=2: 0x%x\n", - name, RHDRegRead(rhdPtr, RV620_DIG1_CNTL), - RHDRegRead(rhdPtr, DIG2_OFFSET + RV620_DIG1_CNTL)); -} - -/* - * - */ static void ATOMTransmitterSet(struct rhdOutput *Output, struct rhdCrtc *Crtc, DisplayModePtr Mode) { @@ -811,44 +870,6 @@ ATOMTransmitterSet(struct rhdOutput *Output, struct rhdCrtc *Crtc, DisplayModePt /* * */ -static CARD32 -digProbeEncoder(struct rhdOutput *Output) -{ - if (Output->Id == RHD_OUTPUT_KLDSKP_LVTMA) { - return ENCODER_DIG2; - } else { - Bool swap = (RHDRegRead(Output, RV620_DCIO_LINK_STEER_CNTL) - & RV62_LINK_STEER_SWAP) == RV62_LINK_STEER_SWAP; - - switch (Output->Id) { - case RHD_OUTPUT_UNIPHYA: - if (swap) { - RHDDebug(Output->scrnIndex, "%s: detected ENCODER_DIG2 for UNIPHYA\n",__func__); - return ENCODER_DIG2; - } else { - RHDDebug(Output->scrnIndex, "%s: detected ENCODER_DIG1 for UNIPHYA\n",__func__); - return ENCODER_DIG1; - } - break; - case RHD_OUTPUT_UNIPHYB: - if (swap) { - RHDDebug(Output->scrnIndex, "%s: detected ENCODER_DIG1 for UNIPHYB\n",__func__); - return ENCODER_DIG1; - } else { - RHDDebug(Output->scrnIndex, "%s: detected ENCODER_DIG2 for UNIPHYB\n",__func__); - return ENCODER_DIG2; - } - break; - default: - return ENCODER_NONE; /* should not get here */ - } - } - return ENCODER_NONE; -} - -/* - * - */ static void ATOMTransmitterPower(struct rhdOutput *Output, int Power) { @@ -1397,20 +1418,10 @@ DigPower(struct rhdOutput *Output, int Power) struct DIGPrivate *Private = (struct DIGPrivate *)Output->Private; struct transmitter *Transmitter = &Private->Transmitter; struct encoder *Encoder = &Private->Encoder; - Bool enableHDMI; RHDDebug(Output->scrnIndex, "%s(%s,%s)\n",__func__,Output->Name, rhdPowerString[Power]); - if(Output->Connector != NULL) { - /* check if attached monitor supports HDMI */ - enableHDMI = RHDConnectorEnableHDMI(Output->Connector); - if (enableHDMI && Private->EncoderMode == TMDS_DVI) - Private->EncoderMode = TMDS_HDMI; - else if (!enableHDMI && Private->EncoderMode == TMDS_HDMI) - Private->EncoderMode = TMDS_DVI; - } - switch (Power) { case RHD_POWER_ON: Encoder->Power(Output, Power); @@ -1444,6 +1455,7 @@ DigPropertyControl(struct rhdOutput *Output, switch(Property) { case RHD_OUTPUT_COHERENT: case RHD_OUTPUT_BACKLIGHT: + case RHD_OUTPUT_HDMI: { if (!Private->Transmitter.Property) return FALSE; @@ -1584,7 +1596,9 @@ DigAllocFree(struct rhdOutput *Output, enum rhdOutputAllocation Alloc) return TRUE; } else return FALSE; - } else { + } else +#if defined(ATOM_BIOS) && defined(ATOM_BIOS_PARSER) + { struct ATOMTransmitterPrivate *transPrivate = (struct ATOMTransmitterPrivate *)Private->Transmitter.Private; struct atomTransmitterConfig *atc = &transPrivate->atomTransmitterConfig; @@ -1605,7 +1619,9 @@ DigAllocFree(struct rhdOutput *Output, enum rhdOutputAllocation Alloc) } else return FALSE; } - +#else + return FALSE; +#endif case RHD_OUTPUT_FREE: Private->EncoderID = ENCODER_NONE; if (rhdPtr->DigEncoderOutput[0] == Output) { @@ -1625,34 +1641,6 @@ DigAllocFree(struct rhdOutput *Output, enum rhdOutputAllocation Alloc) /* * */ -static Bool -rhdDIGSetCoherent(RHDPtr rhdPtr,struct rhdOutput *Output) -{ - Bool coherent = FALSE; - int from = X_CONFIG; - - switch (RhdParseBooleanOption(&rhdPtr->coherent, Output->Name)) { - case RHD_OPTION_NOT_SET: - case RHD_OPTION_DEFAULT: - from = X_DEFAULT; - coherent = FALSE; - break; - case RHD_OPTION_ON: - coherent = TRUE; - break; - case RHD_OPTION_OFF: - coherent = FALSE; - break; - } - xf86DrvMsg(rhdPtr->scrnIndex,from,"Setting %s to %scoherent\n", - Output->Name,coherent ? "" : "in"); - - return coherent; -} - -/* - * - */ #ifdef NOT_YET static Bool digTransmitterPropertyWrapper(struct rhdOutput *Output, @@ -1725,7 +1713,7 @@ RHDDIGInit(RHDPtr rhdPtr, enum rhdOutputType outputType, CARD8 ConnectorType) struct ATOMTransmitterPrivate *transPrivate = (struct ATOMTransmitterPrivate *)Private->Transmitter.Private; struct atomTransmitterConfig *atc = &transPrivate->atomTransmitterConfig; - atc->Coherent = Private->Coherent = rhdDIGSetCoherent(rhdPtr, Output); + atc->Coherent = Private->Coherent = FALSE; atc->Link = atomTransLinkA; atc->Encoder = atomEncoderNone; if (RHDIsIGP(rhdPtr->ChipSet)) { @@ -1770,7 +1758,7 @@ RHDDIGInit(RHDPtr rhdPtr, enum rhdOutputType outputType, CARD8 ConnectorType) struct ATOMTransmitterPrivate *transPrivate = (struct ATOMTransmitterPrivate *)Private->Transmitter.Private; struct atomTransmitterConfig *atc = &transPrivate->atomTransmitterConfig; - atc->Coherent = Private->Coherent = rhdDIGSetCoherent(rhdPtr, Output); + atc->Coherent = Private->Coherent = FALSE; atc->Link = atomTransLinkB; atc->Encoder = atomEncoderNone; if (RHDIsIGP(rhdPtr->ChipSet)) { @@ -1799,7 +1787,7 @@ RHDDIGInit(RHDPtr rhdPtr, enum rhdOutputType outputType, CARD8 ConnectorType) case RHD_OUTPUT_KLDSKP_LVTMA: Output->Name = "UNIPHY_KLDSKP_LVTMA"; - Private->Coherent = rhdDIGSetCoherent(rhdPtr, Output); + Private->Coherent = FALSE; Private->Transmitter.Private = (struct LVTMATransmitterPrivate *)xnfcalloc(sizeof (struct LVTMATransmitterPrivate), 1); Private->Transmitter.Sense = NULL; diff --git a/driver/xf86-video-radeonhd/src/rhd_dri.c b/driver/xf86-video-radeonhd/src/rhd_dri.c index 0ef678025..d06ba4330 100644 --- a/driver/xf86-video-radeonhd/src/rhd_dri.c +++ b/driver/xf86-video-radeonhd/src/rhd_dri.c @@ -1,7 +1,7 @@ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, * Copyright 2000 VA Linux Systems Inc., Fremont, California. - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. @@ -81,6 +81,7 @@ #include "rhd_dri.h" #include "r5xx_accel.h" #include "r5xx_regs.h" +#include "r6xx_accel.h" #include "rhd_cs.h" #define IS_RADEONHD_DRIVER 1 @@ -121,7 +122,6 @@ typedef struct { int dummy; } RADEONDRIContextRec, *RADEONDRIContextPtr; - /* driver data only needed by dri */ struct rhdDri { int scrnIndex; @@ -389,18 +389,32 @@ static void RHDEnterServer(ScreenPtr pScreen) pSAREAPriv = (drm_radeon_sarea_t *)DRIGetSAREAPrivate(pScreen); if (pSAREAPriv->ctx_owner != (signed) DRIGetContext(pScreen)) { - struct R5xx3D *R5xx3D = rhdPtr->ThreeDPrivate; + if (rhdPtr->ChipSet < RHD_R600) { + struct R5xx3D *R5xx3D = rhdPtr->ThreeDPrivate; - if (CS->Clean != RHD_CS_CLEAN_QUEUED) { - R5xxDstCacheFlush(CS); - R5xxZCacheFlush(CS); - R5xxEngineWaitIdleFull(CS); + if (CS->Clean != RHD_CS_CLEAN_QUEUED) { + R5xxDstCacheFlush(CS); + R5xxZCacheFlush(CS); + R5xxEngineWaitIdleFull(CS); - CS->Clean = RHD_CS_CLEAN_QUEUED; - } + CS->Clean = RHD_CS_CLEAN_QUEUED; + } + + if (R5xx3D) + R5xx3D->XHas3DEngineState = FALSE; + } else { + struct r6xx_accel_state *accel_state = rhdPtr->TwoDPrivate; + + if (CS->Clean != RHD_CS_CLEAN_QUEUED) { + R6xxCacheFlush(CS); + R6xxEngineWaitIdleFull(CS); - if (R5xx3D) - R5xx3D->XHas3DEngineState = FALSE; + CS->Clean = RHD_CS_CLEAN_QUEUED; + } + + if (accel_state) + accel_state->XHas3DEngineState = FALSE; + } } else { /* if the engine has been untouched, we need to track this too. */ if (CS->Clean != RHD_CS_CLEAN_QUEUED) @@ -417,13 +431,18 @@ static void RHDEnterServer(ScreenPtr pScreen) static void RHDLeaveServer(ScreenPtr pScreen) { struct RhdCS *CS = RHDPTR(xf86Screens[pScreen->myNum])->CS; + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); /* The CP is always running, but if we've generated any CP commands * we must flush them to the kernel module now. */ if (CS->Clean == RHD_CS_CLEAN_DONE) { - - R5xxDstCacheFlush(CS); - R5xxZCacheFlush(CS); + if (rhdPtr->ChipSet >= RHD_R600) { + R6xxCacheFlush(CS); + } else { + R5xxDstCacheFlush(CS); + R5xxZCacheFlush(CS); + } RHDCSFlush(CS); /* was a Release... */ @@ -510,42 +529,48 @@ static void RHDDRIInitGARTValues(struct rhdDri * rhdDRI) /* Set AGP transfer mode according to requests and constraints */ static Bool RHDSetAgpMode(struct rhdDri * rhdDRI, ScreenPtr pScreen) { + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); unsigned long mode = drmAgpGetMode(rhdDRI->drmFD); /* Default mode */ unsigned int vendor = drmAgpVendorId(rhdDRI->drmFD); unsigned int device = drmAgpDeviceId(rhdDRI->drmFD); - /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with - pcie-agp rialto bridge chip - use the one from bridge which must match */ - CARD32 agp_status = (RHDRegRead (rhdDRI, AGP_STATUS) | AGPv3_MODE) & mode; - Bool is_v3 = (agp_status & AGPv3_MODE); - RHDFUNC(rhdDRI); + if (rhdPtr->ChipSet < RHD_R600) { + /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with + pcie-agp rialto bridge chip - use the one from bridge which must match */ + CARD32 agp_status = (RHDRegRead (rhdDRI, AGP_STATUS) | AGPv3_MODE) & mode; + Bool is_v3 = (agp_status & AGPv3_MODE); - if (is_v3) { - rhdDRI->agpMode = (agp_status & AGPv3_8X_MODE) ? 8 : 4; - } else { - if (agp_status & AGP_4X_MODE) - rhdDRI->agpMode = 4; - else if (agp_status & AGP_2X_MODE) - rhdDRI->agpMode = 2; - else - rhdDRI->agpMode = 1; - } - xf86DrvMsg(pScreen->myNum, X_DEFAULT, "Using AGP %dx\n", rhdDRI->agpMode); - - mode &= ~AGP_MODE_MASK; - if (is_v3) { - /* only set one mode bit for AGPv3 */ - switch (rhdDRI->agpMode) { - case 8: mode |= AGPv3_8X_MODE; break; - case 4: default: mode |= AGPv3_4X_MODE; + RHDFUNC(rhdDRI); + + if (is_v3) { + rhdDRI->agpMode = (agp_status & AGPv3_8X_MODE) ? 8 : 4; + } else { + if (agp_status & AGP_4X_MODE) + rhdDRI->agpMode = 4; + else if (agp_status & AGP_2X_MODE) + rhdDRI->agpMode = 2; + else + rhdDRI->agpMode = 1; } - } else { - switch (rhdDRI->agpMode) { - case 4: mode |= AGP_4X_MODE; - case 2: mode |= AGP_2X_MODE; - case 1: default: mode |= AGP_1X_MODE; + xf86DrvMsg(pScreen->myNum, X_DEFAULT, "Using AGP %dx\n", rhdDRI->agpMode); + + mode &= ~AGP_MODE_MASK; + if (is_v3) { + /* only set one mode bit for AGPv3 */ + switch (rhdDRI->agpMode) { + case 8: mode |= AGPv3_8X_MODE; break; + case 4: default: mode |= AGPv3_4X_MODE; + } + } else { + switch (rhdDRI->agpMode) { + case 4: mode |= AGP_4X_MODE; + case 2: mode |= AGP_2X_MODE; + case 1: default: mode |= AGP_1X_MODE; + } } - } + } else + rhdDRI->agpMode = 8; /* doesn't matter at this point */ xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x]\n", @@ -561,9 +586,13 @@ static Bool RHDSetAgpMode(struct rhdDri * rhdDRI, ScreenPtr pScreen) } /* Initialize Radeon's AGP registers */ -static void RHDSetAgpBase(struct rhdDri * rhdDRI) +static void RHDSetAgpBase(struct rhdDri * rhdDRI, ScreenPtr pScreen) { - RHDRegWrite (rhdDRI, AGP_BASE, drmAgpBase(rhdDRI->drmFD)); + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RHDPtr rhdPtr = RHDPTR(pScrn); + + if (rhdPtr->ChipSet < RHD_R600) + RHDRegWrite (rhdDRI, AGP_BASE, drmAgpBase(rhdDRI->drmFD)); } /* Initialize the AGP state. Request memory for use in AGP space, and @@ -680,7 +709,7 @@ static Bool RHDDRIAgpInit(struct rhdDri * rhdDRI, ScreenPtr pScreen) "[agp] GART Texture map mapped at 0x%08lx\n", (unsigned long)rhdDRI->gartTex); - RHDSetAgpBase(rhdDRI); + RHDSetAgpBase(rhdDRI, pScreen); return TRUE; } @@ -854,6 +883,9 @@ static int RHDDRIKernelInit(RHDPtr rhdPtr, ScreenPtr pScreen) drmInfo.buffers_offset = rhdDRI->bufHandle; drmInfo.gart_textures_offset= rhdDRI->gartTexHandle; + /* Make sure the MC has been set up before DRM_RADEON_CP_INIT is called */ + ASSERT((RHD_CHECKDEBUGFLAG(rhdPtr, MC_SETUP))); + if (drmCommandWrite(rhdDRI->drmFD, DRM_RADEON_CP_INIT, &drmInfo, sizeof(drm_radeon_init_t)) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[dri] CP_INIT failed\n"); @@ -1116,8 +1148,8 @@ Bool RHDDRIPreInit(ScrnInfoPtr pScrn) rhdPtr->directRenderingEnabled = FALSE; if (!rhdPtr->useDRI.val.bool) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering turned off by" - " default. Use Option \"DRI\" to enable.\n"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Direct rendering explicitly turned off.\n"); return FALSE; } @@ -1134,8 +1166,8 @@ Bool RHDDRIPreInit(ScrnInfoPtr pScrn) if (rhdPtr->ChipSet >= RHD_R600) { if (rhdPtr->useDRI.set && rhdPtr->useDRI.val.bool) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Direct rendering for R600 an up forced on - " - "This is NOT officially supported at the hardware level " + "Direct rendering for R600 and up forced on - " + "This is NOT officially supported yet " "and may cause instability or lockups\n"); } else { xf86DrvMsg(pScrn->scrnIndex, X_INFO, @@ -1446,12 +1478,6 @@ RHDDRIGARTBaseGet(RHDPtr rhdPtr) drm_radeon_getparam_t gp; int gart_base; - if (rhdPtr->cardType == RHD_CARD_AGP) { - xf86DrvMsg(rhdPtr->scrnIndex, X_INFO, - "%s: Unable to get GART address (AGP card).\n", __func__); - return 0; - } - memset(&gp, 0, sizeof(gp)); gp.param = RADEON_PARAM_GART_BASE; gp.value = &gart_base; @@ -1462,7 +1488,7 @@ RHDDRIGARTBaseGet(RHDPtr rhdPtr) "%s: Failed to determine GART area MC location.\n", __func__); return 0; } else { - RHDDebug(rhdPtr->scrnIndex, "GART location: 0x08X\n", gart_base); + RHDDebug(rhdPtr->scrnIndex, "GART location: 0x%08X\n", gart_base); return gart_base; } } @@ -1600,13 +1626,9 @@ void RHDDRIEnterVT(ScreenPtr pScreen) if (rhdPtr->cardType == RHD_CARD_AGP) { if (!RHDSetAgpMode(rhdDRI, pScreen)) return; - RHDSetAgpBase(rhdDRI); + RHDSetAgpBase(rhdDRI, pScreen); } - if ( (ret = drmCommandNone(rhdDRI->drmFD, DRM_RADEON_CP_RESUME)) ) - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "%s: CP resume %d\n", __func__, ret); - /* TODO: maybe using CP_INIT instead of CP_RESUME is enough, so we wouldn't * need an additional copy of the GART table in main memory. OTOH the table * must be initialized but not allocated anew. */ @@ -1617,7 +1639,9 @@ void RHDDRIEnterVT(ScreenPtr pScreen) RHDDRISetVBlankInterrupt(pScrn, rhdDRI->have3Dwindows); - DRIUnlock(pScrn->pScreen); + if ( (ret = drmCommandNone(rhdDRI->drmFD, DRM_RADEON_CP_RESUME)) ) + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "%s: CP resume %d\n", __func__, ret); } /* Stop all before vt switch / suspend */ @@ -1803,13 +1827,18 @@ static void RHDDRITransitionTo2d(ScreenPtr pScreen) static int RHDDRIGetPciAperTableSize(ScrnInfoPtr pScrn) { + RHDPtr rhdPtr = RHDPTR(pScrn); int page_size = getpagesize(); int ret_size; int num_pages; num_pages = (RHD_DEFAULT_PCI_APER_SIZE * 1024 * 1024) / page_size; - ret_size = num_pages * sizeof(unsigned int); + if ((rhdPtr->ChipSet >= RHD_R600) || + (rhdPtr->ChipSet == RHD_RS600)) + ret_size = num_pages * sizeof(uint64_t); + else + ret_size = num_pages * sizeof(unsigned int); return ret_size; } @@ -1898,7 +1927,8 @@ RHDDRMCPBuffer(int scrnIndex) int ret = drmDMA(Dri->drmFD, &dma); if (!ret) { buf = &Dri->buffers->list[indx]; - /* RHDDebug(scrnIndex, "%s: index %d, addr %p\n", __func__, buf->idx, buf->address); */ + //xf86DrvMsg(scrnIndex, X_INFO, "%s: index %d, addr %p\n", __func__, buf->idx, buf->address); + buf->used = 0; return buf; } else if (ret != -16) xf86DrvMsg(scrnIndex, X_ERROR, "%s: drmDMA returned %d\n", @@ -1965,3 +1995,14 @@ RHDDRMIndirectBufferDiscard(int scrnIndex, CARD8 *Buffer) __func__, Buffer); } +unsigned int +RHDDRIGetIntGARTLocation(ScrnInfoPtr pScrn) +{ + RHDPtr rhdPtr = RHDPTR(pScrn); + struct rhdDri *rhdDRI = rhdPtr->dri; + + if (!rhdDRI->gartLocation) + return 0; + + return rhdDRI->gartLocation + rhdDRI->bufStart; +} diff --git a/driver/xf86-video-radeonhd/src/rhd_dri.h b/driver/xf86-video-radeonhd/src/rhd_dri.h index d1e0a4107..ac860efb2 100644 --- a/driver/xf86-video-radeonhd/src/rhd_dri.h +++ b/driver/xf86-video-radeonhd/src/rhd_dri.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007-2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007-2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007-2008 Egbert Eich <eich@novell.com> * diff --git a/driver/xf86-video-radeonhd/src/rhd_driver.c b/driver/xf86-video-radeonhd/src/rhd_driver.c index 05bd35a0c..f849faa4a 100644 --- a/driver/xf86-video-radeonhd/src/rhd_driver.c +++ b/driver/xf86-video-radeonhd/src/rhd_driver.c @@ -1,8 +1,8 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007 Matthias Hopf <mhopf@novell.com> - * Copyright 2007 Egbert Eich <eich@novell.com> - * Copyright 2007 Advanced Micro Devices, Inc. + * Copyright 2007-2009 Luc Verhaegen <libv@exsuse.de> + * Copyright 2007-2009 Matthias Hopf <mhopf@novell.com> + * Copyright 2007-2009 Egbert Eich <eich@novell.com> + * Copyright 2007-2009 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -121,6 +121,7 @@ #include "rhd_video.h" #ifdef USE_DRI +#include "r6xx_accel.h" #include "rhd_dri.h" #endif @@ -157,7 +158,7 @@ static void rhdRestore(RHDPtr rhdPtr); static Bool rhdModeLayoutSelect(RHDPtr rhdPtr); static void rhdModeLayoutPrint(RHDPtr rhdPtr); static void rhdModeDPISet(ScrnInfoPtr pScrn); -static void rhdAllIdle(RHDPtr rhdPtr); +static Bool rhdAllIdle(RHDPtr rhdPtr); static void rhdModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode); static void rhdSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode); static Bool rhdMapMMIO(RHDPtr rhdPtr); @@ -765,6 +766,8 @@ RHDPreInit(ScrnInfoPtr pScrn, int flags) xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DRI support has been disabled at compile time\n"); #endif + if (rhdPtr->AccelMethod == RHD_ACCEL_FORCE_SHADOWFB) + rhdPtr->AccelMethod = RHD_ACCEL_SHADOWFB; if (xf86LoadSubModule(pScrn, "i2c")) { if (RHDI2CFunc(pScrn->scrnIndex, NULL, RHD_I2C_INIT, &i2cArg) @@ -803,8 +806,9 @@ RHDPreInit(ScrnInfoPtr pScrn, int flags) goto error1; } { - struct rhdAtomOutputDeviceList *OutputDeviceList = NULL; #ifdef ATOM_BIOS + struct rhdAtomOutputDeviceList *OutputDeviceList = NULL; + if (rhdPtr->Card && rhdPtr->Card->ConnectorInfo[0].Type != RHD_CONNECTOR_NONE && (rhdPtr->Card->DeviceInfo[0][0] != atomNone @@ -1075,10 +1079,13 @@ RHDScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) /* disable all memory accesses for MC setup */ RHDVGADisable(rhdPtr); - rhdAllIdle(rhdPtr); - /* now set up the MC - has to be done before DRI init */ - RHDMCSetup(rhdPtr); + if (!rhdAllIdle(rhdPtr)) + return FALSE; + + /* now set up the MC - has to be done after AllIdle and before DRI init */ + if (!RHDMCSetupFBLocation(rhdPtr, rhdPtr->FbIntAddress, rhdPtr->FbIntSize)) + return FALSE; #ifdef USE_DRI /* Setup DRI after visuals have been established, but before fbScreenInit is @@ -1143,15 +1150,17 @@ RHDScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) } else rhdPtr->AccelMethod = RHD_ACCEL_NONE; break; -#ifdef USE_EXA +#ifdef USE_DRI case RHD_ACCEL_EXA: if (rhdPtr->ChipSet < RHD_R600) { if (!R5xxEXAInit(pScrn, pScreen)) rhdPtr->AccelMethod = RHD_ACCEL_NONE; - } else - rhdPtr->AccelMethod = RHD_ACCEL_NONE; + } else { + if (!R6xxEXAInit(pScrn, pScreen)) + rhdPtr->AccelMethod = RHD_ACCEL_NONE; + } break; -#endif /* USE_EXA */ +#endif /* USE_DRI */ default: rhdPtr->AccelMethod = RHD_ACCEL_NONE; break; @@ -1209,7 +1218,8 @@ RHDScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) if(!miCreateDefColormap(pScreen)) return FALSE; /* fixme */ - if (!xf86HandleColormaps(pScreen, 256, pScrn->rgbBits, + /* Support 10-bits of precision in LUT */ + if (!xf86HandleColormaps(pScreen, 256, 10, RHDLoadPalette, NULL, CMAP_PALETTED_TRUECOLOR | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE; @@ -1240,18 +1250,27 @@ RHDScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) return TRUE; } -static void +static Bool rhdAllIdle(RHDPtr rhdPtr) { int i; + /* Make sure that VGA has been disabled before calling AllIdle() */ + ASSERT(RHD_CHECKDEBUGFLAG(rhdPtr, VGA_SETUP)); + /* stop scanout */ for (i = 0; i < 2; i++) - rhdPtr->Crtc[i]->Power(rhdPtr->Crtc[i], RHD_POWER_RESET); - - if (!RHDMCIdle(rhdPtr, 1000)) - xf86DrvMsg(rhdPtr->scrnIndex, X_WARNING, "MC not idle\n"); + if (!rhdPtr->Crtc[i]->Power(rhdPtr->Crtc[i], RHD_POWER_RESET)) { + xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, "%s: unable to stop CRTC: cannot idle MC\n", + __func__); + return FALSE; + } + if (!RHDMCIdleWait(rhdPtr, 1000)) { + xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, "MC not idle\n"); + return FALSE; + } + return TRUE; } /* @@ -1273,8 +1292,15 @@ rhdEngineIdle(ScrnInfoPtr pScrn) RHDCSIdle(CS); } - if ((rhdPtr->ChipSet < RHD_R600) && rhdPtr->TwoDPrivate) - R5xx2DIdle(pScrn); + if (rhdPtr->TwoDPrivate) { +#ifdef USE_DRI + if (rhdPtr->ChipSet >= RHD_R600) + R6xxIdle(pScrn); + else +#endif /* USE_DRI */ + R5xx2DIdle(pScrn); + } + } /* Mandatory */ @@ -1283,21 +1309,26 @@ RHDCloseScreen(int scrnIndex, ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RHDPtr rhdPtr = RHDPTR(pScrn); - + Bool Idle = TRUE; /* yes, this is correct! */ + /* Make sure our CS and 2D status is clean before destroying it */ - rhdEngineIdle(pScrn); + if (pScrn->vtSema) + rhdEngineIdle(pScrn); /* tear down 2d accel infrastructure */ if (rhdPtr->AccelMethod == RHD_ACCEL_SHADOWFB) RHDShadowCloseScreen(pScreen); -#ifdef USE_EXA +#ifdef USE_DRI else if (rhdPtr->AccelMethod == RHD_ACCEL_EXA) { if (rhdPtr->ChipSet < RHD_R600) { R5xxEXACloseScreen(pScreen); R5xxEXADestroy(pScrn); + } else { + R6xxEXACloseScreen(pScreen); + R6xxEXADestroy(pScrn); } } else -#endif /* USE_EXA */ +#endif /* USE_DRI */ if (rhdPtr->AccelMethod == RHD_ACCEL_XAA) { if (rhdPtr->ChipSet < RHD_R600) R5xxXAADestroy(pScrn); @@ -1310,11 +1341,15 @@ RHDCloseScreen(int scrnIndex, ScreenPtr pScreen) RHDCSStop(rhdPtr->CS); if (pScrn->vtSema) - rhdAllIdle(rhdPtr); + Idle = rhdAllIdle(rhdPtr); #ifdef USE_DRI - if (rhdPtr->dri) - RHDDRICloseScreen(pScreen); + if (rhdPtr->dri) { + if (Idle) + RHDDRICloseScreen(pScreen); + else + xf86DrvMsg(scrnIndex, X_ERROR, "MC not idle, cannot close DRI\n"); + } #endif if (pScrn->vtSema) rhdRestore(rhdPtr); @@ -1347,10 +1382,12 @@ RHDEnterVT(int scrnIndex, int flags) /* disable all memory accesses for MC setup */ RHDVGADisable(rhdPtr); - rhdAllIdle(rhdPtr); + + if (!rhdAllIdle(rhdPtr)) + return FALSE; /* now set up the MC - has to be done before DRI init */ - RHDMCSetup(rhdPtr); + RHDMCSetupFBLocation(rhdPtr, rhdPtr->FbIntAddress, rhdPtr->FbIntSize); #ifdef ATOM_BIOS /* Set accelerator mode in the BIOSScratch registers */ @@ -1379,7 +1416,17 @@ RHDEnterVT(int scrnIndex, int flags) #endif if (rhdPtr->CS) { - if (rhdPtr->ChipSet < RHD_R600) { +#ifdef USE_DRI + if (rhdPtr->ChipSet >= RHD_R600) { + if (rhdPtr->TwoDPrivate) { + R600LoadShaders(pScrn); + R6xxIdle(pScrn); + + ((struct r6xx_accel_state *) rhdPtr->TwoDPrivate)->XHas3DEngineState = + FALSE; + } + } else { +#endif if (rhdPtr->TwoDPrivate) { R5xx2DSetup(pScrn); R5xx2DIdle(pScrn); @@ -1388,7 +1435,9 @@ RHDEnterVT(int scrnIndex, int flags) if (rhdPtr->ThreeDPrivate) ((struct R5xx3D *) rhdPtr->ThreeDPrivate)->XHas3DEngineState = FALSE; +#ifdef USE_DRI } +#endif RHDCSStart(rhdPtr->CS); @@ -1399,6 +1448,12 @@ RHDEnterVT(int scrnIndex, int flags) RHDCSIdle(rhdPtr->CS); } +#ifdef USE_DRI + if (rhdPtr->dri) { + DRIUnlock(pScrn->pScreen); + } +#endif + return TRUE; } @@ -1843,6 +1898,7 @@ rhdUnmapFB(RHDPtr rhdPtr) if (!rhdPtr->FbBase) return; + switch (rhdPtr->ChipSet) { case RHD_RS690: case RHD_RS740: @@ -1858,7 +1914,8 @@ rhdUnmapFB(RHDPtr rhdPtr) rhdPtr->FbMapSize); #endif } - rhdPtr->FbBase = 0; + + rhdPtr->FbBase = NULL; } /* @@ -1937,7 +1994,7 @@ rhdOutputConnectorCheck(struct rhdConnector *Connector) /* Do this before sensing as AtomBIOS sense needs this info */ if ((Output->SensedType = Output->Sense(Output, Connector)) != RHD_SENSED_NONE) { RHDOutputPrintSensedType(Output); - Output->Connector = Connector; + RHDOutputAttachConnector(Output, Connector); break; } } @@ -1949,7 +2006,7 @@ rhdOutputConnectorCheck(struct rhdConnector *Connector) for (i = 0; i < 2; i++) { Output = Connector->Output[i]; if (Output && !Output->Sense) { - Output->Connector = Connector; + RHDOutputAttachConnector(Output, Connector); break; } } @@ -2374,7 +2431,7 @@ rhdSave(RHDPtr rhdPtr) RHDFUNC(rhdPtr); - RHDSaveMC(rhdPtr); + RHDMCSave(rhdPtr); RHDVGASave(rhdPtr); @@ -2401,7 +2458,7 @@ rhdRestore(RHDPtr rhdPtr) RHDFUNC(rhdPtr); - RHDRestoreMC(rhdPtr); + RHDMCRestore(rhdPtr); rhdRestoreCursor(pScrn); @@ -2411,6 +2468,7 @@ rhdRestore(RHDPtr rhdPtr) RHDVGARestore(rhdPtr); + /* restore after restoring CRTCs - check rhd_crtc.c for why */ RHDCrtcRestore(rhdPtr->Crtc[0]); RHDCrtcRestore(rhdPtr->Crtc[1]); @@ -2420,38 +2478,6 @@ rhdRestore(RHDPtr rhdPtr) #endif } -/* - * - */ -CARD32 -_RHDRegRead(int scrnIndex, CARD16 offset) -{ - return *(volatile CARD32 *)((CARD8 *) RHDPTR(xf86Screens[scrnIndex])->MMIOBase + offset); -} - -/* - * - */ -void -_RHDRegWrite(int scrnIndex, CARD16 offset, CARD32 value) -{ - *(volatile CARD32 *)((CARD8 *) RHDPTR(xf86Screens[scrnIndex])->MMIOBase + offset) = value; -} - -/* - * This one might seem clueless, but it is an actual lifesaver. - */ -void -_RHDRegMask(int scrnIndex, CARD16 offset, CARD32 value, CARD32 mask) -{ - CARD32 tmp; - - tmp = _RHDRegRead(scrnIndex, offset); - tmp &= ~mask; - tmp |= (value & mask); - _RHDRegWrite(scrnIndex, offset, tmp); -} - #ifdef RHD_DEBUG /* * @@ -2459,7 +2485,7 @@ _RHDRegMask(int scrnIndex, CARD16 offset, CARD32 value, CARD32 mask) CARD32 _RHDRegReadD(int scrnIndex, CARD16 offset) { - CARD32 tmp = *(volatile CARD32 *)((CARD8 *) RHDPTR(xf86Screens[scrnIndex])->MMIOBase + offset); + CARD32 tmp = MMIO_IN32(RHDPTR(xf86Screens[scrnIndex])->MMIOBase, offset); xf86DrvMsg(scrnIndex, X_INFO, "RHDRegRead(0x%4.4x) = 0x%4.4x\n",offset,tmp); return tmp; } @@ -2471,7 +2497,7 @@ void _RHDRegWriteD(int scrnIndex, CARD16 offset, CARD32 value) { xf86DrvMsg(scrnIndex, X_INFO, "RHDRegWrite(0x%4.4x,0x%4.4x)\n",offset,tmp); - *(volatile CARD32 *)((CARD8 *) RHDPTR(xf86Screens[scrnIndex])->MMIOBase + offset) = value; + MMIO_OUT32(RHDPTR(xf86Screens[scrnIndex])->MMIOBase, offset, value); } /* @@ -2497,11 +2523,11 @@ _RHDReadMC(int scrnIndex, CARD32 addr) CARD32 ret; if (rhdPtr->ChipSet < RHD_RS600) { - _RHDRegWrite(scrnIndex, MC_IND_INDEX, addr); - ret = _RHDRegRead(scrnIndex, MC_IND_DATA); + RHDRegWrite(rhdPtr, MC_IND_INDEX, addr); + ret = RHDRegRead(rhdPtr, MC_IND_DATA); } else if (rhdPtr->ChipSet == RHD_RS600) { - _RHDRegWrite(scrnIndex, RS60_MC_NB_MC_INDEX, addr); - ret = _RHDRegRead(scrnIndex, RS60_MC_NB_MC_DATA); + RHDRegWrite(rhdPtr, RS60_MC_NB_MC_INDEX, addr); + ret = RHDRegRead(rhdPtr, RS60_MC_NB_MC_DATA); } else if (rhdPtr->ChipSet == RHD_RS690 || rhdPtr->ChipSet == RHD_RS740) { #ifdef XSERVER_LIBPCIACCESS CARD32 data = addr & ~RS69_MC_IND_WR_EN; @@ -2521,9 +2547,10 @@ _RHDReadMC(int scrnIndex, CARD32 addr) ret = pciReadLong(rhdPtr->NBPciTag, RS78_NB_MC_IND_DATA); #endif } - +#ifdef RHD_DEBUG RHDDebug(scrnIndex,"%s(0x%08X) = 0x%08X\n",__func__,(unsigned int)addr, (unsigned int)ret); +#endif return ret; } @@ -2532,15 +2559,17 @@ _RHDWriteMC(int scrnIndex, CARD32 addr, CARD32 data) { RHDPtr rhdPtr = RHDPTR(xf86Screens[scrnIndex]); +#ifdef RHD_DEBUG RHDDebug(scrnIndex,"%s(0x%08X, 0x%08X)\n",__func__,(unsigned int)addr, (unsigned int)data); +#endif if (rhdPtr->ChipSet < RHD_RS600) { - _RHDRegWrite(scrnIndex, MC_IND_INDEX, addr | MC_IND_WR_EN); - _RHDRegWrite(scrnIndex, MC_IND_DATA, data); + RHDRegWrite(rhdPtr, MC_IND_INDEX, addr | MC_IND_WR_EN); + RHDRegWrite(rhdPtr, MC_IND_DATA, data); } else if (rhdPtr->ChipSet == RHD_RS600) { - _RHDRegWrite(scrnIndex, RS60_MC_NB_MC_INDEX, addr | RS60_NB_MC_IND_WR_EN); - _RHDRegWrite(scrnIndex, RS60_MC_NB_MC_DATA, data); + RHDRegWrite(rhdPtr, RS60_MC_NB_MC_INDEX, addr | RS60_NB_MC_IND_WR_EN); + RHDRegWrite(rhdPtr, RS60_MC_NB_MC_DATA, data); } else if (rhdPtr->ChipSet == RHD_RS690 || rhdPtr->ChipSet == RHD_RS740) { #ifdef XSERVER_LIBPCIACCESS CARD32 tmp = addr | RS69_MC_IND_WR_EN; @@ -2567,15 +2596,17 @@ _RHDWriteMC(int scrnIndex, CARD32 addr, CARD32 data) CARD32 _RHDReadPLL(int scrnIndex, CARD16 offset) { - _RHDRegWrite(scrnIndex, CLOCK_CNTL_INDEX, (offset & PLL_ADDR)); - return _RHDRegRead(scrnIndex, CLOCK_CNTL_DATA); + RHDPtr rhdPtr = RHDPTR(xf86Screens[scrnIndex]); + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, (offset & PLL_ADDR)); + return RHDRegRead(rhdPtr, CLOCK_CNTL_DATA); } void _RHDWritePLL(int scrnIndex, CARD16 offset, CARD32 data) { - _RHDRegWrite(scrnIndex, CLOCK_CNTL_INDEX, (offset & PLL_ADDR) | PLL_WR_EN); - _RHDRegWrite(scrnIndex, CLOCK_CNTL_DATA, data); + RHDPtr rhdPtr = RHDPTR(xf86Screens[scrnIndex]); + RHDRegWrite(rhdPtr, CLOCK_CNTL_INDEX, (offset & PLL_ADDR) | PLL_WR_EN); + RHDRegWrite(rhdPtr, CLOCK_CNTL_DATA, data); } #ifdef ATOM_BIOS @@ -2685,6 +2716,8 @@ rhdAccelOptionsHandle(ScrnInfoPtr pScrn) if (method.set) { if (!strcasecmp(method.val.string, "none")) rhdPtr->AccelMethod = RHD_ACCEL_NONE; + else if (!strcasecmp(method.val.string, "force-shadowfb")) + rhdPtr->AccelMethod = RHD_ACCEL_FORCE_SHADOWFB; else if (!strcasecmp(method.val.string, "shadowfb")) rhdPtr->AccelMethod = RHD_ACCEL_SHADOWFB; else if (!strcasecmp(method.val.string, "xaa")) @@ -2716,6 +2749,7 @@ rhdAccelOptionsHandle(ScrnInfoPtr pScrn) rhdPtr->AccelMethod = RHD_ACCEL_SHADOWFB; } +#if 0 if (rhdPtr->ChipSet >= RHD_R600) { if (rhdPtr->AccelMethod > RHD_ACCEL_SHADOWFB) { xf86DrvMsg(rhdPtr->scrnIndex, X_WARNING, "%s: HW 2D acceleration is" @@ -2723,6 +2757,7 @@ rhdAccelOptionsHandle(ScrnInfoPtr pScrn) rhdPtr->AccelMethod = RHD_ACCEL_SHADOWFB; } } +#endif /* Now for some pretty print */ switch (rhdPtr->AccelMethod) { #ifdef USE_EXA @@ -2733,6 +2768,9 @@ rhdAccelOptionsHandle(ScrnInfoPtr pScrn) case RHD_ACCEL_XAA: xf86DrvMsg(rhdPtr->scrnIndex, X_CONFIG, "Selected XAA 2D acceleration.\n"); break; + case RHD_ACCEL_FORCE_SHADOWFB: + xf86DrvMsg(rhdPtr->scrnIndex, X_WARNING, "Selected forced ShadowFB (even with DRI). Known to have issues.\n"); + break; case RHD_ACCEL_SHADOWFB: xf86DrvMsg(rhdPtr->scrnIndex, X_CONFIG, "Selected ShadowFB.\n"); break; @@ -2773,15 +2811,17 @@ rhdProcessOptions(ScrnInfoPtr pScrn) RhdGetOptValString (rhdPtr->Options, OPTION_RROUTPUTORDER, &rhdPtr->rrOutputOrder, NULL); RhdGetOptValBool (rhdPtr->Options, OPTION_DRI, - &rhdPtr->useDRI, FALSE); + &rhdPtr->useDRI, TRUE); RhdGetOptValString (rhdPtr->Options, OPTION_TV_MODE, &rhdPtr->tvModeName, NULL); RhdGetOptValString (rhdPtr->Options, OPTION_SCALE_TYPE, &rhdPtr->scaleTypeOpt, "default"); RhdGetOptValBool (rhdPtr->Options, OPTION_UNVERIFIED_FEAT, &rhdPtr->unverifiedFeatures, FALSE); +#ifdef ATOM_BIOS RhdGetOptValBool (rhdPtr->Options, OPTION_USE_ATOMBIOS, &rhdPtr->UseAtomBIOS, FALSE); +#endif RhdGetOptValBool (rhdPtr->Options, OPTION_AUDIO, &rhdPtr->audio, TRUE); RhdGetOptValString (rhdPtr->Options, OPTION_HDMI, @@ -2981,7 +3021,10 @@ rhdGetIGPNorthBridgeInfo(RHDPtr rhdPtr) static enum rhdCardType rhdGetCardType(RHDPtr rhdPtr) { - CARD32 cmd_stat; + uint32_t cmd_stat; + + if (rhdPtr->ChipSet == RHD_RS780) + return RHD_CARD_PCIE; #ifdef XSERVER_LIBPCIACCESS pci_device_cfg_read_u32(rhdPtr->PciInfo, &cmd_stat, PCI_CMD_STAT_REG); @@ -2989,7 +3032,7 @@ rhdGetCardType(RHDPtr rhdPtr) cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG); #endif if (cmd_stat & 0x100000) { - CARD32 cap_ptr, cap_id; + uint32_t cap_ptr, cap_id; #ifdef XSERVER_LIBPCIACCESS pci_device_cfg_read_u32(rhdPtr->PciInfo, &cap_ptr, 0x34); diff --git a/driver/xf86-video-radeonhd/src/rhd_edid.c b/driver/xf86-video-radeonhd/src/rhd_edid.c index 1db9944e4..5b791615c 100644 --- a/driver/xf86-video-radeonhd/src/rhd_edid.c +++ b/driver/xf86-video-radeonhd/src/rhd_edid.c @@ -1,5 +1,5 @@ /* - * Copyright 2006-2007 Luc Verhaegen <lverhaegen@novell.com>. + * Copyright 2006-2007 Luc Verhaegen <libv@exsuse.de>. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/driver/xf86-video-radeonhd/src/rhd_hdmi.c b/driver/xf86-video-radeonhd/src/rhd_hdmi.c index e342ef46b..9a525367c 100644 --- a/driver/xf86-video-radeonhd/src/rhd_hdmi.c +++ b/driver/xf86-video-radeonhd/src/rhd_hdmi.c @@ -1,6 +1,6 @@ /* * Copyright 2008 Christian König <deathsimple@vodafone.de> - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_hdmi.h b/driver/xf86-video-radeonhd/src/rhd_hdmi.h index 7518a1372..42294172b 100644 --- a/driver/xf86-video-radeonhd/src/rhd_hdmi.h +++ b/driver/xf86-video-radeonhd/src/rhd_hdmi.h @@ -1,6 +1,6 @@ /* * Copyright 2008 Christian König <deathsimple@vodafone.de> - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_helper.c b/driver/xf86-video-radeonhd/src/rhd_helper.c index 84f5cd47e..0f47bba4d 100644 --- a/driver/xf86-video-radeonhd/src/rhd_helper.c +++ b/driver/xf86-video-radeonhd/src/rhd_helper.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. @@ -120,9 +120,23 @@ RhdGetOptValString(const OptionInfoRec *table, int token, enum rhdOptStatus RhdParseBooleanOption(struct RHDOpt *Option, char *Name) { + unsigned int i; char* c; char* str = strdup(Name); + const char* off[] = { + "false", + "off", + "no", + "0" + }; + const char* on[] = { + "true", + "on", + "yes", + "1" + }; + /* first fixup the name to match the randr names */ for (c = str; *c; c++) if (isspace(*c)) @@ -146,12 +160,16 @@ RhdParseBooleanOption(struct RHDOpt *Option, char *Name) if (isspace(*ptr) || *ptr == '=') { ptr++; } - if (!strncasecmp("off",ptr,3) || !strncasecmp("0",ptr,1) || !strncasecmp("no",ptr,2)) { - return RHD_OPTION_OFF; - } else if (!strncasecmp("on",ptr,2) || !strncasecmp("1",ptr,1) || !strncasecmp("yes",ptr,3)) { - return RHD_OPTION_ON; - } else - return RHD_OPTION_DEFAULT; + + for(i=0; i<sizeof(on)/sizeof(char*); i++) + if (!strncasecmp(on[i],ptr,strlen(on[i]))) + return RHD_OPTION_OFF; + + for(i=0; i<sizeof(off)/sizeof(char*); i++) + if (!strncasecmp(off[i],ptr,strlen(off[i]))) + return RHD_OPTION_ON; + + return RHD_OPTION_DEFAULT; } else while (*ptr != '\0' && !isspace(*ptr)) ptr++; diff --git a/driver/xf86-video-radeonhd/src/rhd_i2c.c b/driver/xf86-video-radeonhd/src/rhd_i2c.c index ee09ab34f..3a45f8c76 100644 --- a/driver/xf86-video-radeonhd/src/rhd_i2c.c +++ b/driver/xf86-video-radeonhd/src/rhd_i2c.c @@ -1,8 +1,8 @@ /* - * Copyright 2007, 2008 Egbert Eich <eich@novell.com> - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> - * Copyright 2007, 2008 Advanced Micro Devices, Inc. + * Copyright 2007-2009 Egbert Eich <eich@novell.com> + * Copyright 2007-2009 Luc Verhaegen <libv@exsuse.de> + * Copyright 2007-2009 Matthias Hopf <mhopf@novell.com> + * Copyright 2007-2009 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1257,7 +1257,7 @@ rhdInitI2C(int scrnIndex) else if (rhdPtr->ChipSet > RHD_RS740 && sda == rhdDdc4data && scl == rhdDdc4clk) I2C->u.line = 3; /* R6XX only */ else { - xf86DrvMsg(I2CPtr->scrnIndex, X_ERROR, "No DDC line found for index %i: scl=0x%2.2x sda=0x%2.2x\n", + xf86DrvMsg(scrnIndex, X_ERROR, "No DDC line found for index %i: scl=0x%2.2x sda=0x%2.2x\n", i, scl, sda); xfree(I2C); continue; @@ -1270,14 +1270,14 @@ rhdInitI2C(int scrnIndex) if (valid) { if (sda != rhdDdc1data && sda != rhdDdc2data && sda != rhdDdc3data) { - xf86DrvMsg(I2CPtr->scrnIndex, X_ERROR, "Invalid DDC CLK pin found: %i\n", + xf86DrvMsg(scrnIndex, X_ERROR, "Invalid DDC CLK pin found: %i\n", sda); xfree(I2C); continue; } if (scl != rhdDdc1data && scl != rhdDdc2data && scl != rhdDdc3data && scl != rhdDdc1clk && scl != rhdDdc2clk && scl != rhdDdc3clk) { - xf86DrvMsg(I2CPtr->scrnIndex, X_ERROR, "Invalid DDC CLK pin found: %i\n", + xf86DrvMsg(scrnIndex, X_ERROR, "Invalid DDC CLK pin found: %i\n", scl); xfree(I2C); continue; @@ -1288,7 +1288,7 @@ rhdInitI2C(int scrnIndex) I2C->u.Gpio.SclReg = scl_reg; } else { - xf86DrvMsg(I2CPtr->scrnIndex, X_ERROR, "Invalid ClkLine for DDC. " + xf86DrvMsg(scrnIndex, X_ERROR, "Invalid ClkLine for DDC. " "AtomBIOS reported wrong or AtomBIOS unavailable\n"); xfree(I2C); goto error; diff --git a/driver/xf86-video-radeonhd/src/rhd_i2c.h b/driver/xf86-video-radeonhd/src/rhd_i2c.h index 3e6dc3bd1..cfc274708 100644 --- a/driver/xf86-video-radeonhd/src/rhd_i2c.h +++ b/driver/xf86-video-radeonhd/src/rhd_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_id.c b/driver/xf86-video-radeonhd/src/rhd_id.c index 875c35836..4a162c37b 100644 --- a/driver/xf86-video-radeonhd/src/rhd_id.c +++ b/driver/xf86-video-radeonhd/src/rhd_id.c @@ -1,8 +1,8 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007 Matthias Hopf <mhopf@novell.com> - * Copyright 2007 Egbert Eich <eich@novell.com> - * Copyright 2007 Advanced Micro Devices, Inc. + * Copyright 2007-2009 Luc Verhaegen <libv@exsuse.de> + * Copyright 2007-2009 Matthias Hopf <mhopf@novell.com> + * Copyright 2007-2009 Egbert Eich <eich@novell.com> + * Copyright 2007-2009 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -82,6 +82,7 @@ SymTabRec RHDChipsets[] = { { RHD_RV635, "RV635" }, { RHD_M86, "M86" }, { RHD_RS780, "RS780" }, + { RHD_RS880, "RS880" }, { RHD_RV770, "RV770" }, { RHD_RV730, "RV730" }, { RHD_RV710, "RV710" }, @@ -230,11 +231,14 @@ const PCI_ID_LIST = { // RHD_DEVICE_MATCH( 0x9447, RHD_R700 ), /* K2 ATI FirePro Graphics Accelerator */ RHD_DEVICE_MATCH( 0x944A, RHD_M98 ), /* M98 */ RHD_DEVICE_MATCH( 0x944B, RHD_M98 ), /* M98 */ + RHD_DEVICE_MATCH( 0x944C, RHD_RV770 ), /* RV770 */ RHD_DEVICE_MATCH( 0x944E, RHD_RV770 ), /* RV770 */ // RHD_DEVICE_MATCH( 0x944F, RHD_R700 ), /* R700 */ RHD_DEVICE_MATCH( 0x9456, RHD_RV770 ), /* Denali ATI FirePro Graphics Accelerator */ RHD_DEVICE_MATCH( 0x945A, RHD_M98 ), /* M98 */ RHD_DEVICE_MATCH( 0x945B, RHD_M98 ), /* M98 */ + RHD_DEVICE_MATCH( 0x9460, RHD_RV770 ), /* RV790 */ + RHD_DEVICE_MATCH( 0x9462, RHD_RV770 ), /* RV790 */ RHD_DEVICE_MATCH( 0x946A, RHD_M98 ), /* M98 */ RHD_DEVICE_MATCH( 0x946B, RHD_M98 ), /* M98 */ RHD_DEVICE_MATCH( 0x947A, RHD_M98 ), /* M98 */ @@ -315,6 +319,13 @@ const PCI_ID_LIST = { RHD_DEVICE_MATCH( 0x9612, RHD_RS780 ), /* ATI Radeon HD 3200 Graphics */ RHD_DEVICE_MATCH( 0x9613, RHD_RS780 ), /* ATI Radeon 3100 Graphics */ RHD_DEVICE_MATCH( 0x9614, RHD_RS780 ), /* ATI Radeon HD 3300 Graphics */ + RHD_DEVICE_MATCH( 0x9615, RHD_RS780 ), /* ATI Radeon HD 3200 Graphics */ + RHD_DEVICE_MATCH( 0x9616, RHD_RS780 ), /* ATI Radeon HD 3000 Graphics */ + RHD_DEVICE_MATCH( 0x9710, RHD_RS880 ), /* ATI Radeon HD Graphics */ + RHD_DEVICE_MATCH( 0x9711, RHD_RS880 ), /* ATI Radeon Graphics */ + RHD_DEVICE_MATCH( 0x9712, RHD_RS880 ), /* ATI Mobility Radeon HD Graphics */ + RHD_DEVICE_MATCH( 0x9713, RHD_RS880 ), /* ATI Mobility Radeon Graphics */ + RHD_DEVICE_MATCH( 0x9714, RHD_RS880 ), /* ATI Radeon Graphics */ LIST_END }; @@ -323,6 +334,7 @@ static enum RHD_CHIPSETS rhdIGPChipsetList[] = { RHD_RS690, RHD_RS690, RHD_RS780, + RHD_RS880, RHD_UNKNOWN /* end marker */ }; @@ -416,10 +428,12 @@ RHDIsIGP(enum RHD_CHIPSETS chipset) #ifdef ATOM_BIOS # define DEVINFO_EMPTY { { atomNone, atomNone } } +#else +# define DEVINFO_EMPTY #endif /* Radeon RV610 0x94C3 0x0000 0x0000 */ -#define VGA_B1_TV_B_DVI_AA00 \ +#define VGA_B1_TV_B0_DVI_AB00 \ {{ RHD_CONNECTOR_DVI_SINGLE, "VGA CRT2", RHD_DDC_1, RHD_HPD_NONE, \ { RHD_OUTPUT_NONE, RHD_OUTPUT_DACB }}, \ {RHD_CONNECTOR_TV, "7PIN_DIN TV1 CV", RHD_DDC_0, RHD_HPD_NONE, \ @@ -429,7 +443,7 @@ RHDIsIGP(enum RHD_CHIPSETS chipset) /* Radeon X1300 0x7187:0x1545:0x1930 */ -#define VGA_A0_TV_B_DVI_B11 \ +#define VGA_A0_TV_B_DVI_XB11 \ { { RHD_CONNECTOR_VGA, "VGA CRT1", RHD_DDC_0, RHD_HPD_NONE, \ { RHD_OUTPUT_DACA, RHD_OUTPUT_NONE }}, \ { RHD_CONNECTOR_TV, "SVIDEO TV1", RHD_DDC_NONE, RHD_HPD_NONE, \ @@ -445,7 +459,7 @@ RHDIsIGP(enum RHD_CHIPSETS chipset) { RHD_OUTPUT_DACB, RHD_OUTPUT_LVTMA}}} /* 0x7249:0x1043:0x0168 */ -#define DVI_AB10_DVI_A01 \ +#define DVI_BA10_DVI_XB01_TV_B \ { { RHD_CONNECTOR_DVI, "DVI-I DFP1 CRT2", RHD_DDC_1, RHD_HPD_0, \ { RHD_OUTPUT_TMDSA, RHD_OUTPUT_DACB }}, \ { RHD_CONNECTOR_DVI, "DVI-I DFP2", RHD_DDC_0, RHD_HPD_1, \ @@ -453,7 +467,8 @@ RHDIsIGP(enum RHD_CHIPSETS chipset) { RHD_CONNECTOR_TV, "SVIDEO TV1", RHD_DDC_NONE, RHD_HPD_NONE, \ { RHD_OUTPUT_DACB, RHD_OUTPUT_NONE }}} -#define VISIONTEK_C1550 \ +/* Visiontek C1550 */ +#define VGA_A0_TV_B_DVI_BB10 \ { {RHD_CONNECTOR_VGA, "VGA", RHD_DDC_0, RHD_HPD_NONE, \ { RHD_OUTPUT_DACA, RHD_OUTPUT_NONE } }, \ {RHD_CONNECTOR_TV, "SVIDEO", RHD_DDC_NONE, RHD_HPD_NONE, \ @@ -461,8 +476,8 @@ RHDIsIGP(enum RHD_CHIPSETS chipset) {RHD_CONNECTOR_DVI, "DVI-I", RHD_DDC_1, RHD_HPD_0, \ { RHD_OUTPUT_LVTMA, RHD_OUTPUT_DACB } } } -/* MacBook Pro provides a weird atombios connector table. */ -#define ID_CONNECTORINFO_MACBOOKPRO \ +/* MacBook Pro */ +#define PANEL_B2_DVI_BA00 \ { {RHD_CONNECTOR_PANEL, "Panel", RHD_DDC_2, RHD_HPD_NONE, \ { RHD_OUTPUT_LVTMA, RHD_OUTPUT_NONE}}, \ {RHD_CONNECTOR_DVI, "DVI-I", RHD_DDC_0, RHD_HPD_0, \ @@ -471,10 +486,12 @@ RHDIsIGP(enum RHD_CHIPSETS chipset) #ifdef ATOM_BIOS # define DEVINFO_MACBOOKPRO \ { { atomLCD1, atomNone }, { atomCRT2, atomDFP1 } } +#else +# define DEVINFO_MACBOOKPRO #endif /* GeCube HD 2400PRO AGP (GC-RX24PGA2-D3) specifies 2 DVI again.*/ -#define BROKEN_VGA_B1_DVI_AB00 \ +#define DVI_AB00_VGA_B1 \ { {RHD_CONNECTOR_DVI, "DVI-I", RHD_DDC_0, RHD_HPD_0, \ { RHD_OUTPUT_DACA, RHD_OUTPUT_LVTMA}}, \ {RHD_CONNECTOR_VGA, "VGA", RHD_DDC_1, RHD_HPD_NONE, \ @@ -497,7 +514,7 @@ RHDIsIGP(enum RHD_CHIPSETS chipset) { RHD_OUTPUT_NONE, RHD_OUTPUT_DACA }}} /* MSI RX2600PRO-T2D512Z/D2 */ -#define DVI_BA12_TV_B0_DVI_AB01 \ +#define DVI_BA12_TV_B_DVI_AB01 \ { { RHD_CONNECTOR_DVI, "DUAL_LINK_DVI_I DFP1 CRT2", RHD_DDC_1, RHD_HPD_2, \ { RHD_OUTPUT_TMDSA, RHD_OUTPUT_DACB }}, \ { RHD_CONNECTOR_TV, "7PIN_DIN TV1 CV", RHD_DDC_NONE, RHD_HPD_NONE, \ @@ -505,6 +522,16 @@ RHDIsIGP(enum RHD_CHIPSETS chipset) { RHD_CONNECTOR_DVI, "DUAL_LINK_DVI_I CRT1 DFP2", RHD_DDC_0, RHD_HPD_1, \ { RHD_OUTPUT_LVTMA, RHD_OUTPUT_DACA }}} +/* HIS Radeon X1550 PCI claims to have two DVI ports where it has only one */ +#define VGA_A0_TV_B_DVI_BA10 \ + { {RHD_CONNECTOR_VGA, "VGA", RHD_DDC_0, RHD_HPD_NONE, \ + { RHD_OUTPUT_DACA, RHD_OUTPUT_NONE } }, \ + {RHD_CONNECTOR_TV, "SVIDEO", RHD_DDC_NONE, RHD_HPD_NONE, \ + { RHD_OUTPUT_DACB, RHD_OUTPUT_NONE } }, \ + {RHD_CONNECTOR_DVI, "DVI-I", RHD_DDC_1, RHD_HPD_0, \ + { RHD_OUTPUT_TMDSA, RHD_OUTPUT_DACB } } } + + #if defined(USE_ID_CONNECTORS) || !defined(ATOM_BIOS) #define VGA_A0_TVB_DVI_BB12 \ @@ -646,6 +673,7 @@ rhdCards[] = /* 0x7141 : RV505 : RV505 */ /* 0x7142 : RV515 : Radeon X1300/X1550 */ /* 0x7143 : RV505 : Radeon X1550 */ + { 0x7143, 0x17AF, 0x204E, "HIS Radeon X1550 PCI", RHD_CARD_FLAG_NONE, VGA_A0_TV_B_DVI_BA10, DEVINFO_EMPTY }, /* 0x7144 : M54 : M54-GL */ /* 0x7145 : M54 : Mobility Radeon X1400 */ { 0x7145, 0x1028, 0x2002, "Dell Inspiron 9400", RHD_CARD_FLAG_NONE, PANEL_B2_VGA_A0_DVI_A10, DEVINFO_EMPTY }, @@ -658,7 +686,7 @@ rhdCards[] = /* 0x7146 : RV515 : Radeon X1300/X1550 */ { 0x7146, 0x174B, 0x0470, "Sapphire X1300", RHD_CARD_FLAG_NONE, VGA_B1_DVI_AB01, DEVINFO_EMPTY }, { 0x7146, 0x174B, 0x0920, "Sapphire X1300", RHD_CARD_FLAG_HPDSWAP, ID_CONNECTORINFO_EMPTY, DEVINFO_EMPTY }, - { 0x7146, 0x1545, 0x2350, "Visiontek C1550", RHD_CARD_FLAG_NONE, VISIONTEK_C1550, DEVINFO_EMPTY }, + { 0x7146, 0x1545, 0x2350, "Visiontek C1550", RHD_CARD_FLAG_NONE, VGA_A0_TV_B_DVI_BB10, DEVINFO_EMPTY }, /* 0x7147 : RV505 : Radeon X1550 64-bit */ { 0x7147, 0x174B, 0x0840, "Sapphire X1550", RHD_CARD_FLAG_HPDSWAP, ID_CONNECTORINFO_EMPTY, DEVINFO_EMPTY }, /* 0x7149 : M52 : Mobility Radeon X1300 */ @@ -685,7 +713,7 @@ rhdCards[] = /* 0x7187 : RV516 : Radeon X1300/X1550 */ { 0x7187, 0x174B, 0x3000, "RV516 : Radeon X1300/X1550", RHD_CARD_FLAG_HPDSWAP, ID_CONNECTORINFO_EMPTY, DEVINFO_EMPTY }, { 0x7187, 0x1458, 0x215C, "RV516 : Radeon X1300/X1550", RHD_CARD_FLAG_DMS59, ID_CONNECTORINFO_EMPTY, DEVINFO_EMPTY }, - { 0x7187, 0x1545, 0x1930, "RV516 : Radeon X1300", RHD_CARD_FLAG_NONE, VGA_A0_TV_B_DVI_B11, DEVINFO_EMPTY }, + { 0x7187, 0x1545, 0x1930, "RV516 : Radeon X1300", RHD_CARD_FLAG_NONE, VGA_A0_TV_B_DVI_XB11, DEVINFO_EMPTY }, /* 0x7188 : M64 : Mobility Radeon X2300 */ /* 0x718A : M64 : Mobility Radeon X2300 */ /* 0x718B : M62 : Mobility Radeon X1350 */ @@ -709,7 +737,7 @@ rhdCards[] = { 0x71C5, 0x103C, 0x30A3, "HP/Compaq nc8430", RHD_CARD_FLAG_NONE, PANEL_B1_VGA_A0, DEVINFO_EMPTY }, { 0x71C5, 0x103C, 0x30B4, "HP/Compaq nw8440", RHD_CARD_FLAG_NONE, PANEL_B1_VGA_A0, DEVINFO_EMPTY }, { 0x71C5, 0x1043, 0x10B2, "Asus W3J/Z96", RHD_CARD_FLAG_NONE, PANEL_B_VGA_A0, DEVINFO_EMPTY }, - { 0x71C5, 0x106B, 0x0080, "Macbook Pro", RHD_CARD_FLAG_NONE, ID_CONNECTORINFO_MACBOOKPRO, DEVINFO_MACBOOKPRO }, + { 0x71C5, 0x106B, 0x0080, "Macbook Pro", RHD_CARD_FLAG_NONE, PANEL_B2_DVI_BA00, DEVINFO_MACBOOKPRO }, { 0x71C5, 0x1179, 0xFF10, "Toshiba Satellite A100-237", RHD_CARD_FLAG_NONE, PANEL_B1_VGA_A2, DEVINFO_EMPTY }, /* 0x71C6 : RV530 : Radeon X1650 */ { 0x71C6, 0x174B, 0x0850, "Sapphire X1650 Pro AGP", RHD_CARD_FLAG_NONE, VGA_A0_DVI_BA10, DEVINFO_EMPTY }, @@ -741,7 +769,7 @@ rhdCards[] = /* 0x7248 : R580 : Radeon X1900 */ /* 0x7249 : R580 : Radeon X1900 */ { 0x7249, 0x1002, 0x0B12, "ATI Radeon X1900 XTX", RHD_CARD_FLAG_NONE, DVI_BA10_DVI_AB01, DEVINFO_EMPTY }, - /* { 0x7249, 0x1043, 0x016B, "ATI Radeon X1900 XTX", RHD_CARD_FLAG_NONE, DVI_AB10_DVI_A01, DEVINFO_EMPTY }, */ + /* { 0x7249, 0x1043, 0x016B, "ATI Radeon X1900 XTX", RHD_CARD_FLAG_NONE, DVI_BA10_DVI_XB01_TV_B, DEVINFO_EMPTY }, */ /* 0x724A : R580 : Radeon X1900 */ /* 0x724B : R580 : Radeon X1900 */ { 0x724B, 0x1002, 0x0B12, "Sapphire Radeon X1900 GT", RHD_CARD_FLAG_NONE, ID_CONNECTORINFO_EMPTY, DEVINFO_EMPTY }, @@ -790,12 +818,13 @@ rhdCards[] = { 0x94C1, 0x1002, 0x0D02, "ATI Radeon HD 2400 XT", RHD_CARD_FLAG_DMS59, ID_CONNECTORINFO_EMPTY, DEVINFO_EMPTY }, { 0x94C1, 0x1028, 0x0D02, "Dell Radeon HD 2400 XT", RHD_CARD_FLAG_DMS59, ID_CONNECTORINFO_EMPTY, DEVINFO_EMPTY }, { 0x94C1, 0x174B, 0xE390, "Sapphire HD 2400 XT", RHD_CARD_FLAG_NONE, VGA_B1_DVI_AB00, DEVINFO_EMPTY }, - { 0x94C3, 0x0000, 0x0000, "ATI Radeon 2400 HD GENERIC", RHD_CARD_FLAG_NONE, VGA_B1_TV_B_DVI_AA00, DEVINFO_EMPTY }, + { 0x94C3, 0x0000, 0x0000, "ATI Radeon 2400 HD GENERIC", RHD_CARD_FLAG_NONE, VGA_B1_TV_B0_DVI_AB00, DEVINFO_EMPTY }, /* 0x94C3 : RV610 : Radeon HD 2400 Pro */ { 0x94C3, 0x1545, 0x3210, "ATI Radeon 2400HD Pro", RHD_CARD_FLAG_HPDSWAP, ID_CONNECTORINFO_EMPTY, DEVINFO_EMPTY }, { 0x94C3, 0x174B, 0xE370, "Sapphire HD 2400 Pro", RHD_CARD_FLAG_NONE, VGA_A0_DVI_BB10, DEVINFO_EMPTY }, + { 0x94C3, 0x18BC, 0x3550, "GeCube Radeon HD 2400PRO", RHD_CARD_FLAG_NONE, DVI_AB00_VGA_B1, DEVINFO_EMPTY }, /* 0x94C4 : RV610 : ATI Radeon HD 2400 PRO AGP */ - { 0x94C4, 0x18BC, 0x0028, "GeCube Radeon HD 2400PRO AGP", RHD_CARD_FLAG_NONE, BROKEN_VGA_B1_DVI_AB00, DEVINFO_EMPTY }, + { 0x94C4, 0x18BC, 0x0028, "GeCube Radeon HD 2400PRO AGP", RHD_CARD_FLAG_NONE, DVI_AB00_VGA_B1, DEVINFO_EMPTY }, /* 0x94C5 : RV610 : ATI FireGL V4000 */ /* 0x94C6 : RV610 : RV610 */ /* 0x94C7 : RV610 : ATI Radeon HD 2350 */ @@ -810,7 +839,7 @@ rhdCards[] = /* 0x9586 : RV630 : ATI Radeon HD 2600 XT AGP */ /* 0x9587 : RV630 : ATI Radeon HD 2600 Pro AGP */ { 0x9587, 0x1002, 0x0028, "Sapphire Radeon HD 2600 PRO AGP", RHD_CARD_FLAG_NONE, DVI_BA10_TV_B0_VGA_A0, DEVINFO_EMPTY }, - { 0x9587, 0x1462, 0x0028, "MSI HD2600PRO AGP", RHD_CARD_FLAG_NONE, DVI_BA12_TV_B0_DVI_AB01, DEVINFO_EMPTY }, + { 0x9587, 0x1462, 0x0028, "MSI HD2600PRO AGP", RHD_CARD_FLAG_NONE, DVI_BA12_TV_B_DVI_AB01, DEVINFO_EMPTY }, /* 0x9588 : RV630 : Radeon HD 2600 XT */ { 0x9588, 0x1002, 0x2542, "ATI Radeon HD 2600XT DDR4", RHD_CARD_FLAG_NONE, DVI_BA10_DVI_AB01, DEVINFO_EMPTY }, { 0x9588, 0x1448, 0x216C, "Gigabyte HD 2600 XT 256MB DDR3", RHD_CARD_FLAG_NONE, DVI_BA10_DVI_AB01, DEVINFO_EMPTY }, @@ -822,6 +851,7 @@ rhdCards[] = /* 0x958C : RV630 : ATI FireGL V5600 */ /* 0x958D : RV630 : ATI FireGL V3600 */ /* 0x958E : RV630 : ATI Radeon HD 2600 LE */ + { 0x95c5, 0x1787, 0x2252, "PowerColor HD 3450", RHD_CARD_FLAG_HPDOFF, ID_CONNECTORINFO_EMPTY, DEVINFO_EMPTY }, { 0x9610, 0x105B, 0x0E0F, "Foxconn A7GM-S (RS780)", RHD_CARD_FLAG_HPDOFF, ID_CONNECTORINFO_EMPTY, DEVINFO_EMPTY }, { 0, 0, 0, NULL, 0, ID_CONNECTORINFO_EMPTY, DEVINFO_EMPTY } /* KEEP THIS: End marker. */ }; diff --git a/driver/xf86-video-radeonhd/src/rhd_lut.c b/driver/xf86-video-radeonhd/src/rhd_lut.c index 448127b89..848ec137c 100644 --- a/driver/xf86-video-radeonhd/src/rhd_lut.c +++ b/driver/xf86-video-radeonhd/src/rhd_lut.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007-2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007-2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007-2008 Egbert Eich <eich@novell.com> * @@ -32,6 +32,8 @@ #include "rhd_lut.h" #include "rhd_regs.h" +#include <compiler.h> + #define RHD_REGOFFSET_LUTA 0x000 #define RHD_REGOFFSET_LUTB 0x800 @@ -124,7 +126,7 @@ LUTxSet(struct rhdLUT *LUT, int numColors, int *indices, LOCO *colors) { ScrnInfoPtr pScrn = xf86Screens[LUT->scrnIndex]; CARD16 RegOff; - int i, index; + int i, index, hw_index; LUT->Initialised = TRUE; /* thank you RandR */ @@ -151,39 +153,64 @@ LUTxSet(struct rhdLUT *LUT, int numColors, int *indices, LOCO *colors) RHDRegWrite(LUT, DC_LUT_RW_MODE, 0); /* table */ RHDRegWrite(LUT, DC_LUT_WRITE_EN_MASK, 0x0000003F); + /* DC_LUT_RW_INDEX is incremented automatically when DC_LUT_30_COLOR + * is accessed; hw_index is used to track the value of DC_LUT_RW_INDEX + * so that we can properly handle the very unlikely case that the input + * table indexes are not monotonically increasing + */ switch (pScrn->depth) { case 8: case 24: case 32: + RHDRegWrite(LUT, DC_LUT_RW_INDEX, 0); + hw_index = 0; for (i = 0; i < numColors; i++) { - index = indices[i]; - RHDRegWrite(LUT, DC_LUT_RW_INDEX, index); - RHDRegWrite(LUT, DC_LUT_30_COLOR, (colors[index].red << 22) | - (colors[index].green << 12) | (colors[index].blue << 2)); + index = indices[i]; + if (hw_index != index) { + RHDRegWrite(LUT, DC_LUT_RW_INDEX, index); + hw_index = index; + } + RHDRegWrite(LUT, DC_LUT_30_COLOR, (colors[index].red << 20) | + (colors[index].green << 10) | (colors[index].blue)); + hw_index++; } break; case 16: + RHDRegWrite(LUT, DC_LUT_RW_INDEX, 0); + hw_index = 0; for (i = 0; i < numColors; i++) { int j; index = indices[i]; - RHDRegWrite(LUT, DC_LUT_RW_INDEX, 4 * index); - - for (j = 0; j < 4; j++) - RHDRegWrite(LUT, DC_LUT_30_COLOR, (colors[index/2].red << 24) | - (colors[index].green << 14) | (colors[index/2].blue << 4)); + if (hw_index != 4 * index) { + RHDRegWrite(LUT, DC_LUT_RW_INDEX, 4 * index); + hw_index = 4 * index; + } + + for (j = 0; j < 4; j++) { + RHDRegWrite(LUT, DC_LUT_30_COLOR, (colors[index/2].red << 20) | + (colors[index].green << 10) | (colors[index/2].blue)); + hw_index++; + } } break; case 15: + RHDRegWrite(LUT, DC_LUT_RW_INDEX, 0); + hw_index = 0; for (i = 0; i < numColors; i++) { int j; index = indices[i]; - RHDRegWrite(LUT, DC_LUT_RW_INDEX, 8 * index); - - for (j = 0; j < 8; j++) - RHDRegWrite(LUT, DC_LUT_30_COLOR, (colors[index].red << 25) | - (colors[index].green << 15) | (colors[index].blue << 5)); + if (hw_index != 8 * index) { + RHDRegWrite(LUT, DC_LUT_RW_INDEX, 8 * index); + hw_index = 8 * index; + } + + for (j = 0; j < 8; j++) { + RHDRegWrite(LUT, DC_LUT_30_COLOR, (colors[index].red << 20) | + (colors[index].green << 10) | (colors[index].blue)); + hw_index++; + } } break; } @@ -333,9 +360,9 @@ RHDLUTCopyForRR(struct rhdLUT *LUT) entry = RHDRegRead(LUT, DC_LUT_30_COLOR); - colors[i].red = (entry >> 22) & 0xFF; - colors[i].green = (entry >> 12) & 0xFF; - colors[i].blue = (entry >> 2) & 0xFF; + colors[i].red = (entry >> 20) & 0x3FF; + colors[i].green = (entry >> 10) & 0x3FF; + colors[i].blue = (entry) & 0x3FF; } LUT->Set(LUT, 0x100, indices, colors); break; @@ -347,9 +374,9 @@ RHDLUTCopyForRR(struct rhdLUT *LUT) entry = RHDRegRead(LUT, DC_LUT_30_COLOR); - colors[i / 2].red = (entry >> 24) & 0xFF; - colors[i].green = (entry >> 14) & 0xFF; - colors[i / 2].blue = (entry >> 4) & 0xFF; + colors[i / 2].red = (entry >> 20) & 0x3FF; + colors[i].green = (entry >> 10) & 0x3FF; + colors[i / 2].blue = (entry) & 0x3FF; } LUT->Set(LUT, 0x40, indices, colors); break; @@ -361,9 +388,9 @@ RHDLUTCopyForRR(struct rhdLUT *LUT) entry = RHDRegRead(LUT, DC_LUT_30_COLOR); - colors[i].red = (entry >> 25) & 0xFF; - colors[i].green = (entry >> 15) & 0xFF; - colors[i].blue = (entry >> 5) & 0xFF; + colors[i].red = (entry >> 20) & 0x3FF; + colors[i].green = (entry >> 10) & 0x3FF; + colors[i].blue = (entry) & 0x3FF; } LUT->Set(LUT, 0x20, indices, colors); break; diff --git a/driver/xf86-video-radeonhd/src/rhd_lut.h b/driver/xf86-video-radeonhd/src/rhd_lut.h index 84c8bf796..6684210d7 100644 --- a/driver/xf86-video-radeonhd/src/rhd_lut.h +++ b/driver/xf86-video-radeonhd/src/rhd_lut.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_lvtma.c b/driver/xf86-video-radeonhd/src/rhd_lvtma.c index 77eba62cd..6603b05e2 100644 --- a/driver/xf86-video-radeonhd/src/rhd_lvtma.c +++ b/driver/xf86-video-radeonhd/src/rhd_lvtma.c @@ -1,8 +1,8 @@ /* - * Copyright 2007-2008 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007-2008 Matthias Hopf <mhopf@novell.com> - * Copyright 2007-2008 Egbert Eich <eich@novell.com> - * Copyright 2007-2008 Advanced Micro Devices, Inc. + * Copyright 2007-2009 Luc Verhaegen <libv@exsuse.de> + * Copyright 2007-2009 Matthias Hopf <mhopf@novell.com> + * Copyright 2007-2009 Egbert Eich <eich@novell.com> + * Copyright 2007-2009 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -203,13 +203,12 @@ LVDSDebugBacklight(struct rhdOutput *Output) * */ static void -LVDSSetBacklight(struct rhdOutput *Output, int level) +LVDSSetBacklight(struct rhdOutput *Output) { struct LVDSPrivate *Private = (struct LVDSPrivate *) Output->Private; + int level = Private->BlLevel; RHDPtr rhdPtr = RHDPTRI(Output); - Private->BlLevel = level; - xf86DrvMsg(rhdPtr->scrnIndex, X_INFO, "%s: trying to set BL_MOD_LEVEL to: %d\n", __func__, level); @@ -264,7 +263,18 @@ LVDSPropertyControl(struct rhdOutput *Output, enum rhdPropertyAction Action, case RHD_OUTPUT_BACKLIGHT: if (Private->BlLevel < 0) return FALSE; - LVDSSetBacklight(Output, val->integer); + Private->BlLevel = val->integer; + break; + default: + return FALSE; + } + break; + case rhdPropertyCommit: + switch (Property) { + case RHD_OUTPUT_BACKLIGHT: + if (Private->BlLevel < 0) + return FALSE; + LVDSSetBacklight(Output); break; default: return FALSE; @@ -420,10 +430,7 @@ LVDSEnable(struct rhdOutput *Output) __func__, i, (int) tmp); } if (Private->BlLevel >= 0) { - union rhdPropertyData data; - data.integer = Private->BlLevel; - Output->Property(Output, rhdPropertySet, RHD_OUTPUT_BACKLIGHT, - &data); + LVDSSetBacklight(Output); } } @@ -728,6 +735,7 @@ LVDSDestroy(struct rhdOutput *Output) struct rhdTMDSBPrivate { Bool RunsDualLink; Bool Coherent; + Bool HdmiEnabled; DisplayModePtr Mode; struct rhdHdmi *Hdmi; @@ -761,9 +769,6 @@ TMDSBModeValid(struct rhdOutput *Output, DisplayModePtr Mode) { RHDFUNC(Output); - if (Mode->Flags & V_INTERLACE) - return MODE_NO_INTERLACE; - if (Mode->Clock < 25000) return MODE_CLOCK_LOW; @@ -822,7 +827,6 @@ RS600VoltageControl(struct rhdOutput *Output, DisplayModePtr Mode) static void RS690VoltageControl(struct rhdOutput *Output, DisplayModePtr Mode) { - RHDPtr rhdPtr = RHDPTRI(Output); struct rhdTMDSBPrivate *Private = (struct rhdTMDSBPrivate *) Output->Private; CARD32 rev = (RHDRegRead(Output, CONFIG_CNTL) && RS69_CFG_ATI_REV_ID_MASK) >> RS69_CFG_ATI_REV_ID_SHIFT; @@ -891,6 +895,7 @@ RS690VoltageControl(struct rhdOutput *Output, DisplayModePtr Mode) } else { { #ifdef ATOM_BIOS + RHDPtr rhdPtr = RHDPTRI(Output); AtomBiosArgRec data; if (RHDAtomBiosFunc(rhdPtr->scrnIndex, rhdPtr->atomBIOS, @@ -1042,6 +1047,7 @@ TMDSBPropertyControl(struct rhdOutput *Output, case rhdPropertyCheck: switch (Property) { case RHD_OUTPUT_COHERENT: + case RHD_OUTPUT_HDMI: return TRUE; default: return FALSE; @@ -1051,6 +1057,9 @@ TMDSBPropertyControl(struct rhdOutput *Output, case RHD_OUTPUT_COHERENT: val->Bool = Private->Coherent; return TRUE; + case RHD_OUTPUT_HDMI: + val->Bool = Private->HdmiEnabled; + return TRUE; default: return FALSE; } @@ -1059,6 +1068,18 @@ TMDSBPropertyControl(struct rhdOutput *Output, switch (Property) { case RHD_OUTPUT_COHERENT: Private->Coherent = val->Bool; + break; + case RHD_OUTPUT_HDMI: + Private->HdmiEnabled = val->Bool; + break; + default: + return FALSE; + } + break; + case rhdPropertyCommit: + switch (Property) { + case RHD_OUTPUT_COHERENT: + case RHD_OUTPUT_HDMI: Output->Mode(Output, Private->Mode); Output->Power(Output, RHD_POWER_ON); break; @@ -1177,10 +1198,7 @@ TMDSBPower(struct rhdOutput *Output, int Power) RHDRegMask(Output, LVTMA_TRANSMITTER_CONTROL, 0x00000001, 0x00000001); usleep(2); RHDRegMask(Output, LVTMA_TRANSMITTER_CONTROL, 0, 0x00000002); - if(Output->Connector != NULL && RHDConnectorEnableHDMI(Output->Connector)) - RHDHdmiEnable(Private->Hdmi, TRUE); - else - RHDHdmiEnable(Private->Hdmi, FALSE); + RHDHdmiEnable(Private->Hdmi, Private->HdmiEnabled); return; case RHD_POWER_RESET: RHDRegMask(Output, LVTMA_TRANSMITTER_ENABLE, 0, 0x00003E3E); @@ -1363,7 +1381,6 @@ RHDLVTMAInit(RHDPtr rhdPtr, CARD8 Type) } else { struct rhdTMDSBPrivate *Private = xnfcalloc(sizeof(struct rhdTMDSBPrivate), 1); - int from; Output->Name = "TMDS B"; @@ -1379,21 +1396,7 @@ RHDLVTMAInit(RHDPtr rhdPtr, CARD8 Type) Output->Private = Private; Private->RunsDualLink = FALSE; - from = X_CONFIG; - switch (RhdParseBooleanOption(&rhdPtr->coherent, Output->Name)) { - case RHD_OPTION_NOT_SET: - case RHD_OPTION_DEFAULT: - from = X_DEFAULT; - Private->Coherent = FALSE; - break; - case RHD_OPTION_ON: - Private->Coherent = TRUE; - break; - case RHD_OPTION_OFF: - Private->Coherent = FALSE; - break; - } - xf86DrvMsg(rhdPtr->scrnIndex,from,"Setting %s to %scoherent\n",Output->Name,Private->Coherent ? "" : "in"); + Private->Coherent = FALSE; } return Output; diff --git a/driver/xf86-video-radeonhd/src/rhd_mc.c b/driver/xf86-video-radeonhd/src/rhd_mc.c index d15bd3c8d..540594592 100644 --- a/driver/xf86-video-radeonhd/src/rhd_mc.c +++ b/driver/xf86-video-radeonhd/src/rhd_mc.c @@ -1,8 +1,8 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007 Matthias Hopf <mhopf@novell.com> - * Copyright 2007 Egbert Eich <eich@novell.com> - * Copyright 2007 Advanced Micro Devices, Inc. + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> + * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> + * Copyright 2007, 2008 Egbert Eich <eich@novell.com> + * Copyright 2007, 2008 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,6 +23,31 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +/* + * MC idling: + * + * For SetupFBLocation and Restore, we require a fully idle MC as we might lock up + * otherwise. Both calls now check whether the MC is Idle before attempting + * to set up the MC, and complain loudly when this fails. + * + * Likely suspect registers for when the Idle fails: + * DxVGA_CONTROL & D1VGA_MODE_ENABLE (run RHDVGADisable beforehand) + * DxCRTC_CONTROL & 0x1 (run DxCRTCDisable beforehand) + * (... Add more here...) + * + * + * MC addressing: + * + * On R600 and up the MC can use a larger than 32bit card internal address for + * its framebuffer. This is why the Address used inside the MC code is a + * CARD64. + * + * rhdPtr->FbIntAddress is kept as a CARD32 for the time being. This is still + * valid, as this makes the R500 code simpler, and since we pick FbIntAddress + * from a 32bit register anyway on R600. FbIntAddress will also correctly cast + * to a CARD64 when passed to the likes of the SetupFBLocation callback. + */ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -37,823 +62,716 @@ #include "rhd.h" #include "rhd_regs.h" -#include "r5xx_accel.h" - -Bool RHDMCIdle(RHDPtr rhdPtr, CARD32 count); - -Bool RHDMCIdle(RHDPtr rhdPtr, CARD32 count); +#include "rhd_crtc.h" /* for definition of Crtc->Id */ struct rhdMC { + int scrnIndex; + CARD32 FbLocation; - CARD32 HdpFbBase; + CARD32 HdpFbAddress; CARD32 MiscLatencyTimer; + Bool Stored; - void (*SaveMC)(RHDPtr rhdPtr); - void (*RestoreMC)(RHDPtr rhdPtr); - void (*SetupMC)(RHDPtr rhdPtr); - Bool (*MCIdle)(RHDPtr rhdPtr); - CARD32 (*GetFBLocation)(RHDPtr rhdPtr, CARD32 *size); - void (*TuneMCAccessForDisplay)(RHDPtr rhdPtr, int crtc, - DisplayModePtr Mode, DisplayModePtr ScaledToMode); - Bool RV515Variant; + + void (*Save)(struct rhdMC *MC); + void (*Restore)(struct rhdMC *MC); + Bool (*Idle)(struct rhdMC *MC); + CARD64 (*GetFBLocation)(struct rhdMC *MC, CARD32 *size); + void (*SetupFBLocation)(struct rhdMC *MC, CARD64 Address, CARD32 Size); + void (*TuneAccessForDisplay)(struct rhdMC *MC, int crtc, + DisplayModePtr Mode, DisplayModePtr ScaledToMode); }; /* - * Save MC_VM state. + * Some common FB location calculations. */ -static void -rs600SaveMC(RHDPtr rhdPtr) +/* + * Applicable for all R5xx and RS600, RS690, RS740 + */ +static CARD64 +R5xxMCGetFBLocation(CARD32 Value, CARD32 *Size) { - struct rhdMC *MC = rhdPtr->MC; + *Size = (Value & 0xFFFF0000) - ((Value & 0xFFFF) << 16); + return (Value & 0xFFFF) << 16; +} - RHDFUNC(rhdPtr); +#define R5XX_FB_LOCATION(address, size) \ + ((((address) + (size)) & 0xFFFF0000) | (((address) >> 16) & 0xFFFF)) +#define R5XX_HDP_LOCATION(address) \ + (((address) >> 16) & 0xFFFF) - MC->FbLocation = RHDReadMC(rhdPtr, RS60_NB_FB_LOCATION); - MC->HdpFbBase = RHDRegRead(rhdPtr, HDP_FB_LOCATION); +/* + * Applicable for all R6xx and R7xx, and RS780/RS790 + */ +static CARD64 +R6xxMCGetFBLocation(CARD32 Value, CARD32 *Size) +{ + *Size = (((Value & 0xFFFF0000) - ((Value & 0xFFFF) << 16))) << 8; + return (Value & 0xFFFF) << 24; } +#define R6XX_FB_LOCATION(address, size) \ + (((((address) + (size)) >> 8) & 0xFFFF0000) | (((address) >> 24) & 0xFFFF)) +#define R6XX_HDP_LOCATION(address) \ + ((((address) >> 8) & 0x00FF0000)) + /* * */ static void -rs690SaveMC(RHDPtr rhdPtr) +RV515MCSave(struct rhdMC *MC) { - struct rhdMC *MC = rhdPtr->MC; - - RHDFUNC(rhdPtr); - - MC->FbLocation = RHDReadMC(rhdPtr, RS69_MCCFG_FB_LOCATION); - MC->HdpFbBase = RHDRegRead(rhdPtr, HDP_FB_LOCATION); - MC->MiscLatencyTimer = RHDReadMC(rhdPtr, RS69_MC_INIT_MISC_LAT_TIMER); + MC->FbLocation = RHDReadMC(MC, MC_IND_ALL | RV515_MC_FB_LOCATION); + MC->MiscLatencyTimer = RHDReadMC(MC, MC_IND_ALL | RV515_MC_MISC_LAT_TIMER); + MC->HdpFbAddress = RHDRegRead(MC, HDP_FB_LOCATION); } /* * */ static void -r6xxSaveMC(RHDPtr rhdPtr) +RV515MCRestore(struct rhdMC *MC) { - struct rhdMC *MC = rhdPtr->MC; - - RHDFUNC(rhdPtr); - - MC->FbLocation = RHDRegRead(rhdPtr, R6XX_MC_VM_FB_LOCATION); - MC->HdpFbBase = RHDRegRead(rhdPtr, R6XX_HDP_NONSURFACE_BASE); + RHDWriteMC(MC, MC_IND_ALL | RV515_MC_FB_LOCATION, MC->FbLocation); + RHDWriteMC(MC, MC_IND_ALL | RV515_MC_MISC_LAT_TIMER, MC->MiscLatencyTimer); + RHDRegWrite(MC, HDP_FB_LOCATION, MC->HdpFbAddress); } /* * */ -#ifdef NOTYET -static void -rs780SaveMC(RHDPtr rhdPtr) +static Bool +RV515MCWaitIdle(struct rhdMC *MC) { - struct rhdMC *MC = rhdPtr->MC; - - RHDFUNC(rhdPtr); + if (RHDReadMC(MC, MC_IND_ALL | RV515_MC_STATUS) & RV515_MC_IDLE) + return TRUE; + return FALSE; +} - MC->FbLocation = RHDReadMC(rhdPtr, RS78_MC_FB_LOCATION); - /* RS780 uses the same register as R6xx */ - MC->HdpFbBase = RHDRegRead(rhdPtr, R6XX_HDP_NONSURFACE_BASE); +/* + * + */ +static CARD64 +RV515MCGetFBLocation(struct rhdMC *MC, CARD32 *Size) +{ + return R5xxMCGetFBLocation(RHDReadMC(MC, RV515_MC_FB_LOCATION | MC_IND_ALL), Size); } -#endif /* * */ static void -r7xxSaveMC(RHDPtr rhdPtr) +RV515MCSetupFBLocation(struct rhdMC *MC, CARD64 Address, CARD32 Size) { - struct rhdMC *MC = rhdPtr->MC; - - RHDFUNC(rhdPtr); - - MC->FbLocation = RHDRegRead(rhdPtr, R7XX_MC_VM_FB_LOCATION); - MC->HdpFbBase = RHDRegRead(rhdPtr, R6XX_HDP_NONSURFACE_BASE); + RHDWriteMC(MC, RV515_MC_FB_LOCATION | MC_IND_ALL, + R5XX_FB_LOCATION(Address, Size)); + RHDRegWrite(MC, HDP_FB_LOCATION, R5XX_HDP_LOCATION(Address)); } /* * */ static void -r5xxRestoreMC(RHDPtr rhdPtr) +RV515MCTuneMCAccessForDisplay(struct rhdMC *MC, int Crtc, + DisplayModePtr Mode, DisplayModePtr ScaledToMode) { - struct rhdMC *MC = rhdPtr->MC; + CARD32 value, setting = 0x1; - RHDFUNC(rhdPtr); + value = RHDReadMC(MC, RV515_MC_MISC_LAT_TIMER); + + if (Crtc == RHD_CRTC_1) { + value &= ~(0x0F << MC_DISP0R_INIT_LAT_SHIFT); + value |= setting << MC_DISP0R_INIT_LAT_SHIFT; + } else { /* RHD_CRTC_2 */ + value &= ~(0x0F << MC_DISP1R_INIT_LAT_SHIFT); + value |= setting << MC_DISP1R_INIT_LAT_SHIFT; + } - if (MC->RV515Variant) { - RHDWriteMC(rhdPtr, MC_IND_ALL | RV515_MC_FB_LOCATION, - MC->FbLocation); - RHDWriteMC(rhdPtr, MC_IND_ALL | RV515_MC_MISC_LAT_TIMER, - MC->MiscLatencyTimer); - } else - RHDWriteMC(rhdPtr, MC_IND_ALL | R5XX_MC_FB_LOCATION, - MC->FbLocation); - RHDRegWrite(rhdPtr, HDP_FB_LOCATION, MC->HdpFbBase); + RHDWriteMC(MC, RV515_MC_MISC_LAT_TIMER, value); } /* * */ static void -rs600RestoreMC(RHDPtr rhdPtr) +R500MCSave(struct rhdMC *MC) { - struct rhdMC *MC = rhdPtr->MC; - - RHDFUNC(rhdPtr); - - RHDWriteMC(rhdPtr, RS60_NB_FB_LOCATION, MC->FbLocation); - RHDRegWrite(rhdPtr, HDP_FB_LOCATION, MC->HdpFbBase); + MC->FbLocation = RHDReadMC(MC, MC_IND_ALL | R5XX_MC_FB_LOCATION); + MC->HdpFbAddress = RHDRegRead(MC, HDP_FB_LOCATION); } /* * */ static void -rs690RestoreMC(RHDPtr rhdPtr) +R500MCRestore(struct rhdMC *MC) { - struct rhdMC *MC = rhdPtr->MC; + RHDWriteMC(MC, MC_IND_ALL | R5XX_MC_FB_LOCATION, MC->FbLocation); + RHDRegWrite(MC, HDP_FB_LOCATION, MC->HdpFbAddress); +} - RHDFUNC(rhdPtr); +/* + * + */ +static Bool +R500MCWaitIdle(struct rhdMC *MC) +{ + if (RHDReadMC(MC, MC_IND_ALL | R5XX_MC_STATUS) & R5XX_MC_IDLE) + return TRUE; + return FALSE; +} - RHDWriteMC(rhdPtr, RS69_MCCFG_FB_LOCATION, MC->FbLocation); - RHDRegWrite(rhdPtr, HDP_FB_LOCATION, MC->HdpFbBase); - RHDWriteMC(rhdPtr, RS69_MC_INIT_MISC_LAT_TIMER, MC->MiscLatencyTimer); +/* + * + */ +static CARD64 +R500MCGetFBLocation(struct rhdMC *MC, CARD32 *Size) +{ + return R5xxMCGetFBLocation(RHDReadMC(MC, R5XX_MC_FB_LOCATION | MC_IND_ALL), Size); } /* * */ static void -r6xxRestoreMC(RHDPtr rhdPtr) +R500MCSetupFBLocation(struct rhdMC *MC, CARD64 Address, CARD32 Size) { - struct rhdMC *MC = rhdPtr->MC; - - RHDFUNC(rhdPtr); - - RHDRegWrite(rhdPtr, R6XX_MC_VM_FB_LOCATION, MC->FbLocation); - RHDRegWrite(rhdPtr, R6XX_HDP_NONSURFACE_BASE, MC->HdpFbBase); + RHDWriteMC(MC, R5XX_MC_FB_LOCATION | MC_IND_ALL, + R5XX_FB_LOCATION(Address, Size)); + RHDRegWrite(MC, HDP_FB_LOCATION, R5XX_HDP_LOCATION(Address)); } /* * */ -#ifdef NOTYET static void -rs780RestoreMC(RHDPtr rhdPtr) +RS600MCSave(struct rhdMC *MC) { - struct rhdMC *MC = rhdPtr->MC; - - RHDFUNC(rhdPtr); - - RHDWriteMC(rhdPtr, RS78_MC_FB_LOCATION, MC->FbLocation); - /* RS780 uses the same register as R6xx */ - RHDRegWrite(rhdPtr, R6XX_HDP_NONSURFACE_BASE, MC->HdpFbBase); + MC->FbLocation = RHDReadMC(MC, RS60_NB_FB_LOCATION); + MC->HdpFbAddress = RHDRegRead(MC, HDP_FB_LOCATION); } -#endif /* * */ static void -r7xxRestoreMC(RHDPtr rhdPtr) +RS600MCRestore(struct rhdMC *MC) { - struct rhdMC *MC = rhdPtr->MC; - - RHDFUNC(rhdPtr); - - RHDRegWrite(rhdPtr, R7XX_MC_VM_FB_LOCATION, MC->FbLocation); - RHDRegWrite(rhdPtr, R6XX_HDP_NONSURFACE_BASE, MC->HdpFbBase); + RHDWriteMC(MC, RS60_NB_FB_LOCATION, MC->FbLocation); + RHDRegWrite(MC, HDP_FB_LOCATION, MC->HdpFbAddress); } /* - * Setup the MC + * */ +static Bool +RS600MCWaitIdle(struct rhdMC *MC) +{ + if (RHDReadMC(MC, RS60_MC_SYSTEM_STATUS) & RS6X_MC_SEQUENCER_IDLE) + return TRUE; + return FALSE; +} /* * */ -static void -r5xxSetupMC(RHDPtr rhdPtr) +static CARD64 +RS600MCGetFBLocation(struct rhdMC *MC, CARD32 *Size) { - struct rhdMC *MC = rhdPtr->MC; - CARD32 fb_location, fb_location_tmp; - CARD16 fb_size; - unsigned int reg; - - RHDFUNC(rhdPtr); - - - if (MC->RV515Variant) - reg = RV515_MC_FB_LOCATION | MC_IND_ALL; - else - reg = R5XX_MC_FB_LOCATION | MC_IND_ALL; - - fb_location = RHDReadMC(rhdPtr, reg); - fb_size = (fb_location >> 16) - (fb_location & 0xFFFF); - fb_location_tmp = rhdPtr->FbIntAddress >> 16; - fb_location_tmp |= (fb_location_tmp + fb_size) << 16; - - RHDDebug(rhdPtr->scrnIndex, "%s: fb_location: 0x%08X " - "[fb_size: 0x%04X] -> fb_location: 0x%08X\n", - __func__, (unsigned int)fb_location, - fb_size,(unsigned int)fb_location_tmp); - RHDWriteMC(rhdPtr, reg, fb_location_tmp); - RHDRegWrite(rhdPtr, HDP_FB_LOCATION, fb_location_tmp & 0xFFFF); + return R5xxMCGetFBLocation(RHDReadMC(MC, RS60_NB_FB_LOCATION), Size); } /* * */ static void -rs600SetupMC(RHDPtr rhdPtr) +RS600MCSetupFBLocation(struct rhdMC *MC, CARD64 Address, CARD32 Size) { - CARD32 fb_location, fb_location_tmp; - CARD16 fb_size; - - RHDFUNC(rhdPtr); - - fb_location = RHDReadMC(rhdPtr, RS60_NB_FB_LOCATION); - fb_size = (fb_location >> 16) - (fb_location & 0xFFFF); - fb_location_tmp = rhdPtr->FbIntAddress >> 16; - fb_location_tmp |= (fb_location_tmp + fb_size) << 16; - - RHDDebug(rhdPtr->scrnIndex, "%s: fb_location: 0x%08X " - "[fb_size: 0x%04X] -> fb_location: 0x%08X\n", - __func__, (unsigned int)fb_location, - fb_size,(unsigned int)fb_location_tmp); - RHDWriteMC(rhdPtr, RS60_NB_FB_LOCATION, fb_location_tmp); - RHDRegWrite(rhdPtr, HDP_FB_LOCATION, fb_location_tmp & 0xFFFF); /* same ;) */ + RHDWriteMC(MC, RS60_NB_FB_LOCATION, R5XX_FB_LOCATION(Address, Size)); + RHDRegWrite(MC, HDP_FB_LOCATION, R5XX_HDP_LOCATION(Address)); } /* * */ static void -rs690SetupMC(RHDPtr rhdPtr) +RS690MCSave(struct rhdMC *MC) { - CARD32 fb_location, fb_location_tmp; - CARD16 fb_size; - - RHDFUNC(rhdPtr); - - fb_location = RHDReadMC(rhdPtr, RS69_MCCFG_FB_LOCATION); - fb_size = (fb_location >> 16) - (fb_location & 0xFFFF); - fb_location_tmp = rhdPtr->FbIntAddress >> 16; - fb_location_tmp |= (fb_location_tmp + fb_size) << 16; - - RHDDebug(rhdPtr->scrnIndex, "%s: fb_location: 0x%08X " - "[fb_size: 0x%04X] -> fb_location: 0x%08X\n", - __func__, (unsigned int)fb_location, - fb_size,(unsigned int)fb_location_tmp); - RHDWriteMC(rhdPtr, RS69_MCCFG_FB_LOCATION, fb_location_tmp); - RHDRegWrite(rhdPtr, HDP_FB_LOCATION, fb_location_tmp & 0xFFFF); + MC->FbLocation = RHDReadMC(MC, RS69_MCCFG_FB_LOCATION); + MC->HdpFbAddress = RHDRegRead(MC, HDP_FB_LOCATION); + MC->MiscLatencyTimer = RHDReadMC(MC, RS69_MC_INIT_MISC_LAT_TIMER); } /* * */ static void -r6xxSetupMC(RHDPtr rhdPtr) +RS690MCRestore(struct rhdMC *MC) { - CARD32 fb_location, fb_location_tmp, hdp_fbbase_tmp; - CARD16 fb_size; - - RHDFUNC(rhdPtr); - - fb_location = RHDRegRead(rhdPtr, R6XX_MC_VM_FB_LOCATION); - fb_size = (fb_location >> 16) - (fb_location & 0xFFFF); - fb_location_tmp = rhdPtr->FbIntAddress >> 24; - fb_location_tmp |= (fb_location_tmp + fb_size) << 16; - hdp_fbbase_tmp = (rhdPtr->FbIntAddress >> 8) & 0xff0000; + RHDWriteMC(MC, RS69_MCCFG_FB_LOCATION, MC->FbLocation); + RHDRegWrite(MC, HDP_FB_LOCATION, MC->HdpFbAddress); + RHDWriteMC(MC, RS69_MC_INIT_MISC_LAT_TIMER, MC->MiscLatencyTimer); +} - RHDDebug(rhdPtr->scrnIndex, "%s: fb_location: 0x%08X " - "fb_offset: 0x%08X [fb_size: 0x%04X] -> fb_location: 0x%08X " - "fb_offset: 0x%08X\n", - __func__, (unsigned int)fb_location, - RHDRegRead(rhdPtr,R6XX_HDP_NONSURFACE_BASE), fb_size, - (unsigned int)fb_location_tmp, (unsigned int)hdp_fbbase_tmp); +/* + * + */ +static Bool +RS690MCWaitIdle(struct rhdMC *MC) +{ + if (RHDReadMC(MC, RS69_MC_SYSTEM_STATUS) & RS6X_MC_SEQUENCER_IDLE) + return TRUE; + return FALSE; +} - RHDRegWrite(rhdPtr, R6XX_MC_VM_FB_LOCATION, fb_location_tmp); - RHDRegWrite(rhdPtr, R6XX_HDP_NONSURFACE_BASE, hdp_fbbase_tmp); +/* + * + */ +static CARD64 +RS690MCGetFBLocation(struct rhdMC *MC, CARD32 *Size) +{ + return R5xxMCGetFBLocation(RHDReadMC(MC, RS69_MCCFG_FB_LOCATION), Size); } /* * */ -#ifdef NOTYET static void -rs780SetupMC(RHDPtr rhdPtr) +RS690MCSetupFBLocation(struct rhdMC *MC, CARD64 Address, CARD32 Size) { - CARD32 fb_location, fb_location_tmp, hdp_fbbase_tmp; - CARD16 fb_size; - - RHDFUNC(rhdPtr); - - fb_location = RHDReadMC(rhdPtr, RS78_MC_FB_LOCATION); - fb_size = (fb_location >> 16) - (fb_location & 0xFFFF); - fb_location_tmp = rhdPtr->FbIntAddress >> 16; - fb_location_tmp |= (fb_location_tmp + fb_size) << 16; - hdp_fbbase_tmp = (rhdPtr->FbIntAddress >> 8) & 0xff0000; - - RHDDebug(rhdPtr->scrnIndex, "%s: fb_location: 0x%08X " - "[fb_size: 0x%04X] -> fb_location: 0x%08X\n", - __func__, (unsigned int)fb_location, - fb_size,(unsigned int)fb_location_tmp); - RHDWriteMC(rhdPtr, RS78_MC_FB_LOCATION, fb_location_tmp); - /* RS780 uses the same register as R6xx */ - RHDRegWrite(rhdPtr, R6XX_HDP_NONSURFACE_BASE, hdp_fbbase_tmp); + RHDWriteMC(MC, RS69_MCCFG_FB_LOCATION, R5XX_FB_LOCATION(Address, Size)); + RHDRegWrite(MC, HDP_FB_LOCATION, R5XX_HDP_LOCATION(Address)); } -#endif /* * */ static void -r7xxSetupMC(RHDPtr rhdPtr) +RS690MCTuneMCAccessForDisplay(struct rhdMC *MC, int Crtc, + DisplayModePtr Mode, DisplayModePtr ScaledToMode) { - CARD32 fb_location, fb_location_tmp, hdp_fbbase_tmp; - CARD16 fb_size; - - RHDFUNC(rhdPtr); + CARD32 value, setting = 0x1; - fb_location = RHDRegRead(rhdPtr, R7XX_MC_VM_FB_LOCATION); - fb_size = (fb_location >> 16) - (fb_location & 0xFFFF); - fb_location_tmp = rhdPtr->FbIntAddress >> 24; - fb_location_tmp |= (fb_location_tmp + fb_size) << 16; - hdp_fbbase_tmp = (rhdPtr->FbIntAddress >> 8) & 0xff0000; + value = RHDReadMC(MC, RS69_MC_INIT_MISC_LAT_TIMER); - RHDDebug(rhdPtr->scrnIndex, "%s: fb_location: 0x%08X " - "fb_offset: 0x%08X [fb_size: 0x%04X] -> fb_location: 0x%08X " - "fb_offset: 0x%08X\n", - __func__, (unsigned int)fb_location, - RHDRegRead(rhdPtr,R6XX_HDP_NONSURFACE_BASE), fb_size, - (unsigned int)fb_location_tmp, (unsigned int)hdp_fbbase_tmp); + if (Crtc == RHD_CRTC_1) { + value &= ~(0x0F << MC_DISP0R_INIT_LAT_SHIFT); + value |= setting << MC_DISP0R_INIT_LAT_SHIFT; + } else { /* RHD_CRTC_2 */ + value &= ~(0x0F << MC_DISP1R_INIT_LAT_SHIFT); + value |= setting << MC_DISP1R_INIT_LAT_SHIFT; + } - RHDRegWrite(rhdPtr, R7XX_MC_VM_FB_LOCATION, fb_location_tmp); - RHDRegWrite(rhdPtr, R6XX_HDP_NONSURFACE_BASE, hdp_fbbase_tmp); + RHDWriteMC(MC, RS69_MC_INIT_MISC_LAT_TIMER, value); } /* * */ -void -RHDMCSetup(RHDPtr rhdPtr) +static void +R600MCSave(struct rhdMC *MC) { - struct rhdMC *MC = rhdPtr->MC; - RHDFUNC(rhdPtr); - - if (!MC) - return; - /* - * make sure the hw is in a state such that we can update - * the MC - ie no subsystem is currently accessing memory. - */ - ASSERT((RHDRegRead(rhdPtr, D1VGA_CONTROL) & D1VGA_MODE_ENABLE) != D1VGA_MODE_ENABLE); - ASSERT((RHDRegRead(rhdPtr, D2VGA_CONTROL) & D2VGA_MODE_ENABLE) != D2VGA_MODE_ENABLE); - ASSERT((RHDRegRead(rhdPtr, D1CRTC_CONTROL) & 0x1) != 0x1); - ASSERT((RHDRegRead(rhdPtr, D2CRTC_CONTROL) & 0x1) != 0x1); - ASSERT(RHDMCIdle(rhdPtr, 1)); - - MC->SetupMC(rhdPtr); + MC->FbLocation = RHDRegRead(MC, R6XX_MC_VM_FB_LOCATION); + MC->HdpFbAddress = RHDRegRead(MC, R6XX_HDP_NONSURFACE_BASE); } /* - * Get FB location and size. + * */ -static CARD32 -r5xxGetFBLocation(RHDPtr rhdPtr, CARD32 *size) +static void +R600MCRestore(struct rhdMC *MC) { - struct rhdMC *MC = rhdPtr->MC; - CARD32 val; - CARD32 reg; - - if (MC->RV515Variant) - reg = RV515_MC_FB_LOCATION | MC_IND_ALL; - else - reg = R5XX_MC_FB_LOCATION | MC_IND_ALL; - - val = RHDReadMC(rhdPtr, reg); - - if (size) *size = ((val >> 16) - (val & 0xFFFF)) << 16; - - return (val & 0xFFFF) << 16; + RHDRegWrite(MC, R6XX_MC_VM_FB_LOCATION, MC->FbLocation); + RHDRegWrite(MC, R6XX_HDP_NONSURFACE_BASE, MC->HdpFbAddress); } /* * */ -static CARD32 -rs600GetFBLocation(RHDPtr rhdPtr, CARD32 *size) +static Bool +R600MCWaitIdle(struct rhdMC *MC) { - CARD32 val = RHDReadMC(rhdPtr, RS60_NB_FB_LOCATION); - - if (size) *size = ((val >> 16) - (val & 0xFFFF)) << 16; - - return (val & 0xFFFF) << 16; + if (!(RHDRegRead(MC, SRBM_STATUS) & 0x3f00)) + return TRUE; + return FALSE; } /* * */ -static CARD32 -rs690GetFBLocation(RHDPtr rhdPtr, CARD32 *size) +static CARD64 +R600MCGetFBLocation(struct rhdMC *MC, CARD32 *Size) { - CARD32 val = RHDReadMC(rhdPtr, RS69_MCCFG_FB_LOCATION); - - if (size) *size = ((val >> 16) - (val & 0xFFFF)) << 16; - - return (val & 0xFFFF) << 16; + return R6xxMCGetFBLocation(RHDRegRead(MC, R6XX_MC_VM_FB_LOCATION), Size); } /* * */ -static CARD32 -r6xxGetFBLocation(RHDPtr rhdPtr, CARD32 *size) +static void +R600MCSetupFBLocation(struct rhdMC *MC, CARD64 Address, CARD32 Size) { - CARD32 val = RHDRegRead(rhdPtr, R6XX_MC_VM_FB_LOCATION); - - if (size) *size = ((val >> 16) - (val & 0xFFFF)) << 24; - - return (val & 0xFFFF) << 24; + RHDRegWrite(MC, R6XX_MC_VM_FB_LOCATION, R6XX_FB_LOCATION(Address, Size)); + RHDRegWrite(MC, R6XX_HDP_NONSURFACE_BASE, R6XX_HDP_LOCATION(Address)); } /* * */ #ifdef NOTYET -static CARD32 -rs780GetFBLocation(RHDPtr rhdPtr, CARD32 *size) -{ - CARD32 val = RHDReadMC(rhdPtr, RS78_MC_FB_LOCATION); - if (size) *size = ((val >> 16) - (val & 0xFFFF)) << 16; - - return (val & 0xFFFF) << 16; -} -#endif /* * */ -static CARD32 -r7xxGetFBLocation(RHDPtr rhdPtr, CARD32 *size) +static void +RS780MCSave(struct rhdMC *MC) { - CARD32 val = RHDRegRead(rhdPtr, R7XX_MC_VM_FB_LOCATION); - - if (size) *size = ((val >> 16) - (val & 0xFFFF)) << 24; - - return (val & 0xFFFF) << 24; + MC->FbLocation = RHDReadMC(MC, RS78_MC_FB_LOCATION); + MC->HdpFbAddress = RHDRegRead(MC, R6XX_HDP_NONSURFACE_BASE); } /* * */ -CARD32 -RHDGetFBLocation(RHDPtr rhdPtr, CARD32 *size) +static void +RS780MCRestore(struct rhdMC *MC) { - struct rhdMC *MC = rhdPtr->MC; - RHDFUNC(rhdPtr); - - if (!MC) { - if (size) *size = 0; - return 0; - } - - return MC->GetFBLocation(rhdPtr, size); + RHDWriteMC(MC, RS78_MC_FB_LOCATION, MC->FbLocation); + RHDRegWrite(MC, R6XX_HDP_NONSURFACE_BASE, MC->HdpFbAddress); } /* * */ static Bool -rv515MCIdle(RHDPtr rhdPtr) +RS780MCWaitIdle(struct rhdMC *MC) { - RHDFUNC(rhdPtr); - - if (RHDReadMC(rhdPtr, MC_IND_ALL | RV515_MC_STATUS) & RV515_MC_IDLE) + if (RHDReadMC(MC, RS78_MC_SYSTEM_STATUS) & RS78_MC_SEQUENCER_IDLE) return TRUE; return FALSE; } - /* * */ -static Bool -r5xxMCIdle(RHDPtr rhdPtr) +static CARD64 +RS780MCGetFBLocation(struct rhdMC *MC, CARD32 *Size) { - RHDFUNC(rhdPtr); - - if (RHDReadMC(rhdPtr, MC_IND_ALL | R5XX_MC_STATUS) & R5XX_MC_IDLE) - return TRUE; - return FALSE; + /* is this correct? */ + return R5xxMCGetFBLocation(RHDReadMC(MC, RS78_MC_FB_LOCATION), Size); } /* * */ -static Bool -rs600MCIdle(RHDPtr rhdPtr) +static void +RS780MCSetupFBLocation(struct rhdMC *MC, CARD64 Address, CARD32 Size) { - RHDFUNC(rhdPtr); - - if (RHDReadMC(rhdPtr, RS60_MC_SYSTEM_STATUS) & RS6X_MC_SEQUENCER_IDLE) - return TRUE; - return FALSE; + /* is this correct? */ + RHDWriteMC(MC, RS78_MC_FB_LOCATION, R5XX_FB_LOCATION(Address, Size)); + RHDRegWrite(MC, R6XX_HDP_NONSURFACE_BASE, R6XX_HDP_LOCATION(Address)); } +#endif /* NOTYET */ /* * */ -static Bool -rs690MCIdle(RHDPtr rhdPtr) +static void +R700MCSave(struct rhdMC *MC) { - RHDFUNC(rhdPtr); - - if (RHDReadMC(rhdPtr, RS69_MC_SYSTEM_STATUS) & RS6X_MC_SEQUENCER_IDLE) - return TRUE; - return FALSE; + MC->FbLocation = RHDRegRead(MC, R7XX_MC_VM_FB_LOCATION); + MC->HdpFbAddress = RHDRegRead(MC, R6XX_HDP_NONSURFACE_BASE); } /* * */ -static Bool -r6xxMCIdle(RHDPtr rhdPtr) +static void +R700MCRestore(struct rhdMC *MC) { - RHDFUNC(rhdPtr); + RHDFUNC(MC); - if (!(RHDRegRead(rhdPtr, SRBM_STATUS) & 0x3f00)) - return TRUE; - return FALSE; + RHDRegWrite(MC, R7XX_MC_VM_FB_LOCATION, MC->FbLocation); + RHDRegWrite(MC, R6XX_HDP_NONSURFACE_BASE, MC->HdpFbAddress); } /* + * Idle is the R600 one... + */ + +/* * */ -#ifdef NOTYET -static Bool -rs780MCIdle(RHDPtr rhdPtr) +static CARD64 +R700MCGetFBLocation(struct rhdMC *MC, CARD32 *Size) { - RHDFUNC(rhdPtr); - - if (RHDReadMC(rhdPtr, RS78_MC_SYSTEM_STATUS) & RS78_MC_SEQUENCER_IDLE) - return TRUE; - return FALSE; + return R6xxMCGetFBLocation(RHDRegRead(MC, R7XX_MC_VM_FB_LOCATION), Size); } -#endif /* * */ -Bool -RHDMCIdle(RHDPtr rhdPtr, CARD32 count) +static void +R700MCSetupFBLocation(struct rhdMC *MC, CARD64 Address, CARD32 Size) { - struct rhdMC *MC = rhdPtr->MC; - RHDFUNC(rhdPtr); - - if (!MC) - return TRUE; - - do { - if (MC->MCIdle(rhdPtr)) - return TRUE; - usleep(10); - } while (count--); - - RHDDebug(rhdPtr->scrnIndex, "%s: MC not idle\n",__func__); - - return FALSE; + RHDRegWrite(MC, R7XX_MC_VM_FB_LOCATION, R6XX_FB_LOCATION(Address, Size)); + RHDRegWrite(MC, R6XX_HDP_NONSURFACE_BASE, R6XX_HDP_LOCATION(Address)); } + /* * */ void -RHDSaveMC(RHDPtr rhdPtr) +RHDMCInit(RHDPtr rhdPtr) { - struct rhdMC *MC = rhdPtr->MC; + struct rhdMC *MC; + RHDFUNC(rhdPtr); - if (!MC) + /* These devices have an internal address reference, which some other + * address registers in there also use. This can be different from the + * address in the BAR. + * + * We read out the address here from some known location. This address + * is as good a guess as any, we just need to pick one, but then make + * sure that it is made consistent in MCSetupFBLocation and the various MC + * accessing subsystems. + */ + + RHDDebug(rhdPtr->scrnIndex, "MC FB Address: 0x%08X.\n", + rhdPtr->FbIntAddress); + + MC = xnfcalloc(1, sizeof(struct rhdMC)); + MC->scrnIndex = rhdPtr->scrnIndex; + + if (rhdPtr->ChipSet < RHD_RS600) { + switch(rhdPtr->ChipSet) { + case RHD_RV515: + case RHD_RV505: + case RHD_RV516: + case RHD_RV550: + case RHD_M52: + case RHD_M54: + case RHD_M62: + case RHD_M64: + case RHD_M71: + MC->Save = RV515MCSave; + MC->Restore = RV515MCRestore; + MC->SetupFBLocation = RV515MCSetupFBLocation; + MC->GetFBLocation = RV515MCGetFBLocation; + MC->Idle = RV515MCWaitIdle; + MC->TuneAccessForDisplay = RV515MCTuneMCAccessForDisplay; + break; + default: + MC->Save = R500MCSave; + MC->Restore = R500MCRestore; + MC->SetupFBLocation = R500MCSetupFBLocation; + MC->GetFBLocation = R500MCGetFBLocation; + MC->Idle = R500MCWaitIdle; + break; + } + } else if (rhdPtr->ChipSet == RHD_RS600) { + MC->Save = RS600MCSave; + MC->Restore = RS600MCRestore; + MC->SetupFBLocation = RS600MCSetupFBLocation; + MC->Idle = RS600MCWaitIdle; + MC->GetFBLocation = RS600MCGetFBLocation; + } else if (rhdPtr->ChipSet < RHD_R600) { + MC->Save = RS690MCSave; + MC->Restore = RS690MCRestore; + MC->SetupFBLocation = RS690MCSetupFBLocation; + MC->Idle = RS690MCWaitIdle; + MC->GetFBLocation = RS690MCGetFBLocation; + MC->TuneAccessForDisplay = RS690MCTuneMCAccessForDisplay; + } else if (rhdPtr->ChipSet <= RHD_RS880) { + MC->Save = R600MCSave; + MC->Restore = R600MCRestore; + MC->SetupFBLocation = R600MCSetupFBLocation; + MC->Idle = R600MCWaitIdle; + MC->GetFBLocation = R600MCGetFBLocation; + } +#ifdef NOTYET + else if (rhdPtr->ChipSet == RHD_RS880) { + MC->Save = RS780MCSave; + MC->Restore = RS780MCRestore; + MC->SetupFBLocation = RS780MCSetupFBLocation; + MC->Idle = RS780MCWaitIdle; + MC->GetFBLocation = RS780MCGetFBLocation; + } +#endif /* NOTYET */ + else if (rhdPtr->ChipSet >= RHD_RV770) { + MC->Save = R700MCSave; + MC->Restore = R700MCRestore; + MC->SetupFBLocation = R700MCSetupFBLocation; + MC->Idle = R600MCWaitIdle; + MC->GetFBLocation = R700MCGetFBLocation; + } else { + xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, "I don't know anything about MC on this chipset\n"); + xfree(MC); return; + } + if (rhdPtr->ChipSet < RHD_R600) + rhdPtr->FbIntAddress = RHDRegRead(rhdPtr, HDP_FB_LOCATION) << 16; + else + rhdPtr->FbIntAddress = RHDRegRead(rhdPtr, R6XX_CONFIG_FB_BASE); + MC->GetFBLocation(MC, &rhdPtr->FbIntSize); - MC->SaveMC(rhdPtr); + rhdPtr->MC = MC; - MC->Stored = TRUE; } /* - * Restore MC VM state. + * Free structure. */ void -RHDRestoreMC(RHDPtr rhdPtr) +RHDMCDestroy(RHDPtr rhdPtr) { - struct rhdMC *MC = rhdPtr->MC; RHDFUNC(rhdPtr); - if (!MC) - return; - - if (!MC->Stored) { - xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, - "%s: trying to restore uninitialized values.\n",__func__); + if (!rhdPtr->MC) return; - } - /* - * make sure the hw is in a state such that we can update - * the MC - ie no subsystem is currently accessing memory. - */ - ASSERT((RHDRegRead(rhdPtr, D1VGA_CONTROL) & D1VGA_MODE_ENABLE) != D1VGA_MODE_ENABLE); - ASSERT((RHDRegRead(rhdPtr, D2VGA_CONTROL) & D2VGA_MODE_ENABLE) != D2VGA_MODE_ENABLE); - ASSERT((RHDRegRead(rhdPtr, D1CRTC_CONTROL) & 0x1) != 0x1); - ASSERT((RHDRegRead(rhdPtr, D2CRTC_CONTROL) & 0x1) != 0x1); - ASSERT(RHDMCIdle(rhdPtr, 1)); - MC->RestoreMC(rhdPtr); + xfree(rhdPtr->MC); + rhdPtr->MC = NULL; } /* * */ -static void -r5xxSaveMC(RHDPtr rhdPtr) +void +RHDMCSave(RHDPtr rhdPtr) { struct rhdMC *MC = rhdPtr->MC; + ASSERT(MC); + RHDFUNC(rhdPtr); - if (MC->RV515Variant) { - MC->FbLocation = RHDReadMC(rhdPtr, MC_IND_ALL | RV515_MC_FB_LOCATION); - MC->MiscLatencyTimer = RHDReadMC(rhdPtr, MC_IND_ALL | RV515_MC_MISC_LAT_TIMER); - } else - MC->FbLocation = RHDReadMC(rhdPtr, MC_IND_ALL | R5XX_MC_FB_LOCATION); - MC->HdpFbBase = RHDRegRead(rhdPtr, HDP_FB_LOCATION); + MC->Save(MC); + + MC->Stored = TRUE; } /* - * + * Make sure that nothing is accessing memory anymore before calling this. */ -static void -rv515TuneMCAccessForDisplay(RHDPtr rhdPtr, int crtc, - DisplayModePtr Mode, DisplayModePtr ScaledToMode) +void +RHDMCRestore(RHDPtr rhdPtr) { - CARD32 value, setting = 0x1; + struct rhdMC *MC = rhdPtr->MC; + + ASSERT(MC); + RHD_UNSETDEBUGFLAG(rhdPtr, MC_SETUP); RHDFUNC(rhdPtr); - value = RHDReadMC(rhdPtr, RV515_MC_MISC_LAT_TIMER); + if (!MC->Stored) { + xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, + "%s: trying to restore uninitialized values.\n",__func__); + return; + } - value |= (setting << (crtc ? MC_DISP1R_INIT_LAT_SHIFT : MC_DISP0R_INIT_LAT_SHIFT)); - RHDWriteMC(rhdPtr, RV515_MC_MISC_LAT_TIMER, value); + if (MC->Idle(MC)) + MC->Restore(MC); + else + xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, + "%s: MC is still not idle!!!\n", __func__); } /* * */ -static void -rs690TuneMCAccessForDisplay(RHDPtr rhdPtr, int crtc, - DisplayModePtr Mode, DisplayModePtr ScaledToMode) +Bool +RHDMCIdleWait(RHDPtr rhdPtr, CARD32 count) { - CARD32 value, setting = 0x1; + struct rhdMC *MC = rhdPtr->MC; RHDFUNC(rhdPtr); - value = RHDReadMC(rhdPtr, RS69_MC_INIT_MISC_LAT_TIMER); - value |= setting << (crtc ? MC_DISP1R_INIT_LAT_SHIFT : MC_DISP0R_INIT_LAT_SHIFT); - RHDWriteMC(rhdPtr, RS69_MC_INIT_MISC_LAT_TIMER, value); + ASSERT(MC); + + do { + if (MC->Idle(MC)) + return TRUE; + usleep(1000); + } while (count--); + + RHDDebug(rhdPtr->scrnIndex, "%s: MC not idle\n",__func__); + + return FALSE; } /* - * + * Get FB location and size. */ -void -RHDTuneMCAccessForDisplay(RHDPtr rhdPtr, int crtc, - DisplayModePtr Mode, DisplayModePtr ScaledToMode) +CARD64 +RHDMCGetFBLocation(RHDPtr rhdPtr, CARD32 *size) { struct rhdMC *MC = rhdPtr->MC; + ASSERT(MC); + ASSERT(size); + RHDFUNC(rhdPtr); - if (MC->TuneMCAccessForDisplay) - MC->TuneMCAccessForDisplay(rhdPtr, crtc, Mode, ScaledToMode); + return MC->GetFBLocation(MC, size); } /* - * + * Make sure that nothing is accessing memory anymore before calling this. */ -void -RHDMCInit(RHDPtr rhdPtr) +Bool +RHDMCSetupFBLocation(RHDPtr rhdPtr, CARD64 Address, CARD32 Size) { - struct rhdMC *MC; + struct rhdMC *MC = rhdPtr->MC; + CARD64 OldAddress; + CARD32 OldSize; + + ASSERT(MC); + RHD_SETDEBUGFLAG(rhdPtr, MC_SETUP); RHDFUNC(rhdPtr); - /* These devices have an internal address reference, which some other - * address registers in there also use. This can be different from the - * address in the BAR. - * - * We read out the address here from some known location. This address - * is as good a guess as any, we just need to pick one, but then make - * sure that it is made consistent in MCSetup and the various MC - * accessing subsystems. - */ - if (rhdPtr->ChipSet < RHD_R600) - rhdPtr->FbIntAddress = RHDRegRead(rhdPtr, HDP_FB_LOCATION) << 16; - else - rhdPtr->FbIntAddress = RHDRegRead(rhdPtr, R6XX_CONFIG_FB_BASE); + if (!MC->Idle(MC)) { + xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, + "%s: Cannot setup MC: not idle!!!\n", __func__); + return FALSE; + } - RHDDebug(rhdPtr->scrnIndex, "MC FB Address: 0x%08X.\n", - rhdPtr->FbIntAddress); + OldAddress = MC->GetFBLocation(MC, &OldSize); + if (OldAddress == Address && OldSize == Size) + return TRUE; - MC = xnfcalloc(1, sizeof(struct rhdMC)); - MC->Stored = FALSE; + /* If this ever occurs, we might have issues */ + if (OldAddress >> 32) + xf86DrvMsg(rhdPtr->scrnIndex, X_WARNING, "%s: Board claims to use a " + "higher than 32bit address for its FB\n", __func__); - if (rhdPtr->ChipSet < RHD_RS600) { - MC->SaveMC = r5xxSaveMC; - MC->RestoreMC = r5xxRestoreMC; - MC->SetupMC = r5xxSetupMC; - MC->GetFBLocation = r5xxGetFBLocation; - - if (rhdPtr->ChipSet == RHD_RV515 - || rhdPtr->ChipSet == RHD_RV505 - || rhdPtr->ChipSet == RHD_RV516 - || rhdPtr->ChipSet == RHD_RV550 - || rhdPtr->ChipSet == RHD_M52 - || rhdPtr->ChipSet == RHD_M54 - || rhdPtr->ChipSet == RHD_M62 - || rhdPtr->ChipSet == RHD_M64 - || rhdPtr->ChipSet == RHD_M71) { - - MC->RV515Variant = TRUE; - MC->MCIdle = rv515MCIdle; - MC->TuneMCAccessForDisplay = rv515TuneMCAccessForDisplay; - } else { - - MC->RV515Variant = FALSE; - MC->MCIdle = r5xxMCIdle; + RHDDebug(rhdPtr->scrnIndex, + "Setting MC from 0x%08X to 0x%08X [Size 0x%08X]\n", + OldAddress, rhdPtr->FbIntAddress, Size); - } - - } else if (rhdPtr->ChipSet == RHD_RS600) { - MC->SaveMC = rs600SaveMC; - MC->RestoreMC = rs600RestoreMC; - MC->SetupMC = rs600SetupMC; - MC->MCIdle = rs600MCIdle; - MC->GetFBLocation = rs600GetFBLocation; - } else if (rhdPtr->ChipSet < RHD_R600) { - MC->SaveMC = rs690SaveMC; - MC->RestoreMC = rs690RestoreMC; - MC->SetupMC = rs690SetupMC; - MC->MCIdle = rs690MCIdle; - MC->GetFBLocation = rs690GetFBLocation; - MC->TuneMCAccessForDisplay = rs690TuneMCAccessForDisplay; - } else if (rhdPtr->ChipSet <= RHD_RS780) { - MC->SaveMC = r6xxSaveMC; - MC->RestoreMC = r6xxRestoreMC; - MC->SetupMC = r6xxSetupMC; - MC->MCIdle = r6xxMCIdle; - MC->GetFBLocation = r6xxGetFBLocation; - } -#if 0 - else if (rhdPtr->ChipSet == RHD_RS780) { - MC->SaveMC = rs780SaveMC; - MC->RestoreMC = rs780RestoreMC; - MC->SetupMC = rs780SetupMC; - MC->MCIdle = rs780MCIdle; - MC->GetFBLocation = rs780GetFBLocation; - } -#endif - else if (rhdPtr->ChipSet >= RHD_RV770) { - MC->SaveMC = r7xxSaveMC; - MC->RestoreMC = r7xxRestoreMC; - MC->SetupMC = r7xxSetupMC; - MC->MCIdle = r6xxMCIdle; - MC->GetFBLocation = r7xxGetFBLocation; - } else { - xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, "I don't know anything about MC on this chipset\n"); - xfree(MC); - return; - } - rhdPtr->MC = MC; + MC->SetupFBLocation(MC, Address, Size); + return TRUE; } /* - * Free structure. + * */ void -RHDMCDestroy(RHDPtr rhdPtr) +RHDMCTuneAccessForDisplay(RHDPtr rhdPtr, int Crtc, + DisplayModePtr Mode, DisplayModePtr ScaledToMode) { - RHDFUNC(rhdPtr); + struct rhdMC *MC = rhdPtr->MC; - if (!rhdPtr->MC) - return; + ASSERT(MC); - xfree(rhdPtr->MC); - rhdPtr->MC = NULL; + RHDFUNC(rhdPtr); + + if (MC->TuneAccessForDisplay) + MC->TuneAccessForDisplay(MC, Crtc, Mode, ScaledToMode); } /* @@ -877,7 +795,7 @@ RHD_MC_IGP_SideportMemoryPresent(RHDPtr rhdPtr) default: break; } - xf86DrvMsg(rhdPtr->scrnIndex, X_INFO, "IPG sideport memory %s present.\n", Present ? "" : "not"); + xf86DrvMsg(rhdPtr->scrnIndex, X_INFO, "IGP sideport memory %s present.\n", Present ? "" : "not"); return Present; } diff --git a/driver/xf86-video-radeonhd/src/rhd_mc.h b/driver/xf86-video-radeonhd/src/rhd_mc.h index a0481cdbc..2d2bd18bf 100644 --- a/driver/xf86-video-radeonhd/src/rhd_mc.h +++ b/driver/xf86-video-radeonhd/src/rhd_mc.h @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. @@ -27,13 +27,13 @@ extern void RHDMCInit(RHDPtr rhdPtr); extern void RHDMCDestroy(RHDPtr rhdPtr); -extern void RHDSaveMC(RHDPtr rhdPtr); -extern void RHDRestoreMC(RHDPtr rhdPtr); -extern void RHDMCSetup(RHDPtr rhdPtr); -extern Bool RHDMCIdle(RHDPtr rhdPtr, CARD32 count); -extern void RHDTuneMCAccessForDisplay(RHDPtr rhdPtr, int crtc, - DisplayModePtr Mode, DisplayModePtr ScaledToMode); -extern CARD32 RHDGetFBLocation(RHDPtr rhdPtr, CARD32 *size); +extern void RHDMCSave(RHDPtr rhdPtr); +extern void RHDMCRestore(RHDPtr rhdPtr); +extern Bool RHDMCSetupFBLocation(RHDPtr rhdPtr, CARD64 Address, CARD32 Size); +extern Bool RHDMCIdleWait(RHDPtr rhdPtr, CARD32 count); +extern void RHDMCTuneAccessForDisplay(RHDPtr rhdPtr, int Crtc, DisplayModePtr Mode, + DisplayModePtr ScaledToMode); +extern CARD64 RHDMCGetFBLocation(RHDPtr rhdPtr, CARD32 *size); extern Bool RHD_MC_IGP_SideportMemoryPresent(RHDPtr rhdPtr); diff --git a/driver/xf86-video-radeonhd/src/rhd_modes.c b/driver/xf86-video-radeonhd/src/rhd_modes.c index 46e9ff9d5..192f3fd9f 100644 --- a/driver/xf86-video-radeonhd/src/rhd_modes.c +++ b/driver/xf86-video-radeonhd/src/rhd_modes.c @@ -1,5 +1,5 @@ /* - * Copyright 2004-2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2004-2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_modes.h b/driver/xf86-video-radeonhd/src/rhd_modes.h index 4ff628209..be8aaa471 100644 --- a/driver/xf86-video-radeonhd/src/rhd_modes.h +++ b/driver/xf86-video-radeonhd/src/rhd_modes.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_monitor.c b/driver/xf86-video-radeonhd/src/rhd_monitor.c index 2923ecd00..5234c7b43 100644 --- a/driver/xf86-video-radeonhd/src/rhd_monitor.c +++ b/driver/xf86-video-radeonhd/src/rhd_monitor.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_monitor.h b/driver/xf86-video-radeonhd/src/rhd_monitor.h index 68f48ab83..3a83d0d8a 100644 --- a/driver/xf86-video-radeonhd/src/rhd_monitor.h +++ b/driver/xf86-video-radeonhd/src/rhd_monitor.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_output.c b/driver/xf86-video-radeonhd/src/rhd_output.c index 2ab9d5257..7fe2ee9d4 100644 --- a/driver/xf86-video-radeonhd/src/rhd_output.c +++ b/driver/xf86-video-radeonhd/src/rhd_output.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. @@ -205,3 +205,59 @@ RHDOutputPrintSensedType(struct rhdOutput *Output) i++; } } + +/* + * Attach an connector to the specified output and set output properties depending on the connector + */ +void +RHDOutputAttachConnector(struct rhdOutput *Output, struct rhdConnector *Connector) +{ + RHDPtr rhdPtr = RHDPTRI(Output); + + if(Output->Connector == Connector) + return; /* output is allready attached to this connector -> nothing todo */ + + Output->Connector = Connector; + + if(!Output->Property) /* property controll available? */ + return; /* no -> we are done here */ + + /* yes -> check if we need to set any properties */ + if (Output->Property(Output, rhdPropertyCheck, RHD_OUTPUT_COHERENT, NULL)) { + union rhdPropertyData val; + switch(RhdParseBooleanOption(&rhdPtr->coherent, Connector->Name)) { + case RHD_OPTION_NOT_SET: + /* for compatibility with old implementation, test also output name */ + switch(RhdParseBooleanOption(&rhdPtr->coherent, Output->Name)) { + case RHD_OPTION_NOT_SET: + case RHD_OPTION_DEFAULT: + case RHD_OPTION_OFF: + val.Bool = FALSE; + break; + case RHD_OPTION_ON: + val.Bool = TRUE; + break; + } + break; + case RHD_OPTION_DEFAULT: + case RHD_OPTION_OFF: + val.Bool = FALSE; + break; + case RHD_OPTION_ON: + val.Bool = TRUE; + break; + } + if(Output->Property(Output, rhdPropertySet, RHD_OUTPUT_COHERENT, &val)) + xf86DrvMsg(rhdPtr->scrnIndex, X_INFO, "Setting %s to %scoherent\n", Output->Name, val.Bool ? "" : "in"); + else + xf86DrvMsg(rhdPtr->scrnIndex, X_WARNING, "Failed to set %s to %scoherent\n", Output->Name, val.Bool ? "" : "in"); + } + + /* ask attached connector if EEDID or config options say we should enable HDMI */ + if (Output->Property(Output, rhdPropertyCheck, RHD_OUTPUT_HDMI, NULL)) { + union rhdPropertyData val; + val.Bool = RHDConnectorEnableHDMI(Connector); + if(!Output->Property(Output, rhdPropertySet, RHD_OUTPUT_HDMI, &val)) + xf86DrvMsg(rhdPtr->scrnIndex, X_WARNING, "Failed to %s HDMI on %s\n", val.Bool ? "disable" : "enable", Output->Name); + } +} diff --git a/driver/xf86-video-radeonhd/src/rhd_output.h b/driver/xf86-video-radeonhd/src/rhd_output.h index ffd152b2f..22edfe9d0 100644 --- a/driver/xf86-video-radeonhd/src/rhd_output.h +++ b/driver/xf86-video-radeonhd/src/rhd_output.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2004-2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. @@ -58,7 +58,8 @@ typedef enum rhdSensedOutput { enum rhdOutputProperty { RHD_OUTPUT_BACKLIGHT, - RHD_OUTPUT_COHERENT + RHD_OUTPUT_COHERENT, + RHD_OUTPUT_HDMI }; enum rhdOutputAllocation { @@ -113,6 +114,7 @@ void RHDOutputsSave(RHDPtr rhdPtr); void RHDOutputsRestore(RHDPtr rhdPtr); void RHDOutputsDestroy(RHDPtr rhdPtr); void RHDOutputPrintSensedType(struct rhdOutput *Output); +void RHDOutputAttachConnector(struct rhdOutput *Output, struct rhdConnector *Connector); /* output local functions. */ struct rhdOutput *RHDDACAInit(RHDPtr rhdPtr); diff --git a/driver/xf86-video-radeonhd/src/rhd_pll.c b/driver/xf86-video-radeonhd/src/rhd_pll.c index 5d9207bae..45ab03ad5 100644 --- a/driver/xf86-video-radeonhd/src/rhd_pll.c +++ b/driver/xf86-video-radeonhd/src/rhd_pll.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_pll.h b/driver/xf86-video-radeonhd/src/rhd_pll.h index 8cd8f4ee5..cba151cce 100644 --- a/driver/xf86-video-radeonhd/src/rhd_pll.h +++ b/driver/xf86-video-radeonhd/src/rhd_pll.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_randr.c b/driver/xf86-video-radeonhd/src/rhd_randr.c index 75c605697..8794f1c6c 100644 --- a/driver/xf86-video-radeonhd/src/rhd_randr.c +++ b/driver/xf86-video-radeonhd/src/rhd_randr.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. @@ -111,20 +111,24 @@ struct rhdRandrCrtc { } u; }; -#define ATOM_SIGNAL_FORMAT "RANDR_SIGNAL_FORMAT" -#define ATOM_CONNECTOR_TYPE "RANDR_CONNECTOR_TYPE" -#define ATOM_CONNECTOR_NUMBER "RANDR_CONNECTOR_NUMBER" -#define ATOM_OUTPUT_NUMBER "RANDR_OUTPUT_NUMBER" -#define ATOM_PANNING_AREA "RANDR_PANNING_AREA" -#define ATOM_BACKLIGHT "BACKLIGHT" -#define ATOM_COHERENT "COHERENT" +#define ATOM_SIGNAL_FORMAT "SignalFormat" +#define ATOM_CONNECTOR_TYPE "ConnectorType" +#define ATOM_CONNECTOR_NUMBER "ConnectorNumber" +#define ATOM_OUTPUT_NUMBER "_OutputNumber" +#define ATOM_PANNING_AREA "_PanningArea" +#define ATOM_BACKLIGHT "_Backlight" +#define ATOM_COHERENT "_Coherent" +#define ATOM_HDMI "_HDMI" -static Atom atomSignalFormat, atomConnectorType, atomConnectorNumber, - atomOutputNumber, atomPanningArea, atomBacklight, atomCoherent; +static Atom atom_SignalFormat, atom_ConnectorType, atom_ConnectorNumber, + atom_OutputNumber, atom_PanningArea, atom_Backlight, atom_Coherent, + atom_HdmiProperty; +static Atom atom_unknown, atom_VGA, atom_TMDS, atom_LVDS, atom_DisplayPort, atom_TV; +static Atom atom_DVI, atom_DVII, atom_DVID, atom_DVIA, atom_HDMI, atom_Panel; /* Get RandR property values */ -static const char * +static Atom rhdGetSignalFormat(rhdRandrOutputPtr ro) { switch (ro->Output->Id) { @@ -134,10 +138,10 @@ rhdGetSignalFormat(rhdRandrOutputPtr ro) case RHD_CONNECTOR_VGA: case RHD_CONNECTOR_DVI: case RHD_CONNECTOR_DVI_SINGLE: - return "VGA"; - case RHD_CONNECTOR_TV: /* TODO: depending on current format */ + return atom_VGA; + case RHD_CONNECTOR_TV: default: - return "unknown"; + return atom_unknown; /* TODO */ } case RHD_OUTPUT_LVTMA: case RHD_OUTPUT_KLDSKP_LVTMA: @@ -154,37 +158,46 @@ rhdGetSignalFormat(rhdRandrOutputPtr ro) switch (ro->Connector->Type) { case RHD_CONNECTOR_DVI: case RHD_CONNECTOR_DVI_SINGLE: - return "TMDS"; + return atom_TMDS; case RHD_CONNECTOR_PANEL: - return "LVDS"; + return atom_LVDS; default: - return "unknown"; + return atom_unknown; } case RHD_OUTPUT_TMDSA: #if RHD_OUTPUT_TMDSB != RHD_OUTPUT_LVDS case RHD_OUTPUT_TMDSB: #endif - return "TMDS"; + return atom_TMDS; default: - return "unknown"; + return atom_unknown; } } -static const char * +static Atom rhdGetConnectorType(rhdRandrOutputPtr ro) { switch (ro->Connector->Type) { case RHD_CONNECTOR_VGA: - return "VGA"; + return atom_VGA; case RHD_CONNECTOR_DVI: - return "DVI"; /* TODO: DVI-I/A/D / HDMI */ case RHD_CONNECTOR_DVI_SINGLE: - return "DVI (single link)"; +#ifdef NOTYET + if (ro->Output->Connector == RHD_CONNECTOR_HDMI || ro->Output->Connector == RHD_CONNECTOR_HDMI_DUAL) + return atom_HDMI; +#endif + if (strncmp (ro->Connector->Name, "DVI-I", 5) == 0) + return atom_DVII; + if (strncmp (ro->Connector->Name, "DVI-D", 5) == 0) + return atom_DVID; + if (strncmp (ro->Connector->Name, "DVI-A", 5) == 0) + return atom_DVIA; + return atom_DVI; case RHD_CONNECTOR_PANEL: - return "PANEL"; + return atom_Panel; case RHD_CONNECTOR_TV: - return "TV"; + return atom_TV; /* TODO */ default: - return "unknown"; + return atom_unknown; } } @@ -482,9 +495,9 @@ rhdRRCrtcGammaSet(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue, /* thanks so very much */ for (i = 0; i < size; i++) { indices[i] = i; - colors[i].red = red[i]; - colors[i].green = green[i]; - colors[i].blue = blue[i]; + colors[i].red = red[i] >> 6; + colors[i].green = green[i] >> 6; + colors[i].blue = blue[i] >> 6; } rhdCrtc->LUT->Set(rhdCrtc->LUT, size, indices, colors); @@ -499,6 +512,8 @@ rhdRRCrtcModeFixupDUMMY(xf86CrtcPtr crtc, return TRUE; } +#if XF86_CRTC_VERSION >= 2 +/* Entry point for RandR 1.3 panning */ static void rhdRRCrtcSetOrigin(xf86CrtcPtr crtc, int x, int y) { @@ -506,6 +521,7 @@ rhdRRCrtcSetOrigin(xf86CrtcPtr crtc, int x, int y) rhdCrtc->FrameSet(rhdCrtc, x, y); } +#endif /* @@ -518,43 +534,90 @@ rhdRROutputCreateResources(xf86OutputPtr out) RHDPtr rhdPtr = RHDPTR(out->scrn); rhdRandrOutputPtr rout = (rhdRandrOutputPtr) out->driver_private; struct rhdOutput *o; - const char *val; + INT32 val; CARD32 num; - int err; - INT32 range[2]; + int err; + INT32 range[2]; RHDFUNC(rhdPtr); - /* Create atoms for potential RandR 1.3 properties */ - atomSignalFormat = MakeAtom(ATOM_SIGNAL_FORMAT, - sizeof(ATOM_SIGNAL_FORMAT)-1, TRUE); - atomConnectorType = MakeAtom(ATOM_CONNECTOR_TYPE, - sizeof(ATOM_CONNECTOR_TYPE)-1, TRUE); - atomConnectorNumber = MakeAtom(ATOM_CONNECTOR_NUMBER, - sizeof(ATOM_CONNECTOR_NUMBER)-1, TRUE); - atomOutputNumber = MakeAtom(ATOM_OUTPUT_NUMBER, - sizeof(ATOM_OUTPUT_NUMBER)-1, TRUE); - atomPanningArea = MakeAtom(ATOM_PANNING_AREA, - sizeof(ATOM_PANNING_AREA)-1, TRUE); + /* Create atoms for RandR 1.3 properties */ + atom_SignalFormat = MakeAtom(ATOM_SIGNAL_FORMAT, + sizeof(ATOM_SIGNAL_FORMAT)-1, TRUE); + atom_ConnectorType = MakeAtom(ATOM_CONNECTOR_TYPE, + sizeof(ATOM_CONNECTOR_TYPE)-1, TRUE); + atom_ConnectorNumber = MakeAtom(ATOM_CONNECTOR_NUMBER, + sizeof(ATOM_CONNECTOR_NUMBER)-1, TRUE); + atom_OutputNumber = MakeAtom(ATOM_OUTPUT_NUMBER, + sizeof(ATOM_OUTPUT_NUMBER)-1, TRUE); + atom_PanningArea = MakeAtom(ATOM_PANNING_AREA, + sizeof(ATOM_PANNING_AREA)-1, TRUE); + + /* Create atoms for RandR 1.3 property values */ + atom_unknown = MakeAtom("unknown", 7, TRUE); + atom_VGA = MakeAtom("VGA", 3, TRUE); + atom_TMDS = MakeAtom("TMDS", 4, TRUE); + atom_LVDS = MakeAtom("LVDS", 4, TRUE); + atom_DisplayPort = MakeAtom("DisplayPort", 11, TRUE); + atom_TV = MakeAtom("TV", 2, TRUE); + atom_DVI = MakeAtom("DVI", 3, TRUE); + atom_DVII = MakeAtom("DVI-I", 5, TRUE); + atom_DVID = MakeAtom("DVI-D", 5, TRUE); + atom_DVIA = MakeAtom("DVI-A", 5, TRUE); + atom_HDMI = MakeAtom("HDMI", 4, TRUE); + atom_Panel = MakeAtom("Panel", 5, TRUE); /* Set up properties */ - RRConfigureOutputProperty(out->randr_output, atomSignalFormat, - FALSE, FALSE, TRUE, 0, NULL); - RRConfigureOutputProperty(out->randr_output, atomConnectorType, + val = rhdGetSignalFormat(rout); + /* TODO: for TV multiple signal formats will be possible */ + RRConfigureOutputProperty(out->randr_output, atom_SignalFormat, + FALSE, FALSE, TRUE, 1, &val); + RRChangeOutputProperty(out->randr_output, atom_SignalFormat, + XA_ATOM, 32, PropModeReplace, + 1, &val, FALSE, FALSE); + + val = rhdGetConnectorType(rout); + RRConfigureOutputProperty(out->randr_output, atom_ConnectorType, FALSE, FALSE, TRUE, 0, NULL); - RRConfigureOutputProperty(out->randr_output, atomConnectorNumber, + RRChangeOutputProperty(out->randr_output, atom_ConnectorType, + XA_ATOM, 32, PropModeReplace, + 1, &val, FALSE, FALSE); + + for (num = 0; num < RHD_CONNECTORS_MAX; num++) + if (rout->Connector == rhdPtr->Connector[num]) + break; + ASSERT(num < RHD_CONNECTORS_MAX); + num++; /* For RANDR_CONNECTOR_NUMBER 0 is unknown */ + RRConfigureOutputProperty(out->randr_output, atom_ConnectorNumber, FALSE, FALSE, TRUE, 0, NULL); - RRConfigureOutputProperty(out->randr_output, atomPanningArea, + RRChangeOutputProperty(out->randr_output, atom_ConnectorNumber, + XA_INTEGER, 32, PropModeReplace, + 1, &num, FALSE, FALSE); + + for (num = 1, o = rhdPtr->Outputs; o; num++, o = o->Next) + if (rout->Output == o) + break; + ASSERT(o); + RRConfigureOutputProperty(out->randr_output, atom_OutputNumber, + FALSE, FALSE, FALSE, 0, NULL); + RRChangeOutputProperty(out->randr_output, atom_OutputNumber, + XA_INTEGER, 32, PropModeReplace, + 1, &num, FALSE, FALSE); + + RRConfigureOutputProperty(out->randr_output, atom_PanningArea, FALSE, FALSE, FALSE, 0, NULL); + RRChangeOutputProperty(out->randr_output, atom_PanningArea, + XA_STRING, 8, PropModeReplace, + 0, NULL, FALSE, FALSE); if (rout->Output->Property) { if (rout->Output->Property(rout->Output, rhdPropertyCheck, RHD_OUTPUT_BACKLIGHT, NULL)) { - atomBacklight = MakeAtom(ATOM_BACKLIGHT, - sizeof(ATOM_BACKLIGHT)-1, TRUE); + atom_Backlight = MakeAtom(ATOM_BACKLIGHT, + sizeof(ATOM_BACKLIGHT)-1, TRUE); range[0] = 0; range[1] = 255; - err = RRConfigureOutputProperty(out->randr_output, atomBacklight, + err = RRConfigureOutputProperty(out->randr_output, atom_Backlight, FALSE, TRUE, FALSE, 2, range); if (err != 0) xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, @@ -565,7 +628,7 @@ rhdRROutputCreateResources(xf86OutputPtr out) if (!rout->Output->Property(rout->Output, rhdPropertyGet, RHD_OUTPUT_BACKLIGHT, &val)) val.integer = 255; - err = RRChangeOutputProperty(out->randr_output, atomBacklight, + err = RRChangeOutputProperty(out->randr_output, atom_Backlight, XA_INTEGER, 32, PropModeReplace, 1, &val.integer, FALSE, FALSE); if (err != 0) @@ -575,12 +638,12 @@ rhdRROutputCreateResources(xf86OutputPtr out) } } if (rout->Output->Property(rout->Output, rhdPropertyCheck, RHD_OUTPUT_COHERENT, NULL)) { - atomCoherent = MakeAtom(ATOM_COHERENT, + atom_Coherent = MakeAtom(ATOM_COHERENT, sizeof(ATOM_COHERENT)-1, TRUE); range[0] = 0; range[1] = 1; - err = RRConfigureOutputProperty(out->randr_output, atomCoherent, + err = RRConfigureOutputProperty(out->randr_output, atom_Coherent, FALSE, TRUE, FALSE, 2, range); if (err != 0) xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, @@ -590,7 +653,7 @@ rhdRROutputCreateResources(xf86OutputPtr out) if (!rout->Output->Property(rout->Output, rhdPropertyGet, RHD_OUTPUT_COHERENT, &val)) val.Bool = 1; - err = RRChangeOutputProperty(out->randr_output, atomCoherent, + err = RRChangeOutputProperty(out->randr_output, atom_Coherent, XA_INTEGER, 32, PropModeReplace, 1, &val.Bool, FALSE, FALSE); if (err != 0) @@ -599,34 +662,32 @@ rhdRROutputCreateResources(xf86OutputPtr out) __func__, err); } } - } + if (rout->Output->Property(rout->Output, rhdPropertyCheck, RHD_OUTPUT_HDMI, NULL)) { + atom_HdmiProperty = MakeAtom(ATOM_HDMI, sizeof(ATOM_HDMI)-1, TRUE); - val = rhdGetSignalFormat(rout); - RRChangeOutputProperty(out->randr_output, atomSignalFormat, - XA_STRING, 8, PropModeReplace, - strlen(val), (char *) val, FALSE, FALSE); - val = rhdGetConnectorType(rout); - RRChangeOutputProperty(out->randr_output, atomConnectorType, - XA_STRING, 8, PropModeReplace, - strlen(val), (char *) val, FALSE, FALSE); - for (num = 0; num < RHD_CONNECTORS_MAX; num++) - if (rout->Connector == rhdPtr->Connector[num]) - break; - ASSERT(num < RHD_CONNECTORS_MAX); - num++; /* For RANDR_CONNECTOR_NUMBER 0 is unknown */ - RRChangeOutputProperty(out->randr_output, atomConnectorNumber, - XA_INTEGER, 32, PropModeReplace, - 1, &num, FALSE, FALSE); - for (num = 1, o = rhdPtr->Outputs; o; num++, o = o->Next) - if (rout->Output == o) - break; - ASSERT(o); - RRChangeOutputProperty(out->randr_output, atomOutputNumber, - XA_INTEGER, 32, PropModeReplace, - 1, &num, FALSE, FALSE); - RRChangeOutputProperty(out->randr_output, atomPanningArea, - XA_STRING, 8, PropModeReplace, - 0, NULL, FALSE, FALSE); + range[0] = 0; + range[1] = 1; + err = RRConfigureOutputProperty(out->randr_output, atom_HdmiProperty, + FALSE, TRUE, FALSE, 2, range); + if (err != 0) + xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, + "RRConfigureOutputProperty error: %d\n", err); + else { + union rhdPropertyData val; + + if (!rout->Output->Property(rout->Output, rhdPropertyGet, RHD_OUTPUT_HDMI, &val)) + val.Bool = 1; + err = RRChangeOutputProperty(out->randr_output, atom_HdmiProperty, + XA_INTEGER, 32, PropModeReplace, + 1, &val.Bool, FALSE, FALSE); + if (err != 0) + xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, + "In %s RRChangeOutputProperty error: %d\n", + __func__, err); + } + } + + } } /* Turns the output on/off, or sets intermediate power levels if available. */ @@ -956,7 +1017,7 @@ rhdRROutputCommit(xf86OutputPtr out) { RHDPtr rhdPtr = RHDPTR(out->scrn); rhdRandrOutputPtr rout = (rhdRandrOutputPtr) out->driver_private; - const char *val; + CARD32 val; char buf[32]; struct rhdCrtc *rhdCrtc = ((struct rhdRandrCrtc *)(out->crtc->driver_private))->rhdCrtc; @@ -964,21 +1025,21 @@ rhdRROutputCommit(xf86OutputPtr out) ASSERT(rhdCrtc == rout->Output->Crtc); rout->Output->Active = TRUE; - rout->Output->Connector = rout->Connector; /* @@@ */ + RHDOutputAttachConnector(rout->Output, rout->Connector); /* @@@ */ rout->Output->Power(rout->Output, RHD_POWER_ON); /* Some outputs may have physical protocol changes (e.g. TV) */ val = rhdGetSignalFormat(rout); - RRChangeOutputProperty(out->randr_output, atomConnectorType, - XA_STRING, 8, PropModeReplace, - strlen(val), (char *) val, TRUE, FALSE); + RRChangeOutputProperty(out->randr_output, atom_SignalFormat, + XA_ATOM, 32, PropModeReplace, + 1, &val, TRUE, FALSE); /* Should be a crtc property */ if (rhdCrtc->MaxX > rhdCrtc->MinX && rhdCrtc->MaxY > rhdCrtc->MinY) sprintf(buf, "%dx%d+%d+%d", rhdCrtc->MaxX - rhdCrtc->MinX, rhdCrtc->MaxY - rhdCrtc->MinY, rhdCrtc->MinX, rhdCrtc->MinY); else buf[0] = 0; - RRChangeOutputProperty(out->randr_output, atomPanningArea, + RRChangeOutputProperty(out->randr_output, atom_PanningArea, XA_STRING, 8, PropModeReplace, strlen(buf), buf, TRUE, FALSE); @@ -1024,7 +1085,7 @@ rhdRROutputDetect(xf86OutputPtr output) /* Assume that a panel is always connected */ if (rout->Connector->Type == RHD_CONNECTOR_PANEL) { - rout->Output->Connector = rout->Connector; /* @@@ */ + RHDOutputAttachConnector(rout->Output, rout->Connector); /* @@@ */ return XF86OutputStatusConnected; } else if (rout->Connector->Type == RHD_CONNECTOR_TV) /* until TV_OUT is fixed we bail here */ return XF86OutputStatusDisconnected; @@ -1040,7 +1101,7 @@ rhdRROutputDetect(xf86OutputPtr output) = rout->Output->Sense(rout->Output, rout->Connector)) != RHD_SENSED_NONE) { RHDOutputPrintSensedType(rout->Output); - rout->Output->Connector = rout->Connector; /* @@@ */ + RHDOutputAttachConnector(rout->Output, rout->Connector); /* @@@ */ return XF86OutputStatusConnected; } else return XF86OutputStatusDisconnected; @@ -1052,7 +1113,7 @@ rhdRROutputDetect(xf86OutputPtr output) * is attached to this one */ if (rhdRROtherOutputOnConnectorHelper(rhdPtr, rout)) return XF86OutputStatusDisconnected; - rout->Output->Connector = rout->Connector; /* @@@ */ + RHDOutputAttachConnector(rout->Output, rout->Connector); /* @@@ */ return XF86OutputStatusConnected; } } else { @@ -1069,8 +1130,8 @@ rhdRROutputDetect(xf86OutputPtr output) = rout->Output->Sense(rout->Output, rout->Connector); if (rout->Output->SensedType != RHD_SENSED_NONE) { - rout->Output->Connector = rout->Connector; /* @@@ */ RHDOutputPrintSensedType(rout->Output); + RHDOutputAttachConnector(rout->Output, rout->Connector); /* @@@ */ return XF86OutputStatusConnected; } } @@ -1085,8 +1146,8 @@ rhdRROutputDetect(xf86OutputPtr output) rout->Output->SensedType = rout->Output->Sense(rout->Output, rout->Connector); if (rout->Output->SensedType != RHD_SENSED_NONE) { - rout->Output->Connector = rout->Connector; /* @@@ */ RHDOutputPrintSensedType(rout->Output); + RHDOutputAttachConnector(rout->Output, rout->Connector); /* @@@ */ return XF86OutputStatusConnected; } else return XF86OutputStatusDisconnected; @@ -1106,7 +1167,7 @@ rhdRROutputDetect(xf86OutputPtr output) rout_tmp->Output->Name); return XF86OutputStatusDisconnected; } - rout->Output->Connector = rout->Connector; /* @@@ */ + RHDOutputAttachConnector(rout->Output, rout->Connector); /* @@@ */ return XF86OutputStatusConnected; } else { RHDDebug(rout->Output->scrnIndex, "DDC Probing for Output %s returned disconnected\n", @@ -1114,7 +1175,7 @@ rhdRROutputDetect(xf86OutputPtr output) return XF86OutputStatusDisconnected; } } - rout->Output->Connector = rout->Connector; /* @@@ */ + RHDOutputAttachConnector(rout->Output, rout->Connector); /* @@@ */ return XF86OutputStatusUnknown; } } @@ -1234,7 +1295,7 @@ rhdRROutputSetProperty(xf86OutputPtr out, Atom property, RHDFUNC(rhdPtr); - if (property == atomPanningArea) { + if (property == atom_PanningArea) { int w = 0, h = 0, x = 0, y = 0; struct rhdCrtc *Crtc = rout->Output->Crtc; int i; @@ -1271,7 +1332,7 @@ rhdRROutputSetProperty(xf86OutputPtr out, Atom property, default: return FALSE; } - } else if (property == atomBacklight) { + } else if (property == atom_Backlight) { if (value->type != XA_INTEGER || value->format != 32) { xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, "%s: wrong value\n", __func__); return FALSE; @@ -1279,11 +1340,27 @@ rhdRROutputSetProperty(xf86OutputPtr out, Atom property, if (rout->Output->Property) { union rhdPropertyData val; val.integer = *(int*)(value->data); - return rout->Output->Property(rout->Output, rhdPropertySet, - RHD_OUTPUT_BACKLIGHT, &val); + if(rout->Output->Property(rout->Output, rhdPropertySet, + RHD_OUTPUT_BACKLIGHT, &val)) + return rout->Output->Property(rout->Output, rhdPropertyCommit, + RHD_OUTPUT_BACKLIGHT, NULL); + } + return FALSE; + } else if (property == atom_Coherent) { + if (value->type != XA_INTEGER || value->format != 32) { + xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, "%s: wrong value\n", __func__); + return FALSE; + } + if (rout->Output->Property) { + union rhdPropertyData val; + val.Bool = *(int*)(value->data); + if(rout->Output->Property(rout->Output, rhdPropertySet, + RHD_OUTPUT_COHERENT, &val)) + return rout->Output->Property(rout->Output, rhdPropertyCommit, + RHD_OUTPUT_COHERENT, NULL); } return FALSE; - } else if (property == atomCoherent) { + } else if (property == atom_HdmiProperty) { if (value->type != XA_INTEGER || value->format != 32) { xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, "%s: wrong value\n", __func__); return FALSE; @@ -1291,8 +1368,10 @@ rhdRROutputSetProperty(xf86OutputPtr out, Atom property, if (rout->Output->Property) { union rhdPropertyData val; val.Bool = *(int*)(value->data); - return rout->Output->Property(rout->Output, rhdPropertySet, - RHD_OUTPUT_COHERENT, &val); + if(rout->Output->Property(rout->Output, rhdPropertySet, + RHD_OUTPUT_HDMI, &val)) + return rout->Output->Property(rout->Output, rhdPropertyCommit, + RHD_OUTPUT_HDMI, NULL); } return FALSE; } @@ -1424,18 +1503,18 @@ rhdRROutputGetProperty(xf86OutputPtr out, Atom property) xf86DrvMsg(rhdPtr->scrnIndex, X_INFO, "In %s\n", __func__); - if (property == atomBacklight) { + if (property == atom_Backlight) { if (rout->Output->Property == NULL) return FALSE; if (!rout->Output->Property(rout->Output, rhdPropertyGet, RHD_OUTPUT_BACKLIGHT, &val)) return FALSE; - err = RRChangeOutputProperty(out->randr_output, atomBacklight, + err = RRChangeOutputProperty(out->randr_output, atom_Backlight, XA_INTEGER, 32, PropModeReplace, 1, &val.integer, FALSE, FALSE); - } else if (property == atomCoherent) { + } else if (property == atom_Coherent) { if (rout->Output->Property == NULL) return FALSE; @@ -1443,7 +1522,7 @@ rhdRROutputGetProperty(xf86OutputPtr out, Atom property) RHD_OUTPUT_COHERENT, &val)) return FALSE; - err = RRChangeOutputProperty(out->randr_output, atomCoherent, + err = RRChangeOutputProperty(out->randr_output, atom_Coherent, XA_INTEGER, 32, PropModeReplace, 1, &val.Bool, FALSE, FALSE); } @@ -1703,7 +1782,7 @@ createXF86Output(ScrnInfoPtr pScrn, rhdRandrOutputPtr rro) xo->interlaceAllowed = TRUE; xo->doubleScanAllowed = TRUE; xo->subpixel_order = SubPixelUnknown; - xo->use_screen_monitor = FALSE; + xf86OutputUseScreenMonitor (xo, FALSE); return xo; } diff --git a/driver/xf86-video-radeonhd/src/rhd_randr.h b/driver/xf86-video-radeonhd/src/rhd_randr.h index 5bb2a2fad..817613e91 100644 --- a/driver/xf86-video-radeonhd/src/rhd_randr.h +++ b/driver/xf86-video-radeonhd/src/rhd_randr.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_regs.h b/driver/xf86-video-radeonhd/src/rhd_regs.h index da6799595..bf74dd3c7 100644 --- a/driver/xf86-video-radeonhd/src/rhd_regs.h +++ b/driver/xf86-video-radeonhd/src/rhd_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. @@ -189,6 +189,8 @@ enum { /* D1MODE */ D1MODE_DESKTOP_HEIGHT = 0x652C, + D1MODE_VLINE_START_END = 0x6538, + D1MODE_VLINE_STATUS = 0x653C, D1MODE_VIEWPORT_START = 0x6580, D1MODE_VIEWPORT_SIZE = 0x6584, D1MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6588, @@ -253,6 +255,8 @@ enum { /* D2MODE */ D2MODE_DESKTOP_HEIGHT = 0x6D2C, + D2MODE_VLINE_START_END = 0x6D38, + D2MODE_VLINE_STATUS = 0x6D3C, D2MODE_VIEWPORT_START = 0x6D80, D2MODE_VIEWPORT_SIZE = 0x6D84, D2MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6D88, diff --git a/driver/xf86-video-radeonhd/src/rhd_shadow.c b/driver/xf86-video-radeonhd/src/rhd_shadow.c index 0b2e7b9bb..ecb670950 100644 --- a/driver/xf86-video-radeonhd/src/rhd_shadow.c +++ b/driver/xf86-video-radeonhd/src/rhd_shadow.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_shadow.h b/driver/xf86-video-radeonhd/src/rhd_shadow.h index f5a3db1c1..318bf4c2e 100644 --- a/driver/xf86-video-radeonhd/src/rhd_shadow.h +++ b/driver/xf86-video-radeonhd/src/rhd_shadow.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Luc Verhaegen <libv@exsuse.de> * Copyright 2007 Matthias Hopf <mhopf@novell.com> * Copyright 2007 Egbert Eich <eich@novell.com> * Copyright 2007 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/src/rhd_tmds.c b/driver/xf86-video-radeonhd/src/rhd_tmds.c index fe439230c..77529a578 100644 --- a/driver/xf86-video-radeonhd/src/rhd_tmds.c +++ b/driver/xf86-video-radeonhd/src/rhd_tmds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007-2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007-2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007-2008 Egbert Eich <eich@novell.com> * Copyright 2007-2008 Advanced Micro Devices, Inc. @@ -56,6 +56,7 @@ struct rhdTMDSPrivate { Bool RunsDualLink; DisplayModePtr Mode; Bool Coherent; + Bool HdmiEnabled; int PowerState; struct rhdHdmi *Hdmi; @@ -133,9 +134,6 @@ TMDSAModeValid(struct rhdOutput *Output, DisplayModePtr Mode) { RHDFUNC(Output); - if (Mode->Flags & V_INTERLACE) - return MODE_NO_INTERLACE; - if (Mode->Clock < 25000) return MODE_CLOCK_LOW; @@ -242,18 +240,21 @@ TMDSAPropertyControl(struct rhdOutput *Output, RHDFUNC(Output); switch (Action) { case rhdPropertyCheck: - switch (Property) { - case RHD_OUTPUT_COHERENT: - return TRUE; - default: - return FALSE; - } + switch (Property) { + case RHD_OUTPUT_COHERENT: + case RHD_OUTPUT_HDMI: + return TRUE; + default: + return FALSE; + } case rhdPropertyGet: switch (Property) { case RHD_OUTPUT_COHERENT: val->Bool = Private->Coherent; return TRUE; - break; + case RHD_OUTPUT_HDMI: + val->Bool = Private->HdmiEnabled; + return TRUE; default: return FALSE; } @@ -262,6 +263,18 @@ TMDSAPropertyControl(struct rhdOutput *Output, switch (Property) { case RHD_OUTPUT_COHERENT: Private->Coherent = val->Bool; + break; + case RHD_OUTPUT_HDMI: + Private->HdmiEnabled = val->Bool; + break; + default: + return FALSE; + } + break; + case rhdPropertyCommit: + switch (Property) { + case RHD_OUTPUT_COHERENT: + case RHD_OUTPUT_HDMI: Output->Mode(Output, Private->Mode); Output->Power(Output, RHD_POWER_ON); break; @@ -391,10 +404,7 @@ TMDSAPower(struct rhdOutput *Output, int Power) } else RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0x0000001F, 0x00001F1F); - if(Output->Connector != NULL && RHDConnectorEnableHDMI(Output->Connector)) - RHDHdmiEnable(Private->Hdmi, TRUE); - else - RHDHdmiEnable(Private->Hdmi, FALSE); + RHDHdmiEnable(Private->Hdmi, Private->HdmiEnabled); Private->PowerState = RHD_POWER_ON; return; @@ -519,7 +529,6 @@ RHDTMDSAInit(RHDPtr rhdPtr) { struct rhdOutput *Output; struct rhdTMDSPrivate *Private; - int from; RHDFUNC(rhdPtr); @@ -540,21 +549,7 @@ RHDTMDSAInit(RHDPtr rhdPtr) Private = xnfcalloc(sizeof(struct rhdTMDSPrivate), 1); Private->RunsDualLink = FALSE; - from = X_CONFIG; - switch (RhdParseBooleanOption(&rhdPtr->coherent, Output->Name)) { - case RHD_OPTION_NOT_SET: - case RHD_OPTION_DEFAULT: - from = X_DEFAULT; - Private->Coherent = FALSE; - break; - case RHD_OPTION_ON: - Private->Coherent = TRUE; - break; - case RHD_OPTION_OFF: - Private->Coherent = FALSE; - break; - } - xf86DrvMsg(rhdPtr->scrnIndex,from,"Setting %s to %scoherent\n",Output->Name,Private->Coherent ? "" : "in"); + Private->Coherent = FALSE; Private->PowerState = RHD_POWER_UNKNOWN; Private->Hdmi = RHDHdmiInit(rhdPtr, Output); diff --git a/driver/xf86-video-radeonhd/src/rhd_vga.c b/driver/xf86-video-radeonhd/src/rhd_vga.c index f41dc9e2e..c32ead940 100644 --- a/driver/xf86-video-radeonhd/src/rhd_vga.c +++ b/driver/xf86-video-radeonhd/src/rhd_vga.c @@ -1,8 +1,7 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007 Matthias Hopf <mhopf@novell.com> - * Copyright 2007 Egbert Eich <eich@novell.com> - * Copyright 2007 Advanced Micro Devices, Inc. + * Copyright 2007-2008 Luc Verhaegen <libv@exsuse.de> + * Copyright 2007-2008 Matthias Hopf <mhopf@novell.com> + * Copyright 2007-2008 Egbert Eich <eich@novell.com> * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -37,6 +36,20 @@ #include "rhd_regs.h" #include "rhd_mc.h" +struct rhdVGA { + Bool Stored; + + CARD32 FBOffset; + CARD8 *FB; + int FBSize; /* 256kB */ + + CARD32 Render_Control; + CARD32 Mode_Control; + CARD32 HDP_Control; + CARD32 D1_Control; + CARD32 D2_Control; +}; + /* * */ @@ -63,65 +76,72 @@ RHDVGAInit(RHDPtr rhdPtr) } /* - * + * Thoroughly check whether our VGA FB is accessible. + */ +static CARD32 +rhdVGAFBOffsetGet(RHDPtr rhdPtr) +{ + CARD32 FBSize, VGAFBOffset, VGAFBSize = 256 * 1024; + CARD64 FBAddress = RHDMCGetFBLocation(rhdPtr, &FBSize); + CARD64 VGAFBAddress = RHDRegRead(rhdPtr, VGA_MEMORY_BASE_ADDRESS); + + if (VGAFBAddress < FBAddress) + return 0xFFFFFFFF; + + if ((VGAFBAddress + VGAFBSize) > (FBAddress + FBSize)) + return 0xFFFFFFFF; + + VGAFBOffset = VGAFBAddress - FBAddress; /* < FBSize, so 32bit */ + + if ((VGAFBOffset + VGAFBSize) >= rhdPtr->FbMapSize) + return 0xFFFFFFFF; + + return VGAFBOffset; +} + +/* + * This is (usually) ok, as VGASave is called after the memory has been mapped, + * but before the MC is set up. So the use of RHDMCGetFBLocation is correct in + * rhdVGAFBOffsetGet. */ static void rhdVGASaveFB(RHDPtr rhdPtr) { struct rhdVGA *VGA = rhdPtr->VGA; - CARD32 FBLocation; - CARD32 FBSize; - CARD32 VGAFBOffset; + + ASSERT(rhdPtr->FbBase); RHDFUNC(rhdPtr); - if (!VGA) - return; /* We don't need to warn , this is intended use */ + VGA->FBOffset = rhdVGAFBOffsetGet(rhdPtr); + + if (VGA->FBOffset == 0xFFFFFFFF) { + xf86DrvMsg(rhdPtr->scrnIndex, X_WARNING, "%s: Unable to access the VGA " + "framebuffer (0x%08X)\n", __func__, + (unsigned int) RHDRegRead(rhdPtr, VGA_MEMORY_BASE_ADDRESS)); + if (VGA->FB) + xfree(VGA->FB); + VGA->FB = NULL; + VGA->FBSize = 0; + return; + } - /* Store our VGA FB */ - FBLocation = RHDGetFBLocation(rhdPtr, &FBSize); - VGA->FBBase = - RHDRegRead(rhdPtr, VGA_MEMORY_BASE_ADDRESS); - VGAFBOffset = VGA->FBBase - FBLocation; - RHDDebug(rhdPtr->scrnIndex, "%s: VGAFBOffset: 0x%8.8x FBLocation: 0x%8.8x FBSize: 0x%8.8x\n", - __func__, VGAFBOffset, FBLocation, FBSize); - - /* Could be that the VGA internal address no longer is pointing to what - we know as our FB memory, in which case we should give up cleanly. */ - if (VGAFBOffset < (unsigned) (rhdPtr->FbMapSize)) { - - VGA->FBSize = 256 * 1024; - - if ((VGAFBOffset + VGA->FBSize) > (unsigned) (rhdPtr->FbMapSize)) { - /* clamp to the size of the aperture. Otherwise we would have to - remap here */ - VGA->FBSize = (unsigned) (rhdPtr->FbMapSize) - VGAFBOffset; - RHDDebug(rhdPtr->scrnIndex, - "%s: saving %i bytes of VGA memory\n",__func__, - VGA->FBSize); - } + VGA->FBSize = 256 * 1024; + RHDDebug(rhdPtr->scrnIndex, "%s: VGA FB Offset 0x%08X [0x%08X]\n", + __func__, VGA->FBOffset, VGA->FBSize); + + if (!VGA->FB) VGA->FB = xcalloc(VGA->FBSize, 1); - if (VGA->FB) { - RHDDebug(rhdPtr->scrnIndex,"%s: memcpy(%p, %p, 0x%x)\n", - __func__,VGA->FB, ((CARD8 *) rhdPtr->FbBase) - + VGAFBOffset, VGA->FBSize); - memcpy(VGA->FB, ((CARD8 *) rhdPtr->FbBase) + VGAFBOffset, - VGA->FBSize); - } else { - xf86DrvMsg(rhdPtr->scrnIndex, X_WARNING, "%s: Failed to allocate" - " space for storing the VGA framebuffer.\n", __func__); - VGA->FBSize = 0; - VGA->FB = NULL; - } - } else { - xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, "%s: VGA FB Offset (0x%08X) is " - "out of range of the Cards Internal FB Address (0x%08X)\n", - __func__, (int) RHDRegRead(rhdPtr, VGA_MEMORY_BASE_ADDRESS), - rhdPtr->FbIntAddress); - VGA->FBBase = 0xFFFFFFFF; + + if (VGA->FB) + memcpy(VGA->FB, ((CARD8 *) rhdPtr->FbBase) + VGA->FBOffset, + VGA->FBSize); + else { + xf86DrvMsg(rhdPtr->scrnIndex, X_WARNING, "%s: Failed to allocate" + " space for storing the VGA framebuffer.\n", __func__); + VGA->FBOffset = 0xFFFFFFFF; VGA->FBSize = 0; - VGA->FB = NULL; } } @@ -167,18 +187,16 @@ RHDVGARestore(RHDPtr rhdPtr) return; } - if (VGA->FB) { - CARD32 VGAFBOffset = VGA->FBBase - RHDGetFBLocation(rhdPtr, NULL); - - memcpy(((CARD8 *) rhdPtr->FbBase) + VGAFBOffset, - VGA->FB, VGA->FBSize); - } + if (VGA->FB) + memcpy(((CARD8 *) rhdPtr->FbBase) + VGA->FBOffset, VGA->FB, + VGA->FBSize); RHDRegWrite(rhdPtr, VGA_RENDER_CONTROL, VGA->Render_Control); RHDRegWrite(rhdPtr, VGA_MODE_CONTROL, VGA->Mode_Control); RHDRegWrite(rhdPtr, VGA_HDP_CONTROL, VGA->HDP_Control); RHDRegWrite(rhdPtr, D1VGA_CONTROL, VGA->D1_Control); RHDRegWrite(rhdPtr, D2VGA_CONTROL, VGA->D2_Control); + RHD_UNSETDEBUGFLAG(rhdPtr, VGA_SETUP); } /* @@ -194,6 +212,7 @@ RHDVGADisable(RHDPtr rhdPtr) RHDRegMask(rhdPtr, VGA_HDP_CONTROL, 0x00010010, 0x00010010); RHDRegMask(rhdPtr, D1VGA_CONTROL, 0, D1VGA_MODE_ENABLE); RHDRegMask(rhdPtr, D2VGA_CONTROL, 0, D2VGA_MODE_ENABLE); + RHD_SETDEBUGFLAG(rhdPtr, VGA_SETUP); } /* diff --git a/driver/xf86-video-radeonhd/src/rhd_vga.h b/driver/xf86-video-radeonhd/src/rhd_vga.h index 774537216..3b7bff5cc 100644 --- a/driver/xf86-video-radeonhd/src/rhd_vga.h +++ b/driver/xf86-video-radeonhd/src/rhd_vga.h @@ -1,8 +1,7 @@ /* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007 Matthias Hopf <mhopf@novell.com> - * Copyright 2007 Egbert Eich <eich@novell.com> - * Copyright 2007 Advanced Micro Devices, Inc. + * Copyright 2007-2008 Luc Verhaegen <libv@exsuse.de> + * Copyright 2007-2008 Matthias Hopf <mhopf@novell.com> + * Copyright 2007-2008 Egbert Eich <eich@novell.com> * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -26,20 +25,6 @@ #ifndef _RHD_VGA_H #define _RHD_VGA_H -struct rhdVGA { - Bool Stored; - - CARD32 FBBase; - CARD8 *FB; - int FBSize; /* most cases, 256kB */ - - CARD32 Render_Control; - CARD32 Mode_Control; - CARD32 HDP_Control; - CARD32 D1_Control; - CARD32 D2_Control; -}; - void RHDVGAInit(RHDPtr rhdPtr); void RHDVGASave(RHDPtr rhdPtr); void RHDVGARestore(RHDPtr rhdPtr); diff --git a/driver/xf86-video-radeonhd/src/rhd_video.c b/driver/xf86-video-radeonhd/src/rhd_video.c index 64cd950a6..25acc4700 100644 --- a/driver/xf86-video-radeonhd/src/rhd_video.c +++ b/driver/xf86-video-radeonhd/src/rhd_video.c @@ -1,8 +1,8 @@ /* - * Copyright 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2008 Egbert Eich <eich@novell.com> - * Copyright 2008 Alex Deucher + * Copyright 2008 Alex Deucher <alexander.deucher@amd.com> * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -246,6 +246,11 @@ rhdQueryImageAttributes(ScrnInfoPtr pScrn, int id, CARD16 *w, CARD16 *h, *w = 2048; if (*h > 2048) *h = 2048; + } else if (rhdPtr->ChipSet >= RHD_R600) { + if (*w > 8192) + *w = 8192; + if (*h > 8192) + *h = 8192; } else { if (*w > 4096) *w = 4096; @@ -511,6 +516,130 @@ R5xxXvCopyPlanar(RHDPtr rhdPtr, CARD8 *src1, CARD8 *src2, CARD8 *src3, #endif } +static void +R600CopyPlanarHW(ScrnInfoPtr pScrn, + unsigned char *y_src, unsigned char *u_src, unsigned char *v_src, + uint32_t dst_mc_addr, + int srcPitch, int srcPitch2, int dstPitch, + int w, int h) +{ + int dstPitch2 = dstPitch >> 1; + int h2 = h >> 1; + int w2 = w >> 1; + int v_offset, u_offset; + v_offset = dstPitch * h; + v_offset = (v_offset + 255) & ~255; + u_offset = v_offset + (dstPitch2 * h2); + u_offset = (u_offset + 255) & ~255; + + /* Y */ + R600CopyToVRAM(pScrn, + (char *)y_src, srcPitch, + dstPitch, dst_mc_addr, h, 8, + 0, 0, w, h); + + /* V */ + R600CopyToVRAM(pScrn, + (char *)v_src, srcPitch2, + dstPitch2, dst_mc_addr + v_offset, h2, 8, + 0, 0, w2, h2); + + /* U */ + R600CopyToVRAM(pScrn, + (char *)u_src, srcPitch2, + dstPitch2, dst_mc_addr + u_offset, h2, 8, + 0, 0, w2, h2); +} + +static void +R600CopyPackedHW(ScrnInfoPtr pScrn, + unsigned char *src, uint32_t dst_mc_addr, + int srcPitch, int dstPitch, + int w, int h) +{ + /* YUV */ + R600CopyToVRAM(pScrn, + (char *)src, srcPitch, + dstPitch >> 2, dst_mc_addr, h, 32, + 0, 0, w >> 1, h); +} + +static void +R600CopyPlanarSW(ScrnInfoPtr pScrn, + unsigned char *y_src, unsigned char *u_src, unsigned char *v_src, + unsigned char *dst, + int srcPitch, int srcPitch2, int dstPitch, + int w, int h) +{ + int i; + int dstPitch2 = dstPitch >> 1; + int h2 = h >> 1; + + /* Y */ + if (srcPitch == dstPitch) { + memcpy(dst, y_src, srcPitch * h); + dst += (dstPitch * h); + } else { + for (i = 0; i < h; i++) { + memcpy(dst, y_src, srcPitch); + y_src += srcPitch; + dst += dstPitch; + } + } + + /* tex base need 256B alignment */ + if (h & 1) + dst += dstPitch; + + /* V */ + if (srcPitch2 == dstPitch2) { + memcpy(dst, v_src, srcPitch2 * h2); + dst += (dstPitch2 * h2); + } else { + for (i = 0; i < h2; i++) { + memcpy(dst, v_src, srcPitch2); + v_src += srcPitch2; + dst += dstPitch2; + } + } + + /* tex base need 256B alignment */ + if (h2 & 1) + dst += dstPitch2; + + /* U */ + if (srcPitch2 == dstPitch2) { + memcpy(dst, u_src, srcPitch2 * h2); + dst += (dstPitch2 * h2); + } else { + for (i = 0; i < h2; i++) { + memcpy(dst, u_src, srcPitch2); + u_src += srcPitch2; + dst += dstPitch2; + } + } +} + +static void +R600CopyPackedSW(ScrnInfoPtr pScrn, + unsigned char *src, unsigned char *dst, + int srcPitch, int dstPitch, + int w, int h) +{ + int i; + + if (srcPitch == dstPitch) { + memcpy(dst, src, srcPitch * h); + dst += (dstPitch * h); + } else { + for (i = 0; i < h; i++) { + memcpy(dst, src, srcPitch); + src += srcPitch; + dst += dstPitch; + } + } +} + /* * */ @@ -564,11 +693,10 @@ rhdPutImageTextured(ScrnInfoPtr pScrn, pPriv->pDraw = pDraw; - /* The upload blit only supports multiples of 64 bytes */ - if (rhdPtr->CS->Type == RHD_CS_CPDMA) - pPriv->BufferPitch = ALIGN(2 * width, 64); + if (rhdPtr->ChipSet >= RHD_R600) + pPriv->BufferPitch = ALIGN(2 * width, 256); else - pPriv->BufferPitch = ALIGN(2 * width, 16); + pPriv->BufferPitch = ALIGN(2 * width, 64); /* * Now, find out whether we have enough memory available. @@ -594,10 +722,16 @@ rhdPutImageTextured(ScrnInfoPtr pScrn, return BadAlloc; } + if (rhdPtr->ChipSet >= RHD_R600) + pPriv->BufferOffset = (pPriv->BufferOffset + 255) & ~255; + /* * Now copy the buffer to the framebuffer, and convert to planar when necessary. */ - FBBuf = (CARD8 *)rhdPtr->FbBase + pPriv->BufferOffset; + if (rhdPtr->ChipSet >= RHD_R600) + FBBuf = (CARD8 *)rhdPtr->FbBase + rhdPtr->FbScanoutStart + pPriv->BufferOffset; + else + FBBuf = (CARD8 *)rhdPtr->FbBase + pPriv->BufferOffset; switch(id) { case FOURCC_YV12: @@ -609,7 +743,19 @@ rhdPutImageTextured(ScrnInfoPtr pScrn, int s3offset = s2offset + srcPitch2 * (height >> 1); if (id == FOURCC_YV12) { - if (rhdPtr->CS->Type == RHD_CS_CPDMA) + if (rhdPtr->ChipSet >= RHD_R600) { + pPriv->BufferPitch = ALIGN(width, 256); + if (rhdPtr->cardType != RHD_CARD_AGP) + R600CopyPlanarHW(pScrn, buf, buf + s3offset, buf + s2offset, + pPriv->BufferOffset + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart, + srcPitch, srcPitch2, pPriv->BufferPitch, + width, height); + else + R600CopyPlanarSW(pScrn, buf, buf + s3offset, buf + s2offset, + FBBuf, + srcPitch, srcPitch2, pPriv->BufferPitch, + width, height); + } else if (rhdPtr->CS->Type == RHD_CS_CPDMA) R5xxXvCopyPlanarDMA(rhdPtr, buf, buf + s2offset, buf + s3offset, FBBuf, srcPitch, srcPitch2, pPriv->BufferPitch, @@ -620,7 +766,18 @@ rhdPutImageTextured(ScrnInfoPtr pScrn, srcPitch2, pPriv->BufferPitch, height, width); } else { - if (rhdPtr->CS->Type == RHD_CS_CPDMA) + if (rhdPtr->ChipSet >= RHD_R600) { + if (rhdPtr->cardType != RHD_CARD_AGP) + R600CopyPlanarHW(pScrn, buf, buf + s2offset, buf + s3offset, + pPriv->BufferOffset + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart, + srcPitch, srcPitch2, pPriv->BufferPitch, + width, height); + else + R600CopyPlanarSW(pScrn, buf, buf + s2offset, buf + s3offset, + FBBuf, + srcPitch, srcPitch2, pPriv->BufferPitch, + width, height); + } else if (rhdPtr->CS->Type == RHD_CS_CPDMA) R5xxXvCopyPlanarDMA(rhdPtr, buf, buf + s3offset, buf + s2offset, FBBuf, srcPitch, srcPitch2, pPriv->BufferPitch, @@ -636,7 +793,17 @@ rhdPutImageTextured(ScrnInfoPtr pScrn, case FOURCC_UYVY: case FOURCC_YUY2: default: - if (rhdPtr->CS->Type == RHD_CS_CPDMA) + if (rhdPtr->ChipSet >= RHD_R600) { + pPriv->BufferPitch = ALIGN(2 * width, 256); + if (rhdPtr->cardType != RHD_CARD_AGP) + R600CopyPackedHW(pScrn, buf, pPriv->BufferOffset + rhdPtr->FbIntAddress + rhdPtr->FbScanoutStart, + 2 * width, pPriv->BufferPitch, + width, height); + else + R600CopyPackedSW(pScrn, buf, FBBuf, + 2 * width, pPriv->BufferPitch, + width, height); + } else if (rhdPtr->CS->Type == RHD_CS_CPDMA) R5xxXvCopyPackedDMA(rhdPtr, buf, FBBuf, 2 * width, pPriv->BufferPitch, height); else @@ -664,7 +831,10 @@ rhdPutImageTextured(ScrnInfoPtr pScrn, pPriv->w = width; pPriv->h = height; - RHDRADEONDisplayTexturedVideo(pScrn, pPriv); + if (rhdPtr->ChipSet >= RHD_R600) + R600DisplayTexturedVideo(pScrn, pPriv); + else + RHDRADEONDisplayTexturedVideo(pScrn, pPriv); return Success; } @@ -683,6 +853,11 @@ static XF86VideoEncodingRec DummyEncodingR500[1] = { 0, "XV_IMAGE", 4096, 4096, {1, 1}} }; +static XF86VideoEncodingRec DummyEncodingR600[1] = +{ + { 0, "XV_IMAGE", 8192, 8192, {1, 1}} +}; + #define NUM_FORMATS 3 static XF86VideoFormatRec Formats[NUM_FORMATS] = @@ -726,6 +901,8 @@ rhdSetupImageTexturedVideo(ScreenPtr pScreen) if ((rhdPtr->ChipSet == RHD_RS690) || (rhdPtr->ChipSet == RHD_RS600) || (rhdPtr->ChipSet == RHD_RS740)) adapt->pEncodings = DummyEncodingRS600; + else if (rhdPtr->ChipSet >= RHD_R600) + adapt->pEncodings = DummyEncodingR600; else adapt->pEncodings = DummyEncodingR500; @@ -787,25 +964,23 @@ RHDInitVideo(ScreenPtr pScreen) memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr)); adaptors = newAdaptors; - if (rhdPtr->ChipSet < RHD_R600) { - if (rhdPtr->TwoDPrivate && - ((rhdPtr->CS->Type == RHD_CS_CP) || - (rhdPtr->CS->Type == RHD_CS_CPDMA))) { + if (rhdPtr->TwoDPrivate && rhdPtr->CS && + ((rhdPtr->CS->Type == RHD_CS_CP) || + (rhdPtr->CS->Type == RHD_CS_CPDMA))) { - texturedAdaptor = rhdSetupImageTexturedVideo(pScreen); + texturedAdaptor = rhdSetupImageTexturedVideo(pScreen); - adaptors[num_adaptors++] = texturedAdaptor; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Xv: Textured Video initialised.\n"); + adaptors[num_adaptors++] = texturedAdaptor; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Xv: Textured Video initialised.\n"); - /* EXA could've initialised this already */ + /* EXA could've initialised this already */ + if (rhdPtr->ChipSet < RHD_R600) { if (!rhdPtr->ThreeDPrivate) R5xx3DInit(pScrn); - } else - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Xv: No Textured Video " - "possible without the Command Processor.\n"); + } } else - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Xv: No Textured Video possible for %s.\n", pScrn->chipset); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Xv: No Textured Video " + "possible without the Command Processor.\n"); if (num_adaptors) xf86XVScreenInit(pScreen, adaptors, num_adaptors); diff --git a/driver/xf86-video-radeonhd/src/rhd_video.h b/driver/xf86-video-radeonhd/src/rhd_video.h index 0c87ae979..aadebc06c 100644 --- a/driver/xf86-video-radeonhd/src/rhd_video.h +++ b/driver/xf86-video-radeonhd/src/rhd_video.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2008 Egbert Eich <eich@novell.com> * @@ -26,6 +26,10 @@ #ifndef _RHD_VIDEO_H #define _RHD_VIDEO_H +/* seriously ?! @#$%% */ +# define uint32_t CARD32 +# define uint64_t CARD64 + /* Xvideo port struct */ struct RHDPortPriv { DrawablePtr pDraw; @@ -50,5 +54,11 @@ struct RHDPortPriv { extern void RHDRADEONDisplayTexturedVideo(ScrnInfoPtr pScrn, struct RHDPortPriv *pPriv); extern void RHDInitVideo(ScreenPtr pScreen); +extern void R600DisplayTexturedVideo(ScrnInfoPtr pScrn, struct RHDPortPriv *pPriv); +extern Bool +R600CopyToVRAM(ScrnInfoPtr pScrn, + char *src, int src_pitch, + uint32_t dst_pitch, uint32_t dst_mc_addr, uint32_t dst_height, int bpp, + int x, int y, int w, int h); #endif /* _RHD_VIDEO_H */ diff --git a/driver/xf86-video-radeonhd/utils/conntest/git_version.h b/driver/xf86-video-radeonhd/utils/conntest/git_version.h index 84c71967c..03087ff3e 100644 --- a/driver/xf86-video-radeonhd/utils/conntest/git_version.h +++ b/driver/xf86-video-radeonhd/utils/conntest/git_version.h @@ -14,13 +14,13 @@ /* git utilities found */ #undef GIT_NOT_FOUND -#define GIT_VERSION "git version 1.5.6" +#define GIT_VERSION "git version 1.6.0.2" /* git repo found */ #define GIT_REPO 1 /* Git SHA ID of last commit */ -#define GIT_SHAID "4e897263" +#define GIT_SHAID "cb54f48b" /* Branch this tree is on */ #define GIT_BRANCH "master" diff --git a/driver/xf86-video-radeonhd/utils/conntest/rhd_conntest.c b/driver/xf86-video-radeonhd/utils/conntest/rhd_conntest.c index 07a13357d..9e9a595ce 100644 --- a/driver/xf86-video-radeonhd/utils/conntest/rhd_conntest.c +++ b/driver/xf86-video-radeonhd/utils/conntest/rhd_conntest.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. diff --git a/driver/xf86-video-radeonhd/utils/conntest/rhd_dump.c b/driver/xf86-video-radeonhd/utils/conntest/rhd_dump.c index 54c3e2395..7a3902660 100644 --- a/driver/xf86-video-radeonhd/utils/conntest/rhd_dump.c +++ b/driver/xf86-video-radeonhd/utils/conntest/rhd_dump.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> * Copyright 2007, 2008 Egbert Eich <eich@novell.com> * Copyright 2007, 2008 Advanced Micro Devices, Inc. @@ -363,7 +363,7 @@ print_help(const char* progname, const char* message, const char* msgarg) { if (message != NULL) fprintf(stderr, "%s %s\n", message, msgarg); - fprintf(stderr, "Usage: %s [-r start,end | -w addr val] PCI-tag\n" + fprintf(stderr, "Usage: %s [-r start,end | -w addr val | -l {0|1}] PCI-tag\n" " PCI-tag: bus:dev.func\n\n", progname); } @@ -389,7 +389,8 @@ main(int argc, char *argv[]) enum { NONE, READ, - WRITE + WRITE, + LUT } action = READ; /* default */ int i; @@ -451,6 +452,21 @@ main(int argc, char *argv[]) i--; ret = 0; } + } else if (!strncmp("-l", argv[i], 3)) { + action = LUT; + + if (++i < argc) + ret = sscanf(argv[i], "%d", &addr); + else { + i--; + ret = 0; + } + + if (addr > 1) ret = 0; + if (ret != 1) { + print_help(argv[0], "Invalid LUT id:", argv[i]); + return 1; + } } else if (!strncmp("-",argv[i],1)) { print_help(argv[0], "Unknown option", argv[i]); return 1; @@ -524,6 +540,22 @@ main(int argc, char *argv[]) val = RegRead(io, addr); printf("New value: 0x%4.4X: 0x%8.8X\n",addr, val); } + else if (action == LUT) { + RegWrite(io, 0x6480, addr); /* lower half of LUT */ + RegWrite(io, 0x6484, 0); /* table mode */ + RegWrite(io, 0x6488, 0); /* start at 0 */ + + CARD32 r, g, b; + + printf("Printing LUT %d\n", addr); + printf(" R G B\n"); + for (j = 0; j < 256; j++) { + r = RegRead(io, 0x648C) >> 6; + g = RegRead(io, 0x648C) >> 6; + b = RegRead(io, 0x648C) >> 6; + printf("%02X: %3X %3X %3X\n", j, r, g, b); + } + } return 0; } |