Import Mesa 21.1.5

22 files changed, 176 insertions, 254 deletions

diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_batch.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_batch.c
index 1d7da7abe..4db72dc4e 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_batch.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_batch.c
@@ -58,14 +58,6 @@ brw_batch_reset(struct brw_context *brw);
 static void
 brw_new_batch(struct brw_context *brw);
 
-static unsigned
-num_fences(struct brw_batch *batch)
-{
-   return util_dynarray_num_elements(&batch->exec_fences,
-                                     struct drm_i915_gem_exec_fence);
-}
-
-
 static void
 dump_validation_list(struct brw_batch *batch)
 {
@@ -136,9 +128,9 @@ brw_batch_init(struct brw_context *brw)
 {
    struct brw_screen *screen = brw->screen;
    struct brw_batch *batch = &brw->batch;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct gen_device_info *devinfo = &screen->devinfo;
 
-   if (INTEL_DEBUG(DEBUG_BATCH)) {
+   if (INTEL_DEBUG & DEBUG_BATCH) {
       /* The shadow doesn't get relocs written so state decode fails. */
       batch->use_shadow_copy = false;
    } else
@@ -155,15 +147,14 @@ brw_batch_init(struct brw_context *brw)
       malloc(batch->exec_array_size * sizeof(batch->exec_bos[0]));
    batch->validation_list =
       malloc(batch->exec_array_size * sizeof(batch->validation_list[0]));
-   batch->contains_fence_signal = false;
 
-   if (INTEL_DEBUG(DEBUG_BATCH)) {
+   if (INTEL_DEBUG & DEBUG_BATCH) {
       batch->state_batch_sizes =
          _mesa_hash_table_u64_create(NULL);
 
       const unsigned decode_flags =
          INTEL_BATCH_DECODE_FULL |
-         (INTEL_DEBUG(DEBUG_COLOR) ? INTEL_BATCH_DECODE_IN_COLOR : 0) |
+         ((INTEL_DEBUG & DEBUG_COLOR) ? INTEL_BATCH_DECODE_IN_COLOR : 0) |
          INTEL_BATCH_DECODE_OFFSETS |
          INTEL_BATCH_DECODE_FLOATS;
 
@@ -293,9 +284,6 @@ brw_batch_reset(struct brw_context *brw)
    struct brw_bo *identifier_bo = brw->workaround_bo;
    if (identifier_bo)
       add_exec_bo(batch, identifier_bo);
-
-   if (batch->contains_fence_signal)
-      batch->contains_fence_signal = false;
 }
 
 static void
@@ -600,7 +588,7 @@ brw_new_batch(struct brw_context *brw)
     * while, because many programs won't cleanly destroy our context, so the
     * end-of-run printout may not happen.
     */
-   if (INTEL_DEBUG(DEBUG_SHADER_TIME))
+   if (INTEL_DEBUG & DEBUG_SHADER_TIME)
       brw_collect_and_report_shader_time(brw);
 
    brw_batch_maybe_noop(brw);
@@ -616,7 +604,7 @@ brw_new_batch(struct brw_context *brw)
 static void
 brw_finish_batch(struct brw_context *brw)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    brw->batch.no_wrap = true;
 
@@ -740,14 +728,6 @@ execbuffer(int fd,
       execbuf.flags |= I915_EXEC_FENCE_OUT;
    }
 
-   if (num_fences(batch)) {
-      execbuf.flags |= I915_EXEC_FENCE_ARRAY;
-      execbuf.num_cliprects = num_fences(batch);
-      execbuf.cliprects_ptr =
-         (uintptr_t)util_dynarray_begin(&batch->exec_fences);
-   }
-
-
    int ret = drmIoctl(fd, cmd, &execbuf);
    if (ret != 0)
       ret = -errno;
@@ -791,7 +771,7 @@ submit_batch(struct brw_context *brw, int in_fence_fd, int *out_fence_fd)
    brw_bo_unmap(batch->batch.bo);
    brw_bo_unmap(batch->state.bo);
 
-   if (!brw->screen->devinfo.no_hw) {
+   if (!brw->screen->no_hw) {
       /* The requirement for using I915_EXEC_NO_RELOC are:
        *
        *   The addresses written in the objects must match the corresponding
@@ -850,7 +830,7 @@ submit_batch(struct brw_context *brw, int in_fence_fd, int *out_fence_fd)
       throttle(brw);
    }
 
-   if (INTEL_DEBUG(DEBUG_BATCH)) {
+   if (INTEL_DEBUG & DEBUG_BATCH) {
       intel_print_batch(&batch->decoder, batch->batch.map,
                         4 * USED_BATCH(*batch),
                         batch->batch.bo->gtt_offset, false);
@@ -862,7 +842,7 @@ submit_batch(struct brw_context *brw, int in_fence_fd, int *out_fence_fd)
    if (ret != 0) {
       fprintf(stderr, "i965: Failed to submit batchbuffer: %s\n",
               strerror(-ret));
-      abort();
+      exit(1);
    }
 
    return ret;
@@ -882,7 +862,7 @@ _brw_batch_flush_fence(struct brw_context *brw,
 {
    int ret;
 
-   if (USED_BATCH(brw->batch) == 0 && !brw->batch.contains_fence_signal)
+   if (USED_BATCH(brw->batch) == 0)
       return 0;
 
    /* Check that we didn't just wrap our batchbuffer at a bad time. */
@@ -899,7 +879,7 @@ _brw_batch_flush_fence(struct brw_context *brw,
       brw_bo_reference(brw->throttle_batch[0]);
    }
 
-   if (INTEL_DEBUG(DEBUG_BATCH | DEBUG_SUBMIT)) {
+   if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) {
       int bytes_for_commands = 4 * USED_BATCH(brw->batch);
       int bytes_for_state = brw->batch.state_used;
       fprintf(stderr, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
@@ -917,7 +897,7 @@ _brw_batch_flush_fence(struct brw_context *brw,
 
    ret = submit_batch(brw, in_fence_fd, out_fence_fd);
 
-   if (INTEL_DEBUG(DEBUG_SYNC)) {
+   if (INTEL_DEBUG & DEBUG_SYNC) {
       fprintf(stderr, "waiting for idle\n");
       brw_bo_wait_rendering(brw->batch.batch.bo);
    }
@@ -1087,7 +1067,7 @@ brw_state_batch(struct brw_context *brw,
       assert(offset + size < batch->state.bo->size);
    }
 
-   if (INTEL_DEBUG(DEBUG_BATCH)) {
+   if (INTEL_DEBUG & DEBUG_BATCH) {
       _mesa_hash_table_u64_insert(batch->state_batch_sizes,
                                   offset, (void *) (uintptr_t) size);
    }
@@ -1115,7 +1095,7 @@ load_sized_register_mem(struct brw_context *brw,
                         uint32_t offset,
                         int size)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    int i;
 
    /* MI_LOAD_REGISTER_MEM only exists on Gfx7+. */
@@ -1165,7 +1145,7 @@ void
 brw_store_register_mem32(struct brw_context *brw,
                          struct brw_bo *bo, uint32_t reg, uint32_t offset)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    assert(devinfo->ver >= 6);
 
@@ -1191,7 +1171,7 @@ void
 brw_store_register_mem64(struct brw_context *brw,
                          struct brw_bo *bo, uint32_t reg, uint32_t offset)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    assert(devinfo->ver >= 6);
 
@@ -1257,7 +1237,7 @@ brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm)
 void
 brw_load_register_reg(struct brw_context *brw, uint32_t dest, uint32_t src)
 {
-   assert(brw->screen->devinfo.verx10 >= 75);
+   assert(brw->screen->devinfo.ver >= 8 || brw->screen->devinfo.is_haswell);
 
    BEGIN_BATCH(3);
    OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
@@ -1272,7 +1252,7 @@ brw_load_register_reg(struct brw_context *brw, uint32_t dest, uint32_t src)
 void
 brw_load_register_reg64(struct brw_context *brw, uint32_t dest, uint32_t src)
 {
-   assert(brw->screen->devinfo.verx10 >= 75);
+   assert(brw->screen->devinfo.ver >= 8 || brw->screen->devinfo.is_haswell);
 
    BEGIN_BATCH(6);
    OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
@@ -1291,7 +1271,7 @@ void
 brw_store_data_imm32(struct brw_context *brw, struct brw_bo *bo,
                      uint32_t offset, uint32_t imm)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    assert(devinfo->ver >= 6);
 
@@ -1314,7 +1294,7 @@ void
 brw_store_data_imm64(struct brw_context *brw, struct brw_bo *bo,
                      uint32_t offset, uint64_t imm)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    assert(devinfo->ver >= 6);
 
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_blit.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_blit.c
index 95f00e9b1..167b70458 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_blit.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_blit.c
@@ -83,7 +83,7 @@ set_blitter_tiling(struct brw_context *brw,
                    bool dst_y_tiled, bool src_y_tiled,
                    uint32_t *__map)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const unsigned n_dwords = devinfo->ver >= 8 ? 5 : 4;
    assert(devinfo->ver >= 6);
 
@@ -164,23 +164,15 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
                              struct brw_mipmap_tree *mt,
                              uint32_t total_x_offset_el,
                              uint32_t total_y_offset_el,
-                             uint64_t *tile_offset_B,
+                             uint32_t *base_address_offset,
                              uint32_t *x_offset_el,
                              uint32_t *y_offset_el)
 {
-   ASSERTED uint32_t z_offset_el, array_offset;
-   isl_tiling_get_intratile_offset_el(mt->surf.tiling, mt->surf.dim,
-                                      mt->surf.msaa_layout,
-                                      mt->cpp * 8, mt->surf.samples,
-                                      mt->surf.row_pitch_B,
-                                      mt->surf.array_pitch_el_rows,
-                                      total_x_offset_el, total_y_offset_el, 0, 0,
-                                      tile_offset_B,
-                                      x_offset_el, y_offset_el,
-                                      &z_offset_el, &array_offset);
-   assert(z_offset_el == 0);
-   assert(array_offset == 0);
-
+   isl_tiling_get_intratile_offset_el(mt->surf.tiling,
+                                      mt->cpp * 8, mt->surf.row_pitch_B,
+                                      total_x_offset_el, total_y_offset_el,
+                                      base_address_offset,
+                                      x_offset_el, y_offset_el);
    if (mt->surf.tiling == ISL_TILING_LINEAR) {
       /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
        *
@@ -192,12 +184,12 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
        * The offsets we get from ISL in the tiled case are already aligned.
        * In the linear case, we need to do some of our own aligning.
        */
-      uint32_t delta = *tile_offset_B & 63;
+      uint32_t delta = *base_address_offset & 63;
       assert(delta % mt->cpp == 0);
-      *tile_offset_B -= delta;
+      *base_address_offset -= delta;
       *x_offset_el += delta / mt->cpp;
    } else {
-      assert(*tile_offset_B % 4096 == 0);
+      assert(*base_address_offset % 4096 == 0);
    }
 }
 
@@ -205,7 +197,7 @@ static bool
 alignment_valid(struct brw_context *brw, unsigned offset,
                 enum isl_tiling tiling)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    /* Tiled buffers must be page-aligned (4K). */
    if (tiling != ISL_TILING_LINEAR)
@@ -264,7 +256,7 @@ emit_copy_blit(struct brw_context *brw,
                GLshort w, GLshort h,
                enum gl_logicop_mode logic_op)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    GLuint CMD, BR13;
    int dst_y2 = dst_y + h;
    int dst_x2 = dst_x + w;
@@ -421,14 +413,12 @@ emit_miptree_blit(struct brw_context *brw,
          const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
          const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
 
-         uint64_t src_offset;
-         uint32_t src_tile_x, src_tile_y;
+         uint32_t src_offset, src_tile_x, src_tile_y;
          get_blit_intratile_offset_el(brw, src_mt,
                                       src_x + chunk_x, src_y + chunk_y,
                                       &src_offset, &src_tile_x, &src_tile_y);
 
-         uint64_t dst_offset;
-         uint32_t dst_tile_x, dst_tile_y;
+         uint32_t dst_offset, dst_tile_x, dst_tile_y;
          get_blit_intratile_offset_el(brw, dst_mt,
                                       dst_x + chunk_x, dst_y + chunk_y,
                                       &dst_offset, &dst_tile_x, &dst_tile_y);
@@ -638,7 +628,7 @@ brw_emit_immediate_color_expand_blit(struct brw_context *brw,
                                      GLshort w, GLshort h,
                                      enum gl_logicop_mode logic_op)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    int dwords = ALIGN(src_size, 8) / 4;
    uint32_t opcode, br13, blit_cmd;
 
@@ -719,7 +709,7 @@ brw_miptree_set_alpha_to_one(struct brw_context *brw,
                              struct brw_mipmap_tree *mt,
                              int x, int y, int width, int height)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    uint32_t BR13, CMD;
    int pitch, cpp;
 
@@ -763,11 +753,10 @@ brw_miptree_set_alpha_to_one(struct brw_context *brw,
          const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
          const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
 
-         uint64_t offset_B;
-         uint32_t tile_x, tile_y;
+         uint32_t offset, tile_x, tile_y;
          get_blit_intratile_offset_el(brw, mt,
                                       x + chunk_x, y + chunk_y,
-                                      &offset_B, &tile_x, &tile_y);
+                                      &offset, &tile_x, &tile_y);
 
          BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
          OUT_BATCH(CMD | (length - 2));
@@ -777,9 +766,9 @@ brw_miptree_set_alpha_to_one(struct brw_context *brw,
          OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) |
                    SET_FIELD(x + chunk_x + chunk_w, BLT_X));
          if (devinfo->ver >= 8) {
-            OUT_RELOC64(mt->bo, RELOC_WRITE, mt->offset + offset_B);
+            OUT_RELOC64(mt->bo, RELOC_WRITE, mt->offset + offset);
          } else {
-            OUT_RELOC(mt->bo, RELOC_WRITE, mt->offset + offset_B);
+            OUT_RELOC(mt->bo, RELOC_WRITE, mt->offset + offset);
          }
          OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
          ADVANCE_BATCH_TILED(dst_y_tiled, false);
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_buffer_objects.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_buffer_objects.c
index 929ff2237..b7d44e421 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_buffer_objects.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_buffer_objects.c
@@ -219,39 +219,6 @@ brw_buffer_data(struct gl_context *ctx,
    return true;
 }
 
-static GLboolean
-brw_buffer_data_mem(struct gl_context *ctx,
-                    GLenum target,
-                    GLsizeiptrARB size,
-                    struct gl_memory_object *memObj,
-                    GLuint64 offset,
-                    GLenum usage,
-                    struct gl_buffer_object *bufObj)
-{
-   struct brw_buffer_object *intel_obj = brw_buffer_object(bufObj);
-   struct brw_memory_object *intel_memObj = brw_memory_object(memObj);
-
-   /* Part of the ABI, but this function doesn't use it.
-    */
-   (void) target;
-
-   intel_obj->Base.Size = size;
-   intel_obj->Base.Usage = usage;
-   intel_obj->Base.StorageFlags = 0;
-
-   assert(!bufObj->Mappings[MAP_USER].Pointer); /* Mesa should have unmapped it */
-   assert(!bufObj->Mappings[MAP_INTERNAL].Pointer);
-
-   if (intel_obj->buffer != NULL)
-      release_buffer(intel_obj);
-
-   if (size != 0) {
-      intel_obj->buffer = intel_memObj->bo;
-      mark_buffer_valid_data(intel_obj, offset, size);
-   }
-
-   return true;
-}
 
 /**
  * The BufferSubData() driver hook.
@@ -700,7 +667,6 @@ brw_init_buffer_object_functions(struct dd_function_table *functions)
    functions->NewBufferObject = brw_new_buffer_object;
    functions->DeleteBuffer = brw_delete_buffer;
    functions->BufferData = brw_buffer_data;
-   functions->BufferDataMem = brw_buffer_data_mem;
    functions->BufferSubData = brw_buffer_subdata;
    functions->GetBufferSubData = brw_get_buffer_subdata;
    functions->MapBufferRange = brw_map_buffer_range;
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_buffer_objects.h b/lib/mesa/src/mesa/drivers/dri/i965/brw_buffer_objects.h
index 3ed09304f..fef07232e 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_buffer_objects.h
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_buffer_objects.h
@@ -127,15 +127,4 @@ brw_buffer_object(struct gl_buffer_object *obj)
    return (struct brw_buffer_object *) obj;
 }
 
-struct brw_memory_object {
-   struct gl_memory_object Base;
-   struct brw_bo *bo;
-};
-
-static inline struct brw_memory_object *
-brw_memory_object(struct gl_memory_object *obj)
-{
-   return (struct brw_memory_object *)obj;
-}
-
 #endif
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_buffers.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_buffers.c
index 55b692530..ea7aa6fca 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_buffers.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_buffers.c
@@ -42,8 +42,7 @@ brw_drawbuffer(struct gl_context *ctx)
        * time, invalidate our DRI drawable so we'll ask for new buffers
        * (including the fake front) before we start rendering again.
        */
-      if (brw->driContext->driDrawablePriv)
-          dri2InvalidateDrawable(brw->driContext->driDrawablePriv);
+      dri2InvalidateDrawable(brw->driContext->driDrawablePriv);
       brw_prepare_render(brw);
    }
 }
@@ -59,8 +58,7 @@ brw_readbuffer(struct gl_context * ctx, GLenum mode)
        * time, invalidate our DRI drawable so we'll ask for new buffers
        * (including the fake front) before we start reading again.
        */
-      if (brw->driContext->driDrawablePriv)
-          dri2InvalidateDrawable(brw->driContext->driReadablePriv);
+      dri2InvalidateDrawable(brw->driContext->driReadablePriv);
       brw_prepare_render(brw);
    }
 }
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_copy_image.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_copy_image.c
index 5b9f49a63..d53b53bcb 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_copy_image.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_copy_image.c
@@ -42,7 +42,7 @@ copy_miptrees(struct brw_context *brw,
               int dst_x, int dst_y, int dst_z, unsigned dst_level,
               int src_width, int src_height)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    if (devinfo->ver <= 5) {
       /* On gfx4-5, try BLT first.
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_extensions.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_extensions.c
index b143caea0..f5f59a69f 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_extensions.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_extensions.c
@@ -37,7 +37,7 @@ void
 brw_init_extensions(struct gl_context *ctx)
 {
    struct brw_context *brw = brw_context(ctx);
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    assert(devinfo->ver >= 4);
 
@@ -87,6 +87,7 @@ brw_init_extensions(struct gl_context *ctx)
    ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true;
    ctx->Extensions.ARB_texture_non_power_of_two = true;
    ctx->Extensions.ARB_texture_rg = true;
+   ctx->Extensions.ARB_texture_rgb10_a2ui = true;
    ctx->Extensions.ARB_vertex_program = true;
    ctx->Extensions.ARB_vertex_shader = true;
    ctx->Extensions.ARB_vertex_type_2_10_10_10_rev = true;
@@ -111,6 +112,7 @@ brw_init_extensions(struct gl_context *ctx)
    ctx->Extensions.EXT_texture_array = true;
    ctx->Extensions.EXT_texture_env_dot3 = true;
    ctx->Extensions.EXT_texture_filter_anisotropic = true;
+   ctx->Extensions.EXT_texture_integer = true;
    ctx->Extensions.EXT_texture_norm16 = true;
    ctx->Extensions.EXT_texture_shared_exponent = true;
    ctx->Extensions.EXT_texture_snorm = true;
@@ -200,10 +202,8 @@ brw_init_extensions(struct gl_context *ctx)
       ctx->Extensions.ARB_texture_cube_map_array = true;
       ctx->Extensions.ARB_texture_gather = true;
       ctx->Extensions.ARB_texture_multisample = true;
-      ctx->Extensions.ARB_texture_rgb10_a2ui = true;
       ctx->Extensions.ARB_uniform_buffer_object = true;
       ctx->Extensions.EXT_gpu_shader4 = true;
-      ctx->Extensions.EXT_texture_integer = true;
       ctx->Extensions.EXT_texture_shadow_lod = true;
 
       if (ctx->API != API_OPENGL_COMPAT ||
@@ -271,7 +271,7 @@ brw_init_extensions(struct gl_context *ctx)
              ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) {
             ctx->Extensions.ARB_compute_shader = true;
             ctx->Extensions.ARB_ES3_1_compatibility =
-               devinfo->verx10 >= 75;
+               devinfo->ver >= 8 || devinfo->is_haswell;
             ctx->Extensions.NV_compute_shader_derivatives = true;
             ctx->Extensions.ARB_compute_variable_group_size = true;
          }
@@ -286,7 +286,7 @@ brw_init_extensions(struct gl_context *ctx)
       ctx->Extensions.ARB_spirv_extensions = true;
    }
 
-   if (devinfo->verx10 >= 75) {
+   if (devinfo->ver >= 8 || devinfo->is_haswell) {
       ctx->Extensions.ARB_stencil_texturing = true;
       ctx->Extensions.ARB_texture_stencil8 = true;
       ctx->Extensions.OES_geometry_shader = true;
@@ -294,7 +294,7 @@ brw_init_extensions(struct gl_context *ctx)
       ctx->Extensions.OES_viewport_array = true;
    }
 
-   if (devinfo->verx10 >= 75 || devinfo->is_baytrail) {
+   if (devinfo->ver >= 8 || devinfo->is_haswell || devinfo->is_baytrail) {
       ctx->Extensions.ARB_robust_buffer_access_behavior = true;
    }
 
@@ -374,7 +374,7 @@ brw_init_extensions(struct gl_context *ctx)
       ctx->Extensions.ARB_fragment_shader_interlock = true;
    }
 
-   if (intel_device_info_is_9lp(devinfo))
+   if (gen_device_info_is_9lp(devinfo))
       ctx->Extensions.KHR_texture_compression_astc_hdr = true;
 
    if (devinfo->ver >= 6)
@@ -393,11 +393,4 @@ brw_init_extensions(struct gl_context *ctx)
    ctx->Extensions.EXT_demote_to_helper_invocation = true;
 
    ctx->Const.PrimitiveRestartFixedIndex = true;
-
-   if (devinfo->ver >= 7) {
-      ctx->Extensions.EXT_memory_object_fd = true;
-      ctx->Extensions.EXT_memory_object = true;
-      ctx->Extensions.EXT_semaphore = true;
-      ctx->Extensions.EXT_semaphore_fd = true;
-   }
 }
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_fbo.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_fbo.c
index ff30385e4..7695546d2 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_fbo.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_fbo.c
@@ -249,7 +249,7 @@ static mesa_format
 brw_renderbuffer_format(struct gl_context * ctx, GLenum internalFormat)
 {
    struct brw_context *brw = brw_context(ctx);
-   ASSERTED const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   ASSERTED const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    switch (internalFormat) {
    default:
@@ -647,7 +647,7 @@ static void
 brw_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
 {
    struct brw_context *brw = brw_context(ctx);
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct brw_renderbuffer *depthRb =
       brw_get_renderbuffer(fb, BUFFER_DEPTH);
    struct brw_renderbuffer *stencilRb =
@@ -895,7 +895,7 @@ brw_blit_framebuffer(struct gl_context *ctx,
                      GLbitfield mask, GLenum filter)
 {
    struct brw_context *brw = brw_context(ctx);
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    /* Page 679 of OpenGL 4.4 spec says:
     *    "Added BlitFramebuffer to commands affected by conditional rendering in
@@ -1014,7 +1014,7 @@ brw_cache_sets_clear(struct brw_context *brw)
 static void
 flush_depth_and_render_caches(struct brw_context *brw, struct brw_bo *bo)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    if (devinfo->ver >= 6) {
       brw_emit_pipe_control_flush(brw,
@@ -1135,5 +1135,4 @@ brw_fbo_init(struct brw_context *brw)
                                                _mesa_key_pointer_equal);
    brw->depth_cache = _mesa_set_create(brw->mem_ctx, _mesa_hash_pointer,
                                        _mesa_key_pointer_equal);
-   util_dynarray_init(&brw->batch.exec_fences, NULL);
 }
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_mipmap_tree.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_mipmap_tree.c
index 2c85f9b39..9a599e286 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_mipmap_tree.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_mipmap_tree.c
@@ -69,7 +69,7 @@ static void brw_miptree_unmap_raw(struct brw_mipmap_tree *mt);
  * format variant for check for CCS_E compatibility.
  */
 static bool
-format_ccs_e_compat_with_miptree(const struct intel_device_info *devinfo,
+format_ccs_e_compat_with_miptree(const struct gen_device_info *devinfo,
                                  const struct brw_mipmap_tree *mt,
                                  enum isl_format access_format)
 {
@@ -146,7 +146,7 @@ needs_separate_stencil(const struct brw_context *brw,
                        struct brw_mipmap_tree *mt,
                        mesa_format format)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    if (_mesa_get_format_base_format(format) != GL_DEPTH_STENCIL)
       return false;
@@ -170,7 +170,7 @@ brw_miptree_choose_aux_usage(struct brw_context *brw,
    if (_mesa_is_format_color_format(mt->format)) {
       if (mt->surf.samples > 1) {
          mt->aux_usage = ISL_AUX_USAGE_MCS;
-      } else if (!INTEL_DEBUG(DEBUG_NO_RBC) &&
+      } else if (!(INTEL_DEBUG & DEBUG_NO_RBC) &&
                  format_supports_ccs_e(brw, mt->format)) {
          mt->aux_usage = ISL_AUX_USAGE_CCS_E;
       } else if (brw->mesa_format_supports_render[mt->format]) {
@@ -195,7 +195,7 @@ brw_miptree_choose_aux_usage(struct brw_context *brw,
 mesa_format
 brw_lower_compressed_format(struct brw_context *brw, mesa_format format)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    /* No need to lower ETC formats on these platforms,
     * they are supported natively.
@@ -332,7 +332,7 @@ static bool
 need_to_retile_as_x(const struct brw_context *brw, uint64_t size,
                     enum isl_tiling tiling)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    /* If the BO is too large to fit in the aperture, we need to use the
     * BLT engine to support it.  Prior to Sandybridge, the BLT paths can't
@@ -478,7 +478,7 @@ miptree_create(struct brw_context *brw,
                GLuint num_samples,
                enum brw_miptree_create_flags flags)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const uint32_t alloc_flags =
       (flags & MIPTREE_CREATE_BUSY || num_samples > 1) ? BO_ALLOC_BUSY : 0;
    isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
@@ -585,7 +585,7 @@ brw_miptree_create_for_bo(struct brw_context *brw,
                           enum isl_tiling tiling,
                           enum brw_miptree_create_flags flags)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct brw_mipmap_tree *mt;
    const GLenum target = depth > 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D;
    const GLenum base_format = _mesa_get_format_base_format(format);
@@ -728,8 +728,8 @@ create_ccs_buf_for_image(struct brw_context *brw,
    /* We shouldn't already have a CCS */
    assert(!mt->aux_buf);
 
-   if (!isl_surf_get_ccs_surf(&brw->isl_dev, &mt->surf, NULL,
-                              &temp_ccs_surf, image->aux_pitch))
+   if (!isl_surf_get_ccs_surf(&brw->isl_dev, &mt->surf, &temp_ccs_surf, NULL,
+                              image->aux_pitch))
       return false;
 
    assert(image->aux_offset < image->bo->size);
@@ -848,7 +848,7 @@ brw_miptree_create_for_dri_image(struct brw_context *brw,
     * for EGL images from non-tile aligned sufaces in gfx4 hw and earlier which has
     * trouble resolving back to destination image due to alignment issues.
     */
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    if (!devinfo->has_surface_tile_offset) {
       uint32_t draw_x, draw_y;
       brw_miptree_get_tile_offsets(mt, 0, 0, &draw_x, &draw_y);
@@ -1132,7 +1132,7 @@ brw_miptree_get_image_offset(const struct brw_mipmap_tree *mt,
       return;
    }
 
-   uint32_t x_offset_sa, y_offset_sa, z_offset_sa, array_offset;
+   uint32_t x_offset_sa, y_offset_sa;
 
    /* Miptree itself can have an offset only if it represents a single
     * slice in an imported buffer object.
@@ -1150,13 +1150,10 @@ brw_miptree_get_image_offset(const struct brw_mipmap_tree *mt,
    const unsigned z = mt->surf.dim == ISL_SURF_DIM_3D ? slice : 0;
    slice = mt->surf.dim == ISL_SURF_DIM_3D ? 0 : slice;
    isl_surf_get_image_offset_el(&mt->surf, level, slice, z,
-                                &x_offset_sa, &y_offset_sa,
-                                &z_offset_sa, &array_offset);
+                                &x_offset_sa, &y_offset_sa);
 
    *x = x_offset_sa;
    *y = y_offset_sa;
-   assert(z_offset_sa == 0);
-   assert(array_offset == 0);
 }
 
 /**
@@ -1285,7 +1282,7 @@ brw_miptree_copy_slice(struct brw_context *brw,
                        struct brw_mipmap_tree *dst_mt,
                        unsigned dst_level, unsigned dst_layer)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    mesa_format format = src_mt->format;
    unsigned width = minify(src_mt->surf.phys_level0_sa.width,
                            src_level - src_mt->first_level);
@@ -1486,12 +1483,12 @@ brw_miptree_level_enable_hiz(struct brw_context *brw,
                              struct brw_mipmap_tree *mt,
                              uint32_t level)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    assert(mt->aux_buf);
    assert(mt->surf.size_B > 0);
 
-   if (devinfo->verx10 >= 75) {
+   if (devinfo->ver >= 8 || devinfo->is_haswell) {
       uint32_t width = minify(mt->surf.phys_level0_sa.width, level);
       uint32_t height = minify(mt->surf.phys_level0_sa.height, level);
 
@@ -1576,7 +1573,7 @@ brw_miptree_alloc_aux(struct brw_context *brw, struct brw_mipmap_tree *mt)
       initial_state = ISL_AUX_STATE_PASS_THROUGH;
       memset_value = 0;
       aux_surf_ok =
-         isl_surf_get_ccs_surf(&brw->isl_dev, &mt->surf, NULL, &aux_surf, 0);
+         isl_surf_get_ccs_surf(&brw->isl_dev, &mt->surf, &aux_surf, NULL, 0);
       break;
 
    default:
@@ -1623,7 +1620,7 @@ bool
 brw_miptree_sample_with_hiz(struct brw_context *brw,
                             struct brw_mipmap_tree *mt)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    if (!devinfo->has_sample_with_hiz) {
       return false;
@@ -1808,7 +1805,7 @@ brw_miptree_finish_write(struct brw_context *brw,
                          uint32_t start_layer, uint32_t num_layers,
                          enum isl_aux_usage aux_usage)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    if (mt->format == MESA_FORMAT_S_UINT8 && devinfo->ver <= 7) {
       mt->shadow_needs_update = true;
@@ -1899,7 +1896,7 @@ can_texture_with_ccs(struct brw_context *brw,
    if (!format_ccs_e_compat_with_miptree(&brw->screen->devinfo,
                                          mt, view_format)) {
       perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
-                 isl_format_get_name(view_format),
+                 isl_format_get_layout(view_format)->name,
                  _mesa_get_format_name(mt->format));
       return false;
    }
@@ -2016,7 +2013,7 @@ brw_miptree_render_aux_usage(struct brw_context *brw,
                              bool blend_enabled,
                              bool draw_aux_disabled)
 {
-   struct intel_device_info *devinfo = &brw->screen->devinfo;
+   struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    if (draw_aux_disabled)
       return ISL_AUX_USAGE_NONE;
@@ -2290,7 +2287,7 @@ void
 brw_update_r8stencil(struct brw_context *brw,
                        struct brw_mipmap_tree *mt)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    assert(devinfo->ver >= 7);
    struct brw_mipmap_tree *src =
@@ -2432,7 +2429,7 @@ brw_miptree_unmap_blit(struct brw_context *brw,
                        unsigned int level,
                        unsigned int slice)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct gl_context *ctx = &brw->ctx;
 
    brw_miptree_unmap_raw(map->linear_mt);
@@ -2610,7 +2607,7 @@ brw_miptree_map_blit(struct brw_context *brw,
                      struct brw_miptree_map *map,
                      unsigned int level, unsigned int slice)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    map->linear_mt = make_surface(brw, GL_TEXTURE_2D, mt->format,
                                  0, 0, map->w, map->h, 1, 1,
                                  ISL_TILING_LINEAR_BIT,
@@ -3030,7 +3027,7 @@ use_blitter_to_map(struct brw_context *brw,
                    struct brw_mipmap_tree *mt,
                    const struct brw_miptree_map *map)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    if (devinfo->has_llc &&
       /* It's probably not worth swapping to the blit ring because of
@@ -3079,7 +3076,7 @@ brw_miptree_map(struct brw_context *brw,
                 void **out_ptr,
                 ptrdiff_t *out_stride)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct brw_miptree_map *map;
 
    assert(mt->surf.samples == 1);
@@ -3166,7 +3163,7 @@ get_isl_surf_dim(GLenum target)
 }
 
 enum isl_dim_layout
-get_isl_dim_layout(const struct intel_device_info *devinfo,
+get_isl_dim_layout(const struct gen_device_info *devinfo,
                    enum isl_tiling tiling, GLenum target)
 {
    switch (target) {
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_mipmap_tree.h b/lib/mesa/src/mesa/drivers/dri/i965/brw_mipmap_tree.h
index c17e72e34..231fdbe37 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_mipmap_tree.h
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_mipmap_tree.h
@@ -456,7 +456,7 @@ enum isl_surf_dim
 get_isl_surf_dim(GLenum target);
 
 enum isl_dim_layout
-get_isl_dim_layout(const struct intel_device_info *devinfo,
+get_isl_dim_layout(const struct gen_device_info *devinfo,
                    enum isl_tiling tiling, GLenum target);
 
 void
@@ -716,7 +716,7 @@ static inline bool
 brw_miptree_needs_fake_etc(struct brw_context *brw,
                              struct brw_mipmap_tree *mt)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    bool is_etc = _mesa_is_format_etc2(mt->format) ||
                  (mt->format == MESA_FORMAT_ETC1_RGB8);
 
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_pixel_bitmap.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_pixel_bitmap.c
index aa8c2fc5a..d62fac8ab 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_pixel_bitmap.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_pixel_bitmap.c
@@ -311,7 +311,7 @@ do_blit_bitmap(struct gl_context *ctx,
    }
 out:
 
-   if (INTEL_DEBUG(DEBUG_SYNC))
+   if (INTEL_DEBUG & DEBUG_SYNC)
       brw_batch_flush(brw);
 
    if (unpack->BufferObj) {
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_pixel_read.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_pixel_read.c
index 1c874eca2..3444ce3ab 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_pixel_read.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_pixel_read.c
@@ -73,7 +73,7 @@ brw_readpixels_tiled_memcpy(struct gl_context *ctx,
 {
    struct brw_context *brw = brw_context(ctx);
    struct gl_renderbuffer *rb = ctx->ReadBuffer->_ColorReadBuffer;
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    /* This path supports reading from color buffers only */
    if (rb == NULL)
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_screen.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_screen.c
index fbf81e6b6..89b591c94 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_screen.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_screen.c
@@ -95,9 +95,9 @@ static const driOptionDescription brw_driconf[] = {
    DRI_CONF_SECTION_MISCELLANEOUS
       DRI_CONF_GLSL_ZERO_INIT(false)
       DRI_CONF_VS_POSITION_ALWAYS_INVARIANT(false)
-      DRI_CONF_VS_POSITION_ALWAYS_PRECISE(false)
       DRI_CONF_ALLOW_RGB10_CONFIGS(false)
       DRI_CONF_ALLOW_RGB565_CONFIGS(true)
+      DRI_CONF_ALLOW_FP16_CONFIGS(false)
    DRI_CONF_SECTION_END
 };
 
@@ -346,16 +346,16 @@ static const struct brw_image_format brw_image_formats[] = {
 
 static const struct {
    uint64_t modifier;
-   unsigned since_ver;
+   unsigned since_gen;
 } supported_modifiers[] = {
-   { .modifier = DRM_FORMAT_MOD_LINEAR       , .since_ver = 1 },
-   { .modifier = I915_FORMAT_MOD_X_TILED     , .since_ver = 1 },
-   { .modifier = I915_FORMAT_MOD_Y_TILED     , .since_ver = 6 },
-   { .modifier = I915_FORMAT_MOD_Y_TILED_CCS , .since_ver = 9 },
+   { .modifier = DRM_FORMAT_MOD_LINEAR       , .since_gen = 1 },
+   { .modifier = I915_FORMAT_MOD_X_TILED     , .since_gen = 1 },
+   { .modifier = I915_FORMAT_MOD_Y_TILED     , .since_gen = 6 },
+   { .modifier = I915_FORMAT_MOD_Y_TILED_CCS , .since_gen = 9 },
 };
 
 static bool
-modifier_is_supported(const struct intel_device_info *devinfo,
+modifier_is_supported(const struct gen_device_info *devinfo,
                       const struct brw_image_format *fmt, int dri_format,
                       unsigned use, uint64_t modifier)
 {
@@ -374,7 +374,7 @@ modifier_is_supported(const struct intel_device_info *devinfo,
 
    if (modinfo->aux_usage == ISL_AUX_USAGE_CCS_E) {
       /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
-      if (INTEL_DEBUG(DEBUG_NO_RBC))
+      if (INTEL_DEBUG & DEBUG_NO_RBC)
          return false;
 
       /* CCS_E is not supported for planar images */
@@ -401,7 +401,7 @@ modifier_is_supported(const struct intel_device_info *devinfo,
       if (supported_modifiers[i].modifier != modifier)
          continue;
 
-      return supported_modifiers[i].since_ver <= devinfo->ver;
+      return supported_modifiers[i].since_gen <= devinfo->ver;
    }
 
    return false;
@@ -690,7 +690,7 @@ const uint64_t priority_to_modifier[] = {
 };
 
 static uint64_t
-select_best_modifier(struct intel_device_info *devinfo,
+select_best_modifier(struct gen_device_info *devinfo,
                      int dri_format,
                      unsigned use,
                      const uint64_t *modifiers,
@@ -737,6 +737,11 @@ brw_create_image_common(__DRIscreen *dri_screen,
    uint64_t modifier = DRM_FORMAT_MOD_INVALID;
    bool ok;
 
+   /* Callers of this may specify a modifier, or a dri usage, but not both. The
+    * newer modifier interface deprecates the older usage flags.
+    */
+   assert(!(use && count));
+
    if (use & __DRI_IMAGE_USE_CURSOR) {
       if (width != 64 || height != 64)
          return NULL;
@@ -792,7 +797,7 @@ brw_create_image_common(__DRIscreen *dri_screen,
 
    struct isl_surf aux_surf = {0,};
    if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
-      ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, NULL, &aux_surf, 0);
+      ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, NULL, 0);
       if (!ok) {
          free(image);
          return NULL;
@@ -917,17 +922,6 @@ brw_create_image_with_modifiers(__DRIscreen *dri_screen,
                                   modifiers, count, loaderPrivate);
 }
 
-static __DRIimage *
-brw_create_image_with_modifiers2(__DRIscreen *dri_screen,
-                                 int width, int height, int format,
-                                 const uint64_t *modifiers,
-                                 const unsigned count, unsigned int use,
-                                 void *loaderPrivate)
-{
-   return brw_create_image_common(dri_screen, width, height, format, use,
-                                  modifiers, count, loaderPrivate);
-}
-
 static GLboolean
 brw_query_image(__DRIimage *image, int attrib, int *value)
 {
@@ -1233,7 +1227,7 @@ brw_create_image_from_fds_common(__DRIscreen *dri_screen,
       }
 
       struct isl_surf aux_surf = {0,};
-      ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, NULL, &aux_surf,
+      ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, NULL,
                                  image->aux_pitch);
       if (!ok) {
          brw_bo_unreference(image->bo);
@@ -1350,7 +1344,7 @@ brw_create_image_from_dma_bufs(__DRIscreen *dri_screen,
 }
 
 static bool
-brw_image_format_is_supported(const struct intel_device_info *devinfo,
+brw_image_format_is_supported(const struct gen_device_info *devinfo,
                                 const struct brw_image_format *fmt)
 {
    /* Currently, all formats with an brw_image_format are available on all
@@ -1523,7 +1517,7 @@ brw_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
 }
 
 static const __DRIimageExtension brwImageExtension = {
-    .base = { __DRI_IMAGE, 19 },
+    .base = { __DRI_IMAGE, 16 },
 
     .createImageFromName                = brw_create_image_from_name,
     .createImageFromRenderbuffer        = brw_create_image_from_renderbuffer,
@@ -1546,7 +1540,6 @@ static const __DRIimageExtension brwImageExtension = {
     .queryDmaBufFormats                 = brw_query_dma_buf_formats,
     .queryDmaBufModifiers               = brw_query_dma_buf_modifiers,
     .queryDmaBufFormatModifierAttribs   = brw_query_format_modifier_attribs,
-    .createImageWithModifiers2          = brw_create_image_with_modifiers2,
 };
 
 static int
@@ -1889,6 +1882,9 @@ brw_init_bufmgr(struct brw_screen *screen)
 {
    __DRIscreen *dri_screen = screen->driScrnPriv;
 
+   if (getenv("INTEL_NO_HW") != NULL)
+      screen->no_hw = true;
+
    bool bo_reuse = false;
    int bo_reuse_mode = driQueryOptioni(&screen->optionCache, "bo_reuse");
    switch (bo_reuse_mode) {
@@ -2001,7 +1997,7 @@ static bool
 brw_detect_pipelined_register(struct brw_screen *screen,
                                 int reg, uint32_t expected_value, bool reset)
 {
-   if (screen->devinfo.no_hw)
+   if (screen->no_hw)
       return false;
 
    struct brw_bo *results, *bo;
@@ -2092,7 +2088,7 @@ err:
 static bool
 brw_detect_pipelined_so(struct brw_screen *screen)
 {
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct gen_device_info *devinfo = &screen->devinfo;
 
    /* Supposedly, Broadwell just works. */
    if (devinfo->ver >= 8)
@@ -2164,8 +2160,7 @@ brw_allowed_format(__DRIscreen *dri_screen, mesa_format format)
    if (!allow_rgba_ordering &&
        (format == MESA_FORMAT_R8G8B8A8_UNORM ||
         format == MESA_FORMAT_R8G8B8X8_UNORM ||
-        format == MESA_FORMAT_R8G8B8A8_SRGB ||
-        format == MESA_FORMAT_R8G8B8X8_SRGB))
+        format == MESA_FORMAT_R8G8B8A8_SRGB))
       return false;
 
     /* Shall we expose 10 bpc formats? */
@@ -2183,7 +2178,9 @@ brw_allowed_format(__DRIscreen *dri_screen, mesa_format format)
       return false;
 
    /* Shall we expose fp16 formats? */
-   bool allow_fp16_configs = brw_loader_get_cap(dri_screen, DRI_LOADER_CAP_FP16);
+   bool allow_fp16_configs = driQueryOptionb(&screen->optionCache,
+                                             "allow_fp16_configs");
+   allow_fp16_configs &= brw_loader_get_cap(dri_screen, DRI_LOADER_CAP_FP16);
    if (!allow_fp16_configs &&
        (format == MESA_FORMAT_RGBA_FLOAT16 ||
         format == MESA_FORMAT_RGBX_FLOAT16))
@@ -2227,11 +2224,11 @@ brw_screen_make_configs(__DRIscreen *dri_screen)
 
       /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
       MESA_FORMAT_R8G8B8A8_UNORM,
-      MESA_FORMAT_R8G8B8A8_SRGB,
 
       /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
       MESA_FORMAT_R8G8B8X8_UNORM,
-      MESA_FORMAT_R8G8B8X8_SRGB,
+
+      MESA_FORMAT_R8G8B8A8_SRGB,
    };
 
    /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
@@ -2242,7 +2239,7 @@ brw_screen_make_configs(__DRIscreen *dri_screen)
    static const uint8_t singlesample_samples[1] = {0};
 
    struct brw_screen *screen = dri_screen->driverPrivate;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct gen_device_info *devinfo = &screen->devinfo;
    uint8_t depth_bits[4], stencil_bits[4];
    __DRIconfig **configs = NULL;
 
@@ -2468,13 +2465,14 @@ set_max_gl_versions(struct brw_screen *screen)
 }
 
 static void
-shader_debug_log_mesa(void *data, unsigned *msg_id, const char *fmt, ...)
+shader_debug_log_mesa(void *data, const char *fmt, ...)
 {
    struct brw_context *brw = (struct brw_context *)data;
    va_list args;
 
    va_start(args, fmt);
-   _mesa_gl_vdebugf(&brw->ctx, msg_id,
+   GLuint msg_id = 0;
+   _mesa_gl_vdebugf(&brw->ctx, &msg_id,
                     MESA_DEBUG_SOURCE_SHADER_COMPILER,
                     MESA_DEBUG_TYPE_OTHER,
                     MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
@@ -2482,14 +2480,14 @@ shader_debug_log_mesa(void *data, unsigned *msg_id, const char *fmt, ...)
 }
 
 static void
-shader_perf_log_mesa(void *data, unsigned *msg_id, const char *fmt, ...)
+shader_perf_log_mesa(void *data, const char *fmt, ...)
 {
    struct brw_context *brw = (struct brw_context *)data;
 
    va_list args;
    va_start(args, fmt);
 
-   if (INTEL_DEBUG(DEBUG_PERF)) {
+   if (INTEL_DEBUG & DEBUG_PERF) {
       va_list args_copy;
       va_copy(args_copy, args);
       vfprintf(stderr, fmt, args_copy);
@@ -2497,7 +2495,8 @@ shader_perf_log_mesa(void *data, unsigned *msg_id, const char *fmt, ...)
    }
 
    if (brw->perf_debug) {
-      _mesa_gl_vdebugf(&brw->ctx, msg_id,
+      GLuint msg_id = 0;
+      _mesa_gl_vdebugf(&brw->ctx, &msg_id,
                        MESA_DEBUG_SOURCE_SHADER_COMPILER,
                        MESA_DEBUG_TYPE_PERFORMANCE,
                        MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
@@ -2539,17 +2538,18 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
 
    driParseOptionInfo(&options, brw_driconf, ARRAY_SIZE(brw_driconf));
    driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum,
-                       "i965", NULL, NULL, NULL, 0, NULL, 0);
+                       "i965", NULL, NULL, 0, NULL, 0);
    driDestroyOptionCache(&options);
 
    screen->driScrnPriv = dri_screen;
    dri_screen->driverPrivate = (void *) screen;
 
-   if (!intel_get_device_info_from_fd(dri_screen->fd, &screen->devinfo))
+   if (!gen_get_device_info_from_fd(dri_screen->fd, &screen->devinfo))
       return NULL;
 
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct gen_device_info *devinfo = &screen->devinfo;
    screen->deviceID = devinfo->chipset_id;
+   screen->no_hw = devinfo->no_hw;
 
    if (devinfo->ver >= 12) {
       fprintf(stderr, "gfx12 and newer are not supported on i965\n");
@@ -2561,7 +2561,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
 
    brw_process_intel_debug_variable();
 
-   if (INTEL_DEBUG(DEBUG_SHADER_TIME) && devinfo->ver < 7) {
+   if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->ver < 7) {
       fprintf(stderr,
               "shader_time debugging requires gfx7 (Ivybridge) or better.\n");
       intel_debug &= ~DEBUG_SHADER_TIME;
@@ -2609,6 +2609,10 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
    isl_device_init(&screen->isl_dev, &screen->devinfo,
                    screen->hw_has_swizzling);
 
+   /* GENs prior to 8 do not support EU/Subslice info */
+   screen->subslice_total = gen_device_info_subslice_total(devinfo);
+   screen->eu_total = gen_device_info_eu_total(devinfo);
+
    /* Gfx7-7.5 kernel requirements / command parser saga:
     *
     * - pre-v3.16:
@@ -2801,7 +2805,6 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
       !(screen->kernel_features & KERNEL_ALLOWS_CONTEXT_ISOLATION);
 
    screen->compiler->glsl_compiler_options[MESA_SHADER_VERTEX].PositionAlwaysInvariant = driQueryOptionb(&screen->optionCache, "vs_position_always_invariant");
-   screen->compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].PositionAlwaysPrecise = driQueryOptionb(&screen->optionCache, "vs_position_always_precise");
 
    screen->compiler->supports_pull_constants = true;
    screen->compiler->compact_params = true;
@@ -2812,7 +2815,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
 
    brw_screen_init_surface_formats(screen);
 
-   if (INTEL_DEBUG(DEBUG_BATCH | DEBUG_SUBMIT)) {
+   if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) {
       unsigned int caps = brw_get_integer(screen, I915_PARAM_HAS_SCHEDULER);
       if (caps) {
          fprintf(stderr, "Kernel scheduler detected: %08x\n", caps);
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_screen.h b/lib/mesa/src/mesa/drivers/dri/i965/brw_screen.h
index d2cefc2be..226cd3387 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_screen.h
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_screen.h
@@ -34,7 +34,7 @@
 #include "isl/isl.h"
 #include "dri_util.h"
 #include "brw_bufmgr.h"
-#include "dev/intel_device_info.h"
+#include "dev/gen_device_info.h"
 #include "drm-uapi/i915_drm.h"
 #include "util/xmlconfig.h"
 
@@ -47,7 +47,7 @@ extern "C" {
 struct brw_screen
 {
    int deviceID;
-   struct intel_device_info devinfo;
+   struct gen_device_info devinfo;
 
    __DRIscreen *driScrnPriv;
 
@@ -59,6 +59,7 @@ struct brw_screen
    /** DRM fd associated with this screen. Not owned by this object. Do not close. */
    int fd;
 
+   bool no_hw;
    bool hw_has_swizzling;
    bool has_exec_fence; /**< I915_PARAM_HAS_EXEC_FENCE */
 
@@ -107,6 +108,16 @@ struct brw_screen
     */
    int cmd_parser_version;
 
+   /**
+    * Number of subslices reported by the I915_PARAM_SUBSLICE_TOTAL parameter
+    */
+   int subslice_total;
+
+   /**
+    * Number of EUs reported by the I915_PARAM_EU_TOTAL parameter
+    */
+   int eu_total;
+
    bool mesa_format_supports_texture[MESA_FORMAT_COUNT];
    bool mesa_format_supports_render[MESA_FORMAT_COUNT];
    enum isl_format mesa_to_isl_render_format[MESA_FORMAT_COUNT];
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_tex_image.c b/lib/mesa/src/mesa/drivers/dri/i965/brw_tex_image.c
index 02e9d6438..2f95918e5 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_tex_image.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_tex_image.c
@@ -184,7 +184,7 @@ brw_texsubimage_tiled_memcpy(struct gl_context * ctx,
                              const struct gl_pixelstore_attrib *packing)
 {
    struct brw_context *brw = brw_context(ctx);
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct brw_texture_image *image = brw_texture_image(texImage);
    int src_pitch;
 
@@ -732,7 +732,7 @@ brw_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
                                 const struct gl_pixelstore_attrib *packing)
 {
    struct brw_context *brw = brw_context(ctx);
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct brw_texture_image *image = brw_texture_image(texImage);
    int dst_pitch;
 
@@ -970,10 +970,8 @@ brw_compressedtexsubimage(struct gl_context *ctx, GLuint dims,
    bool is_linear_astc = _mesa_is_astc_format(gl_format) &&
                         !_mesa_is_srgb_format(gl_format);
    struct brw_context *brw = (struct brw_context*) ctx;
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
-   if (devinfo->ver == 9 &&
-       !intel_device_info_is_9lp(devinfo) &&
-       is_linear_astc)
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
+   if (devinfo->ver == 9 && !gen_device_info_is_9lp(devinfo) && is_linear_astc)
       flush_astc_denorms(ctx, dims, texImage,
                          xoffset, yoffset, zoffset,
                          width, height, depth);
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/gfx6_constant_state.c b/lib/mesa/src/mesa/drivers/dri/i965/gfx6_constant_state.c
index 1f0e9fb83..6241502f7 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/gfx6_constant_state.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/gfx6_constant_state.c
@@ -133,7 +133,7 @@ gfx6_upload_push_constants(struct brw_context *brw,
                            const struct brw_stage_prog_data *prog_data,
                            struct brw_stage_state *stage_state)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct gl_context *ctx = &brw->ctx;
 
    bool active = prog_data &&
@@ -156,7 +156,7 @@ gfx6_upload_push_constants(struct brw_context *brw,
       int i;
       const int size = prog_data->nr_params * sizeof(gl_constant_value);
       gl_constant_value *param;
-      if (devinfo->verx10 >= 75) {
+      if (devinfo->ver >= 8 || devinfo->is_haswell) {
          param = brw_upload_space(&brw->upload, size, 32,
                                   &stage_state->push_const_bo,
                                   &stage_state->push_const_offset);
@@ -308,11 +308,9 @@ brw_upload_cs_push_constants(struct brw_context *brw,
    /* XXX: Should this happen somewhere before to get our state flag set? */
    _mesa_load_state_parameters(ctx, prog->Parameters);
 
-   const struct brw_cs_dispatch_info dispatch =
-      brw_cs_get_dispatch_info(&brw->screen->devinfo, cs_prog_data,
-                               brw->compute.group_size);
+   const struct brw_cs_parameters cs_params = brw_cs_get_parameters(brw);
    const unsigned push_const_size =
-      brw_cs_push_const_total_size(cs_prog_data, dispatch.threads);
+      brw_cs_push_const_total_size(cs_prog_data, cs_params.threads);
 
    if (push_const_size == 0) {
       stage_state->push_const_size = 0;
@@ -339,7 +337,7 @@ brw_upload_cs_push_constants(struct brw_context *brw,
    }
 
    if (cs_prog_data->push.per_thread.size > 0) {
-      for (unsigned t = 0; t < dispatch.threads; t++) {
+      for (unsigned t = 0; t < cs_params.threads; t++) {
          unsigned dst =
             8 * (cs_prog_data->push.per_thread.regs * t +
                  cs_prog_data->push.cross_thread.regs);
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/gfx6_queryobj.c b/lib/mesa/src/mesa/drivers/dri/i965/gfx6_queryobj.c
index d6067d3c0..fcfe8bc56 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/gfx6_queryobj.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/gfx6_queryobj.c
@@ -34,7 +34,7 @@
 #include "brw_context.h"
 #include "brw_defines.h"
 #include "brw_state.h"
-#include "perf/intel_perf_regs.h"
+#include "perf/gen_perf_regs.h"
 #include "brw_batch.h"
 #include "brw_buffer_objects.h"
 
@@ -79,7 +79,7 @@ static void
 write_primitives_generated(struct brw_context *brw,
                            struct brw_bo *query_bo, int stream, int idx)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    brw_emit_mi_flush(brw);
 
@@ -97,7 +97,7 @@ static void
 write_xfb_primitives_written(struct brw_context *brw,
                              struct brw_bo *bo, int stream, int idx)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    brw_emit_mi_flush(brw);
 
@@ -116,7 +116,7 @@ write_xfb_overflow_streams(struct gl_context *ctx,
                            int idx)
 {
    struct brw_context *brw = brw_context(ctx);
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    brw_emit_mi_flush(brw);
 
@@ -172,7 +172,7 @@ static void
 emit_pipeline_stat(struct brw_context *brw, struct brw_bo *bo,
                    int stream, int target, int idx)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    /* One source of confusion is the tessellation shader statistics. The
     * hardware has no statistics specific to the TE unit. Ideally we could have
@@ -223,7 +223,7 @@ gfx6_queryobj_get_results(struct gl_context *ctx,
                           struct brw_query_object *query)
 {
    struct brw_context *brw = brw_context(ctx);
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    if (query->bo == NULL)
       return;
@@ -235,12 +235,12 @@ gfx6_queryobj_get_results(struct gl_context *ctx,
        * Subtract the two and convert to nanoseconds.
        */
       query->Base.Result = brw_raw_timestamp_delta(brw, results[0], results[1]);
-      query->Base.Result = intel_device_info_timebase_scale(devinfo, query->Base.Result);
+      query->Base.Result = gen_device_info_timebase_scale(devinfo, query->Base.Result);
       break;
 
    case GL_TIMESTAMP:
       /* The query BO contains a single timestamp value in results[0]. */
-      query->Base.Result = intel_device_info_timebase_scale(devinfo, results[0]);
+      query->Base.Result = gen_device_info_timebase_scale(devinfo, results[0]);
 
       /* Ensure the scaled timestamp overflows according to
        * GL_QUERY_COUNTER_BITS
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/gfx6_sol.c b/lib/mesa/src/mesa/drivers/dri/i965/gfx6_sol.c
index 56470dafc..4df644c8b 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/gfx6_sol.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/gfx6_sol.c
@@ -279,7 +279,7 @@ void
 brw_save_primitives_written_counters(struct brw_context *brw,
                                      struct brw_transform_feedback_object *obj)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const struct gl_context *ctx = &brw->ctx;
    const int streams = ctx->Const.MaxVertexStreams;
 
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/gfx6_urb.c b/lib/mesa/src/mesa/drivers/dri/i965/gfx6_urb.c
index 8b69409bc..bf69a5637 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/gfx6_urb.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/gfx6_urb.c
@@ -52,7 +52,7 @@ gfx6_upload_urb(struct brw_context *brw, unsigned vs_size,
 {
    int nr_vs_entries, nr_gs_entries;
    int total_urb_size = brw->urb.size * 1024; /* in bytes */
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    /* Calculate how many entries fit in each stage's section of the URB */
    if (gs_present) {
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/gfx7_l3_state.c b/lib/mesa/src/mesa/drivers/dri/i965/gfx7_l3_state.c
index f7ef5c1d3..f9992fb39 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/gfx7_l3_state.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/gfx7_l3_state.c
@@ -70,7 +70,7 @@ get_pipeline_state_l3_weights(const struct brw_context *brw)
 static void
 setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const bool has_dc = cfg->n[INTEL_L3P_DC] || cfg->n[INTEL_L3P_ALL];
    const bool has_is = cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_RO] ||
                        cfg->n[INTEL_L3P_ALL];
@@ -194,7 +194,7 @@ setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg)
 static void
 update_urb_size(struct brw_context *brw, const struct intel_l3_config *cfg)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const unsigned sz = intel_get_l3_config_urb_size(devinfo, cfg);
 
    if (brw->urb.size != sz) {
@@ -242,7 +242,7 @@ brw_emit_l3_state(struct brw_context *brw)
       update_urb_size(brw, cfg);
       brw->l3.config = cfg;
 
-      if (INTEL_DEBUG(DEBUG_L3)) {
+      if (INTEL_DEBUG & DEBUG_L3) {
          fprintf(stderr, "L3 config transition (%f > %f): ", dw, dw_threshold);
          intel_dump_l3_config(cfg, stderr);
       }
@@ -300,7 +300,7 @@ const struct brw_tracked_state gfx7_l3_state = {
 void
 gfx7_restore_default_l3_config(struct brw_context *brw)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const struct intel_l3_config *const cfg = intel_get_default_l3_config(devinfo);
 
    if (cfg != brw->l3.config &&
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/gfx7_urb.c b/lib/mesa/src/mesa/drivers/dri/i965/gfx7_urb.c
index 79c28c156..1f1757487 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/gfx7_urb.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/gfx7_urb.c
@@ -62,7 +62,7 @@
 static void
 gfx7_allocate_push_constants(struct brw_context *brw)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    /* BRW_NEW_GEOMETRY_PROGRAM */
    bool gs_present = brw->programs[MESA_SHADER_GEOMETRY];
@@ -71,7 +71,8 @@ gfx7_allocate_push_constants(struct brw_context *brw)
    bool tess_present = brw->programs[MESA_SHADER_TESS_EVAL];
 
    unsigned avail_size = 16;
-   unsigned multiplier = devinfo->max_constant_urb_size_kb / 16;
+   unsigned multiplier =
+      (devinfo->ver >= 8 || (devinfo->is_haswell && devinfo->gt == 3)) ? 2 : 1;
 
    int stages = 2 + gs_present + 2 * tess_present;
 
@@ -114,7 +115,7 @@ gfx7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
                               unsigned hs_size, unsigned ds_size,
                               unsigned gs_size, unsigned fs_size)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    unsigned offset = 0;
 
    /* From the SKL PRM, Workarounds section (#878):
@@ -172,7 +173,7 @@ gfx7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
     *
     * No such restriction exists for Haswell or Baytrail.
     */
-   if (devinfo->verx10 <= 70 && !devinfo->is_baytrail)
+   if (devinfo->ver < 8 && !devinfo->is_haswell && !devinfo->is_baytrail)
       gfx7_emit_cs_stall_flush(brw);
 }
 
@@ -206,7 +207,7 @@ void
 gfx7_upload_urb(struct brw_context *brw, unsigned vs_size,
                 bool gs_present, bool tess_present)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    /* BRW_NEW_{VS,TCS,TES,GS}_PROG_DATA */
    struct brw_vue_prog_data *prog_data[4] = {
@@ -251,7 +252,7 @@ gfx7_upload_urb(struct brw_context *brw, unsigned vs_size,
                         tess_present, gs_present, entry_size,
                         entries, start, NULL, &constrained);
 
-   if (devinfo->verx10 == 70 && !devinfo->is_baytrail)
+   if (devinfo->ver == 7 && !devinfo->is_haswell && !devinfo->is_baytrail)
       gfx7_emit_vs_workaround_flush(brw);
 
    BEGIN_BATCH(8);
diff --git a/lib/mesa/src/mesa/drivers/dri/i965/gfx8_depth_state.c b/lib/mesa/src/mesa/drivers/dri/i965/gfx8_depth_state.c
index e04135536..be54a8585 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/gfx8_depth_state.c
+++ b/lib/mesa/src/mesa/drivers/dri/i965/gfx8_depth_state.c
@@ -171,7 +171,7 @@ gfx8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
 static void
 gfx8_emit_pma_stall_workaround(struct brw_context *brw)
 {
-   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    uint32_t bits = 0;
 
    if (devinfo->ver >= 9)