diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2020-01-22 02:11:50 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2020-01-22 02:11:50 +0000 |
| commit | e1ff49e4ee5b1dee2913a8b3401989ca44a7f9f9 (patch) | |
| tree | 03c90df411d814eb423c14fd6609e6279b1db41a | |
| parent | f14390a27b66904d0b6b06fbf40be01d7ce12327 (diff) | |
Import Mesa 19.2.8
33 files changed, 720 insertions, 1710 deletions
diff --git a/lib/mesa/appveyor.yml b/lib/mesa/appveyor.yml index 5b4c9f7be..ccb84fd34 100644 --- a/lib/mesa/appveyor.yml +++ b/lib/mesa/appveyor.yml @@ -38,7 +38,6 @@ cache: - '%LOCALAPPDATA%\pip\Cache -> appveyor.yml' - win_flex_bison-2.5.15.zip - llvm-5.0.1-msvc2017-mtd.7z -- subprojects\packagecache -> subprojects\*.wrap os: Visual Studio 2017 @@ -50,21 +49,41 @@ init: environment: WINFLEXBISON_VERSION: 2.5.15 LLVM_ARCHIVE: llvm-5.0.1-msvc2017-mtd.7z - matrix: - - compiler: msvc - buildsystem: scons - - compiler: msvc - buildsystem: meson - path: C:\Python38-x64;C:\Python38-x64\Scripts;%path% install: -- cmd: .appveyor\appveyor_msvc.bat install +# Check git config +- git config core.autocrlf +# Check pip +- python --version +- python -m pip --version +# Install Mako +- python -m pip install Mako==1.0.7 +# Install pywin32 extensions, needed by SCons +- python -m pip install pypiwin32 +# Install python wheels, necessary to install SCons via pip +- python -m pip install wheel +# Install SCons +- python -m pip install scons==3.0.1 +- scons --version +# Install flex/bison +- set WINFLEXBISON_ARCHIVE=win_flex_bison-%WINFLEXBISON_VERSION%.zip +- if not exist "%WINFLEXBISON_ARCHIVE%" appveyor DownloadFile "https://github.com/lexxmark/winflexbison/releases/download/v%WINFLEXBISON_VERSION%/%WINFLEXBISON_ARCHIVE%" +- 7z x -y -owinflexbison\ "%WINFLEXBISON_ARCHIVE%" > nul +- set Path=%CD%\winflexbison;%Path% +- win_flex --version +- win_bison --version +# Download and extract LLVM +- if not exist "%LLVM_ARCHIVE%" appveyor DownloadFile "https://people.freedesktop.org/~jrfonseca/llvm/%LLVM_ARCHIVE%" +- 7z x -y "%LLVM_ARCHIVE%" > nul +- mkdir llvm\bin +- set LLVM=%CD%\llvm build_script: -- cmd: .appveyor\appveyor_msvc.bat build_script +- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=14.1 llvm=1 + +after_build: +- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=14.1 llvm=1 check -test_script: -- cmd: .appveyor\appveyor_msvc.bat test_script # It's possible to setup notification here, as described in # http://www.appveyor.com/docs/notifications#appveyor-yml-configuration , but diff --git a/lib/mesa/bin/get-pick-list.sh b/lib/mesa/bin/get-pick-list.sh index 40a1388f9..9cbef0617 100755 --- a/lib/mesa/bin/get-pick-list.sh +++ b/lib/mesa/bin/get-pick-list.sh @@ -92,7 +92,7 @@ is_revert_nomination() } # Use the last branchpoint as our limit for the search -latest_branchpoint=`git merge-base origin/master HEAD` +latest_branchpoint=`git merge-base upstream/master HEAD` # List all the commits between day 1 and the branch point... git log --reverse --pretty=%H $latest_branchpoint > already_landed @@ -103,7 +103,7 @@ git log --reverse --pretty=medium --grep="cherry picked from commit" $latest_bra sed -e 's/^[[:space:]]*(cherry picked from commit[[:space:]]*//' -e 's/)//' > already_picked # Grep for potential candidates -git log --reverse --pretty=%H -i --grep='^CC:.*mesa-stable\|^CC:.*mesa-dev\|\<fixes\>\|\<broken by\>\|This reverts commit' $latest_branchpoint..origin/master |\ +git log --reverse --pretty=%H -i --grep='^CC:.*mesa-stable\|^CC:.*mesa-dev\|\<fixes\>\|\<broken by\>\|This reverts commit' $latest_branchpoint..upstream/master |\ while read sha do # Check to see whether the patch is on the ignore list. diff --git a/lib/mesa/docs/relnotes/19.2.0.html b/lib/mesa/docs/relnotes/19.2.0.html index 4ad4e432e..b36ce8094 100644 --- a/lib/mesa/docs/relnotes/19.2.0.html +++ b/lib/mesa/docs/relnotes/19.2.0.html @@ -14,7 +14,7 @@ <iframe src="../contents.html"></iframe> <div class="content"> -<h1>Mesa 19.2.0 Release Notes / 2019.09.25</h1> +<h1>Mesa 19.2.0 Release Notes / TBD</h1> <p> Mesa 19.2.0 is a new development release. People who are concerned @@ -37,7 +37,7 @@ depends on the particular driver being used. <h2>SHA256 checksums</h2> <pre> - b060caa2a00f856431160ff7377d0e8f58f2aa48c16ee5a9e265ebdccb10852a mesa-19.2.0.tar.xz +TBD. </pre> @@ -66,6 +66,8 @@ depends on the particular driver being used. <ul> +<ul> + <li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103674">Bug 103674</a> - u_queue.c:173:7: error: implicit declaration of function 'timespec_get' is invalid in C99</li> <li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104395">Bug 104395</a> - [CTS] GTF-GL46.gtf32.GL3Tests.packed_pixels.packed_pixels tests fail on 32bit Mesa</li> @@ -117,9 +119,12 @@ depends on the particular driver being used. <li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111734">Bug 111734</a> - Geometry shader with double interpolators fails in LLVM</li> </ul> +</ul> <h2>Changes</h2> +<ul> + <p>Adam Jackson (1):</p> <ul> <li>docs: Update bug report URLs for the gitlab migration</li> @@ -439,6 +444,8 @@ depends on the particular driver being used. <li>travis: Fail build if any command in if statement fails.</li> </ul> +</ul> + </div> </body> </html> diff --git a/lib/mesa/docs/relnotes/19.2.2.html b/lib/mesa/docs/relnotes/19.2.2.html index 3d4067b1e..a9640bf7b 100644 --- a/lib/mesa/docs/relnotes/19.2.2.html +++ b/lib/mesa/docs/relnotes/19.2.2.html @@ -36,7 +36,7 @@ depends on the particular driver being used. <h2>SHA256 checksum</h2> <pre> - 7e4f0e2678bfcf3b94f533078b514f37943378a4a8604e477c888ec8a2904394 mesa-19.2.2.tar.xz +TBD. </pre> diff --git a/lib/mesa/docs/relnotes/19.2.3.html b/lib/mesa/docs/relnotes/19.2.3.html index a0081041c..d841836ec 100644 --- a/lib/mesa/docs/relnotes/19.2.3.html +++ b/lib/mesa/docs/relnotes/19.2.3.html @@ -36,7 +36,7 @@ depends on the particular driver being used. <h2>SHA256 checksum</h2> <pre> - 5ee6e42504fe41dcc9a6eba26982656a675b2550a640946f463927ed7f1c5047 mesa-19.2.3.tar.xz +TBD. </pre> diff --git a/lib/mesa/docs/relnotes/19.2.6.html b/lib/mesa/docs/relnotes/19.2.6.html index 6dc4e76a8..bc915e4dc 100644 --- a/lib/mesa/docs/relnotes/19.2.6.html +++ b/lib/mesa/docs/relnotes/19.2.6.html @@ -36,7 +36,7 @@ depends on the particular driver being used. <h2>SHA256 checksum</h2> <pre> - 9d7b24fa60c82db34788196450042a55ce6cb2d70c7a8d5c31401619b6907797 mesa-19.2.6.tar.xz +TBD. </pre> diff --git a/lib/mesa/docs/relnotes/19.2.8.html b/lib/mesa/docs/relnotes/19.2.8.html index f25c9849b..d95452a1b 100644 --- a/lib/mesa/docs/relnotes/19.2.8.html +++ b/lib/mesa/docs/relnotes/19.2.8.html @@ -36,7 +36,7 @@ depends on the particular driver being used. <h2>SHA256 checksum</h2> <pre> - cffa8fa755c7422ce014c39ca0b770a092d9e0bbae537ceb2609c106916e5a57 mesa-19.2.8.tar.xz +TBD. </pre> diff --git a/lib/mesa/src/amd/addrlib/src/chip/gfx10/gfx10_gb_reg.h b/lib/mesa/src/amd/addrlib/src/chip/gfx10/gfx10_gb_reg.h index 8526171c7..103887742 100644 --- a/lib/mesa/src/amd/addrlib/src/chip/gfx10/gfx10_gb_reg.h +++ b/lib/mesa/src/amd/addrlib/src/chip/gfx10/gfx10_gb_reg.h @@ -39,9 +39,9 @@ // #include "util/u_endian.h" -#if UTIL_ARCH_LITTLE_ENDIAN +#if defined(PIPE_ARCH_LITTLE_ENDIAN) #define LITTLEENDIAN_CPU -#elif UTIL_ARCH_BIG_ENDIAN +#elif defined(PIPE_ARCH_BIG_ENDIAN) #define BIGENDIAN_CPU #endif diff --git a/lib/mesa/src/amd/vulkan/gfx10_format_table.py b/lib/mesa/src/amd/vulkan/gfx10_format_table.py index f55b302bf..34ad5f6cd 100644 --- a/lib/mesa/src/amd/vulkan/gfx10_format_table.py +++ b/lib/mesa/src/amd/vulkan/gfx10_format_table.py @@ -21,7 +21,7 @@ # USE OR OTHER DEALINGS IN THE SOFTWARE. # """ -Script that generates the mapping from Vulkan VK_FORMAT_xxx to gfx10 +Script that generates the mapping from Gallium PIPE_FORMAT_xxx to gfx10 IMG_FORMAT_xxx enums. """ @@ -34,10 +34,12 @@ import re import sys AMD_REGISTERS = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), "../registers")) +#GALLIUM_UTIL = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), "../../auxiliary/util")) sys.path.extend([AMD_REGISTERS]) from regdb import Object, RegisterDatabase from vk_format_parse import * +#from u_format_parse import * # ---------------------------------------------------------------------------- # Hard-coded mappings @@ -66,11 +68,6 @@ HARDCODED = { 'VK_FORMAT_BC6H_SFLOAT_BLOCK': hardcoded_format('BC6_SFLOAT'), 'VK_FORMAT_BC7_UNORM_BLOCK': hardcoded_format('BC7_UNORM'), 'VK_FORMAT_BC7_SRGB_BLOCK': hardcoded_format('BC7_SRGB'), - - # DS - 'VK_FORMAT_D16_UNORM_S8_UINT': hardcoded_format('INVALID'), - 'VK_FORMAT_D24_UNORM_S8_UINT': hardcoded_format('8_24_UNORM'), - 'VK_FORMAT_D32_SFLOAT_S8_UINT': hardcoded_format('X24_8_32_FLOAT'), } @@ -85,11 +82,11 @@ header_template = mako.template.Template("""\ ##__VA_ARGS__ } static const struct gfx10_format gfx10_format_table[VK_FORMAT_RANGE_SIZE] = { -% for vk_format, args in formats: +% for pipe_format, args in formats: % if args is not None: - [${vk_format}] = FMT(${args}), + [${pipe_format}] = FMT(${args}), % else: -/* ${vk_format} is not supported */ +/* ${pipe_format} is not supported */ % endif % endfor }; @@ -117,8 +114,8 @@ class Gfx10Format(object): class Gfx10FormatMapping(object): - def __init__(self, vk_formats, gfx10_formats): - self.vk_formats = vk_formats + def __init__(self, pipe_formats, gfx10_formats): + self.pipe_formats = pipe_formats self.gfx10_formats = gfx10_formats self.plain_gfx10_formats = dict( @@ -222,17 +219,17 @@ class Gfx10FormatMapping(object): if __name__ == '__main__': - vk_formats = parse(sys.argv[1]) + pipe_formats = parse(sys.argv[1]) with open(sys.argv[2], 'r') as filp: db = RegisterDatabase.from_json(json.load(filp)) gfx10_formats = [Gfx10Format(entry) for entry in db.enum('IMG_FORMAT').entries] - mapping = Gfx10FormatMapping(vk_formats, gfx10_formats) + mapping = Gfx10FormatMapping(pipe_formats, gfx10_formats) formats = [] - for fmt in vk_formats: + for fmt in pipe_formats: if fmt.name in HARDCODED: obj = HARDCODED[fmt.name] else: diff --git a/lib/mesa/src/freedreno/ir3/ir3_sun.c b/lib/mesa/src/freedreno/ir3/ir3_sun.c index ed518736d..7fea9a073 100644 --- a/lib/mesa/src/freedreno/ir3/ir3_sun.c +++ b/lib/mesa/src/freedreno/ir3/ir3_sun.c @@ -38,7 +38,7 @@ * is computed in multiple paths into a block, I think we should only have to * consider the worst-case. * - * [1] https://www.cs.princeton.edu/~appel/papers/sun.pdf + * [1] https://pdfs.semanticscholar.org/ae53/6010b214612c2571f483354c264b0b39c545.pdf */ static unsigned @@ -96,11 +96,11 @@ ir3_sun(struct ir3 *ir) ir3_clear_mark(ir); - struct ir3_instruction *out; - foreach_output(out, ir) - max = MAX2(max, number_instr(out)); + for (unsigned i = 0; i < ir->noutputs; i++) + if (ir->outputs[i]) + max = MAX2(max, number_instr(ir->outputs[i])); - foreach_block (block, &ir->block_list) { + list_for_each_entry (struct ir3_block, block, &ir->block_list, node) { for (unsigned i = 0; i < block->keeps_count; i++) max = MAX2(max, number_instr(block->keeps[i])); if (block->condition) diff --git a/lib/mesa/src/freedreno/registers/a2xx.xml b/lib/mesa/src/freedreno/registers/a2xx.xml index 88cb35542..1b0bf44bd 100644 --- a/lib/mesa/src/freedreno/registers/a2xx.xml +++ b/lib/mesa/src/freedreno/registers/a2xx.xml @@ -834,191 +834,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <value value="56" name="RBPERF_ACCUM_CAM_HIT_FLUSHING"/> </enum> -<enum name="a2xx_mh_perfcnt_select"> - <value value="0" name="CP_R0_REQUESTS"/> - <value value="1" name="CP_R1_REQUESTS"/> - <value value="2" name="CP_R2_REQUESTS"/> - <value value="3" name="CP_R3_REQUESTS"/> - <value value="4" name="CP_R4_REQUESTS"/> - <value value="5" name="CP_TOTAL_READ_REQUESTS"/> - <value value="6" name="CP_TOTAL_WRITE_REQUESTS"/> - <value value="7" name="CP_TOTAL_REQUESTS"/> - <value value="8" name="CP_DATA_BYTES_WRITTEN"/> - <value value="9" name="CP_WRITE_CLEAN_RESPONSES"/> - <value value="10" name="CP_R0_READ_BURSTS_RECEIVED"/> - <value value="11" name="CP_R1_READ_BURSTS_RECEIVED"/> - <value value="12" name="CP_R2_READ_BURSTS_RECEIVED"/> - <value value="13" name="CP_R3_READ_BURSTS_RECEIVED"/> - <value value="14" name="CP_R4_READ_BURSTS_RECEIVED"/> - <value value="15" name="CP_TOTAL_READ_BURSTS_RECEIVED"/> - <value value="16" name="CP_R0_DATA_BEATS_READ"/> - <value value="17" name="CP_R1_DATA_BEATS_READ"/> - <value value="18" name="CP_R2_DATA_BEATS_READ"/> - <value value="19" name="CP_R3_DATA_BEATS_READ"/> - <value value="20" name="CP_R4_DATA_BEATS_READ"/> - <value value="21" name="CP_TOTAL_DATA_BEATS_READ"/> - <value value="22" name="VGT_R0_REQUESTS"/> - <value value="23" name="VGT_R1_REQUESTS"/> - <value value="24" name="VGT_TOTAL_REQUESTS"/> - <value value="25" name="VGT_R0_READ_BURSTS_RECEIVED"/> - <value value="26" name="VGT_R1_READ_BURSTS_RECEIVED"/> - <value value="27" name="VGT_TOTAL_READ_BURSTS_RECEIVED"/> - <value value="28" name="VGT_R0_DATA_BEATS_READ"/> - <value value="29" name="VGT_R1_DATA_BEATS_READ"/> - <value value="30" name="VGT_TOTAL_DATA_BEATS_READ"/> - <value value="31" name="TC_TOTAL_REQUESTS"/> - <value value="32" name="TC_ROQ_REQUESTS"/> - <value value="33" name="TC_INFO_SENT"/> - <value value="34" name="TC_READ_BURSTS_RECEIVED"/> - <value value="35" name="TC_DATA_BEATS_READ"/> - <value value="36" name="TCD_BURSTS_READ"/> - <value value="37" name="RB_REQUESTS"/> - <value value="38" name="RB_DATA_BYTES_WRITTEN"/> - <value value="39" name="RB_WRITE_CLEAN_RESPONSES"/> - <value value="40" name="AXI_READ_REQUESTS_ID_0"/> - <value value="41" name="AXI_READ_REQUESTS_ID_1"/> - <value value="42" name="AXI_READ_REQUESTS_ID_2"/> - <value value="43" name="AXI_READ_REQUESTS_ID_3"/> - <value value="44" name="AXI_READ_REQUESTS_ID_4"/> - <value value="45" name="AXI_READ_REQUESTS_ID_5"/> - <value value="46" name="AXI_READ_REQUESTS_ID_6"/> - <value value="47" name="AXI_READ_REQUESTS_ID_7"/> - <value value="48" name="AXI_TOTAL_READ_REQUESTS"/> - <value value="49" name="AXI_WRITE_REQUESTS_ID_0"/> - <value value="50" name="AXI_WRITE_REQUESTS_ID_1"/> - <value value="51" name="AXI_WRITE_REQUESTS_ID_2"/> - <value value="52" name="AXI_WRITE_REQUESTS_ID_3"/> - <value value="53" name="AXI_WRITE_REQUESTS_ID_4"/> - <value value="54" name="AXI_WRITE_REQUESTS_ID_5"/> - <value value="55" name="AXI_WRITE_REQUESTS_ID_6"/> - <value value="56" name="AXI_WRITE_REQUESTS_ID_7"/> - <value value="57" name="AXI_TOTAL_WRITE_REQUESTS"/> - <value value="58" name="AXI_TOTAL_REQUESTS_ID_0"/> - <value value="59" name="AXI_TOTAL_REQUESTS_ID_1"/> - <value value="60" name="AXI_TOTAL_REQUESTS_ID_2"/> - <value value="61" name="AXI_TOTAL_REQUESTS_ID_3"/> - <value value="62" name="AXI_TOTAL_REQUESTS_ID_4"/> - <value value="63" name="AXI_TOTAL_REQUESTS_ID_5"/> - <value value="64" name="AXI_TOTAL_REQUESTS_ID_6"/> - <value value="65" name="AXI_TOTAL_REQUESTS_ID_7"/> - <value value="66" name="AXI_TOTAL_REQUESTS"/> - <value value="67" name="AXI_READ_CHANNEL_BURSTS_ID_0"/> - <value value="68" name="AXI_READ_CHANNEL_BURSTS_ID_1"/> - <value value="69" name="AXI_READ_CHANNEL_BURSTS_ID_2"/> - <value value="70" name="AXI_READ_CHANNEL_BURSTS_ID_3"/> - <value value="71" name="AXI_READ_CHANNEL_BURSTS_ID_4"/> - <value value="72" name="AXI_READ_CHANNEL_BURSTS_ID_5"/> - <value value="73" name="AXI_READ_CHANNEL_BURSTS_ID_6"/> - <value value="74" name="AXI_READ_CHANNEL_BURSTS_ID_7"/> - <value value="75" name="AXI_READ_CHANNEL_TOTAL_BURSTS"/> - <value value="76" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0"/> - <value value="77" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1"/> - <value value="78" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2"/> - <value value="79" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3"/> - <value value="80" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4"/> - <value value="81" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5"/> - <value value="82" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6"/> - <value value="83" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7"/> - <value value="84" name="AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ"/> - <value value="85" name="AXI_WRITE_CHANNEL_BURSTS_ID_0"/> - <value value="86" name="AXI_WRITE_CHANNEL_BURSTS_ID_1"/> - <value value="87" name="AXI_WRITE_CHANNEL_BURSTS_ID_2"/> - <value value="88" name="AXI_WRITE_CHANNEL_BURSTS_ID_3"/> - <value value="89" name="AXI_WRITE_CHANNEL_BURSTS_ID_4"/> - <value value="90" name="AXI_WRITE_CHANNEL_BURSTS_ID_5"/> - <value value="91" name="AXI_WRITE_CHANNEL_BURSTS_ID_6"/> - <value value="92" name="AXI_WRITE_CHANNEL_BURSTS_ID_7"/> - <value value="93" name="AXI_WRITE_CHANNEL_TOTAL_BURSTS"/> - <value value="94" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0"/> - <value value="95" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1"/> - <value value="96" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2"/> - <value value="97" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3"/> - <value value="98" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4"/> - <value value="99" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5"/> - <value value="100" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6"/> - <value value="101" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7"/> - <value value="102" name="AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN"/> - <value value="103" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0"/> - <value value="104" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1"/> - <value value="105" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2"/> - <value value="106" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3"/> - <value value="107" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4"/> - <value value="108" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5"/> - <value value="109" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6"/> - <value value="110" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7"/> - <value value="111" name="AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES"/> - <value value="112" name="TOTAL_MMU_MISSES"/> - <value value="113" name="MMU_READ_MISSES"/> - <value value="114" name="MMU_WRITE_MISSES"/> - <value value="115" name="TOTAL_MMU_HITS"/> - <value value="116" name="MMU_READ_HITS"/> - <value value="117" name="MMU_WRITE_HITS"/> - <value value="118" name="SPLIT_MODE_TC_HITS"/> - <value value="119" name="SPLIT_MODE_TC_MISSES"/> - <value value="120" name="SPLIT_MODE_NON_TC_HITS"/> - <value value="121" name="SPLIT_MODE_NON_TC_MISSES"/> - <value value="122" name="STALL_AWAITING_TLB_MISS_FETCH"/> - <value value="123" name="MMU_TLB_MISS_READ_BURSTS_RECEIVED"/> - <value value="124" name="MMU_TLB_MISS_DATA_BEATS_READ"/> - <value value="125" name="CP_CYCLES_HELD_OFF"/> - <value value="126" name="VGT_CYCLES_HELD_OFF"/> - <value value="127" name="TC_CYCLES_HELD_OFF"/> - <value value="128" name="TC_ROQ_CYCLES_HELD_OFF"/> - <value value="129" name="TC_CYCLES_HELD_OFF_TCD_FULL"/> - <value value="130" name="RB_CYCLES_HELD_OFF"/> - <value value="131" name="TOTAL_CYCLES_ANY_CLNT_HELD_OFF"/> - <value value="132" name="TLB_MISS_CYCLES_HELD_OFF"/> - <value value="133" name="AXI_READ_REQUEST_HELD_OFF"/> - <value value="134" name="AXI_WRITE_REQUEST_HELD_OFF"/> - <value value="135" name="AXI_REQUEST_HELD_OFF"/> - <value value="136" name="AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT"/> - <value value="137" name="AXI_WRITE_DATA_HELD_OFF"/> - <value value="138" name="CP_SAME_PAGE_BANK_REQUESTS"/> - <value value="139" name="VGT_SAME_PAGE_BANK_REQUESTS"/> - <value value="140" name="TC_SAME_PAGE_BANK_REQUESTS"/> - <value value="141" name="TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS"/> - <value value="142" name="RB_SAME_PAGE_BANK_REQUESTS"/> - <value value="143" name="TOTAL_SAME_PAGE_BANK_REQUESTS"/> - <value value="144" name="CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/> - <value value="145" name="VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/> - <value value="146" name="TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/> - <value value="147" name="RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/> - <value value="148" name="TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT"/> - <value value="149" name="TOTAL_MH_READ_REQUESTS"/> - <value value="150" name="TOTAL_MH_WRITE_REQUESTS"/> - <value value="151" name="TOTAL_MH_REQUESTS"/> - <value value="152" name="MH_BUSY"/> - <value value="153" name="CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/> - <value value="154" name="VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/> - <value value="155" name="TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/> - <value value="156" name="RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/> - <value value="157" name="TC_ROQ_N_VALID_ENTRIES"/> - <value value="158" name="ARQ_N_ENTRIES"/> - <value value="159" name="WDB_N_ENTRIES"/> - <value value="160" name="MH_READ_LATENCY_OUTST_REQ_SUM"/> - <value value="161" name="MC_READ_LATENCY_OUTST_REQ_SUM"/> - <value value="162" name="MC_TOTAL_READ_REQUESTS"/> - <value value="163" name="ELAPSED_CYCLES_MH_GATED_CLK"/> - <value value="164" name="ELAPSED_CLK_CYCLES"/> - <value value="165" name="CP_W_16B_REQUESTS"/> - <value value="166" name="CP_W_32B_REQUESTS"/> - <value value="167" name="TC_16B_REQUESTS"/> - <value value="168" name="TC_32B_REQUESTS"/> - <value value="169" name="PA_REQUESTS"/> - <value value="170" name="PA_DATA_BYTES_WRITTEN"/> - <value value="171" name="PA_WRITE_CLEAN_RESPONSES"/> - <value value="172" name="PA_CYCLES_HELD_OFF"/> - <value value="173" name="AXI_READ_REQUEST_DATA_BEATS_ID_0"/> - <value value="174" name="AXI_READ_REQUEST_DATA_BEATS_ID_1"/> - <value value="175" name="AXI_READ_REQUEST_DATA_BEATS_ID_2"/> - <value value="176" name="AXI_READ_REQUEST_DATA_BEATS_ID_3"/> - <value value="177" name="AXI_READ_REQUEST_DATA_BEATS_ID_4"/> - <value value="178" name="AXI_READ_REQUEST_DATA_BEATS_ID_5"/> - <value value="179" name="AXI_READ_REQUEST_DATA_BEATS_ID_6"/> - <value value="180" name="AXI_READ_REQUEST_DATA_BEATS_ID_7"/> - <value value="181" name="AXI_TOTAL_READ_REQUEST_DATA_BEATS"/> -</enum> - <domain name="A2XX" width="32"> <bitset name="a2xx_vgt_current_bin_id_min_max" inline="yes"> @@ -1572,8 +1387,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x2357" name="A225_GRAS_UCP5W"/> <reg32 offset="0x2360" name="A225_GRAS_UCP_ENABLED"/> <reg32 offset="0x2380" name="PA_SU_POLY_OFFSET_FRONT_SCALE"/> - <reg32 offset="0x2381" name="PA_SU_POLY_OFFSET_FRONT_OFFSET"/> - <reg32 offset="0x2382" name="PA_SU_POLY_OFFSET_BACK_SCALE"/> <reg32 offset="0x2383" name="PA_SU_POLY_OFFSET_BACK_OFFSET"/> <reg32 offset="0x4000" name="SQ_CONSTANT_0"/> <reg32 offset="0x4800" name="SQ_FETCH_0"/> @@ -1687,6 +1500,12 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0a4c" name="MH_PERFCOUNTER1_LOW"/> <reg32 offset="0x0a49" name="MH_PERFCOUNTER0_HI"/> <reg32 offset="0x0a4d" name="MH_PERFCOUNTER1_HI"/> + <reg32 offset="0x0395" name="RBBM_PERFCOUNTER1_SELECT"/> + <reg32 offset="0x0397" name="RBBM_PERFCOUNTER1_LO"/> + <reg32 offset="0x0398" name="RBBM_PERFCOUNTER1_HI"/> + <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT"/> + <reg32 offset="0x0446" name="CP_PERFCOUNTER_LO"/> + <reg32 offset="0x0447" name="CP_PERFCOUNTER_HI"/> <reg32 offset="0x0f04" name="RB_PERFCOUNTER0_SELECT"/> <reg32 offset="0x0f08" name="RB_PERFCOUNTER0_LOW"/> <reg32 offset="0x0f09" name="RB_PERFCOUNTER0_HI"/> @@ -1740,11 +1559,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <value name="SQ_TEX_BORDER_COLOR_ACBCRY_BLACK" value="3"/> </enum> <enum name="sq_tex_sign"> - <value name="SQ_TEX_SIGN_UNSIGNED" value="0"/> + <value name="SQ_TEX_SIGN_UNISIGNED" value="0"/> <value name="SQ_TEX_SIGN_SIGNED" value="1"/> <!-- biased: 2*color-1 (range -1,1 when sampling) --> - <value name="SQ_TEX_SIGN_UNSIGNED_BIASED" value="2"/> - <!-- gamma: sRGB to linear - doesn't seem to work on adreno? --> + <value name="SQ_TEX_SIGN_UNISIGNED_BIASED" value="2"/> + <!-- gamma: sRGB to linear? --> <value name="SQ_TEX_SIGN_GAMMA" value="3"/> </enum> <enum name="sq_tex_endian"> @@ -1799,7 +1618,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <bitfield name="SWIZ_Y" low="4" high="6" type="sq_tex_swiz"/> <bitfield name="SWIZ_Z" low="7" high="9" type="sq_tex_swiz"/> <bitfield name="SWIZ_W" low="10" high="12" type="sq_tex_swiz"/> - <bitfield name="EXP_ADJUST" low="13" high="18" type="int"/> + <bitfield name="EXP_ADJUST" low="13" high="18" type="uint"/> <bitfield name="XY_MAG_FILTER" low="19" high="20" type="sq_tex_filter"/> <bitfield name="XY_MIN_FILTER" low="21" high="22" type="sq_tex_filter"/> <bitfield name="MIP_FILTER" low="23" high="24" type="sq_tex_filter"/> diff --git a/lib/mesa/src/freedreno/registers/a3xx.xml b/lib/mesa/src/freedreno/registers/a3xx.xml index 93b14e139..bf93b0cb0 100644 --- a/lib/mesa/src/freedreno/registers/a3xx.xml +++ b/lib/mesa/src/freedreno/registers/a3xx.xml @@ -1186,6 +1186,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x2243" name="VFD_INDEX_MAX" type="uint"/> <reg32 offset="0x2244" name="VFD_INSTANCEID_OFFSET" type="uint"/> <reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/> + <reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/> <array offset="0x2246" name="VFD_FETCH" stride="2" length="16"> <reg32 offset="0x0" name="INSTR_0"> <bitfield name="FETCHSIZE" low="0" high="6" type="uint"/> diff --git a/lib/mesa/src/freedreno/registers/a4xx.xml b/lib/mesa/src/freedreno/registers/a4xx.xml index 0fa914847..5012e1bd3 100644 --- a/lib/mesa/src/freedreno/registers/a4xx.xml +++ b/lib/mesa/src/freedreno/registers/a4xx.xml @@ -1304,6 +1304,8 @@ perhaps they should be taken with a grain of salt <reg32 offset="0x0113" name="RBBM_PERFCTR_UCHE_7_HI"/> <reg32 offset="0x0114" name="RBBM_PERFCTR_TP_0_LO"/> <reg32 offset="0x0115" name="RBBM_PERFCTR_TP_0_HI"/> + <reg32 offset="0x0114" name="RBBM_PERFCTR_TP_0_LO"/> + <reg32 offset="0x0115" name="RBBM_PERFCTR_TP_0_HI"/> <reg32 offset="0x0116" name="RBBM_PERFCTR_TP_1_LO"/> <reg32 offset="0x0117" name="RBBM_PERFCTR_TP_1_HI"/> <reg32 offset="0x0118" name="RBBM_PERFCTR_TP_2_LO"/> @@ -1433,6 +1435,7 @@ perhaps they should be taken with a grain of salt <reg32 offset="0x0099" name="RBBM_SP_REGFILE_SLEEP_CNTL_0"/> <reg32 offset="0x009a" name="RBBM_SP_REGFILE_SLEEP_CNTL_1"/> + <reg32 offset="0x0168" name="RBBM_PERFCTR_PWR_1_LO"/> <reg32 offset="0x0170" name="RBBM_PERFCTR_CTL"/> <reg32 offset="0x0171" name="RBBM_PERFCTR_LOAD_CMD0"/> <reg32 offset="0x0172" name="RBBM_PERFCTR_LOAD_CMD1"/> diff --git a/lib/mesa/src/freedreno/registers/a5xx.xml b/lib/mesa/src/freedreno/registers/a5xx.xml index 42726fceb..16b8d2c7b 100644 --- a/lib/mesa/src/freedreno/registers/a5xx.xml +++ b/lib/mesa/src/freedreno/registers/a5xx.xml @@ -1385,6 +1385,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0468" name="RBBM_PERFCTR_LOAD_CMD3"/> <reg32 offset="0x0469" name="RBBM_PERFCTR_LOAD_VALUE_LO"/> <reg32 offset="0x046a" name="RBBM_PERFCTR_LOAD_VALUE_HI"/> + <reg32 offset="0x046b" name="RBBM_PERFCTR_RBBM_SEL_0"/> + <reg32 offset="0x046c" name="RBBM_PERFCTR_RBBM_SEL_1"/> + <reg32 offset="0x046d" name="RBBM_PERFCTR_RBBM_SEL_2"/> + <reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3"/> <reg32 offset="0x046f" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/> <reg32 offset="0x04ed" name="RBBM_AHB_ERROR"/> <reg32 offset="0x0504" name="RBBM_CFG_DBGBUS_EVENT_LOGIC"/> @@ -1703,6 +1707,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0xa892" name="GPMU_PWR_COL_INTER_FRAME_CTRL"/> <reg32 offset="0xa893" name="GPMU_PWR_COL_INTER_FRAME_HYST"/> <reg32 offset="0xa894" name="GPMU_PWR_COL_BINNING_CTRL"/> + <reg32 offset="0xa8a3" name="GPMU_CLOCK_THROTTLE_CTRL"/> <reg32 offset="0xa8c1" name="GPMU_WFI_CONFIG"/> <reg32 offset="0xa8d6" name="GPMU_RBBM_INTR_INFO"/> <reg32 offset="0xa8d8" name="GPMU_CM3_SYSRESET"/> diff --git a/lib/mesa/src/freedreno/registers/a6xx.xml b/lib/mesa/src/freedreno/registers/a6xx.xml index 2cfa49f0a..6868ed552 100644 --- a/lib/mesa/src/freedreno/registers/a6xx.xml +++ b/lib/mesa/src/freedreno/registers/a6xx.xml @@ -26,11 +26,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <value value="0x18" name="RB6_R16_UINT"/> <value value="0x19" name="RB6_R16_SINT"/> <value value="0x30" name="RB6_R8G8B8A8_UNORM"/> - <value value="0x31" name="RB6_R8G8B8X8_UNORM"/> <!-- 32 bpp format, samples 1 for alpha --> + <value value="0x31" name="RB6_R8G8B8_UNORM"/> <value value="0x32" name="RB6_R8G8B8A8_SNORM"/> <value value="0x33" name="RB6_R8G8B8A8_UINT"/> <value value="0x34" name="RB6_R8G8B8A8_SINT"/> - <value value="0x36" name="RB6_R10G10B10A2_FLOAT16"/> <!-- float16 for 2d blit? --> <value value="0x37" name="RB6_R10G10B10A2_UNORM"/> <!-- GL_RGB10_A2 --> <value value="0x3a" name="RB6_R10G10B10A2_UINT"/> <!-- GL_RGB10_A2UI --> <value value="0x42" name="RB6_R11G11B10_FLOAT"/> <!-- GL_R11F_G11F_B10F --> @@ -53,8 +52,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <value value="0x82" name="RB6_R32G32B32A32_FLOAT"/> <value value="0x83" name="RB6_R32G32B32A32_UINT"/> <value value="0x84" name="RB6_R32G32B32A32_SINT"/> - <value value="0x91" name="RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/> - <value value="0xa0" name="RB6_Z24_UNORM_S8_UINT"/> + <value value="0x91" name="RB6_Z24_UNORM_S8_UINT"/> + <value value="0xa0" name="RB6_X8Z24_UNORM"/> </enum> <!-- these might be same as a5xx --> @@ -231,9 +230,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <value value="0xcc" name="TFMT6_ASTC_10x10"/> <value value="0xcd" name="TFMT6_ASTC_12x10"/> <value value="0xce" name="TFMT6_ASTC_12x12"/> - - <!-- same as X8Z24_UNORM but for sampling stencil (integer, 2nd channel) --> - <value value="0xea" name="TFMT6_S8Z24_UINT"/> </enum> <enum name="a6xx_tex_fetchsize"> @@ -948,7 +944,7 @@ blending? The one exception is that 16b unorm and 32b float use the same value... maybe 16b unorm is uncommon enough that it was just easier to upconvert to 32b float internally? - 8b unorm: 10 (sometimes 0, is the high bit part of something else?) + 8b unorm: 10 16b unorm: 4 32b int: 7 @@ -965,12 +961,10 @@ to upconvert to 32b float internally? <value value="0x5" name="R2D_INT8"/> <value value="0x4" name="R2D_FLOAT32"/> <value value="0x3" name="R2D_FLOAT16"/> - <value value="0x1" name="R2D_UNORM8_SRGB"/> - <value value="0x0" name="R2D_RAW"/> </enum> <domain name="A6XX" width="32"> - <bitset name="A6XX_RBBM_INT_0_MASK" inline="yes"> + <bitset name="A6XX_RBBM_INT_0_MASK"> <bitfield name="RBBM_GPU_IDLE" pos="0"/> <bitfield name="CP_AHB_ERROR" pos="1"/> <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/> @@ -1376,36 +1370,6 @@ to upconvert to 32b float internally? <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/> <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/> <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/> - - <!--- - This block of registers aren't tied to perf counters. They - count various geometry stats, for example number of - vertices in, number of primnitives assembled etc. - --> - - <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in --> - <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/> - <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out --> - <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/> - <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in --> - <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/> - <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out --> - <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/> - <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in --> - <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/> - <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out --> - <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/> - <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in --> - <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/> - <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out --> - <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/> - <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out --> - <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/> - <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in --> - <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/> - <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/> - <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/> - <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/> <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/> <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/> @@ -1780,7 +1744,6 @@ to upconvert to 32b float internally? </reg32> <reg32 offset="0x0c03" name="VSC_SIZE_ADDRESS_LO"/> <reg32 offset="0x0c04" name="VSC_SIZE_ADDRESS_HI"/> - <reg64 offset="0x0c03" name="VSC_SIZE_ADDRESS" type="waddress"/> <reg32 offset="0x0c06" name="VSC_BIN_COUNT"> <bitfield name="NX" low="1" high="10" type="uint"/> <bitfield name="NY" low="11" high="20" type="uint"/> @@ -1821,12 +1784,10 @@ to upconvert to 32b float internally? --> <reg32 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS_LO"/> <reg32 offset="0x0c31" name="VSC_PIPE_DATA2_ADDRESS_HI"/> - <reg64 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS" type="waddress"/> <reg32 offset="0x0c32" name="VSC_PIPE_DATA2_PITCH"/> <reg32 offset="0x0c33" name="VSC_PIPE_DATA2_ARRAY_PITCH" shr="4" type="uint"/> <reg32 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS_LO"/> <reg32 offset="0x0c35" name="VSC_PIPE_DATA_ADDRESS_HI"/> - <reg64 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS" type="waddress"/> <reg32 offset="0x0c36" name="VSC_PIPE_DATA_PITCH"/> <reg32 offset="0x0c37" name="VSC_PIPE_DATA_ARRAY_PITCH" shr="4" type="uint"/> @@ -1862,20 +1823,9 @@ to upconvert to 32b float internally? <reg32 offset="0x8000" name="GRAS_UNKNOWN_8000"/> <reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/> - <reg32 offset="0x8002" name="GRAS_UNKNOWN_8002"/> - <reg32 offset="0x8003" name="GRAS_UNKNOWN_8003"/> - - <enum name="a6xx_layer_type"> - <value value="0x0" name="LAYER_MULTISAMPLE_ARRAY"/> - <value value="0x1" name="LAYER_3D"/> - <value value="0x2" name="LAYER_CUBEMAP"/> - <value value="0x3" name="LAYER_2D_ARRAY"/> - </enum> - <reg32 offset="0x8004" name="GRAS_LAYER_CNTL"> - <bitfield name="LAYERED" pos="0" type="boolean"/> - <bitfield name="TYPE" low="1" high="2" type="a6xx_layer_type"/> - </reg32> + <!-- always 0x0 ? --> + <reg32 offset="0x8004" name="GRAS_UNKNOWN_8004"/> <reg32 offset="0x8005" name="GRAS_CNTL"> <!-- see also RB_RENDER_CONTROL0 --> @@ -1939,12 +1889,6 @@ to upconvert to 32b float internally? <!-- always 0x0 ? --> <reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/> - <reg32 offset="0x809c" name="GRAS_UNKNOWN_809C"> - <bitfield name="GS_WRITES_LAYER" pos="0" type="boolean"/> - </reg32> - - <reg32 offset="0x809d" name="GRAS_UNKNOWN_809D"/> - <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/> <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL"> @@ -1981,9 +1925,10 @@ to upconvert to 32b float internally? <bitfield name="LRZ_WRITE" pos="1" type="boolean"/> <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc> <bitfield name="GREATER" pos="2" type="boolean"/> + <!-- set at end of batch that had LRZ enabled (to flush/disable it?) --> <bitfield name="UNK3" pos="3" type="boolean"/> <!-- set when depth-test + depth-write enabled --> - <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/> + <bitfield name="UNK4" pos="4" type="boolean"/> </reg32> <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/> <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO"> @@ -1991,14 +1936,12 @@ to upconvert to 32b float internally? </reg32> <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/> <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/> - <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" type="waddress"/> <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH"> <bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/> <bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? --> </reg32> <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/> <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/> - <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" type="waddress"/> <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL"> <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> @@ -2011,22 +1954,19 @@ to upconvert to 32b float internally? <value value="0x1" name="ROTATE_90"/> <value value="0x2" name="ROTATE_180"/> <value value="0x3" name="ROTATE_270"/> - <value value="0x4" name="ROTATE_HFLIP"/> - <value value="0x5" name="ROTATE_VFLIP"/> </enum> <bitset name="a6xx_2d_blit_cntl" inline="yes"> - <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/> - <bitfield name="SOLID_COLOR" pos="7" type="boolean"/> + <bitfield name="ROTATE" low="0" high="1" type="a6xx_rotation"/> + <bitfield name="HORIZONTAL_FLIP" low="2" high="2" type="boolean"/> + <bitfield name="SOLID_COLOR" low="4" high="4" type="boolean"/> <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_color_fmt"/> <bitfield name="SCISSOR" pos="16" type="boolean"/> - - <bitfield name="UNK" low="17" high="18" type="uint"/> - - <!-- required when blitting D24S8/D24X8 --> - <bitfield name="D24S8" pos="19" type="boolean"/> - <!-- some sort of channel mask, disabled channels are set to zero ? --> - <bitfield name="MASK" low="20" high="23"/> + <!-- double check these: + <bitfield name="FLAGS" pos="18" type="boolean"/> + <bitfield name="TILE_MODE" low="20" high="21" type="a6xx_tile_mode"/> + <bitfield name="COLOR_SWAP" low="22" high="23" type="a3xx_color_swap"/> + --> <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/> </bitset> @@ -2210,9 +2150,6 @@ to upconvert to 32b float internally? --> <reg32 offset="0x5" name="BASE_LO"/> <reg32 offset="0x6" name="BASE_HI"/> - - <reg64 offset="0x5" name="BASE" type="waddress"/> - <reg32 offset="0x7" name="BASE_GMEM"/> </array> @@ -2256,7 +2193,6 @@ to upconvert to 32b float internally? </reg32> <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/> <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/> - <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress"/> <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/> <!-- always 0x0 ? --> @@ -2294,7 +2230,6 @@ to upconvert to 32b float internally? </reg32> <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/> <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/> - <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress"/> <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/> <reg32 offset="0x8887" name="RB_STENCILREF"> <bitfield name="REF" low="0" high="7"/> @@ -2333,13 +2268,11 @@ to upconvert to 32b float internally? <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_color_fmt"/> <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/> </reg32> - <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress"/> <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/> <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/> <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/> <!-- array-pitch is size of layer --> <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/> - <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress"/> <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/> <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/> <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH"> @@ -2374,7 +2307,6 @@ to upconvert to 32b float internally? <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/> <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/> - <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress"/> <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH"> <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> @@ -2382,7 +2314,6 @@ to upconvert to 32b float internally? <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8"> <reg32 offset="0" name="ADDR_LO"/> <reg32 offset="1" name="ADDR_HI"/> - <reg64 offset="0" name="ADDR" type="waddress"/> <reg32 offset="2" name="PITCH"> <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> <!-- ??? --> @@ -2394,20 +2325,13 @@ to upconvert to 32b float internally? <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/> <reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/> - <bitset name="a6xx_2d_surf_info" inline="yes"> + <reg32 offset="0x8c17" name="RB_2D_DST_INFO"> <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/> <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled --> <bitfield name="FLAGS" pos="12" type="boolean"/> - <bitfield name="SRGB" pos="13" type="boolean"/> - <!-- the rest is only for src --> - <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/> - <bitfield name="FILTER" pos="16" type="boolean"/> - <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/> - </bitset> - - <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/> + </reg32> <reg32 offset="0x8c18" name="RB_2D_DST_LO"/> <reg32 offset="0x8c19" name="RB_2D_DST_HI"/> <reg32 offset="0x8c1a" name="RB_2D_DST_SIZE"> @@ -2434,20 +2358,11 @@ to upconvert to 32b float internally? <reg32 offset="0x8e07" name="RB_CCU_CNTL"/> <!-- always 7c400004 or 10000000 --> - <reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/> - <!-- always 0x00ffff00 ? */ --> <reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/> - <reg32 offset="0x9102" name="VPC_UNKNOWN_9102"/> - <reg32 offset="0x9103" name="VPC_UNKNOWN_9103"/> <reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/> - <reg32 offset="0x9105" name="VPC_UNKNOWN_9105"> - <bitfield name="LAYERLOC" low="0" high="7" type="uint"/> - </reg32> - - <reg32 offset="0x9106" name="VPC_UNKNOWN_9106"/> <reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/> <reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/> @@ -2479,18 +2394,12 @@ to upconvert to 32b float internally? <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/> <bitfield name="B_EN" pos="23" type="boolean"/> </reg32> - - <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/> - <reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/> - <array offset="0x921a" name="VPC_SO" stride="7" length="4"> - <reg64 offset="0" name="BUFFER_BASE" type="waddress"/> <reg32 offset="0" name="BUFFER_BASE_LO"/> <reg32 offset="1" name="BUFFER_BASE_HI"/> <reg32 offset="2" name="BUFFER_SIZE"/> <reg32 offset="3" name="NCOMP"/> <!-- component count --> <reg32 offset="4" name="BUFFER_OFFSET"/> - <reg64 offset="5" name="FLUSH_BASE" type="waddress"/> <reg32 offset="5" name="FLUSH_BASE_LO"/> <reg32 offset="6" name="FLUSH_BASE_HI"/> </array> @@ -2510,7 +2419,7 @@ to upconvert to 32b float internally? hw streamout (rather than stg instructions in shader) </doc> <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> - <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/> + <bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/> <!-- This seems to be the OUTLOC for the psize output. It could possibly be the max-OUTLOC position, but it is only set when VS writes psize @@ -2519,28 +2428,16 @@ to upconvert to 32b float internally? <bitfield name="PSIZELOC" low="16" high="23" type="uint"/> </reg32> - <reg32 offset="0x9302" name="VPC_PACK_GS"> + <reg32 offset="0x9303" name="VPC_PACK_3"> <doc> + domain shader version + num of varyings plus four for gl_Position (plus one if gl_PointSize) plus # of transform-feedback (streamout) varyings if using the hw streamout (rather than stg instructions in shader) </doc> <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> - <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/> - <!-- - This seems to be the OUTLOC for the psize output. It could possibly - be the max-OUTLOC position, but it is only set when VS writes psize - (and blob always puts psize at highest OUTLOC) - --> - <bitfield name="PSIZELOC" low="16" high="23" type="uint"/> - </reg32> - - <reg32 offset="0x9303" name="VPC_PACK_3"> - <doc> - domain shader version of VPC_PACK - </doc> - <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> - <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/> + <bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/> <!-- This seems to be the OUTLOC for the psize output. It could possibly be the max-OUTLOC position, but it is only set when VS writes psize @@ -2581,16 +2478,10 @@ to upconvert to 32b float internally? <value value="0x3" name="TESS_FRACTIONAL_EVEN"/> </enum> - <enum name="a6xx_tess_output"> - <value value="0x0" name="TESS_POINTS"/> - <value value="0x1" name="TESS_LINES"/> - <value value="0x2" name="TESS_CW_TRIS"/> - <value value="0x3" name="TESS_CCW_TRIS"/> - </enum> - <reg32 offset="0x9802" name="PC_TESS_CNTL"> <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> - <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/> + <bitfield name="CCW" pos="2" type="boolean"/> + <bitfield name="PRIMITIVES" pos="3" type="boolean"/> </reg32> <!-- probably: --> @@ -2623,16 +2514,6 @@ to upconvert to 32b float internally? <bitfield name="PSIZE" pos="8" type="boolean"/> </reg32> - <reg32 offset="0x9b02" name="PC_PRIMITIVE_CNTL_2"> - <doc> - geometry shader - </doc> - <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/> - <bitfield name="PSIZE" pos="8" type="boolean"/> - <bitfield name="LAYER" pos="9" type="boolean"/> - <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/> - </reg32> - <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3"> <doc> hull shader? @@ -2655,22 +2536,8 @@ to upconvert to 32b float internally? <bitfield name="PSIZE" pos="8" type="boolean"/> </reg32> - <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5"> - <doc> - geometry shader - </doc> - <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/> - <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/> - <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/> - </reg32> - - <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6"> - <doc> - size in vec4s of per-primitive storage for gs - </doc> - <bitfield name="STRIDE_IN_VPC" low="0" high="8" type="uint"/> - </reg32> - + <!-- always 0x0 ? --> + <reg32 offset="0x9b06" name="PC_UNKNOWN_9B06"/> <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/> <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/> @@ -2699,7 +2566,6 @@ to upconvert to 32b float internally? <reg32 offset="0xa004" name="VFD_CONTROL_4"> </reg32> <reg32 offset="0xa005" name="VFD_CONTROL_5"> - <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/> </reg32> <reg32 offset="0xa006" name="VFD_CONTROL_6"> </reg32> @@ -2710,17 +2576,11 @@ to upconvert to 32b float internally? <!-- always 0x0 ? --> <reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/> - <reg32 offset="0xa009" name="VFD_ADD_OFFSET"> - <!-- add VFD_INDEX_OFFSET to REGID4VTX --> - <bitfield name="VERTEX" pos="0" type="boolean"/> - <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST --> - <bitfield name="INSTANCE" pos="1" type="boolean"/> - </reg32> + <reg32 offset="0xa009" name="VFD_UNKNOWN_A009"/> <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/> <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/> <array offset="0xa010" name="VFD_FETCH" stride="4" length="32"> - <reg64 offset="0x0" name="BASE" type="address"/> <reg32 offset="0x0" name="BASE_LO"/> <reg32 offset="0x1" name="BASE_HI"/> <reg32 offset="0x2" name="SIZE" type="uint"/> @@ -2748,6 +2608,34 @@ to upconvert to 32b float internally? <!-- always 0x1 ? --> <reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/> + <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL"> + <!-- # of VS outputs including pos/psize --> + <bitfield name="VSOUT" low="0" high="4" type="uint"/> + </reg32> + <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16"> + <reg32 offset="0x0" name="REG"> + <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> + <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> + <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> + <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> + </reg32> + </array> + <!-- + Starting with a5xx, position/psize outputs from shader end up in the + SP_VS_OUT map, with highest OUTLOCn position. (Generally they are + the last entries too, except when gl_PointCoord is used, blob inserts + an extra varying after, but with a lower OUTLOC position. If present, + psize is last, preceded by position. + --> + <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8"> + <reg32 offset="0x0" name="REG"> + <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> + <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> + <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> + <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> + </reg32> + </array> + <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes"> <!-- When b31 set we just see FULLREGFOOTPRINT set. The pattern of @@ -2769,8 +2657,6 @@ to upconvert to 32b float internally? <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/> <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/> <bitfield name="VARYING" pos="22" type="boolean"/> - <!-- set when dFdxFine/dFdyFine is used --> - <bitfield name="DIFF_FINE" pos="23" type="boolean"/> <bitfield name="PIXLODENABLE" pos="26" type="boolean"/> <bitfield name="MERGEDREGS" pos="31" type="boolean"/> </bitset> @@ -2787,34 +2673,6 @@ to upconvert to 32b float internally? </bitset> <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> - <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL"> - <!-- # of VS outputs including pos/psize --> - <bitfield name="VSOUT" low="0" high="4" type="uint"/> - </reg32> - <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16"> - <reg32 offset="0x0" name="REG"> - <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> - <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> - <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> - <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> - </reg32> - </array> - <!-- - Starting with a5xx, position/psize outputs from shader end up in the - SP_VS_OUT map, with highest OUTLOCn position. (Generally they are - the last entries too, except when gl_PointCoord is used, blob inserts - an extra varying after, but with a lower OUTLOC position. If present, - psize is last, preceded by position. - --> - <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8"> - <reg32 offset="0x0" name="REG"> - <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> - <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> - <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> - <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> - </reg32> - </array> - <reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/> <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/> <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/> @@ -2862,31 +2720,6 @@ to upconvert to 32b float internally? <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> <reg32 offset="0xa871" name="SP_GS_UNKNOWN_A871"/> - - <reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS"> - <!-- # of VS outputs including pos/psize --> - <bitfield name="GSOUT" low="0" high="4" type="uint"/> - <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/> - </reg32> - - <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16"> - <reg32 offset="0x0" name="REG"> - <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> - <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> - <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> - <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> - </reg32> - </array> - - <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8"> - <reg32 offset="0x0" name="REG"> - <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> - <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> - <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> - <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> - </reg32> - </array> - <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/> <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/> <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/> @@ -2911,14 +2744,6 @@ to upconvert to 32b float internally? <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/> <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/> - <reg32 offset="0xa981" name="SP_UNKNOWN_A981"> - <bitfield name="FACE0" pos="0" type="boolean"/> - <bitfield name="FACE1" pos="1" type="boolean"/> - <bitfield name="FACE2" pos="2" type="boolean"/> - <bitfield name="FACE3" pos="3" type="boolean"/> - <bitfield name="FACE4" pos="4" type="boolean"/> - <bitfield name="FACE5" pos="5" type="boolean"/> - </reg32> <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/> <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/> <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/> @@ -2965,28 +2790,7 @@ to upconvert to 32b float internally? </reg32> </array> - <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL"> - <!-- unknown bits 0x7fc0 always set --> - <bitfield name="COUNT" low="0" high="2" type="uint"/> - <!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? --> - <bitfield name="UNK3" pos="3" type="boolean"/> - <bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/> - </reg32> - <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4"> - <reg32 offset="0" name="CMD"> - <bitfield name="SRC" low="0" high="6" type="uint"/> - <bitfield name="SAMP_ID" low="7" high="10" type="uint"/> - <bitfield name="TEX_ID" low="11" high="15" type="uint"/> - <bitfield name="DST" low="16" high="21" type="a3xx_regid"/> - <bitfield name="WRMASK" low="22" high="25" type="hex"/> - <bitfield name="HALF" pos="26" type="boolean"/> - <!-- - CMD seems always 0x4?? 3d, textureProj, textureLod seem to - skip pre-fetch.. TODO test texelFetch - --> - <bitfield name="CMD" low="27" high="31"/> - </reg32> - </array> + <reg32 offset="0xa99e" name="SP_UNKNOWN_A99E"/> <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/> @@ -3046,19 +2850,14 @@ to upconvert to 32b float internally? <reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/> <!-- - not really src, COLOR_FORMAT/SRGB seem to be related to ifmt which is for dst + I believe this describes the src format, but haven't seen traces with + src_format != dst_format --> <reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT"> <bitfield name="NORM" pos="0" type="boolean"/> <bitfield name="SINT" pos="1" type="boolean"/> <bitfield name="UINT" pos="2" type="boolean"/> - <!-- looks like HW only cares about the base type of this format, - which matches the ifmt? --> <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_color_fmt"/> - <!-- set when ifmt is R2D_UNORM8_SRGB --> - <bitfield name="SRGB" pos="11" type="boolean"/> - <!-- some sort of channel mask, not sure what it is for --> - <bitfield name="MASK" low="12" high="15"/> </reg32> <!-- always 0x0 --> @@ -3085,7 +2884,6 @@ to upconvert to 32b float internally? </reg32> <!-- looks to work in the same way as a5xx: --> - <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/> <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/> <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/> <!-- always 0x0 ? --> @@ -3098,7 +2896,15 @@ to upconvert to 32b float internally? badly named or the functionality moved in a6xx. But downstream kernel calls this "a6xx_sp_ps_tp_2d_cluster" --> - <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/> + <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO"> + <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/> + <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> + <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> + <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled --> + <bitfield name="FLAGS" pos="12" type="boolean"/> + <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/> + <bitfield name="FILTER" pos="16" type="boolean"/> + </reg32> <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE"> <bitfield name="WIDTH" low="0" high="14" type="uint"/> <bitfield name="HEIGHT" low="15" high="29" type="uint"/> @@ -3319,12 +3125,7 @@ to upconvert to 32b float internally? --> <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/> <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/> - <!-- - by default levels with w < 16 are linear - TILE_ALL makes all levels have tiling - seems required when using UBWC, since all levels have UBWC (can possibly be disabled?) - --> - <bitfield name="TILE_ALL" pos="27" type="boolean"/> + <bitfield name="UNK27" pos="27" type="boolean"/> <bitfield name="FLAG" pos="28" type="boolean"/> </reg32> <reg32 offset="4" name="4"> @@ -3345,10 +3146,11 @@ to upconvert to 32b float internally? <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/> </reg32> <reg32 offset="10" name="10"> + <!-- + I see some other bits set by blob above FLAG_BUFFER_PITCH, but they + don't seem to be particularly sensible... or needed for UBWC to work + --> <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/> - <!-- log2 size of the first level, required for mipmapping --> - <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/> - <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/> </reg32> <reg32 offset="11" name="11"/> <reg32 offset="12" name="12"/> @@ -3432,6 +3234,18 @@ with a better name. </reg32> </domain> +<domain name="CP_UNK_A6XX_55" width="32"> + <reg32 offset="0" name="0"> + <bitfield name="BASE_LO" low="0" high="31"/> + </reg32> + <reg32 offset="1" name="1"> + <bitfield name="BASE_HI" low="0" high="16"/> + </reg32> + <reg32 offset="2" name="2"> + <bitfield name="SIZE" low="0" high="15"/> + </reg32> +</domain> + <domain name="A6XX_PDC" width="32"> <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/> <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/> diff --git a/lib/mesa/src/freedreno/registers/adreno_pm4.xml b/lib/mesa/src/freedreno/registers/adreno_pm4.xml index 78847fbc0..06175d3e1 100644 --- a/lib/mesa/src/freedreno/registers/adreno_pm4.xml +++ b/lib/mesa/src/freedreno/registers/adreno_pm4.xml @@ -15,9 +15,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <value name="VIZQUERY_START" value="7"/> <!-- on a2xx (??) --> <value name="VIZQUERY_END" value="8"/> <value name="SC_WAIT_WC" value="9"/> - <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/> - <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/> - <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/> <value name="RST_PIX_CNT" value="13"/> <value name="RST_VTX_CNT" value="14"/> <value name="TILE_FLUSH" value="15"/> @@ -65,39 +62,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/> <value name="DI_PT_TRI_ADJ" value="0xc"/> <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/> - - <value name="DI_PT_PATCHES0" value="0x1f"/> - <value name="DI_PT_PATCHES1" value="0x20"/> - <value name="DI_PT_PATCHES2" value="0x21"/> - <value name="DI_PT_PATCHES3" value="0x22"/> - <value name="DI_PT_PATCHES4" value="0x23"/> - <value name="DI_PT_PATCHES5" value="0x24"/> - <value name="DI_PT_PATCHES6" value="0x25"/> - <value name="DI_PT_PATCHES7" value="0x26"/> - <value name="DI_PT_PATCHES8" value="0x27"/> - <value name="DI_PT_PATCHES9" value="0x28"/> - <value name="DI_PT_PATCHES10" value="0x29"/> - <value name="DI_PT_PATCHES11" value="0x2a"/> - <value name="DI_PT_PATCHES12" value="0x2b"/> - <value name="DI_PT_PATCHES13" value="0x2c"/> - <value name="DI_PT_PATCHES14" value="0x2d"/> - <value name="DI_PT_PATCHES15" value="0x2e"/> - <value name="DI_PT_PATCHES16" value="0x2f"/> - <value name="DI_PT_PATCHES17" value="0x30"/> - <value name="DI_PT_PATCHES18" value="0x31"/> - <value name="DI_PT_PATCHES19" value="0x32"/> - <value name="DI_PT_PATCHES20" value="0x33"/> - <value name="DI_PT_PATCHES21" value="0x34"/> - <value name="DI_PT_PATCHES22" value="0x35"/> - <value name="DI_PT_PATCHES23" value="0x36"/> - <value name="DI_PT_PATCHES24" value="0x37"/> - <value name="DI_PT_PATCHES25" value="0x38"/> - <value name="DI_PT_PATCHES26" value="0x39"/> - <value name="DI_PT_PATCHES27" value="0x3a"/> - <value name="DI_PT_PATCHES28" value="0x3b"/> - <value name="DI_PT_PATCHES29" value="0x3c"/> - <value name="DI_PT_PATCHES30" value="0x3d"/> - <value name="DI_PT_PATCHES31" value="0x3e"/> + <value name="DI_PT_PATCHES" value="0x29"/> </enum> <enum name="pc_di_src_sel"> @@ -157,12 +122,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <value name="CP_PREEMPT_ENABLE" value="0x1c"/> <value name="CP_PREEMPT_TOKEN" value="0x1e"/> <value name="CP_INDIRECT_BUFFER" value="0x3f"/> - <doc> - Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to - another buffer at the same level. Must be at the end of IB, and - doesn't work with draw state IB's. - </doc> - <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/> <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc> <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/> <doc>wait for the IDLE state of the engine</doc> @@ -225,7 +184,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <doc>load sequencer instruction memory (code embedded in packet)</doc> <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/> <doc>load constants from a location in memory</doc> - <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/> + <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e"/> <doc>selective invalidation of state pointers</doc> <value name="CP_INVALIDATE_STATE" value="0x3b"/> <doc>dynamically changes shader instruction memory partition</doc> @@ -272,7 +231,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <doc>Load a buffer with pre-fetch enabled</doc> <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/> <doc>Set bin (?)</doc> - <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/> + <value name="CP_SET_BIN" value="0x4c"/> <doc>test 2 memory locations to dword values specified</doc> <value name="CP_TEST_TWO_MEMS" value="0x71"/> @@ -316,7 +275,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> for A4xx Write to register with address that does not fit into type-0 pkt </doc> - <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/> + <value name="CP_WIDE_REG_WRITE" value="0x74"/> <doc>copy from ME scratch RAM to a register</doc> <value name="CP_SCRATCH_TO_REG" value="0x4d"/> @@ -419,16 +378,15 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <!-- jmptable entry used to handle type4 packet on a5xx+: --> <value name="PKT4" value="0x04" variants="A5XX,A6XX"/> +<!-- +unknown a6xx opcodes: - <!-- TODO do these exist on A5xx? --> - <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/> - <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX"/> - <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX"/> - <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/> - <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/> - <value name="CP_MEMCPY" value="0x75" variants="A6XX"/> - <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX"/> - <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX"/> +opcode: (null) (14) (5 dwords) +opcode: (null) (55) (4 dwords) +opcode: (null) (6d) (4 dwords) + --> + <value name="CP_UNK_A6XX_14" value="0x14" variants="A6XX"/> + <value name="CP_UNK_A6XX_55" value="0x55" variants="A6XX"/> <!-- Seems to always have the payload: @@ -652,7 +610,6 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/> <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/> <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/> - <bitfield name="GS_ENABLE" pos="16" type="boolean"/> <bitfield name="TESS_ENABLE" pos="17" type="boolean"/> </bitset> @@ -693,23 +650,9 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) </reg32> <reg32 offset="3" name="3"> </reg32> - - <stripe variants="A5XX-"> - <reg32 offset="4" name="4"> - <bitfield name="INDX_BASE_LO" low="0" high="31"/> - </reg32> - <reg32 offset="5" name="5"> - <bitfield name="INDX_BASE_HI" low="0" high="31"/> - </reg32> - <reg32 offset="6" name="6"> - <bitfield name="INDX_SIZE" low="0" high="31"/> - </reg32> - </stripe> - <reg32 offset="4" name="4"> <bitfield name="INDX_BASE" low="0" high="31"/> </reg32> - <reg32 offset="5" name="5"> <bitfield name="INDX_SIZE" low="0" high="31"/> </reg32> @@ -769,9 +712,13 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <bitfield name="DISABLE" pos="17" type="boolean"/> <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/> <bitfield name="LOAD_IMMED" pos="19" type="boolean"/> - <bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/> - <bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/> - <bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/> + <!-- + I think this is a bitmask of states that this group applies to + (ie. binning/bypass/gmem)? At least starting w/ a6xx blob + emits different VS state at the same time, with ENABLE_MASK=0x1 + for binning pass VS state, and ENABLE_MASK=0x6 for full VS. + --> + <bitfield name="ENABLE_MASK" low="20" high="23" variants="A6XX-"/> <bitfield name="GROUP_ID" low="24" high="28" type="uint"/> </reg32> <reg32 offset="1" name="1"> @@ -837,112 +784,14 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) </reg32> </domain> -<domain name="CP_SET_BIN_DATA5_OFFSET" width="32"> - <doc> - Like CP_SET_BIN_DATA5, but set the pointers as offsets from the - pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful - for Vulkan where these values aren't known when the command - stream is recorded. - </doc> - <reg32 offset="0" name="0"> - <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> - <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> - <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> - <bitfield name="VSC_N" low="22" high="26" type="uint"/> - </reg32> - <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> - <reg32 offset="1" name="1"> - <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> - </reg32> - <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> - <reg32 offset="2" name="2"> - <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> - </reg32> - <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> - <reg32 offset="3" name="3"> - <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> - </reg32> -</domain> - -<domain name="CP_REG_RMW" width="32"> - <doc> - Modifies DST_REG using two sources that can either be registers - or immediates. If SRC1_ADD is set, then do the following: - - $dst = (($dst & $src0) rot $rotate) + $src1 - - Otherwise: - - $dst = (($dst & $src0) rot $rotate) | $src1 - - Here "rot" means rotate left. - </doc> - <reg32 offset="0" name="0"> - <bitfield name="DST_REG" low="0" high="17" type="hex"/> - <bitfield name="ROTATE" low="24" high="28" type="uint"/> - <bitfield name="SRC1_ADD" pos="29" type="boolean"/> - <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/> - <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/> - </reg32> - <reg32 offset="1" name="1"> - <bitfield name="SRC0" low="0" high="31" type="uint"/> - </reg32> - <reg32 offset="2" name="2"> - <bitfield name="SRC1" low="0" high="31" type="uint"/> - </reg32> -</domain> - <domain name="CP_REG_TO_MEM" width="32"> <reg32 offset="0" name="0"> <bitfield name="REG" low="0" high="15" type="hex"/> - <!-- number of registers/dwords copied is max(CNT, 1). --> - <bitfield name="CNT" low="18" high="29" type="uint"/> - <bitfield name="64B" pos="30" type="boolean"/> - <bitfield name="ACCUMULATE" pos="31" type="boolean"/> - </reg32> - <reg32 offset="1" name="1"> - <bitfield name="DEST" low="0" high="31"/> - </reg32> - <reg32 offset="2" name="2" variants="A5XX-"> - <bitfield name="DEST_HI" low="0" high="31"/> - </reg32> -</domain> - -<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32"> - <doc> - Like CP_REG_TO_MEM, but the memory address to write to can be - offsetted using either one or two registers or scratch - registers. - </doc> - <reg32 offset="0" name="0"> - <bitfield name="REG" low="0" high="15" type="hex"/> - <!-- number of registers/dwords copied is max(CNT, 1). --> - <bitfield name="CNT" low="18" high="29" type="uint"/> - <bitfield name="64B" pos="30" type="boolean"/> - <bitfield name="ACCUMULATE" pos="31" type="boolean"/> - </reg32> - <reg32 offset="1" name="1"> - <bitfield name="DEST" low="0" high="31"/> - </reg32> - <reg32 offset="2" name="2" variants="A5XX-"> - <bitfield name="DEST_HI" low="0" high="31"/> - </reg32> - <reg32 offset="3" name="3"> - <bitfield name="OFFSET0" low="0" high="17" type="hex"/> - <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/> - </reg32> - <!-- followed by an optional identical OFFSET1 dword --> -</domain> - -<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32"> - <doc> - Like CP_REG_TO_MEM, but the memory address to write to can be - offsetted using a DWORD in memory. - </doc> - <reg32 offset="0" name="0"> - <bitfield name="REG" low="0" high="15" type="hex"/> - <!-- number of registers/dwords copied is max(CNT, 1). --> - <bitfield name="CNT" low="18" high="29" type="uint"/> + <!-- + number of regsiters/dwords copied is CNT+1.. unsure + about # of bits + --> + <bitfield name="CNT" low="19" high="29" type="uint"/> <bitfield name="64B" pos="30" type="boolean"/> <bitfield name="ACCUMULATE" pos="31" type="boolean"/> </reg32> @@ -952,23 +801,18 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <reg32 offset="2" name="2" variants="A5XX-"> <bitfield name="DEST_HI" low="0" high="31"/> </reg32> - <reg32 offset="3" name="3"> - <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/> - </reg32> - <reg32 offset="4" name="4"> - <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/> - </reg32> </domain> <domain name="CP_MEM_TO_REG" width="32"> <reg32 offset="0" name="0"> <bitfield name="REG" low="0" high="15" type="hex"/> - <!-- number of registers/dwords copied is max(CNT, 1). --> + <!-- + number of regsiters/dwords copied is CNT+1.. unsure + about # of bits + --> <bitfield name="CNT" low="19" high="29" type="uint"/> - <!-- shift each DWORD left by 2 while copying --> - <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/> - <!-- does the same thing as CP_MEM_TO_MEM::UNK31 --> - <bitfield name="UNK31" pos="31" type="boolean"/> + <bitfield name="64B" pos="30" type="boolean"/> + <bitfield name="ACCUMULATE" pos="31" type="boolean"/> </reg32> <reg32 offset="1" name="1"> <bitfield name="SRC" low="0" high="31"/> @@ -990,10 +834,6 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <!-- if set treat src/dst as 64bit values --> <bitfield name="DOUBLE" pos="29" type="boolean"/> - <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand --> - <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/> - <!-- some other kind of wait --> - <bitfield name="UNK31" pos="31" type="boolean"/> </reg32> <!-- followed by sequence of addresses.. the first is the @@ -1005,61 +845,6 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) --> </domain> -<domain name="CP_MEMCPY" width="32"> - <reg32 offset="0" name="0"> - <bitfield name="DWORDS" low="0" high="31" type="uint"/> - </reg32> - <reg32 offset="1" name="1"> - <bitfield name="SRC_LO" low="0" high="31" type="hex"/> - </reg32> - <reg32 offset="2" name="2"> - <bitfield name="SRC_HI" low="0" high="31" type="hex"/> - </reg32> - <reg32 offset="3" name="3"> - <bitfield name="DST_LO" low="0" high="31" type="hex"/> - </reg32> - <reg32 offset="4" name="4"> - <bitfield name="DST_HI" low="0" high="31" type="hex"/> - </reg32> -</domain> - -<domain name="CP_REG_TO_SCRATCH" width="32"> - <reg32 offset="0" name="0"> - <bitfield name="REG" low="0" high="17" type="hex"/> - <bitfield name="SCRATCH" low="20" high="22" type="uint"/> - <!-- number of registers/dwords copied is CNT + 1. --> - <bitfield name="CNT" low="24" high="26" type="uint"/> - </reg32> -</domain> - -<domain name="CP_SCRATCH_TO_REG" width="32"> - <reg32 offset="0" name="0"> - <bitfield name="REG" low="0" high="17" type="hex"/> - <!-- note: CP_MEM_TO_REG always sets this when writing to the register --> - <bitfield name="UNK18" pos="18" type="boolean"/> - <bitfield name="SCRATCH" low="20" high="22" type="uint"/> - <!-- number of registers/dwords copied is CNT + 1. --> - <bitfield name="CNT" low="24" high="26" type="uint"/> - </reg32> -</domain> - -<domain name="CP_SCRATCH_WRITE" width="32"> - <reg32 offset="0" name="0"> - <bitfield name="SCRATCH" low="20" high="22" type="uint"/> - </reg32> - <!-- followed by one or more DWORDs to write to scratch registers --> -</domain> - -<domain name="CP_MEM_WRITE" width="32"> - <reg32 offset="0" name="0"> - <bitfield name="ADDR_LO" low="0" high="31"/> - </reg32> - <reg32 offset="1" name="1"> - <bitfield name="ADDR_HI" low="0" high="31"/> - </reg32> - <!-- followed by the DWORDs to write --> -</domain> - <enum name="cp_cond_function"> <value value="0" name="WRITE_ALWAYS"/> <value value="1" name="WRITE_LT"/> @@ -1096,10 +881,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <domain name="CP_COND_WRITE5" width="32"> <reg32 offset="0" name="0"> <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> - <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> - <!-- if both POLL_MEMORY and POLL_SCRATCH are false, it polls a register at POLL_ADDR_LO instead. --> <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> - <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/> <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> </reg32> <reg32 offset="1" name="1"> @@ -1125,71 +907,6 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) </reg32> </domain> -<domain name="CP_WAIT_MEM_GTE" width="32"> - <doc> - Wait until a memory value is greater than or equal to the - reference, using signed comparison. - </doc> - <reg32 offset="0" name="0"> - <!-- Reserved for flags, presumably? Unused in FW --> - <bitfield name="RESERVED" low="0" high="31" type="hex"/> - </reg32> - <reg32 offset="1" name="1"> - <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> - </reg32> - <reg32 offset="2" name="2"> - <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> - </reg32> - <reg32 offset="3" name="3"> - <bitfield name="REF" low="0" high="31"/> - </reg32> -</domain> - -<domain name="CP_WAIT_REG_MEM" width="32"> - <doc> - This uses the same internal comparison as CP_COND_WRITE, - but waits until the comparison is true instead. It busy-loops in - the CP for the given number of cycles before trying again. - </doc> - <reg32 offset="0" name="0"> - <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> - <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> - <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> - <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/> - <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> - </reg32> - <reg32 offset="1" name="1"> - <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> - </reg32> - <reg32 offset="2" name="2"> - <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> - </reg32> - <reg32 offset="3" name="3"> - <bitfield name="REF" low="0" high="31"/> - </reg32> - <reg32 offset="4" name="4"> - <bitfield name="MASK" low="0" high="31"/> - </reg32> - <reg32 offset="5" name="5"> - <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/> - </reg32> -</domain> - -<domain name="CP_WAIT_TWO_REGS" width="32"> - <doc> - Waits for REG0 to not be 0 or REG1 to not equal REF - </doc> - <reg32 offset="0" name="0"> - <bitfield name="REG0" low="0" high="17" type="hex"/> - </reg32> - <reg32 offset="1" name="1"> - <bitfield name="REG1" low="0" high="17" type="hex"/> - </reg32> - <reg32 offset="2" name="2"> - <bitfield name="REF" low="0" high="31" type="uint"/> - </reg32> -</domain> - <domain name="CP_DISPATCH_COMPUTE" width="32"> <reg32 offset="0" name="0"/> <reg32 offset="1" name="1"> @@ -1386,22 +1103,13 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <value value="4" name="RM6_GMEM"/> <value value="5" name="RM6_BLIT2D"/> <value value="6" name="RM6_RESOLVE"/> - <value value="7" name="RM6_YIELD"/> <value value="0xc" name="RM6_BLIT2DSCALE"/> - - <!-- - These values come from a6xx_set_marker() in the - downstream kernel, and they can only be set by the kernel - --> - <value value="0xd" name="RM6_IB1LIST_START"/> - <value value="0xe" name="RM6_IB1LIST_END"/> - <!-- IFPC - inter-frame power collapse --> - <value value="0x100" name="RM6_IFPC_ENABLE"/> - <value value="0x101" name="RM6_IFPC_DISABLE"/> </enum> <reg32 offset="0" name="0"> <bitfield name="MARKER" low="0" high="3"/> - <bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/> + <bitfield name="MODE" low="0" high="3" type="a6xx_render_mode"/> + <!-- IFPC - inter-frame power collapse --> + <bitfield name="IFPC" pos="8" type="boolean"/> </reg32> </domain> @@ -1447,122 +1155,19 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <bitfield name="REG" low="0" high="11"/> <!-- the bit to test --> <bitfield name="BIT" low="20" high="24" type="uint"/> - <!-- execute CP_WAIT_FOR_ME beforehand --> - <bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/> + <bitfield name="UNK25" pos="25" type="boolean"/> </reg32> </domain> <!-- I *think* this existed at least as far back as a4xx --> <domain name="CP_COND_REG_EXEC" width="32"> - <enum name="compare_mode"> - <!-- use the predicate bit set by CP_REG_TEST --> - <value value="1" name="PRED_TEST"/> - <!-- compare two registers directly for equality --> - <value value="2" name="REG_COMPARE"/> - <!-- test if certain render modes are set via CP_SET_MARKER --> - <value value="3" name="RENDER_MODE" variants="A6XX-"/> - </enum> <reg32 offset="0" name="0"> - <bitfield name="REG0" low="0" high="17" type="hex"/> - - <!-- - Note: these bits have the same meaning, and use the same - internal mechanism as the bits in CP_SET_DRAW_STATE. - When RENDER_MODE is selected, they're used as - a bitmask of which modes pass the test. - --> - - <!-- RM6_BINNING --> - <bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/> - <!-- all others --> - <bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/> - <!-- RM6_BYPASS --> - <bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/> - - <bitfield name="MODE" low="28" high="31" type="compare_mode"/> + <bitfield name="UNK28" pos="28" type="boolean"/> </reg32> - - <!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 --> - <reg32 offset="1" name="1"> <bitfield name="DWORDS" low="0" high="31" type="uint"/> </reg32> </domain> -<domain name="CP_COND_EXEC" width="32"> - <doc> - Executes the following DWORDs of commands if the dword at ADDR0 - is not equal to 0 and the dword at ADDR1 is less than REF - (signed comparison). - </doc> - <reg32 offset="0" name="0"> - <bitfield name="ADDR0_LO" low="0" high="31"/> - </reg32> - <reg32 offset="1" name="1"> - <bitfield name="ADDR0_HI" low="0" high="31"/> - </reg32> - <reg32 offset="2" name="2"> - <bitfield name="ADDR1_LO" low="0" high="31"/> - </reg32> - <reg32 offset="3" name="3"> - <bitfield name="ADDR1_HI" low="0" high="31"/> - </reg32> - <reg32 offset="4" name="4"> - <bitfield name="REF" low="0" high="31"/> - </reg32> - <reg32 offset="1" name="1"> - <bitfield name="DWORDS" low="0" high="31" type="uint"/> - </reg32> -</domain> - -<domain name="CP_SET_CTXSWITCH_IB" width="32"> - <doc> - Used by the userspace driver to set various IB's which are - executed during context save/restore for handling - state that isn't restored by the - context switch routine itself. - </doc> - <enum name="ctxswitch_ib"> - <value name="RESTORE_IB" value="0"> - <doc>Executed unconditionally when switching back to the context.</doc> - </value> - <value name="YIELD_RESTORE_IB" value="1"> - <doc> - Executed when switching back after switching - away during execution of - a CP_SET_MARKER packet with RM6_YIELD as the - payload *and* the normal save routine was - bypassed for a shorter one. I think this is - connected to the "skipsaverestore" bit set by - the kernel when preempting. - </doc> - </value> - <value name="SAVE_IB" value="2"> - <doc> - Executed when switching away from the context, - except for context switches initiated via - CP_YIELD. - </doc> - </value> - <value name="RB_SAVE_IB" value="3"> - <doc> - This can only be set by the RB (i.e. the kernel) - and executes with protected mode off, but - is otherwise similar to SAVE_IB. - </doc> - </value> - </enum> - <reg32 offset="0" name="0"> - <bitfield name="ADDR_LO" low="0" high="31"/> - </reg32> - <reg32 offset="1" name="1"> - <bitfield name="ADDR_HI" low="0" high="31"/> - </reg32> - <reg32 offset="2" name="2"> - <bitfield name="DWORDS" low="0" high="19" type="uint"/> - <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/> - </reg32> -</domain> - </database> diff --git a/lib/mesa/src/freedreno/vulkan/tu_fence.c b/lib/mesa/src/freedreno/vulkan/tu_fence.c index 9e4a92370..793f0ab3c 100644 --- a/lib/mesa/src/freedreno/vulkan/tu_fence.c +++ b/lib/mesa/src/freedreno/vulkan/tu_fence.c @@ -86,7 +86,6 @@ tu_fence_init(struct tu_fence *fence, bool signaled) { fence->signaled = signaled; fence->fd = -1; - fence->fence_wsi = NULL; } void @@ -94,8 +93,6 @@ tu_fence_finish(struct tu_fence *fence) { if (fence->fd >= 0) close(fence->fd); - if (fence->fence_wsi) - fence->fence_wsi->destroy(fence->fence_wsi); } /** @@ -211,10 +208,6 @@ tu_fence_init_poll_fds(uint32_t fence_count, for (uint32_t i = 0; i < fence_count; i++) { TU_FROM_HANDLE(tu_fence, fence, fences[i]); - /* skip wsi fences */ - if (fence->fence_wsi) - continue; - if (fence->signaled) { if (wait_all) { /* skip signaled fences */ @@ -296,10 +289,6 @@ tu_fence_update_fences_and_poll_fds(uint32_t fence_count, for (uint32_t i = 0; i < fence_count; i++) { TU_FROM_HANDLE(tu_fence, fence, fences[i]); - /* skip wsi fences */ - if (fence->fence_wsi) - continue; - /* no signaled fence in fds */ if (fence->signaled) continue; @@ -360,18 +349,6 @@ tu_WaitForFences(VkDevice _device, if (fds != stack_fds) vk_free(&device->alloc, fds); - if (result != VK_SUCCESS) - return result; - - for (uint32_t i = 0; i < fenceCount; ++i) { - TU_FROM_HANDLE(tu_fence, fence, pFences[i]); - if (fence->fence_wsi) { - VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout); - if (result != VK_SUCCESS) - return result; - } - } - return result; } @@ -399,15 +376,6 @@ tu_GetFenceStatus(VkDevice _device, VkFence _fence) else if (err && errno != ETIME) return VK_ERROR_OUT_OF_HOST_MEMORY; } - if (fence->fence_wsi) { - VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0); - - if (result != VK_SUCCESS) { - if (result == VK_TIMEOUT) - return VK_NOT_READY; - return result; - } - } return fence->signaled ? VK_SUCCESS : VK_NOT_READY; } diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.h index 564db9052..c89ab9a94 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.h @@ -32,12 +32,23 @@ #include "compiler/nir/nir_worklist.h" #include "util/register_allocate.h" +struct emit_options { + unsigned max_temps; /* max # of vec4 registers */ + unsigned max_consts; /* max # of vec4 consts */ + unsigned id_reg; /* register with vertex/instance id */ + bool single_const_src : 1; /* limited to 1 vec4 const src */ + bool etna_new_transcendentals : 1; + void *user; + uint64_t *consts; +}; + #define ALU_SWIZ(s) INST_SWIZ((s)->swizzle[0], (s)->swizzle[1], (s)->swizzle[2], (s)->swizzle[3]) #define SRC_DISABLE ((hw_src){}) #define SRC_CONST(idx, s) ((hw_src){.use=1, .rgroup = INST_RGROUP_UNIFORM_0, .reg=idx, .swiz=s}) #define SRC_REG(idx, s) ((hw_src){.use=1, .rgroup = INST_RGROUP_TEMP, .reg=idx, .swiz=s}) -#define emit(type, args...) etna_emit_##type(state->c, args) +#define option(name) (state->options->name) +#define emit(type, args...) etna_emit_##type(state->options->user, args) typedef struct etna_inst_dst hw_dst; typedef struct etna_inst_src hw_src; @@ -48,8 +59,7 @@ enum { }; struct state { - struct etna_compile *c; - + const struct emit_options *options; unsigned const_count; nir_shader *shader; @@ -62,18 +72,10 @@ struct state { unsigned num_nodes; }; -#define compile_error(ctx, args...) ({ \ - printf(args); \ - ctx->error = true; \ - assert(0); \ -}) - static inline hw_src src_swizzle(hw_src src, unsigned swizzle) { - if (src.rgroup != INST_RGROUP_IMMEDIATE) - src.swiz = inst_swiz_compose(src.swiz, swizzle); - + src.swiz = inst_swiz_compose(src.swiz, swizzle); return src; } @@ -94,6 +96,7 @@ static inline bool is_sysval(nir_instr *instr) #define CONST_VAL(a, b) (nir_const_value) {.u64 = (uint64_t)(a) << 32 | (uint64_t)(b)} #define CONST(x) CONST_VAL(ETNA_IMMEDIATE_CONSTANT, x) #define UNIFORM(x) CONST_VAL(ETNA_IMMEDIATE_UNIFORM, x) +#define UNIFORM_BASE(x) CONST_VAL(ETNA_IMMEDIATE_UBO0_ADDR, x) #define TEXSCALE(x, i) CONST_VAL(ETNA_IMMEDIATE_TEXRECT_SCALE_X + (i), x) static int @@ -111,28 +114,10 @@ const_add(uint64_t *c, uint64_t value) static hw_src const_src(struct state *state, nir_const_value *value, unsigned num_components) { - /* use inline immediates if possible */ - if (state->c->specs->halti >= 2 && num_components == 1 && - value[0].u64 >> 32 == ETNA_IMMEDIATE_CONSTANT) { - uint32_t bits = value[0].u32; - - /* "float" - shifted by 12 */ - if ((bits & 0xfff) == 0) - return etna_immediate_src(0, bits >> 12); - - /* "unsigned" - raw 20 bit value */ - if (bits < (1 << 20)) - return etna_immediate_src(2, bits); - - /* "signed" - sign extended 20-bit (sign included) value */ - if (bits >= 0xfff80000) - return etna_immediate_src(1, bits); - } - unsigned i; int swiz = -1; for (i = 0; swiz < 0; i++) { - uint64_t *a = &state->c->consts[i*4]; + uint64_t *a = &option(consts)[i*4]; uint64_t save[4]; memcpy(save, a, sizeof(save)); swiz = 0; @@ -147,7 +132,7 @@ const_src(struct state *state, nir_const_value *value, unsigned num_components) } } - assert(i <= ETNA_MAX_IMM / 4); + assert(i <= option(max_consts)); state->const_count = MAX2(state->const_count, i); return SRC_CONST(i - 1, swiz); @@ -172,9 +157,6 @@ enum { REG_CLASS_VEC4, /* special vec2 class for fast transcendentals, limited to XY or ZW */ REG_CLASS_VIRT_VEC2T, - /* special classes for LOAD - contiguous components */ - REG_CLASS_VIRT_VEC2C, - REG_CLASS_VIRT_VEC3C, NUM_REG_CLASSES, } reg_class; @@ -196,11 +178,6 @@ enum { REG_TYPE_VIRT_SCALAR_W, REG_TYPE_VIRT_VEC2T_XY, REG_TYPE_VIRT_VEC2T_ZW, - REG_TYPE_VIRT_VEC2C_XY, - REG_TYPE_VIRT_VEC2C_YZ, - REG_TYPE_VIRT_VEC2C_ZW, - REG_TYPE_VIRT_VEC3C_XYZ, - REG_TYPE_VIRT_VEC3C_YZW, NUM_REG_TYPES, } reg_type; @@ -212,23 +189,18 @@ reg_writemask[NUM_REG_TYPES] = { [REG_TYPE_VIRT_SCALAR_Y] = 0x2, [REG_TYPE_VIRT_VEC2_XY] = 0x3, [REG_TYPE_VIRT_VEC2T_XY] = 0x3, - [REG_TYPE_VIRT_VEC2C_XY] = 0x3, [REG_TYPE_VIRT_SCALAR_Z] = 0x4, [REG_TYPE_VIRT_VEC2_XZ] = 0x5, [REG_TYPE_VIRT_VEC2_YZ] = 0x6, - [REG_TYPE_VIRT_VEC2C_YZ] = 0x6, [REG_TYPE_VIRT_VEC3_XYZ] = 0x7, - [REG_TYPE_VIRT_VEC3C_XYZ] = 0x7, [REG_TYPE_VIRT_SCALAR_W] = 0x8, [REG_TYPE_VIRT_VEC2_XW] = 0x9, [REG_TYPE_VIRT_VEC2_YW] = 0xa, [REG_TYPE_VIRT_VEC3_XYW] = 0xb, [REG_TYPE_VIRT_VEC2_ZW] = 0xc, [REG_TYPE_VIRT_VEC2T_ZW] = 0xc, - [REG_TYPE_VIRT_VEC2C_ZW] = 0xc, [REG_TYPE_VIRT_VEC3_XZW] = 0xd, [REG_TYPE_VIRT_VEC3_YZW] = 0xe, - [REG_TYPE_VIRT_VEC3C_YZW] = 0xe, }; /* how to swizzle when used as a src */ @@ -239,23 +211,18 @@ reg_swiz[NUM_REG_TYPES] = { [REG_TYPE_VIRT_SCALAR_Y] = SWIZZLE(Y, Y, Y, Y), [REG_TYPE_VIRT_VEC2_XY] = INST_SWIZ_IDENTITY, [REG_TYPE_VIRT_VEC2T_XY] = INST_SWIZ_IDENTITY, - [REG_TYPE_VIRT_VEC2C_XY] = INST_SWIZ_IDENTITY, [REG_TYPE_VIRT_SCALAR_Z] = SWIZZLE(Z, Z, Z, Z), [REG_TYPE_VIRT_VEC2_XZ] = SWIZZLE(X, Z, X, Z), [REG_TYPE_VIRT_VEC2_YZ] = SWIZZLE(Y, Z, Y, Z), - [REG_TYPE_VIRT_VEC2C_YZ] = SWIZZLE(Y, Z, Y, Z), [REG_TYPE_VIRT_VEC3_XYZ] = INST_SWIZ_IDENTITY, - [REG_TYPE_VIRT_VEC3C_XYZ] = INST_SWIZ_IDENTITY, [REG_TYPE_VIRT_SCALAR_W] = SWIZZLE(W, W, W, W), [REG_TYPE_VIRT_VEC2_XW] = SWIZZLE(X, W, X, W), [REG_TYPE_VIRT_VEC2_YW] = SWIZZLE(Y, W, Y, W), [REG_TYPE_VIRT_VEC3_XYW] = SWIZZLE(X, Y, W, X), [REG_TYPE_VIRT_VEC2_ZW] = SWIZZLE(Z, W, Z, W), [REG_TYPE_VIRT_VEC2T_ZW] = SWIZZLE(Z, W, Z, W), - [REG_TYPE_VIRT_VEC2C_ZW] = SWIZZLE(Z, W, Z, W), [REG_TYPE_VIRT_VEC3_XZW] = SWIZZLE(X, Z, W, X), [REG_TYPE_VIRT_VEC3_YZW] = SWIZZLE(Y, Z, W, X), - [REG_TYPE_VIRT_VEC3C_YZW] = SWIZZLE(Y, Z, W, X), }; /* how to swizzle when used as a dest */ @@ -266,23 +233,18 @@ reg_dst_swiz[NUM_REG_TYPES] = { [REG_TYPE_VIRT_SCALAR_Y] = SWIZZLE(X, X, X, X), [REG_TYPE_VIRT_VEC2_XY] = INST_SWIZ_IDENTITY, [REG_TYPE_VIRT_VEC2T_XY] = INST_SWIZ_IDENTITY, - [REG_TYPE_VIRT_VEC2C_XY] = INST_SWIZ_IDENTITY, [REG_TYPE_VIRT_SCALAR_Z] = SWIZZLE(X, X, X, X), [REG_TYPE_VIRT_VEC2_XZ] = SWIZZLE(X, X, Y, Y), [REG_TYPE_VIRT_VEC2_YZ] = SWIZZLE(X, X, Y, Y), - [REG_TYPE_VIRT_VEC2C_YZ] = SWIZZLE(X, X, Y, Y), [REG_TYPE_VIRT_VEC3_XYZ] = INST_SWIZ_IDENTITY, - [REG_TYPE_VIRT_VEC3C_XYZ] = INST_SWIZ_IDENTITY, [REG_TYPE_VIRT_SCALAR_W] = SWIZZLE(X, X, X, X), [REG_TYPE_VIRT_VEC2_XW] = SWIZZLE(X, X, Y, Y), [REG_TYPE_VIRT_VEC2_YW] = SWIZZLE(X, X, Y, Y), [REG_TYPE_VIRT_VEC3_XYW] = SWIZZLE(X, Y, Z, Z), [REG_TYPE_VIRT_VEC2_ZW] = SWIZZLE(X, X, X, Y), [REG_TYPE_VIRT_VEC2T_ZW] = SWIZZLE(X, X, X, Y), - [REG_TYPE_VIRT_VEC2C_ZW] = SWIZZLE(X, X, X, Y), [REG_TYPE_VIRT_VEC3_XZW] = SWIZZLE(X, Y, Y, Z), [REG_TYPE_VIRT_VEC3_YZW] = SWIZZLE(X, X, Y, Z), - [REG_TYPE_VIRT_VEC3C_YZW] = SWIZZLE(X, X, Y, Z), }; static inline int reg_get_type(int virt_reg) @@ -294,15 +256,10 @@ static inline int reg_get_base(struct state *state, int virt_reg) { /* offset by 1 to avoid reserved position register */ if (state->shader->info.stage == MESA_SHADER_FRAGMENT) - return (virt_reg / NUM_REG_TYPES + 1) % ETNA_MAX_TEMPS; + return virt_reg / NUM_REG_TYPES + 1; return virt_reg / NUM_REG_TYPES; } -/* use "r63.z" for depth reg, it will wrap around to r0.z by reg_get_base - * (fs registers are offset by 1 to avoid reserving r0) - */ -#define REG_FRAG_DEPTH ((ETNA_MAX_TEMPS - 1) * NUM_REG_TYPES + REG_TYPE_VIRT_SCALAR_Z) - static inline int reg_get_class(int virt_reg) { switch (reg_get_type(virt_reg)) { @@ -328,13 +285,6 @@ static inline int reg_get_class(int virt_reg) case REG_TYPE_VIRT_VEC2T_XY: case REG_TYPE_VIRT_VEC2T_ZW: return REG_CLASS_VIRT_VEC2T; - case REG_TYPE_VIRT_VEC2C_XY: - case REG_TYPE_VIRT_VEC2C_YZ: - case REG_TYPE_VIRT_VEC2C_ZW: - return REG_CLASS_VIRT_VEC2C; - case REG_TYPE_VIRT_VEC3C_XYZ: - case REG_TYPE_VIRT_VEC3C_YZW: - return REG_CLASS_VIRT_VEC3C; } assert(false); @@ -387,15 +337,13 @@ get_src(struct state *state, nir_src *src) case nir_intrinsic_load_input: case nir_intrinsic_load_instance_id: case nir_intrinsic_load_uniform: - case nir_intrinsic_load_ubo: return ra_src(state, src); case nir_intrinsic_load_front_face: return (hw_src) { .use = 1, .rgroup = INST_RGROUP_INTERNAL }; case nir_intrinsic_load_frag_coord: return SRC_REG(0, INST_SWIZ_IDENTITY); default: - compile_error(state->c, "Unhandled NIR intrinsic type: %s\n", - nir_intrinsic_infos[intr->intrinsic].name); + assert(0); break; } } break; @@ -408,7 +356,7 @@ get_src(struct state *state, nir_src *src) return src_swizzle(const_src(state, &value, 1), SWIZZLE(X,X,X,X)); } default: - compile_error(state->c, "Unhandled NIR instruction type: %d\n", instr->type); + assert(0); break; } @@ -581,18 +529,15 @@ dest_for_instr(nir_instr *instr) dest = &nir_instr_as_alu(instr)->dest.dest; break; case nir_instr_type_tex: - dest = &nir_instr_as_tex(instr)->dest; + dest =&nir_instr_as_tex(instr)->dest; break; case nir_instr_type_intrinsic: { nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); if (intr->intrinsic == nir_intrinsic_load_uniform || - intr->intrinsic == nir_intrinsic_load_ubo || intr->intrinsic == nir_intrinsic_load_input || intr->intrinsic == nir_intrinsic_load_instance_id) dest = &intr->dest; - } break; - case nir_instr_type_deref: - return NULL; + } default: break; } @@ -653,7 +598,7 @@ set_src_live(nir_src *src, void *void_state) if (src->is_ssa) { nir_instr *instr = src->ssa->parent_instr; - if (is_sysval(instr) || instr->type == nir_instr_type_deref) + if (is_sysval(instr)) return true; switch (instr->type) { @@ -788,7 +733,7 @@ live_defs(nir_function_impl *impl, struct live_def *defs, unsigned *live_map) /* output live till the end */ if (instr->type == nir_instr_type_intrinsic) { nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); - if (intr->intrinsic == nir_intrinsic_store_deref) + if (intr->intrinsic == nir_intrinsic_store_output) state.index = ~0u; } @@ -815,12 +760,13 @@ live_defs(nir_function_impl *impl, struct live_def *defs, unsigned *live_map) /* apply live_in/live_out to ranges */ nir_foreach_block(block, impl) { + BITSET_WORD tmp; int i; - BITSET_FOREACH_SET(i, block->live_in, state.num_defs) + BITSET_FOREACH_SET(i, tmp, block->live_in, state.num_defs) range_include(&state.defs[i], block_live_index[block->index]); - BITSET_FOREACH_SET(i, block->live_out, state.num_defs) + BITSET_FOREACH_SET(i, tmp, block->live_out, state.num_defs) range_include(&state.defs[i], block_live_index[block->index + 1]); } @@ -829,19 +775,17 @@ live_defs(nir_function_impl *impl, struct live_def *defs, unsigned *live_map) /* precomputed by register_allocate */ static unsigned int *q_values[] = { - (unsigned int[]) {1, 2, 3, 4, 2, 2, 3, }, - (unsigned int[]) {3, 5, 6, 6, 5, 5, 6, }, - (unsigned int[]) {3, 4, 4, 4, 4, 4, 4, }, - (unsigned int[]) {1, 1, 1, 1, 1, 1, 1, }, - (unsigned int[]) {1, 2, 2, 2, 1, 2, 2, }, - (unsigned int[]) {2, 3, 3, 3, 2, 3, 3, }, - (unsigned int[]) {2, 2, 2, 2, 2, 2, 2, }, + (unsigned int[]) { 1, 2, 3, 4, 2 }, + (unsigned int[]) { 3, 5, 6, 6, 5 }, + (unsigned int[]) { 3, 4, 4, 4, 4 }, + (unsigned int[]) { 1, 1, 1, 1, 1 }, + (unsigned int[]) { 1, 2, 2, 2, 1 }, }; static void ra_assign(struct state *state, nir_shader *shader) { - struct ra_regs *regs = ra_alloc_reg_set(NULL, ETNA_MAX_TEMPS * + struct ra_regs *regs = ra_alloc_reg_set(NULL, option(max_temps) * NUM_REG_TYPES, false); /* classes always be created from index 0, so equal to the class enum @@ -850,10 +794,10 @@ ra_assign(struct state *state, nir_shader *shader) for (int c = 0; c < NUM_REG_CLASSES; c++) ra_alloc_reg_class(regs); /* add each register of each class */ - for (int r = 0; r < NUM_REG_TYPES * ETNA_MAX_TEMPS; r++) + for (int r = 0; r < NUM_REG_TYPES * option(max_temps); r++) ra_class_add_reg(regs, reg_get_class(r), r); /* set conflicts */ - for (int r = 0; r < ETNA_MAX_TEMPS; r++) { + for (int r = 0; r < option(max_temps); r++) { for (int i = 0; i < NUM_REG_TYPES; i++) { for (int j = 0; j < i; j++) { if (reg_writemask[i] & reg_writemask[j]) { @@ -891,35 +835,21 @@ ra_assign(struct state *state, nir_shader *shader) for (unsigned i = 0; i < num_nodes; i++) { nir_instr *instr = defs[i].instr; nir_dest *dest = defs[i].dest; - unsigned c = nir_dest_num_components(*dest) - 1; - if (instr->type == nir_instr_type_alu && - state->c->specs->has_new_transcendentals) { + ra_set_node_class(g, i, nir_dest_num_components(*dest) - 1); + + if (instr->type == nir_instr_type_alu && option(etna_new_transcendentals)) { switch (nir_instr_as_alu(instr)->op) { case nir_op_fdiv: case nir_op_flog2: case nir_op_fsin: case nir_op_fcos: assert(dest->is_ssa); - c = REG_CLASS_VIRT_VEC2T; + ra_set_node_class(g, i, REG_CLASS_VIRT_VEC2T); default: break; } } - - if (instr->type == nir_instr_type_intrinsic) { - nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); - /* can't have dst swizzle or sparse writemask on UBO loads */ - if (intr->intrinsic == nir_intrinsic_load_ubo) { - assert(dest == &intr->dest); - if (dest->ssa.num_components == 2) - c = REG_CLASS_VIRT_VEC2C; - if (dest->ssa.num_components == 3) - c = REG_CLASS_VIRT_VEC3C; - } - } - - ra_set_node_class(g, i, c); } nir_foreach_block(block, impl) { @@ -932,20 +862,11 @@ ra_assign(struct state *state, nir_shader *shader) unsigned reg; switch (intr->intrinsic) { - case nir_intrinsic_store_deref: { - /* don't want outputs to be swizzled + case nir_intrinsic_store_output: { + /* don't want output to be swizzled * TODO: better would be to set the type to X/XY/XYZ/XYZW - * TODO: what if fragcoord.z is read after writing fragdepth? */ - nir_deref_instr *deref = nir_src_as_deref(intr->src[0]); - unsigned index = live_map[src_index(impl, &intr->src[1])]; - - if (shader->info.stage == MESA_SHADER_FRAGMENT && - deref->var->data.location == FRAG_RESULT_DEPTH) { - ra_set_node_reg(g, index, REG_FRAG_DEPTH); - } else { - ra_set_node_class(g, index, REG_CLASS_VEC4); - } + ra_set_node_class(g, live_map[src_index(impl, &intr->src[0])], REG_CLASS_VEC4); } continue; case nir_intrinsic_load_input: reg = nir_intrinsic_base(intr) * NUM_REG_TYPES + (unsigned[]) { @@ -956,7 +877,7 @@ ra_assign(struct state *state, nir_shader *shader) }[nir_dest_num_components(*dest) - 1]; break; case nir_intrinsic_load_instance_id: - reg = state->c->variant->infile.num_reg * NUM_REG_TYPES + REG_TYPE_VIRT_SCALAR_Y; + reg = option(id_reg) * NUM_REG_TYPES + REG_TYPE_VIRT_SCALAR_Y; break; default: continue; @@ -1061,7 +982,8 @@ emit_tex(struct state *state, nir_tex_instr * tex) { unsigned dst_swiz; hw_dst dst = ra_dest(state, &tex->dest, &dst_swiz); - nir_src *coord = NULL, *lod_bias = NULL, *compare = NULL; + nir_src *coord = NULL; + nir_src *lod_bias = NULL; for (unsigned i = 0; i < tex->num_srcs; i++) { switch (tex->src[i].src_type) { @@ -1073,67 +995,34 @@ emit_tex(struct state *state, nir_tex_instr * tex) assert(!lod_bias); lod_bias = &tex->src[i].src; break; - case nir_tex_src_comparator: - compare = &tex->src[i].src; - break; default: - compile_error(state->c, "Unhandled NIR tex src type: %d\n", - tex->src[i].src_type); + assert(0); break; } } emit(tex, tex->op, tex->sampler_index, dst_swiz, dst, get_src(state, coord), - lod_bias ? get_src(state, lod_bias) : SRC_DISABLE, - compare ? get_src(state, compare) : SRC_DISABLE); + lod_bias ? get_src(state, lod_bias) : SRC_DISABLE); } static void emit_intrinsic(struct state *state, nir_intrinsic_instr * intr) { switch (intr->intrinsic) { - case nir_intrinsic_store_deref: - emit(output, nir_src_as_deref(intr->src[0])->var, get_src(state, &intr->src[1])); + case nir_intrinsic_store_output: + emit(output, nir_intrinsic_base(intr), get_src(state, &intr->src[0])); break; case nir_intrinsic_discard_if: emit(discard, get_src(state, &intr->src[0])); - break; + break; case nir_intrinsic_discard: emit(discard, SRC_DISABLE); break; case nir_intrinsic_load_uniform: { unsigned dst_swiz; - struct etna_inst_dst dst = ra_dest(state, &intr->dest, &dst_swiz); - - /* TODO: rework so extra MOV isn't required, load up to 4 addresses at once */ - emit_inst(state->c, &(struct etna_inst) { - .opcode = INST_OPCODE_MOVAR, - .dst.write_mask = 0x1, - .src[2] = get_src(state, &intr->src[0]), - }); - emit_inst(state->c, &(struct etna_inst) { - .opcode = INST_OPCODE_MOV, - .dst = dst, - .src[2] = { - .use = 1, - .rgroup = INST_RGROUP_UNIFORM_0, - .reg = nir_intrinsic_base(intr), - .swiz = dst_swiz, - .amode = INST_AMODE_ADD_A_X, - }, - }); - } break; - case nir_intrinsic_load_ubo: { - /* TODO: if offset is of the form (x + C) then add C to the base instead */ - unsigned idx = nir_src_as_const_value(intr->src[0])[0].u32; - unsigned dst_swiz; - emit_inst(state->c, &(struct etna_inst) { - .opcode = INST_OPCODE_LOAD, - .type = INST_TYPE_U32, - .dst = ra_dest(state, &intr->dest, &dst_swiz), - .src[0] = get_src(state, &intr->src[1]), - .src[1] = const_src(state, &CONST_VAL(ETNA_IMMEDIATE_UBO0_ADDR + idx, 0), 1), - }); + hw_dst dst = ra_dest(state, &intr->dest, &dst_swiz); + /* TODO: might have a problem with dst_swiz .. */ + emit(load_ubo, dst, get_src(state, &intr->src[0]), const_src(state, &UNIFORM_BASE(nir_intrinsic_base(intr) * 16), 1)); } break; case nir_intrinsic_load_front_face: case nir_intrinsic_load_frag_coord: @@ -1143,8 +1032,7 @@ emit_intrinsic(struct state *state, nir_intrinsic_instr * intr) case nir_intrinsic_load_instance_id: break; default: - compile_error(state->c, "Unhandled NIR intrinsic type: %s\n", - nir_intrinsic_infos[intr->intrinsic].name); + assert(0); } } @@ -1165,10 +1053,9 @@ emit_instr(struct state *state, nir_instr * instr) assert(nir_instr_is_last(instr)); case nir_instr_type_load_const: case nir_instr_type_ssa_undef: - case nir_instr_type_deref: break; default: - compile_error(state->c, "Unhandled NIR instruction type: %d\n", instr->type); + assert(0); break; } } @@ -1221,7 +1108,7 @@ emit_cf_list(struct state *state, struct exec_list *list) emit_cf_list(state, &nir_cf_node_as_loop(node)->body); break; default: - compile_error(state->c, "Unknown NIR node type\n"); + assert(0); break; } } @@ -1293,13 +1180,41 @@ lower_alu(struct state *state, nir_alu_instr *alu) switch (alu->op) { case nir_op_vec2: case nir_op_vec3: - case nir_op_vec4: - break; - default: - /* pre-GC7000L can only have 1 uniform src per instruction */ - if (state->c->specs->halti >= 5) + case nir_op_vec4: { + nir_const_value value[4]; + unsigned num_components = 0; + + for (unsigned i = 0; i < info->num_inputs; i++) { + nir_const_value *cv = nir_src_as_const_value(alu->src[i].src); + if (cv) + value[num_components++] = cv[alu->src[i].swizzle[0]]; + } + + if (num_components <= 1) /* nothing to do */ + break; + + nir_ssa_def *def = nir_build_imm(&b, num_components, 32, value); + + if (num_components == info->num_inputs) { + nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(def)); + nir_instr_remove(&alu->instr); return; + } + for (unsigned i = 0, j = 0; i < info->num_inputs; i++) { + nir_const_value *cv = nir_src_as_const_value(alu->src[i].src); + if (!cv) + continue; + + nir_instr_rewrite_src(&alu->instr, &alu->src[i].src, nir_src_for_ssa(def)); + alu->src[i].swizzle[0] = j++; + } + } break; + default: { + if (!option(single_const_src)) + return; + + /* pre-GC7000L can only have 1 uniform src per instruction */ nir_const_value value[4] = {}; uint8_t swizzle[4][4] = {}; unsigned swiz_max = 0, num_const = 0; @@ -1353,39 +1268,7 @@ lower_alu(struct state *state, nir_alu_instr *alu) nir_ssa_def *mov = nir_mov(&b, alu->src[i].src.ssa); nir_instr_rewrite_src(&alu->instr, &alu->src[i].src, nir_src_for_ssa(mov)); } - return; - } - - nir_const_value value[4]; - unsigned num_components = 0; - - for (unsigned i = 0; i < info->num_inputs; i++) { - nir_const_value *cv = nir_src_as_const_value(alu->src[i].src); - if (cv) - value[num_components++] = cv[alu->src[i].swizzle[0]]; - } - - /* if there is more than one constant source to the vecN, combine them - * into a single load_const (removing the vecN completely if all components - * are constant) - */ - if (num_components > 1) { - nir_ssa_def *def = nir_build_imm(&b, num_components, 32, value); - - if (num_components == info->num_inputs) { - nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(def)); - nir_instr_remove(&alu->instr); - return; - } - - for (unsigned i = 0, j = 0; i < info->num_inputs; i++) { - nir_const_value *cv = nir_src_as_const_value(alu->src[i].src); - if (!cv) - continue; - - nir_instr_rewrite_src(&alu->instr, &alu->src[i].src, nir_src_for_ssa(def)); - alu->src[i].swizzle[0] = j++; - } + } return; } unsigned finished_write_mask = 0; @@ -1422,17 +1305,14 @@ lower_alu(struct state *state, nir_alu_instr *alu) } static bool -emit_shader(struct etna_compile *c, unsigned *num_temps, unsigned *num_consts) +emit_shader(nir_shader *shader, const struct emit_options *options, + unsigned *num_temps, unsigned *num_consts) { - nir_shader *shader = c->nir; - struct state state = { - .c = c, + .options = options, .shader = shader, .impl = nir_shader_get_entrypoint(shader), }; - bool have_indirect_uniform = false; - unsigned indirect_max = 0; nir_builder b; nir_builder_init(&b, state.impl); @@ -1452,25 +1332,13 @@ emit_shader(struct etna_compile *c, unsigned *num_temps, unsigned *num_consts) } break; case nir_instr_type_intrinsic: { nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); - /* TODO: load_ubo can also become a constant in some cases - * (at the moment it can end up emitting a LOAD with two - * uniform sources, which could be a problem on HALTI2) - */ if (intr->intrinsic != nir_intrinsic_load_uniform) break; nir_const_value *off = nir_src_as_const_value(intr->src[0]); - if (!off || off[0].u64 >> 32 != ETNA_IMMEDIATE_CONSTANT) { - have_indirect_uniform = true; - indirect_max = nir_intrinsic_base(intr) + nir_intrinsic_range(intr); + if (!off || off[0].u64 >> 32 != ETNA_IMMEDIATE_CONSTANT) break; - } - unsigned base = nir_intrinsic_base(intr); - /* pre halti2 uniform offset will be float */ - if (c->specs->halti < 2) - base += (unsigned) off[0].f32; - else - base += off[0].u32; + unsigned base = nir_intrinsic_base(intr) + off[0].u32 / 16; nir_const_value value[4]; for (unsigned i = 0; i < intr->dest.ssa.num_components; i++) { @@ -1492,13 +1360,6 @@ emit_shader(struct etna_compile *c, unsigned *num_temps, unsigned *num_consts) } } - /* TODO: only emit required indirect uniform ranges */ - if (have_indirect_uniform) { - for (unsigned i = 0; i < indirect_max * 4; i++) - c->consts[i] = UNIFORM(i).u64; - state.const_count = indirect_max; - } - /* add mov for any store output using sysval/const */ nir_foreach_block(block, state.impl) { nir_foreach_instr_safe(instr, block) { @@ -1508,8 +1369,8 @@ emit_shader(struct etna_compile *c, unsigned *num_temps, unsigned *num_consts) nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); switch (intr->intrinsic) { - case nir_intrinsic_store_deref: { - nir_src *src = &intr->src[1]; + case nir_intrinsic_store_output: { + nir_src *src = &intr->src[0]; if (nir_src_is_const(*src) || is_sysval(src->ssa->parent_instr)) { b.cursor = nir_before_instr(instr); nir_instr_rewrite_src(instr, src, nir_src_for_ssa(nir_mov(&b, src->ssa))); diff --git a/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_blend.c b/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_blend.c index 4f3a91945..4ed9b53b6 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_blend.c +++ b/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_blend.c @@ -82,7 +82,7 @@ nir_alpha_saturate( { nir_ssa_def *Asrc = nir_channel(b, src, 3); nir_ssa_def *Adst = nir_channel(b, dst, 3); - nir_ssa_def *one = nir_imm_float(b, 1.0); + nir_ssa_def *one = nir_imm_float16(b, 1.0); nir_ssa_def *Adsti = nir_fsub(b, one, Adst); return (chan < 3) ? nir_fmin(b, Asrc, Adsti) : one; @@ -99,7 +99,7 @@ nir_blend_factor_value( { switch (factor) { case BLEND_FACTOR_ZERO: - return nir_imm_float(b, 0.0); + return nir_imm_float16(b, 0.0); case BLEND_FACTOR_SRC_COLOR: return nir_channel(b, src, chan); case BLEND_FACTOR_DST_COLOR: @@ -132,7 +132,7 @@ nir_blend_factor( nir_blend_factor_value(b, src, dst, bconst, chan, factor); if (inverted) - f = nir_fsub(b, nir_imm_float(b, 1.0), f); + f = nir_fsub(b, nir_imm_float16(b, 1.0), f); return nir_fmul(b, raw_scalar, f); } @@ -167,7 +167,7 @@ nir_blend( nir_ssa_def *src, nir_ssa_def *dst) { /* Grab the blend constant ahead of time */ - nir_ssa_def *bconst = nir_load_blend_const_color_rgba(b); + nir_ssa_def *bconst = nir_f2f16(b, nir_load_blend_const_color_rgba(b)); /* We blend per channel and recombine later */ nir_ssa_def *channels[4]; @@ -175,7 +175,7 @@ nir_blend( for (unsigned c = 0; c < 4; ++c) { /* Decide properties based on channel */ nir_lower_blend_channel chan = - (c < 3) ? options.rgb : options.alpha; + (c < 3) ? options.rt[0].rgb : options.rt[0].alpha; nir_ssa_def *psrc = nir_channel(b, src, c); nir_ssa_def *pdst = nir_channel(b, dst, c); @@ -197,7 +197,7 @@ nir_blend( /* Then just recombine with an applied colormask */ nir_ssa_def *blended = nir_vec(b, channels, 4); - return nir_color_mask(b, options.colormask, blended, dst); + return nir_color_mask(b, options.rt[0].colormask, blended, dst); } static bool @@ -214,8 +214,8 @@ static bool nir_is_blend_replace(nir_lower_blend_options options) { return - nir_is_blend_channel_replace(options.rgb) && - nir_is_blend_channel_replace(options.alpha); + nir_is_blend_channel_replace(options.rt[0].rgb) && + nir_is_blend_channel_replace(options.rt[0].alpha); } void @@ -249,13 +249,13 @@ nir_lower_blend(nir_shader *shader, nir_lower_blend_options options) b.cursor = nir_before_instr(instr); /* Grab the input color */ - nir_ssa_def *src = nir_ssa_for_src(&b, intr->src[1], 4); + nir_ssa_def *src = nir_f2f16(&b, nir_ssa_for_src(&b, intr->src[1], 4)); /* Grab the tilebuffer color - io lowered to load_output */ - nir_ssa_def *dst = nir_load_var(&b, var); + nir_ssa_def *dst = nir_f2f16(&b, nir_load_var(&b, var)); /* Blend the two colors per the passed options */ - nir_ssa_def *blended = nir_blend(&b, options, src, dst); + nir_ssa_def *blended = nir_f2f32(&b, nir_blend(&b, options, src, dst)); /* Write out the final color instead of the input */ nir_instr_rewrite_src(instr, &intr->src[1], diff --git a/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_blend.h b/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_blend.h index d150e99c7..ea99e2348 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_blend.h +++ b/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_blend.h @@ -43,17 +43,18 @@ typedef struct { } nir_lower_blend_channel; typedef struct { - nir_lower_blend_channel rgb; - nir_lower_blend_channel alpha; + struct { + nir_lower_blend_channel rgb; + nir_lower_blend_channel alpha; - /* 4-bit colormask. 0x0 for none, 0xF for RGBA, 0x1 for R */ - unsigned colormask; + /* 4-bit colormask. 0x0 for none, 0xF for RGBA, 0x1 for R */ + unsigned colormask; + } rt[8]; } nir_lower_blend_options; void nir_lower_blend(nir_shader *shader, nir_lower_blend_options options); void -nir_lower_framebuffer(nir_shader *shader, enum pipe_format format, - unsigned gpu_id); +nir_lower_framebuffer(nir_shader *shader, enum pipe_format format); #endif diff --git a/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_framebuffer.c b/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_framebuffer.c index 887b3662d..040cf6987 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_framebuffer.c +++ b/lib/mesa/src/gallium/drivers/panfrost/nir/nir_lower_framebuffer.c @@ -41,30 +41,7 @@ #include "compiler/nir/nir_builder.h" #include "compiler/nir/nir_format_convert.h" #include "nir_lower_blend.h" -#include "util/format/u_format.h" - -/* Determines the best NIR intrinsic to load a tile buffer of a given type, - * using native format conversion where possible. RGBA8 UNORM has a fast path - * (on some chips). Otherwise, we default to raw reads. */ - -static nir_intrinsic_op -nir_best_load_for_format( - const struct util_format_description *desc, - unsigned *special_bitsize, - unsigned *special_components, - unsigned gpu_id) -{ - if (util_format_is_unorm8(desc) && gpu_id != 0x750) { - *special_bitsize = 16; - return nir_intrinsic_load_output_u8_as_fp16_pan; - } else if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) { - *special_bitsize = 32; - *special_components = 1; - return nir_intrinsic_load_raw_output_pan; - } else - return nir_intrinsic_load_raw_output_pan; -} - +#include "util/u_format.h" /* Converters for UNORM8 formats, e.g. R8G8B8A8_UNORM */ @@ -72,14 +49,14 @@ static nir_ssa_def * nir_float_to_unorm8(nir_builder *b, nir_ssa_def *c_float) { /* First, we degrade quality to fp16; we don't need the extra bits */ - nir_ssa_def *degraded = /*nir_f2f16(b, c_float)*/c_float; + nir_ssa_def *degraded = nir_f2f16(b, c_float); /* Scale from [0, 1] to [0, 255.0] */ nir_ssa_def *scaled = nir_fmul_imm(b, nir_fsat(b, degraded), 255.0); /* Next, we type convert */ nir_ssa_def *converted = nir_u2u8(b, nir_f2u16(b, - nir_fround_even(b, nir_f2f16(b, scaled)))); + nir_fround_even(b, scaled))); return converted; } @@ -88,7 +65,7 @@ static nir_ssa_def * nir_unorm8_to_float(nir_builder *b, nir_ssa_def *c_native) { /* First, we convert up from u8 to f16 */ - nir_ssa_def *converted = nir_f2f32(b, nir_u2f16(b, nir_u2u16(b, c_native))); + nir_ssa_def *converted = nir_u2f16(b, nir_u2u16(b, c_native)); /* Next, we scale down from [0, 255.0] to [0, 1] */ nir_ssa_def *scaled = nir_fsat(b, nir_fmul_imm(b, converted, 1.0/255.0)); @@ -227,7 +204,6 @@ nir_shader_to_native(nir_builder *b, static nir_ssa_def * nir_native_to_shader(nir_builder *b, nir_ssa_def *c_native, - nir_intrinsic_op op, const struct util_format_description *desc, unsigned bits, bool homogenous_bits) @@ -236,45 +212,18 @@ nir_native_to_shader(nir_builder *b, util_format_is_float(desc->format) || util_format_is_pure_integer(desc->format); - /* Handle preconverted formats */ - if (op == nir_intrinsic_load_output_u8_as_fp16_pan) { - assert(util_format_is_unorm8(desc)); - return nir_f2f32(b, c_native); - } - - /* Otherwise, we're raw */ - assert(op == nir_intrinsic_load_raw_output_pan); - if (util_format_is_unorm8(desc)) return nir_unorm8_to_float(b, c_native); else if (homogenous_bits && float_or_pure_int) return c_native; /* type is already correct */ - - /* Special formats */ - switch (desc->format) { - case PIPE_FORMAT_R11G11B10_FLOAT: { - nir_ssa_def *unpacked = nir_format_unpack_11f11f10f(b, c_native); - - /* Extend to vec4 with alpha */ - nir_ssa_def *components[4] = { - nir_channel(b, unpacked, 0), - nir_channel(b, unpacked, 1), - nir_channel(b, unpacked, 2), - nir_imm_float(b, 1.0) - }; - - return nir_vec(b, components, 4); - } - - default: + else { printf("%s\n", desc->name); unreachable("Unknown format name"); } } void -nir_lower_framebuffer(nir_shader *shader, enum pipe_format format, - unsigned gpu_id) +nir_lower_framebuffer(nir_shader *shader, enum pipe_format format) { /* Blend shaders are represented as special fragment shaders */ assert(shader->info.stage == MESA_SHADER_FRAGMENT); @@ -338,22 +287,6 @@ nir_lower_framebuffer(nir_shader *shader, enum pipe_format format, /* Grab the input color */ nir_ssa_def *c_nir = nir_ssa_for_src(&b, intr->src[1], 4); - /* Apply sRGB transform */ - - if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) { - nir_ssa_def *rgb = nir_channels(&b, c_nir, 0x7); - nir_ssa_def *trans = nir_format_linear_to_srgb(&b, rgb); - - nir_ssa_def *comp[4] = { - nir_channel(&b, trans, 0), - nir_channel(&b, trans, 1), - nir_channel(&b, trans, 2), - nir_channel(&b, c_nir, 3), - }; - - c_nir = nir_vec(&b, comp, 4); - } - /* Format convert */ nir_ssa_def *converted = nir_shader_to_native(&b, c_nir, format_desc, bits, homogenous_bits); @@ -381,29 +314,20 @@ nir_lower_framebuffer(nir_shader *shader, enum pipe_format format, /* For loads, add conversion after */ b.cursor = nir_after_instr(instr); - /* Determine the best op for the format/hardware */ - unsigned bitsize = raw_bitsize_in; - unsigned components = 4; - nir_intrinsic_op op = nir_best_load_for_format(format_desc, - &bitsize, - &components, - gpu_id); - /* Rewrite to use a native load by creating a new intrinsic */ - nir_intrinsic_instr *new = nir_intrinsic_instr_create(shader, op); - new->num_components = components; - nir_ssa_dest_init(&new->instr, &new->dest, components, bitsize, NULL); + nir_intrinsic_instr *new = + nir_intrinsic_instr_create(shader, nir_intrinsic_load_raw_output_pan); + + new->num_components = 4; + + unsigned bitsize = raw_bitsize_in; + nir_ssa_dest_init(&new->instr, &new->dest, 4, bitsize, NULL); nir_builder_instr_insert(&b, &new->instr); /* Convert the raw value */ nir_ssa_def *raw = &new->dest.ssa; - nir_ssa_def *converted = nir_native_to_shader(&b, raw, op, format_desc, bits, homogenous_bits); - - if (util_format_is_float(format)) - converted = nir_f2f32(&b, converted); - else - converted = nir_i2i32(&b, converted); + nir_ssa_def *converted = nir_native_to_shader(&b, raw, format_desc, bits, homogenous_bits); /* Rewrite to use the converted value */ nir_src rewritten = nir_src_for_ssa(converted); diff --git a/lib/mesa/src/gallium/drivers/panfrost/pan_allocate.c b/lib/mesa/src/gallium/drivers/panfrost/pan_allocate.c index b16a1253a..f549c864c 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/pan_allocate.c +++ b/lib/mesa/src/gallium/drivers/panfrost/pan_allocate.c @@ -29,19 +29,42 @@ #include <assert.h> #include <panfrost-misc.h> #include <panfrost-job.h> -#include "pan_bo.h" #include "pan_context.h" /* TODO: What does this actually have to be? */ #define ALIGNMENT 128 +/* Allocate a new transient slab */ + +static struct panfrost_bo * +panfrost_create_slab(struct panfrost_screen *screen, unsigned *index) +{ + /* Allocate a new slab on the screen */ + + struct panfrost_bo **new = + util_dynarray_grow(&screen->transient_bo, + struct panfrost_bo *, 1); + + struct panfrost_bo *alloc = panfrost_drm_create_bo(screen, TRANSIENT_SLAB_SIZE, 0); + + *new = alloc; + + /* Return the BO as well as the index we just added */ + + *index = util_dynarray_num_elements(&screen->transient_bo, void *) - 1; + return alloc; +} + /* Transient command stream pooling: command stream uploads try to simply copy * into whereever we left off. If there isn't space, we allocate a new entry * into the pool and copy there */ struct panfrost_transfer -panfrost_allocate_transient(struct panfrost_batch *batch, size_t sz) +panfrost_allocate_transient(struct panfrost_context *ctx, size_t sz) { + struct panfrost_screen *screen = pan_screen(ctx->base.screen); + struct panfrost_job *batch = panfrost_get_job_for_fbo(ctx); + /* Pad the size */ sz = ALIGN_POT(sz, ALIGNMENT); @@ -49,37 +72,56 @@ panfrost_allocate_transient(struct panfrost_batch *batch, size_t sz) struct panfrost_bo *bo = NULL; unsigned offset = 0; + bool update_offset = false; + bool has_current = batch->transient_indices.size; bool fits_in_current = (batch->transient_offset + sz) < TRANSIENT_SLAB_SIZE; - if (likely(batch->transient_bo && fits_in_current)) { - /* We can reuse the current BO, so get it */ - bo = batch->transient_bo; + if (likely(has_current && fits_in_current)) { + /* We can reuse the topmost BO, so get it */ + unsigned idx = util_dynarray_top(&batch->transient_indices, unsigned); + bo = pan_bo_for_index(screen, idx); /* Use the specified offset */ offset = batch->transient_offset; - batch->transient_offset = offset + sz; - } else { - size_t bo_sz = sz < TRANSIENT_SLAB_SIZE ? - TRANSIENT_SLAB_SIZE : ALIGN_POT(sz, 4096); - - /* We can't reuse the current BO, but we can create a new one. - * We don't know what the BO will be used for, so let's flag it - * RW and attach it to both the fragment and vertex/tiler jobs. - * TODO: if we want fine grained BO assignment we should pass - * flags to this function and keep the read/write, - * fragment/vertex+tiler pools separate. - */ - bo = panfrost_batch_create_bo(batch, bo_sz, 0, - PAN_BO_ACCESS_PRIVATE | - PAN_BO_ACCESS_RW | - PAN_BO_ACCESS_VERTEX_TILER | - PAN_BO_ACCESS_FRAGMENT); - - if (sz < TRANSIENT_SLAB_SIZE) { - batch->transient_bo = bo; - batch->transient_offset = offset + sz; + update_offset = true; + } else if (sz < TRANSIENT_SLAB_SIZE) { + /* We can't reuse the topmost BO, but we can get a new one. + * First, look for a free slot */ + + unsigned count = util_dynarray_num_elements(&screen->transient_bo, void *); + unsigned index = 0; + + unsigned free = __bitset_ffs( + screen->free_transient, + count / BITSET_WORDBITS); + + if (likely(free)) { + /* Use this one */ + index = free - 1; + + /* It's ours, so no longer free */ + BITSET_CLEAR(screen->free_transient, index); + + /* Grab the BO */ + bo = pan_bo_for_index(screen, index); + } else { + /* Otherwise, create a new BO */ + bo = panfrost_create_slab(screen, &index); } + + /* Remember we created this */ + util_dynarray_append(&batch->transient_indices, unsigned, index); + + update_offset = true; + } else { + /* Create a new BO and reference it */ + bo = panfrost_drm_create_bo(screen, ALIGN_POT(sz, 4096), 0); + panfrost_job_add_bo(batch, bo); + + /* Creating a BO adds a reference, and then the job adds a + * second one. So we need to pop back one reference */ + panfrost_bo_unreference(&screen->base, bo); } struct panfrost_transfer ret = { @@ -87,15 +129,40 @@ panfrost_allocate_transient(struct panfrost_batch *batch, size_t sz) .gpu = bo->gpu + offset, }; + if (update_offset) + batch->transient_offset = offset + sz; + return ret; } mali_ptr -panfrost_upload_transient(struct panfrost_batch *batch, const void *data, - size_t sz) +panfrost_upload_transient(struct panfrost_context *ctx, const void *data, size_t sz) { - struct panfrost_transfer transfer = panfrost_allocate_transient(batch, sz); + struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sz); memcpy(transfer.cpu, data, sz); return transfer.gpu; } + +/* The code below is exclusively for the use of shader memory and is subject to + * be rewritten soon enough since it never frees the memory it allocates. Here + * be dragons, etc. */ + +mali_ptr +panfrost_upload(struct panfrost_memory *mem, const void *data, size_t sz) +{ + size_t aligned_sz = ALIGN_POT(sz, ALIGNMENT); + + /* Bounds check */ + if ((mem->stack_bottom + aligned_sz) >= mem->bo->size) { + printf("Out of memory, tried to upload %zd but only %zd available\n", + sz, mem->bo->size - mem->stack_bottom); + assert(0); + } + + memcpy((uint8_t *) mem->bo->cpu + mem->stack_bottom, data, sz); + mali_ptr gpu = mem->bo->gpu + mem->stack_bottom; + + mem->stack_bottom += aligned_sz; + return gpu; +} diff --git a/lib/mesa/src/gallium/drivers/panfrost/pan_allocate.h b/lib/mesa/src/gallium/drivers/panfrost/pan_allocate.h index f18218fb3..0e06567d2 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/pan_allocate.h +++ b/lib/mesa/src/gallium/drivers/panfrost/pan_allocate.h @@ -33,7 +33,7 @@ #include "util/list.h" -struct panfrost_batch; +struct panfrost_context; /* Represents a fat pointer for GPU-mapped memory, returned from the transient * allocator and not used for much else */ @@ -43,11 +43,46 @@ struct panfrost_transfer { mali_ptr gpu; }; +struct panfrost_bo { + /* Must be first for casting */ + struct list_head link; + + struct pipe_reference reference; + + /* Mapping for the entire object (all levels) */ + uint8_t *cpu; + + /* GPU address for the object */ + mali_ptr gpu; + + /* Size of all entire trees */ + size_t size; + + int gem_handle; + + uint32_t flags; +}; + +struct panfrost_memory { + /* Backing for the slab in memory */ + struct panfrost_bo *bo; + int stack_bottom; +}; + +/* Functions for the actual Galliumish driver */ +mali_ptr panfrost_upload(struct panfrost_memory *mem, const void *data, size_t sz); + struct panfrost_transfer -panfrost_allocate_transient(struct panfrost_batch *batch, size_t sz); +panfrost_allocate_transient(struct panfrost_context *ctx, size_t sz); mali_ptr -panfrost_upload_transient(struct panfrost_batch *batch, const void *data, - size_t sz); +panfrost_upload_transient(struct panfrost_context *ctx, const void *data, size_t sz); + +static inline mali_ptr +panfrost_reserve(struct panfrost_memory *mem, size_t sz) +{ + mem->stack_bottom += sz; + return mem->bo->gpu + (mem->stack_bottom - sz); +} #endif /* __PAN_ALLOCATE_H__ */ diff --git a/lib/mesa/src/gallium/drivers/panfrost/pan_blend.h b/lib/mesa/src/gallium/drivers/panfrost/pan_blend.h index 1b1cb9df3..83fe35e32 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/pan_blend.h +++ b/lib/mesa/src/gallium/drivers/panfrost/pan_blend.h @@ -55,8 +55,8 @@ struct panfrost_blend_shader { /* A blend shader descriptor ready for actual use */ struct panfrost_blend_shader_final { - /* GPU address where we're compiled to */ - uint64_t gpu; + /* The compiled shader in GPU memory, possibly patched */ + struct panfrost_bo *bo; /* First instruction tag (for tagging the pointer) */ unsigned first_tag; @@ -113,6 +113,6 @@ void panfrost_blend_context_init(struct pipe_context *pipe); struct panfrost_blend_final -panfrost_get_blend_for_context(struct panfrost_context *ctx, unsigned rt, struct panfrost_bo **bo, unsigned *shader_offset); +panfrost_get_blend_for_context(struct panfrost_context *ctx, unsigned rt); #endif diff --git a/lib/mesa/src/gallium/drivers/panfrost/pan_blend_shaders.c b/lib/mesa/src/gallium/drivers/panfrost/pan_blend_shaders.c index cca2eb567..2ee86b4e7 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/pan_blend_shaders.c +++ b/lib/mesa/src/gallium/drivers/panfrost/pan_blend_shaders.c @@ -85,41 +85,43 @@ */ static nir_lower_blend_options -nir_make_options(const struct pipe_blend_state *blend, unsigned i) +nir_make_options(const struct pipe_blend_state *blend, unsigned nr_cbufs) { nir_lower_blend_options options; - /* If blend is disabled, we just use replace mode */ - - nir_lower_blend_channel rgb = { - .func = BLEND_FUNC_ADD, - .src_factor = BLEND_FACTOR_ZERO, - .invert_src_factor = true, - .dst_factor = BLEND_FACTOR_ZERO, - .invert_dst_factor = false - }; - - nir_lower_blend_channel alpha = rgb; - - if (blend->rt[i].blend_enable) { - rgb.func = util_blend_func_to_shader(blend->rt[i].rgb_func); - rgb.src_factor = util_blend_factor_to_shader(blend->rt[i].rgb_src_factor); - rgb.dst_factor = util_blend_factor_to_shader(blend->rt[i].rgb_dst_factor); - rgb.invert_src_factor = util_blend_factor_is_inverted(blend->rt[i].rgb_src_factor); - rgb.invert_dst_factor = util_blend_factor_is_inverted(blend->rt[i].rgb_dst_factor); - - alpha.func = util_blend_func_to_shader(blend->rt[i].alpha_func); - alpha.src_factor = util_blend_factor_to_shader(blend->rt[i].alpha_src_factor); - alpha.dst_factor = util_blend_factor_to_shader(blend->rt[i].alpha_dst_factor); - alpha.invert_src_factor = util_blend_factor_is_inverted(blend->rt[i].alpha_src_factor); - alpha.invert_dst_factor = util_blend_factor_is_inverted(blend->rt[i].alpha_dst_factor); + for (unsigned i = 0; i < nr_cbufs; ++i) { + /* If blend is disabled, we just use replace mode */ + + nir_lower_blend_channel rgb = { + .func = BLEND_FUNC_ADD, + .src_factor = BLEND_FACTOR_ZERO, + .invert_src_factor = true, + .dst_factor = BLEND_FACTOR_ZERO, + .invert_dst_factor = false + }; + + nir_lower_blend_channel alpha = rgb; + + if (blend->rt[i].blend_enable) { + rgb.func = util_blend_func_to_shader(blend->rt[i].rgb_func); + rgb.src_factor = util_blend_factor_to_shader(blend->rt[i].rgb_src_factor); + rgb.dst_factor = util_blend_factor_to_shader(blend->rt[i].rgb_dst_factor); + rgb.invert_src_factor = util_blend_factor_is_inverted(blend->rt[i].rgb_src_factor); + rgb.invert_dst_factor = util_blend_factor_is_inverted(blend->rt[i].rgb_dst_factor); + + alpha.func = util_blend_func_to_shader(blend->rt[i].alpha_func); + alpha.src_factor = util_blend_factor_to_shader(blend->rt[i].alpha_src_factor); + alpha.dst_factor = util_blend_factor_to_shader(blend->rt[i].alpha_dst_factor); + alpha.invert_src_factor = util_blend_factor_is_inverted(blend->rt[i].alpha_src_factor); + alpha.invert_dst_factor = util_blend_factor_is_inverted(blend->rt[i].alpha_dst_factor); + } + + options.rt[i].rgb = rgb; + options.rt[i].alpha = alpha; + + options.rt[i].colormask = blend->rt[i].colormask; } - options.rgb = rgb; - options.alpha = alpha; - - options.colormask = blend->rt[i].colormask; - return options; } @@ -127,10 +129,8 @@ struct panfrost_blend_shader panfrost_compile_blend_shader( struct panfrost_context *ctx, struct pipe_blend_state *cso, - enum pipe_format format, - unsigned rt) + enum pipe_format format) { - struct panfrost_screen *screen = pan_screen(ctx->base.screen); struct panfrost_blend_shader res; res.ctx = ctx; @@ -164,15 +164,18 @@ panfrost_compile_blend_shader( nir_store_var(b, c_out, s_src, 0xFF); nir_lower_blend_options options = - nir_make_options(cso, rt); + nir_make_options(cso, 1); NIR_PASS_V(shader, nir_lower_blend, options); - NIR_PASS_V(shader, nir_lower_framebuffer, format, screen->gpu_id); + NIR_PASS_V(shader, nir_lower_framebuffer, format); /* Compile the built shader */ midgard_program program; - midgard_compile_shader_nir(shader, &program, true, rt, screen->gpu_id, false); + midgard_compile_shader_nir(&ctx->compiler, shader, &program, true); + + /* At least two work registers are needed due to an encoding quirk */ + res.work_count = MAX2(program.work_register_count, 2); /* Allow us to patch later */ res.patch_index = program.blend_patch_offset; diff --git a/lib/mesa/src/gallium/drivers/panfrost/pan_blend_shaders.h b/lib/mesa/src/gallium/drivers/panfrost/pan_blend_shaders.h index 5931cbc41..88ece5436 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/pan_blend_shaders.h +++ b/lib/mesa/src/gallium/drivers/panfrost/pan_blend_shaders.h @@ -35,7 +35,6 @@ struct panfrost_blend_shader panfrost_compile_blend_shader( struct panfrost_context *ctx, struct pipe_blend_state *cso, - enum pipe_format format, - unsigned rt); + enum pipe_format format); #endif diff --git a/lib/mesa/src/gallium/drivers/panfrost/pan_blending.c b/lib/mesa/src/gallium/drivers/panfrost/pan_blending.c index 297bd0f3f..2788d213f 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/pan_blending.c +++ b/lib/mesa/src/gallium/drivers/panfrost/pan_blending.c @@ -26,7 +26,7 @@ #include "pan_blending.h" #include "pan_context.h" #include "gallium/auxiliary/util/u_blend.h" -#include "util/format/u_format.h" +#include "util/u_format.h" /* * Implements fixed-function blending on Midgard. diff --git a/lib/mesa/src/gallium/drivers/panfrost/pan_fragment.c b/lib/mesa/src/gallium/drivers/panfrost/pan_fragment.c index 88b2db3c9..778bc8510 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/pan_fragment.c +++ b/lib/mesa/src/gallium/drivers/panfrost/pan_fragment.c @@ -25,15 +25,14 @@ #include "pan_context.h" #include "pan_util.h" #include "pan_format.h" -#include "panfrost-quirks.h" -#include "util/format/u_format.h" +#include "util/u_format.h" /* Mark a surface as written */ static void panfrost_initialize_surface( - struct panfrost_batch *batch, + struct panfrost_job *batch, struct pipe_surface *surf) { if (!surf) @@ -43,25 +42,28 @@ panfrost_initialize_surface( struct panfrost_resource *rsrc = pan_resource(surf->texture); rsrc->slices[level].initialized = true; + + assert(rsrc->bo); + panfrost_job_add_bo(batch, rsrc->bo); } /* Generate a fragment job. This should be called once per frame. (According to * presentations, this is supposed to correspond to eglSwapBuffers) */ mali_ptr -panfrost_fragment_job(struct panfrost_batch *batch, bool has_draws, - struct mali_job_descriptor_header **header_cpu) +panfrost_fragment_job(struct panfrost_context *ctx, bool has_draws) { - struct panfrost_screen *screen = pan_screen(batch->ctx->base.screen); + struct panfrost_screen *screen = pan_screen(ctx->base.screen); - mali_ptr framebuffer = (screen->quirks & MIDGARD_SFBD) ? - panfrost_sfbd_fragment(batch, has_draws) : - panfrost_mfbd_fragment(batch, has_draws); + mali_ptr framebuffer = screen->require_sfbd ? + panfrost_sfbd_fragment(ctx, has_draws) : + panfrost_mfbd_fragment(ctx, has_draws); /* Mark the affected buffers as initialized, since we're writing to it. * Also, add the surfaces we're writing to to the batch */ - struct pipe_framebuffer_state *fb = &batch->key; + struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer; + struct panfrost_job *batch = panfrost_get_job_for_fbo(ctx); for (unsigned i = 0; i < fb->nr_cbufs; ++i) { panfrost_initialize_surface(batch, fb->cbufs[i]); @@ -76,6 +78,8 @@ panfrost_fragment_job(struct panfrost_batch *batch, bool has_draws, .job_descriptor_size = 1 }; + struct panfrost_job *job = panfrost_get_job_for_fbo(ctx); + /* The passed tile coords can be out of range in some cases, so we need * to clamp them to the framebuffer size to avoid a TILE_RANGE_FAULT. * Theoretically we also need to clamp the coordinates positive, but we @@ -87,24 +91,27 @@ panfrost_fragment_job(struct panfrost_batch *batch, bool has_draws, * But that can't happen if any actual drawing occurs (beyond a * wallpaper reload), so this is again irrelevant in practice. */ - batch->maxx = MIN2(batch->maxx, fb->width); - batch->maxy = MIN2(batch->maxy, fb->height); + job->maxx = MIN2(job->maxx, fb->width); + job->maxy = MIN2(job->maxy, fb->height); /* Rendering region must be at least 1x1; otherwise, there is nothing * to do and the whole job chain should have been discarded. */ - assert(batch->maxx > batch->minx); - assert(batch->maxy > batch->miny); + assert(job->maxx > job->minx); + assert(job->maxy > job->miny); struct mali_payload_fragment payload = { - .min_tile_coord = MALI_COORDINATE_TO_TILE_MIN(batch->minx, batch->miny), - .max_tile_coord = MALI_COORDINATE_TO_TILE_MAX(batch->maxx, batch->maxy), + .min_tile_coord = MALI_COORDINATE_TO_TILE_MIN(job->minx, job->miny), + .max_tile_coord = MALI_COORDINATE_TO_TILE_MAX(job->maxx, job->maxy), .framebuffer = framebuffer, }; - struct panfrost_transfer transfer = panfrost_allocate_transient(batch, sizeof(header) + sizeof(payload)); + /* Normally, there should be no padding. However, fragment jobs are + * shared with 64-bit Bifrost systems, and accordingly there is 4-bytes + * of zero padding in between. */ + + struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(header) + sizeof(payload)); memcpy(transfer.cpu, &header, sizeof(header)); memcpy(transfer.cpu + sizeof(header), &payload, sizeof(payload)); - *header_cpu = (struct mali_job_descriptor_header *)transfer.cpu; return transfer.gpu; } diff --git a/lib/mesa/src/gallium/drivers/panfrost/pan_mfbd.c b/lib/mesa/src/gallium/drivers/panfrost/pan_mfbd.c index fe427c452..bae3429af 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/pan_mfbd.c +++ b/lib/mesa/src/gallium/drivers/panfrost/pan_mfbd.c @@ -22,12 +22,34 @@ * */ -#include "pan_bo.h" #include "pan_context.h" #include "pan_util.h" #include "pan_format.h" -#include "util/format/u_format.h" +#include "util/u_format.h" + +static void +panfrost_invert_swizzle(const unsigned char *in, unsigned char *out) +{ + /* First, default to all zeroes to prevent uninitialized junk */ + + for (unsigned c = 0; c < 4; ++c) + out[c] = PIPE_SWIZZLE_0; + + /* Now "do" what the swizzle says */ + + for (unsigned c = 0; c < 4; ++c) { + unsigned char i = in[c]; + + /* Who cares? */ + if (i < PIPE_SWIZZLE_X || i > PIPE_SWIZZLE_W) + continue; + + /* Invert */ + unsigned idx = i - PIPE_SWIZZLE_X; + out[idx] = PIPE_SWIZZLE_X + c; + } +} static struct mali_rt_format panfrost_mfbd_format(struct pipe_surface *surf) @@ -156,28 +178,28 @@ panfrost_mfbd_format(struct pipe_surface *surf) static void panfrost_mfbd_clear( - struct panfrost_batch *batch, + struct panfrost_job *job, struct bifrost_framebuffer *fb, struct bifrost_fb_extra *fbx, struct bifrost_render_target *rts, unsigned rt_count) { for (unsigned i = 0; i < rt_count; ++i) { - if (!(batch->clear & (PIPE_CLEAR_COLOR0 << i))) + if (!(job->clear & (PIPE_CLEAR_COLOR0 << i))) continue; - rts[i].clear_color_1 = batch->clear_color[i][0]; - rts[i].clear_color_2 = batch->clear_color[i][1]; - rts[i].clear_color_3 = batch->clear_color[i][2]; - rts[i].clear_color_4 = batch->clear_color[i][3]; + rts[i].clear_color_1 = job->clear_color[i][0]; + rts[i].clear_color_2 = job->clear_color[i][1]; + rts[i].clear_color_3 = job->clear_color[i][2]; + rts[i].clear_color_4 = job->clear_color[i][3]; } - if (batch->clear & PIPE_CLEAR_DEPTH) { - fb->clear_depth = batch->clear_depth; + if (job->clear & PIPE_CLEAR_DEPTH) { + fb->clear_depth = job->clear_depth; } - if (batch->clear & PIPE_CLEAR_STENCIL) { - fb->clear_stencil = batch->clear_stencil; + if (job->clear & PIPE_CLEAR_STENCIL) { + fb->clear_stencil = job->clear_stencil; } } @@ -200,15 +222,15 @@ panfrost_mfbd_set_cbuf( /* Now, we set the layout specific pieces */ if (rsrc->layout == PAN_LINEAR) { - rt->format.block = MALI_BLOCK_LINEAR; + rt->format.block = MALI_MFBD_BLOCK_LINEAR; rt->framebuffer = base; rt->framebuffer_stride = stride / 16; } else if (rsrc->layout == PAN_TILED) { - rt->format.block = MALI_BLOCK_TILED; + rt->format.block = MALI_MFBD_BLOCK_TILED; rt->framebuffer = base; rt->framebuffer_stride = stride; } else if (rsrc->layout == PAN_AFBC) { - rt->format.block = MALI_BLOCK_AFBC; + rt->format.block = MALI_MFBD_BLOCK_AFBC; unsigned header_size = rsrc->slices[level].header_size; @@ -226,6 +248,20 @@ panfrost_mfbd_set_cbuf( } } +/* Is a format encoded like Z24S8 and therefore compatible for render? */ + +static bool +panfrost_is_z24s8_variant(enum pipe_format fmt) +{ + switch (fmt) { + case PIPE_FORMAT_Z24_UNORM_S8_UINT: + case PIPE_FORMAT_Z24X8_UNORM: + return true; + default: + return false; + } +} + static void panfrost_mfbd_set_zsbuf( struct bifrost_framebuffer *fb, @@ -235,23 +271,26 @@ panfrost_mfbd_set_zsbuf( struct panfrost_resource *rsrc = pan_resource(surf->texture); unsigned level = surf->u.tex.level; - unsigned first_layer = surf->u.tex.first_layer; - assert(surf->u.tex.last_layer == first_layer); + assert(surf->u.tex.first_layer == 0); - mali_ptr base = panfrost_get_texture_address(rsrc, level, first_layer); + unsigned offset = rsrc->slices[level].offset; if (rsrc->layout == PAN_AFBC) { /* The only Z/S format we can compress is Z24S8 or variants * thereof (handled by the state tracker) */ assert(panfrost_is_z24s8_variant(surf->format)); + mali_ptr base = rsrc->bo->gpu + offset; unsigned header_size = rsrc->slices[level].header_size; fb->mfbd_flags |= MALI_MFBD_EXTRA; - fbx->flags_hi |= MALI_EXTRA_PRESENT; - fbx->flags_lo |= MALI_EXTRA_ZS | 0x1; /* unknown */ - fbx->zs_block = MALI_BLOCK_AFBC; + fbx->flags = + MALI_EXTRA_PRESENT | + MALI_EXTRA_AFBC | + MALI_EXTRA_AFBC_ZS | + MALI_EXTRA_ZS | + 0x1; /* unknown */ fbx->ds_afbc.depth_stencil = base + header_size; fbx->ds_afbc.depth_stencil_afbc_metadata = base; @@ -259,43 +298,34 @@ panfrost_mfbd_set_zsbuf( fbx->ds_afbc.zero1 = 0x10009; fbx->ds_afbc.padding = 0x1000; - } else if (rsrc->layout == PAN_LINEAR || rsrc->layout == PAN_TILED) { + } else if (rsrc->layout == PAN_LINEAR) { /* TODO: Z32F(S8) support, which is always linear */ int stride = rsrc->slices[level].stride; fb->mfbd_flags |= MALI_MFBD_EXTRA; - fbx->flags_hi |= MALI_EXTRA_PRESENT; - fbx->flags_lo |= MALI_EXTRA_ZS; + fbx->flags |= MALI_EXTRA_PRESENT | MALI_EXTRA_ZS; - fbx->ds_linear.depth = base; - - if (rsrc->layout == PAN_LINEAR) { - fbx->zs_block = MALI_BLOCK_LINEAR; - fbx->ds_linear.depth_stride = stride / 16; - } else { - fbx->zs_block = MALI_BLOCK_TILED; - fbx->ds_linear.depth_stride = stride; - } + fbx->ds_linear.depth = rsrc->bo->gpu + offset; + fbx->ds_linear.depth_stride = stride; if (panfrost_is_z24s8_variant(surf->format)) { - fbx->flags_lo |= 0x1; + fbx->flags |= 0x1; } else if (surf->format == PIPE_FORMAT_Z32_UNORM) { /* default flags (0 in bottom place) */ } else if (surf->format == PIPE_FORMAT_Z32_FLOAT) { - fbx->flags_lo |= 0xA; + fbx->flags |= 0xA; fb->mfbd_flags ^= 0x100; fb->mfbd_flags |= 0x200; } else if (surf->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { - fbx->flags_hi |= 0x400; - fbx->flags_lo |= 0xA; + fbx->flags |= 0x1000A; fb->mfbd_flags ^= 0x100; fb->mfbd_flags |= 0x201; struct panfrost_resource *stencil = rsrc->separate_stencil; struct panfrost_slice stencil_slice = stencil->slices[level]; - fbx->ds_linear.stencil = panfrost_get_texture_address(stencil, level, first_layer); + fbx->ds_linear.stencil = stencil->bo->gpu + stencil_slice.offset; fbx->ds_linear.stencil_stride = stencil_slice.stride; } @@ -314,7 +344,8 @@ panfrost_mfbd_set_zsbuf( } static mali_ptr -panfrost_mfbd_upload(struct panfrost_batch *batch, +panfrost_mfbd_upload( + struct panfrost_context *ctx, struct bifrost_framebuffer *fb, struct bifrost_fb_extra *fbx, struct bifrost_render_target *rts, @@ -333,7 +364,7 @@ panfrost_mfbd_upload(struct panfrost_batch *batch, sizeof(struct bifrost_render_target) * 4; struct panfrost_transfer m_f_trans = - panfrost_allocate_transient(batch, total_sz); + panfrost_allocate_transient(ctx, total_sz); /* Do the transfer */ @@ -349,7 +380,7 @@ panfrost_mfbd_upload(struct panfrost_batch *batch, /* Return pointer suitable for the fragment section */ unsigned tag = MALI_MFBD | - (has_extra ? MALI_MFBD_TAG_EXTRA : 0) | + (has_extra ? 0x2 : 0x0) | (MALI_POSITIVE(rt_count) << 2); return m_f_trans.gpu | tag; @@ -357,74 +388,34 @@ panfrost_mfbd_upload(struct panfrost_batch *batch, #undef UPLOAD -static struct bifrost_framebuffer -panfrost_emit_mfbd(struct panfrost_batch *batch, unsigned vertex_count) -{ - struct panfrost_context *ctx = batch->ctx; - struct pipe_context *gallium = (struct pipe_context *) ctx; - struct panfrost_screen *screen = pan_screen(gallium->screen); - - unsigned width = batch->key.width; - unsigned height = batch->key.height; - - unsigned shift = panfrost_get_stack_shift(batch->stack_size); - - struct bifrost_framebuffer framebuffer = { - .width1 = MALI_POSITIVE(width), - .height1 = MALI_POSITIVE(height), - .width2 = MALI_POSITIVE(width), - .height2 = MALI_POSITIVE(height), - - .unk1 = 0x1080, - - .rt_count_1 = MALI_POSITIVE(batch->key.nr_cbufs), - .rt_count_2 = 4, - - .unknown2 = 0x1f, - .tiler = panfrost_emit_midg_tiler(batch, vertex_count), - - .stack_shift = shift, - .unk0 = 0x1e, - .scratchpad = panfrost_batch_get_scratchpad(batch, shift, screen->thread_tls_alloc, screen->core_count)->gpu - }; - - return framebuffer; -} - -void -panfrost_attach_mfbd(struct panfrost_batch *batch, unsigned vertex_count) -{ - struct bifrost_framebuffer mfbd = - panfrost_emit_mfbd(batch, vertex_count); - - memcpy(batch->framebuffer.cpu, &mfbd, sizeof(mfbd)); -} - /* Creates an MFBD for the FRAGMENT section of the bound framebuffer */ mali_ptr -panfrost_mfbd_fragment(struct panfrost_batch *batch, bool has_draws) +panfrost_mfbd_fragment(struct panfrost_context *ctx, bool has_draws) { - struct bifrost_framebuffer fb = panfrost_emit_mfbd(batch, has_draws); - struct bifrost_fb_extra fbx = {0}; - struct bifrost_render_target rts[4] = {0}; + struct panfrost_job *job = panfrost_get_job_for_fbo(ctx); + + struct bifrost_framebuffer fb = panfrost_emit_mfbd(ctx, has_draws); + struct bifrost_fb_extra fbx = {}; + struct bifrost_render_target rts[4] = {}; /* We always upload at least one dummy GL_NONE render target */ - unsigned rt_descriptors = MAX2(batch->key.nr_cbufs, 1); + unsigned rt_descriptors = + MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); fb.rt_count_1 = MALI_POSITIVE(rt_descriptors); fb.rt_count_2 = rt_descriptors; fb.mfbd_flags = 0x100; /* TODO: MRT clear */ - panfrost_mfbd_clear(batch, &fb, &fbx, rts, fb.rt_count_2); + panfrost_mfbd_clear(job, &fb, &fbx, rts, fb.rt_count_2); /* Upload either the render target or a dummy GL_NONE target */ for (int cb = 0; cb < rt_descriptors; ++cb) { - struct pipe_surface *surf = batch->key.cbufs[cb]; + struct pipe_surface *surf = ctx->pipe_framebuffer.cbufs[cb]; if (surf) { panfrost_mfbd_set_cbuf(&rts[cb], surf); @@ -450,8 +441,8 @@ panfrost_mfbd_fragment(struct panfrost_batch *batch, bool has_draws) rts[cb].format.unk1 |= (cb * 0x400); } - if (batch->key.zsbuf) { - panfrost_mfbd_set_zsbuf(&fb, &fbx, batch->key.zsbuf); + if (ctx->pipe_framebuffer.zsbuf) { + panfrost_mfbd_set_zsbuf(&fb, &fbx, ctx->pipe_framebuffer.zsbuf); } /* When scanning out, the depth buffer is immediately invalidated, so @@ -462,12 +453,13 @@ panfrost_mfbd_fragment(struct panfrost_batch *batch, bool has_draws) * The exception is ReadPixels, but this is not supported on GLES so we * can safely ignore it. */ - if (panfrost_batch_is_scanout(batch)) - batch->requirements &= ~PAN_REQ_DEPTH_WRITE; + if (panfrost_is_scanout(ctx)) { + job->requirements &= ~PAN_REQ_DEPTH_WRITE; + } /* Actualize the requirements */ - if (batch->requirements & PAN_REQ_MSAA) { + if (job->requirements & PAN_REQ_MSAA) { rts[0].format.flags |= MALI_MFBD_FORMAT_MSAA; /* XXX */ @@ -475,13 +467,13 @@ panfrost_mfbd_fragment(struct panfrost_batch *batch, bool has_draws) fb.rt_count_2 = 4; } - if (batch->requirements & PAN_REQ_DEPTH_WRITE) + if (job->requirements & PAN_REQ_DEPTH_WRITE) fb.mfbd_flags |= MALI_MFBD_DEPTH_WRITE; /* Checksumming only works with a single render target */ - if (batch->key.nr_cbufs == 1) { - struct pipe_surface *surf = batch->key.cbufs[0]; + if (ctx->pipe_framebuffer.nr_cbufs == 1) { + struct pipe_surface *surf = ctx->pipe_framebuffer.cbufs[0]; struct panfrost_resource *rsrc = pan_resource(surf->texture); struct panfrost_bo *bo = rsrc->bo; @@ -490,11 +482,11 @@ panfrost_mfbd_fragment(struct panfrost_batch *batch, bool has_draws) struct panfrost_slice *slice = &rsrc->slices[level]; fb.mfbd_flags |= MALI_MFBD_EXTRA; - fbx.flags_lo |= MALI_EXTRA_PRESENT; + fbx.flags |= MALI_EXTRA_PRESENT; fbx.checksum_stride = slice->checksum_stride; fbx.checksum = bo->gpu + slice->checksum_offset; } } - return panfrost_mfbd_upload(batch, &fb, &fbx, rts, rt_descriptors); + return panfrost_mfbd_upload(ctx, &fb, &fbx, rts, rt_descriptors); } diff --git a/lib/mesa/src/gallium/drivers/panfrost/pan_scoreboard.c b/lib/mesa/src/gallium/drivers/panfrost/pan_scoreboard.c index 927a6f61f..692f54254 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/pan_scoreboard.c +++ b/lib/mesa/src/gallium/drivers/panfrost/pan_scoreboard.c @@ -30,7 +30,7 @@ /* * Within a batch (panfrost_job), there are various types of Mali jobs: * - * - WRITE_VALUE: generic write primitive, used to zero tiler field + * - SET_VALUE: initializes tiler * - VERTEX: runs a vertex shader * - TILER: runs tiling and sets up a fragment shader * - FRAGMENT: runs fragment shaders and writes out @@ -100,6 +100,17 @@ * */ +/* Accessor to set the next job field */ + +static void +panfrost_set_job_next(struct mali_job_descriptor_header *first, mali_ptr next) +{ + if (first->job_descriptor_size) + first->next_job_64 = (u64) (uintptr_t) next; + else + first->next_job_32 = (u32) (uintptr_t) next; +} + /* Coerce a panfrost_transfer to a header */ static inline struct mali_job_descriptor_header * @@ -110,11 +121,11 @@ job_descriptor_header(struct panfrost_transfer t) static void panfrost_assign_index( - struct panfrost_batch *batch, + struct panfrost_job *job, struct panfrost_transfer transfer) { /* Assign the index */ - unsigned index = ++batch->job_index; + unsigned index = ++job->job_index; job_descriptor_header(transfer)->job_index = index; } @@ -146,7 +157,7 @@ panfrost_add_dependency( static void panfrost_scoreboard_queue_job_internal( - struct panfrost_batch *batch, + struct panfrost_job *batch, struct panfrost_transfer job) { panfrost_assign_index(batch, job); @@ -163,7 +174,7 @@ panfrost_scoreboard_queue_job_internal( void panfrost_scoreboard_queue_compute_job( - struct panfrost_batch *batch, + struct panfrost_job *batch, struct panfrost_transfer job) { panfrost_scoreboard_queue_job_internal(batch, job); @@ -181,7 +192,7 @@ panfrost_scoreboard_queue_compute_job( void panfrost_scoreboard_queue_vertex_job( - struct panfrost_batch *batch, + struct panfrost_job *batch, struct panfrost_transfer vertex, bool requires_tiling) { @@ -196,7 +207,7 @@ panfrost_scoreboard_queue_vertex_job( void panfrost_scoreboard_queue_tiler_job( - struct panfrost_batch *batch, + struct panfrost_job *batch, struct panfrost_transfer tiler) { panfrost_scoreboard_queue_compute_job(batch, tiler); @@ -215,7 +226,7 @@ panfrost_scoreboard_queue_tiler_job( void panfrost_scoreboard_queue_fused_job( - struct panfrost_batch *batch, + struct panfrost_job *batch, struct panfrost_transfer vertex, struct panfrost_transfer tiler) { @@ -229,7 +240,7 @@ panfrost_scoreboard_queue_fused_job( void panfrost_scoreboard_queue_fused_job_prepend( - struct panfrost_batch *batch, + struct panfrost_job *batch, struct panfrost_transfer vertex, struct panfrost_transfer tiler) { @@ -256,34 +267,33 @@ panfrost_scoreboard_queue_fused_job_prepend( batch->first_tiler = tiler; } -/* Generates a write value job, used to initialize the tiler structures. */ +/* Generates a set value job, used below as part of TILER job scheduling. */ static struct panfrost_transfer -panfrost_write_value_job(struct panfrost_batch *batch, mali_ptr polygon_list) +panfrost_set_value_job(struct panfrost_context *ctx, mali_ptr polygon_list) { struct mali_job_descriptor_header job = { - .job_type = JOB_TYPE_WRITE_VALUE, + .job_type = JOB_TYPE_SET_VALUE, .job_descriptor_size = 1, }; - struct mali_payload_write_value payload = { - .address = polygon_list, - .value_descriptor = MALI_WRITE_VALUE_ZERO, + struct mali_payload_set_value payload = { + .out = polygon_list, + .unknown = 0x3, }; - struct panfrost_transfer transfer = panfrost_allocate_transient(batch, sizeof(job) + sizeof(payload)); + struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(job) + sizeof(payload)); memcpy(transfer.cpu, &job, sizeof(job)); memcpy(transfer.cpu + sizeof(job), &payload, sizeof(payload)); return transfer; } -/* If there are any tiler jobs, we need to initialize the tiler by writing - * zeroes to a magic tiler structure. We do so via a WRITE_VALUE job linked to - * the first vertex job feeding into tiling. */ +/* If there are any tiler jobs, there needs to be a corresponding set value job + * linked to the first vertex job feeding into tiling. */ static void -panfrost_scoreboard_initialize_tiler(struct panfrost_batch *batch) +panfrost_scoreboard_set_value(struct panfrost_job *batch) { /* Check if we even need tiling */ if (!batch->last_tiler.gpu) @@ -292,11 +302,11 @@ panfrost_scoreboard_initialize_tiler(struct panfrost_batch *batch) /* Okay, we do. Let's generate it. We'll need the job's polygon list * regardless of size. */ - mali_ptr polygon_list = panfrost_batch_get_polygon_list(batch, - MALI_TILER_MINIMUM_HEADER_SIZE); + struct panfrost_context *ctx = batch->ctx; + mali_ptr polygon_list = panfrost_job_get_polygon_list(batch, 0); struct panfrost_transfer job = - panfrost_write_value_job(batch, polygon_list); + panfrost_set_value_job(ctx, polygon_list); /* Queue it */ panfrost_scoreboard_queue_compute_job(batch, job); @@ -336,10 +346,10 @@ panfrost_scoreboard_initialize_tiler(struct panfrost_batch *batch) mali_ptr, count)) void -panfrost_scoreboard_link_batch(struct panfrost_batch *batch) +panfrost_scoreboard_link_batch(struct panfrost_job *batch) { /* Finalize the batch */ - panfrost_scoreboard_initialize_tiler(batch); + panfrost_scoreboard_set_value(batch); /* Let no_incoming represent the set S described. */ @@ -362,7 +372,7 @@ panfrost_scoreboard_link_batch(struct panfrost_batch *batch) * Proposition: Given a node N of type T, no more than one other node * depends on N. * - * If type is WRITE_VALUE: The only dependency added against us is from + * If type is SET_VALUE: The only dependency added against us is from * the first tiler job, so there is 1 dependent. * * If type is VERTEX: If there is a tiler node, that tiler node depends @@ -404,12 +414,12 @@ panfrost_scoreboard_link_batch(struct panfrost_batch *batch) if (dep_1) { assert(!dependents[dep_1 - 1]); - dependents[dep_1 - 1] = i + 1; + dependents[dep_1 - 1] = i; } if (dep_2) { assert(!dependents[dep_2 - 1]); - dependents[dep_2 - 1] = i + 1; + dependents[dep_2 - 1] = i; } } @@ -441,7 +451,7 @@ panfrost_scoreboard_link_batch(struct panfrost_batch *batch) if (tail) { /* Link us to the last node */ - tail->next_job = addr; + panfrost_set_job_next(tail, addr); } else { /* We are the first/last node */ batch->first_job.cpu = (uint8_t *) n; @@ -451,11 +461,9 @@ panfrost_scoreboard_link_batch(struct panfrost_batch *batch) tail = n; /* Grab the dependent, if there is one */ - unsigned node_m_1 = dependents[node_n]; - - if (node_m_1) { - unsigned node_m = node_m_1 - 1; + unsigned node_m = dependents[node_n]; + if (node_m) { struct mali_job_descriptor_header *m = DESCRIPTOR_FOR_NODE(node_m); diff --git a/lib/mesa/src/gallium/drivers/panfrost/pan_sfbd.c b/lib/mesa/src/gallium/drivers/panfrost/pan_sfbd.c index 97d006510..63dde9303 100644 --- a/lib/mesa/src/gallium/drivers/panfrost/pan_sfbd.c +++ b/lib/mesa/src/gallium/drivers/panfrost/pan_sfbd.c @@ -22,100 +22,54 @@ * */ -#include "pan_bo.h" #include "pan_context.h" #include "pan_util.h" #include "pan_format.h" -#include "util/format/u_format.h" +#include "util/u_format.h" -static struct mali_sfbd_format +static unsigned panfrost_sfbd_format(struct pipe_surface *surf) { - /* Explode details on the format */ - - const struct util_format_description *desc = - util_format_description(surf->format); - - /* The swizzle for rendering is inverted from texturing */ - - unsigned char swizzle[4]; - panfrost_invert_swizzle(desc->swizzle, swizzle); - - struct mali_sfbd_format fmt = { - .unk1 = 0x1, - .swizzle = panfrost_translate_swizzle_4(swizzle), - .nr_channels = MALI_POSITIVE(desc->nr_channels), - .unk2 = 0x4, - .unk3 = 0xb, - }; - - if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) - fmt.unk2 |= MALI_SFBD_FORMAT_SRGB; - - /* sRGB handled as a dedicated flag */ - enum pipe_format linearized = util_format_linear(surf->format); - - /* If RGB, we're good to go */ - if (util_format_is_unorm8(desc)) - return fmt; - - switch (linearized) { - case PIPE_FORMAT_B5G6R5_UNORM: - fmt.unk1 = 0x5; - fmt.nr_channels = MALI_POSITIVE(2); - fmt.unk2 = 0x5; - break; - - case PIPE_FORMAT_A4B4G4R4_UNORM: - case PIPE_FORMAT_B4G4R4A4_UNORM: - fmt.unk1 = 0x4; - fmt.nr_channels = MALI_POSITIVE(1); - fmt.unk2 = 0x5; - break; - - default: - unreachable("Invalid format rendering"); - } - - return fmt; + /* TODO */ + return 0xb84e0281; /* RGB32, no MSAA */ } static void panfrost_sfbd_clear( - struct panfrost_batch *batch, + struct panfrost_job *job, struct mali_single_framebuffer *sfbd) { - if (batch->clear & PIPE_CLEAR_COLOR) { - sfbd->clear_color_1 = batch->clear_color[0][0]; - sfbd->clear_color_2 = batch->clear_color[0][1]; - sfbd->clear_color_3 = batch->clear_color[0][2]; - sfbd->clear_color_4 = batch->clear_color[0][3]; + if (job->clear & PIPE_CLEAR_COLOR) { + sfbd->clear_color_1 = job->clear_color[0][0]; + sfbd->clear_color_2 = job->clear_color[0][1]; + sfbd->clear_color_3 = job->clear_color[0][2]; + sfbd->clear_color_4 = job->clear_color[0][3]; } - if (batch->clear & PIPE_CLEAR_DEPTH) { - sfbd->clear_depth_1 = batch->clear_depth; - sfbd->clear_depth_2 = batch->clear_depth; - sfbd->clear_depth_3 = batch->clear_depth; - sfbd->clear_depth_4 = batch->clear_depth; + if (job->clear & PIPE_CLEAR_DEPTH) { + sfbd->clear_depth_1 = job->clear_depth; + sfbd->clear_depth_2 = job->clear_depth; + sfbd->clear_depth_3 = job->clear_depth; + sfbd->clear_depth_4 = job->clear_depth; } - if (batch->clear & PIPE_CLEAR_STENCIL) { - sfbd->clear_stencil = batch->clear_stencil; + if (job->clear & PIPE_CLEAR_STENCIL) { + sfbd->clear_stencil = job->clear_stencil; } /* Set flags based on what has been cleared, for the SFBD case */ /* XXX: What do these flags mean? */ int clear_flags = 0x101100; - if (!(batch->clear & ~(PIPE_CLEAR_COLOR | PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) { + if (!(job->clear & ~(PIPE_CLEAR_COLOR | PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) { /* On a tiler like this, it's fastest to clear all three buffers at once */ clear_flags |= MALI_CLEAR_FAST; } else { clear_flags |= MALI_CLEAR_SLOW; - if (batch->clear & PIPE_CLEAR_STENCIL) + if (job->clear & PIPE_CLEAR_STENCIL) clear_flags |= MALI_CLEAR_SLOW_STENCIL; } @@ -130,22 +84,16 @@ panfrost_sfbd_set_cbuf( struct panfrost_resource *rsrc = pan_resource(surf->texture); unsigned level = surf->u.tex.level; - unsigned first_layer = surf->u.tex.first_layer; - assert(surf->u.tex.last_layer == first_layer); - signed stride = rsrc->slices[level].stride; - - mali_ptr base = panfrost_get_texture_address(rsrc, level, first_layer); + assert(surf->u.tex.first_layer == 0); fb->format = panfrost_sfbd_format(surf); - fb->framebuffer = base; - fb->stride = stride; + unsigned offset = rsrc->slices[level].offset; + signed stride = rsrc->slices[level].stride; - if (rsrc->layout == PAN_LINEAR) - fb->format.block = MALI_BLOCK_LINEAR; - else if (rsrc->layout == PAN_TILED) { - fb->format.block = MALI_BLOCK_TILED; - fb->stride *= 16; + if (rsrc->layout == PAN_LINEAR) { + fb->framebuffer = rsrc->bo->gpu + offset; + fb->stride = stride; } else { fprintf(stderr, "Invalid render layout\n"); assert(0); @@ -158,116 +106,46 @@ panfrost_sfbd_set_zsbuf( struct pipe_surface *surf) { struct panfrost_resource *rsrc = pan_resource(surf->texture); - struct panfrost_context *ctx = pan_context(surf->context); unsigned level = surf->u.tex.level; assert(surf->u.tex.first_layer == 0); - if (rsrc->layout != PAN_TILED) - unreachable("Invalid render layout."); - - fb->depth_buffer = rsrc->bo->gpu + rsrc->slices[level].offset; - fb->depth_stride = rsrc->slices[level].stride; - - /* No stencil? Job done. */ - if (!ctx->depth_stencil || !ctx->depth_stencil->stencil[0].enabled) - return; - - if (panfrost_is_z24s8_variant(surf->format)) { - - /* Stencil data is interleaved with depth */ - fb->stencil_buffer = fb->depth_buffer; - fb->stencil_stride = fb->depth_stride; - } else if (surf->format == PIPE_FORMAT_Z32_UNORM || - surf->format == PIPE_FORMAT_Z32_FLOAT) { - - /* No stencil, nothing to do */ - } else if (surf->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { + unsigned offset = rsrc->slices[level].offset; - /* Stencil data in separate buffer */ - struct panfrost_resource *stencil = rsrc->separate_stencil; - struct panfrost_slice stencil_slice = stencil->slices[level]; + if (rsrc->layout == PAN_LINEAR) { + /* TODO: What about format selection? */ + /* TODO: Z/S stride selection? */ - fb->stencil_buffer = stencil->bo->gpu + stencil_slice.offset; - fb->stencil_stride = stencil_slice.stride; - } else - unreachable("Unsupported depth/stencil format."); -} - - -static struct mali_single_framebuffer -panfrost_emit_sfbd(struct panfrost_batch *batch, unsigned vertex_count) -{ - struct panfrost_context *ctx = batch->ctx; - struct pipe_context *gallium = (struct pipe_context *) ctx; - struct panfrost_screen *screen = pan_screen(gallium->screen); - - unsigned width = batch->key.width; - unsigned height = batch->key.height; - - /* TODO: Why do we need to make the stack bigger than other platforms? */ - unsigned shift = panfrost_get_stack_shift(MAX2(batch->stack_size, 512)); + fb->depth_buffer = rsrc->bo->gpu + offset; + fb->depth_buffer_enable = MALI_DEPTH_STENCIL_ENABLE; - /* TODO: where do we specify the shift? */ - - struct mali_single_framebuffer framebuffer = { - .width = MALI_POSITIVE(width), - .height = MALI_POSITIVE(height), - .unknown2 = 0x1f, - .format = { - .unk3 = 0x3, - }, - .clear_flags = 0x1000, - .scratchpad = panfrost_batch_get_scratchpad(batch, shift, screen->thread_tls_alloc, screen->core_count)->gpu, - .tiler = panfrost_emit_midg_tiler(batch, vertex_count), - }; - - return framebuffer; -} - -void -panfrost_attach_sfbd(struct panfrost_batch *batch, unsigned vertex_count) -{ - struct mali_single_framebuffer sfbd = - panfrost_emit_sfbd(batch, vertex_count); - - memcpy(batch->framebuffer.cpu, &sfbd, sizeof(sfbd)); + fb->stencil_buffer = rsrc->bo->gpu + offset; + fb->stencil_buffer_enable = MALI_DEPTH_STENCIL_ENABLE; + } else { + fprintf(stderr, "Invalid render layout\n"); + assert(0); + } } /* Creates an SFBD for the FRAGMENT section of the bound framebuffer */ mali_ptr -panfrost_sfbd_fragment(struct panfrost_batch *batch, bool has_draws) +panfrost_sfbd_fragment(struct panfrost_context *ctx, bool has_draws) { - struct mali_single_framebuffer fb = panfrost_emit_sfbd(batch, has_draws); + struct panfrost_job *job = panfrost_get_job_for_fbo(ctx); + struct mali_single_framebuffer fb = panfrost_emit_sfbd(ctx, has_draws); - panfrost_sfbd_clear(batch, &fb); + panfrost_sfbd_clear(job, &fb); /* SFBD does not support MRT natively; sanity check */ - assert(batch->key.nr_cbufs <= 1); - if (batch->key.nr_cbufs) { - struct pipe_surface *surf = batch->key.cbufs[0]; - struct panfrost_resource *rsrc = pan_resource(surf->texture); - struct panfrost_bo *bo = rsrc->bo; + assert(ctx->pipe_framebuffer.nr_cbufs == 1); + panfrost_sfbd_set_cbuf(&fb, ctx->pipe_framebuffer.cbufs[0]); - panfrost_sfbd_set_cbuf(&fb, surf); + if (ctx->pipe_framebuffer.zsbuf) + panfrost_sfbd_set_zsbuf(&fb, ctx->pipe_framebuffer.zsbuf); - if (rsrc->checksummed) { - unsigned level = surf->u.tex.level; - struct panfrost_slice *slice = &rsrc->slices[level]; - - fb.checksum_stride = slice->checksum_stride; - fb.checksum = bo->gpu + slice->checksum_offset; - } - } - - if (batch->key.zsbuf) - panfrost_sfbd_set_zsbuf(&fb, batch->key.zsbuf); - - if (batch->requirements & PAN_REQ_MSAA) { - fb.format.unk1 |= MALI_SFBD_FORMAT_MSAA_A; - fb.format.unk2 |= MALI_SFBD_FORMAT_MSAA_B; - } + if (job->requirements & PAN_REQ_MSAA) + fb.format |= MALI_FRAMEBUFFER_MSAA_A | MALI_FRAMEBUFFER_MSAA_B; - return panfrost_upload_transient(batch, &fb, sizeof(fb)); + return panfrost_upload_transient(ctx, &fb, sizeof(fb)) | MALI_SFBD; } diff --git a/lib/mesa/src/gallium/drivers/radeonsi/gfx10_format_table.py b/lib/mesa/src/gallium/drivers/radeonsi/gfx10_format_table.py index dd091e7d3..48a2f8870 100644 --- a/lib/mesa/src/gallium/drivers/radeonsi/gfx10_format_table.py +++ b/lib/mesa/src/gallium/drivers/radeonsi/gfx10_format_table.py @@ -34,8 +34,8 @@ import re import sys AMD_REGISTERS = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), "../../../amd/registers")) -UTIL_FORMAT = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), "../../../util/format")) -sys.path.extend([AMD_REGISTERS, UTIL_FORMAT]) +GALLIUM_UTIL = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), "../../auxiliary/util")) +sys.path.extend([AMD_REGISTERS, GALLIUM_UTIL]) from regdb import Object, RegisterDatabase from u_format_parse import * diff --git a/lib/mesa/src/intel/common/gen_mi_builder.h b/lib/mesa/src/intel/common/gen_mi_builder.h index bcd685754..dd7d87fc6 100644 --- a/lib/mesa/src/intel/common/gen_mi_builder.h +++ b/lib/mesa/src/intel/common/gen_mi_builder.h @@ -358,9 +358,6 @@ _gen_mi_copy_no_unref(struct gen_mi_builder *b, case GEN_MI_VALUE_TYPE_IMM: gen_mi_builder_emit(b, GENX(MI_STORE_DATA_IMM), sdi) { sdi.Address = dst.addr; -#if GEN_GEN >= 12 - sdi.ForceWriteCompletionCheck = true; -#endif sdi.ImmediateData = src.imm; } break; |