Import Mesa 10.2.7

50 files changed, 434 insertions, 133 deletions

diff --git a/dist/Mesa/src/egl/drivers/dri2/platform_android.c b/dist/Mesa/src/egl/drivers/dri2/platform_android.c
index 61beaab01..bb4bdc84f 100644
--- a/dist/Mesa/src/egl/drivers/dri2/platform_android.c
+++ b/dist/Mesa/src/egl/drivers/dri2/platform_android.c
@@ -54,8 +54,6 @@ get_format_bpp(int native)
       bpp = 3;
       break;
    case HAL_PIXEL_FORMAT_RGB_565:
-   case HAL_PIXEL_FORMAT_RGBA_5551:
-   case HAL_PIXEL_FORMAT_RGBA_4444:
       bpp = 2;
       break;
    default:
@@ -371,8 +369,6 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp, _EGLContext *ctx,
       format = __DRI_IMAGE_FORMAT_XBGR8888;
       break;
    case HAL_PIXEL_FORMAT_RGB_888:
-   case HAL_PIXEL_FORMAT_RGBA_5551:
-   case HAL_PIXEL_FORMAT_RGBA_4444:
       /* unsupported */
    default:
       _eglLog(_EGL_WARNING, "unsupported native buffer format 0x%x", buf->format);
diff --git a/dist/Mesa/src/egl/main/Android.mk b/dist/Mesa/src/egl/main/Android.mk
index 580289f8a..4cab2f1f4 100644
--- a/dist/Mesa/src/egl/main/Android.mk
+++ b/dist/Mesa/src/egl/main/Android.mk
@@ -95,6 +95,12 @@ gallium_DRIVERS :=
 # swrast
 gallium_DRIVERS += libmesa_pipe_softpipe libmesa_winsys_sw_android
 
+# freedreno
+ifneq ($(filter freedreno, $(MESA_GPU_DRIVERS)),)
+gallium_DRIVERS += libmesa_winsys_freedreno libmesa_pipe_freedreno
+LOCAL_SHARED_LIBRARIES += libdrm_freedreno
+endif
+
 # i915g
 ifneq ($(filter i915g, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_winsys_i915 libmesa_pipe_i915
@@ -109,28 +115,29 @@ endif
 
 # nouveau
 ifneq ($(filter nouveau, $(MESA_GPU_DRIVERS)),)
-gallium_DRIVERS += \
-	libmesa_winsys_nouveau \
-	libmesa_pipe_nvfx \
-	libmesa_pipe_nv50 \
-	libmesa_pipe_nvc0 \
-	libmesa_pipe_nouveau
+gallium_DRIVERS +=  libmesa_winsys_nouveau libmesa_pipe_nouveau
 LOCAL_SHARED_LIBRARIES += libdrm_nouveau
+LOCAL_SHARED_LIBRARIES += libstlport
 endif
 
 # r300g/r600g/radeonsi
 ifneq ($(filter r300g r600g radeonsi, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_winsys_radeon
+LOCAL_SHARED_LIBRARIES += libdrm_radeon
 ifneq ($(filter r300g, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_pipe_r300
-endif
+endif # r300g
+ifneq ($(filter r600g radeonsi, $(MESA_GPU_DRIVERS)),)
 ifneq ($(filter r600g, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_pipe_r600
-endif
+LOCAL_SHARED_LIBRARIES += libstlport
+endif # r600g
 ifneq ($(filter radeonsi, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_pipe_radeonsi
-endif
-endif
+endif # radeonsi
+gallium_DRIVERS += libmesa_pipe_radeon
+endif # r600g || radeonsi
+endif # r300g || r600g || radeonsi
 
 # vmwgfx
 ifneq ($(filter vmwgfx, $(MESA_GPU_DRIVERS)),)
diff --git a/dist/Mesa/src/gallium/Android.mk b/dist/Mesa/src/gallium/Android.mk
index 85334cf69..767361a8a 100644
--- a/dist/Mesa/src/gallium/Android.mk
+++ b/dist/Mesa/src/gallium/Android.mk
@@ -34,6 +34,11 @@ SUBDIRS := \
 # swrast
 SUBDIRS += winsys/sw/android drivers/softpipe
 
+# freedreno
+ifneq ($(filter freedreno, $(MESA_GPU_DRIVERS)),)
+SUBDIRS += winsys/freedreno/drm drivers/freedreno
+endif
+
 # i915g
 ifneq ($(filter i915g, $(MESA_GPU_DRIVERS)),)
 SUBDIRS += winsys/i915/drm drivers/i915
@@ -57,6 +62,8 @@ SUBDIRS += winsys/radeon/drm
 ifneq ($(filter r300g, $(MESA_GPU_DRIVERS)),)
 SUBDIRS += drivers/r300
 endif
+ifneq ($(filter r600g radeonsi, $(MESA_GPU_DRIVERS)),)
+SUBDIRS += drivers/radeon
 ifneq ($(filter r600g, $(MESA_GPU_DRIVERS)),)
 SUBDIRS += drivers/r600
 endif
@@ -64,6 +71,7 @@ ifneq ($(filter radeonsi, $(MESA_GPU_DRIVERS)),)
 SUBDIRS += drivers/radeonsi
 endif
 endif
+endif
 
 # vmwgfx
 ifneq ($(filter vmwgfx, $(MESA_GPU_DRIVERS)),)
diff --git a/dist/Mesa/src/gallium/auxiliary/pipe-loader/pipe_loader.h b/dist/Mesa/src/gallium/auxiliary/pipe-loader/pipe_loader.h
index caef6c16b..cfe2c2040 100644
--- a/dist/Mesa/src/gallium/auxiliary/pipe-loader/pipe_loader.h
+++ b/dist/Mesa/src/gallium/auxiliary/pipe-loader/pipe_loader.h
@@ -66,7 +66,7 @@ struct pipe_loader_device {
       } pci;
    } u; /**< Discriminated by \a type */
 
-   const char *driver_name;
+   char *driver_name;
    const struct pipe_loader_ops *ops;
 };
 
diff --git a/dist/Mesa/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c b/dist/Mesa/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
index a3fc186aa..228168fe1 100644
--- a/dist/Mesa/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
+++ b/dist/Mesa/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
@@ -256,6 +256,7 @@ pipe_loader_drm_release(struct pipe_loader_device **dev)
       util_dl_close(ddev->lib);
 
    close(ddev->fd);
+   FREE(ddev->base.driver_name);
    FREE(ddev);
    *dev = NULL;
 }
diff --git a/dist/Mesa/src/gallium/drivers/freedreno/Android.mk b/dist/Mesa/src/gallium/drivers/freedreno/Android.mk
new file mode 100644
index 000000000..6cab31fd7
--- /dev/null
+++ b/dist/Mesa/src/gallium/drivers/freedreno/Android.mk
@@ -0,0 +1,44 @@
+# Copyright (C) 2014 Emil Velikov <emil.l.velikov@gmail.com>
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+LOCAL_PATH := $(call my-dir)
+
+# get C_SOURCES
+include $(LOCAL_PATH)/Makefile.sources
+
+include $(CLEAR_VARS)
+
+LOCAL_SRC_FILES := \
+	$(C_SOURCES) \
+	$(a2xx_SOURCES) \
+	$(a3xx_SOURCES)
+
+LOCAL_CFLAGS := \
+	-Wno-packed-bitfield-compat
+
+LOCAL_C_INCLUDES := \
+	$(LOCAL_PATH)/ir3 \
+	$(TARGET_OUT_HEADERS)/libdrm \
+	$(TARGET_OUT_HEADERS)/freedreno
+
+LOCAL_MODULE := libmesa_pipe_freedreno
+
+include $(GALLIUM_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
diff --git a/dist/Mesa/src/gallium/drivers/freedreno/Makefile.am b/dist/Mesa/src/gallium/drivers/freedreno/Makefile.am
index 7947dd1a5..f110bad0c 100644
--- a/dist/Mesa/src/gallium/drivers/freedreno/Makefile.am
+++ b/dist/Mesa/src/gallium/drivers/freedreno/Makefile.am
@@ -5,8 +5,6 @@ include $(top_srcdir)/src/gallium/Automake.inc
 
 AM_CFLAGS = \
 	-Wno-packed-bitfield-compat \
-	-I$(top_srcdir)/src/gallium/drivers/freedreno/a3xx \
-	-I$(top_srcdir)/src/gallium/drivers/freedreno/a2xx \
 	$(GALLIUM_DRIVER_CFLAGS) \
 	$(FREEDRENO_CFLAGS)
 
diff --git a/dist/Mesa/src/gallium/drivers/freedreno/Makefile.in b/dist/Mesa/src/gallium/drivers/freedreno/Makefile.in
index 132dcdd18..4597691e7 100644
--- a/dist/Mesa/src/gallium/drivers/freedreno/Makefile.in
+++ b/dist/Mesa/src/gallium/drivers/freedreno/Makefile.in
@@ -613,8 +613,6 @@ GALLIUM_WINSYS_CFLAGS = \
 
 AM_CFLAGS = \
 	-Wno-packed-bitfield-compat \
-	-I$(top_srcdir)/src/gallium/drivers/freedreno/a3xx \
-	-I$(top_srcdir)/src/gallium/drivers/freedreno/a2xx \
 	$(GALLIUM_DRIVER_CFLAGS) \
 	$(FREEDRENO_CFLAGS)
 
diff --git a/dist/Mesa/src/gallium/drivers/freedreno/freedreno_screen.c b/dist/Mesa/src/gallium/drivers/freedreno/freedreno_screen.c
index 332501ecd..936b381a1 100644
--- a/dist/Mesa/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/dist/Mesa/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -50,8 +50,8 @@
 #include "freedreno_query.h"
 #include "freedreno_util.h"
 
-#include "fd2_screen.h"
-#include "fd3_screen.h"
+#include "a2xx/fd2_screen.h"
+#include "a3xx/fd3_screen.h"
 
 /* XXX this should go away */
 #include "state_tracker/drm_driver.h"
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/Android.mk b/dist/Mesa/src/gallium/drivers/nouveau/Android.mk
index 5275aa601..5870aa04b 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/Android.mk
+++ b/dist/Mesa/src/gallium/drivers/nouveau/Android.mk
@@ -28,18 +28,19 @@ include $(LOCAL_PATH)/Makefile.sources
 
 include $(CLEAR_VARS)
 
-LOCAL_SRC_FILES := $(C_SOURCES) \
+LOCAL_SRC_FILES := \
+	$(C_SOURCES) \
 	$(NV30_C_SOURCES) \
 	$(NV50_CODEGEN_SOURCES) \
 	$(NV50_C_SOURES) \
 	$(NVC0_CODEGEN_SOURCES) \
 	$(NVC0_C_SOURCES)
 
-LOCAL_C_INCLUDES := $(DRM_TOP) \
-	$(DRM_TOP)/include/drm \
-	$(DRM_TOP)/nouveau
+LOCAL_C_INCLUDES := \
+	$(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_pipe_nouveau
 
+include external/stlport/libstlport.mk
 include $(GALLIUM_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 2ba3c1c8e..200fe1ff0 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2504,7 +2504,7 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
       break;
    case TGSI_OPCODE_TXB2:
    case TGSI_OPCODE_TXL2:
-      handleTEX(dst0, 2, 2, 0x10, 0x11, 0x00, 0x00);
+      handleTEX(dst0, 2, 2, 0x10, 0x0f, 0x00, 0x00);
       break;
    case TGSI_OPCODE_SAMPLE:
    case TGSI_OPCODE_SAMPLE_B:
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
index ed06def24..e28342484 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -797,6 +797,16 @@ NV50LoweringPreSSA::handleTXB(TexInstruction *i)
    const CondCode cc[4] = { CC_EQU, CC_S, CC_C, CC_O };
    int l, d;
 
+   // We can't actually apply bias *and* do a compare for a cube
+   // texture. Since the compare has to be done before the filtering, just
+   // drop the bias on the floor.
+   if (i->tex.target == TEX_TARGET_CUBE_SHADOW) {
+      i->op = OP_TEX;
+      i->setSrc(3, i->getSrc(4));
+      i->setSrc(4, NULL);
+      return handleTEX(i);
+   }
+
    handleTEX(i);
    Value *bias = i->getSrc(i->tex.target.getArgCount());
    if (bias->isUniform())
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 0b439ddf3..ea1a17a44 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -26,6 +26,7 @@
 #include "codegen/nv50_ir_target_nvc0.h"
 
 #include <limits>
+#include <tr1/unordered_set>
 
 namespace nv50_ir {
 
@@ -148,7 +149,8 @@ private:
    bool insertTextureBarriers(Function *);
    inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
    void findFirstUses(const Instruction *tex, const Instruction *def,
-                      std::list<TexUse>&);
+                      std::list<TexUse>&,
+                      std::tr1::unordered_set<const Instruction *>&);
    void findOverwritingDefs(const Instruction *tex, Instruction *insn,
                             const BasicBlock *term,
                             std::list<TexUse>&);
@@ -230,15 +232,31 @@ NVC0LegalizePostRA::findOverwritingDefs(const Instruction *texi,
 }
 
 void
-NVC0LegalizePostRA::findFirstUses(const Instruction *texi,
-                                  const Instruction *insn,
-                                  std::list<TexUse> &uses)
+NVC0LegalizePostRA::findFirstUses(
+      const Instruction *texi,
+      const Instruction *insn,
+      std::list<TexUse> &uses,
+      std::tr1::unordered_set<const Instruction *>& visited)
 {
    for (int d = 0; insn->defExists(d); ++d) {
       Value *v = insn->getDef(d);
       for (Value::UseIterator u = v->uses.begin(); u != v->uses.end(); ++u) {
          Instruction *usei = (*u)->getInsn();
 
+         /* XXX HACK ALERT XXX
+          *
+          * This shouldn't have to be here, we should always be making forward
+          * progress by looking at the uses. However this somehow does not
+          * appear to be the case. Probably because this is being done right
+          * after RA, when the defs/uses lists have been messed with by node
+          * merging. This should probably be moved to being done right before
+          * RA. But this will do for now.
+          */
+         if (visited.find(usei) != visited.end())
+            continue;
+
+         visited.insert(usei);
+
          if (usei->op == OP_PHI || usei->op == OP_UNION) {
             // need a barrier before WAW cases
             for (int s = 0; usei->srcExists(s); ++s) {
@@ -253,11 +271,11 @@ NVC0LegalizePostRA::findFirstUses(const Instruction *texi,
              usei->op == OP_PHI ||
              usei->op == OP_UNION) {
             // these uses don't manifest in the machine code
-            findFirstUses(texi, usei, uses);
+            findFirstUses(texi, usei, uses, visited);
          } else
          if (usei->op == OP_MOV && usei->getDef(0)->equals(usei->getSrc(0)) &&
              usei->subOp != NV50_IR_SUBOP_MOV_FINAL) {
-            findFirstUses(texi, usei, uses);
+            findFirstUses(texi, usei, uses, visited);
          } else {
             addTexUse(uses, usei, insn);
          }
@@ -313,8 +331,10 @@ NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
    uses = new std::list<TexUse>[texes.size()];
    if (!uses)
       return false;
-   for (size_t i = 0; i < texes.size(); ++i)
-      findFirstUses(texes[i], texes[i], uses[i]);
+   for (size_t i = 0; i < texes.size(); ++i) {
+      std::tr1::unordered_set<const Instruction *> visited;
+      findFirstUses(texes[i], texes[i], uses[i], visited);
+   }
 
    // determine the barrier level at each use
    for (size_t i = 0; i < texes.size(); ++i) {
@@ -814,6 +834,7 @@ NVC0LoweringPass::handleManualTXD(TexInstruction *i)
    Value *zero = bld.loadImm(bld.getSSA(), 0);
    int l, c;
    const int dim = i->tex.target.getDim();
+   const int array = i->tex.target.isArray();
 
    i->op = OP_TEX; // no need to clone dPdx/dPdy later
 
@@ -824,7 +845,7 @@ NVC0LoweringPass::handleManualTXD(TexInstruction *i)
    for (l = 0; l < 4; ++l) {
       // mov coordinates from lane l to all lanes
       for (c = 0; c < dim; ++c)
-         bld.mkQuadop(0x00, crd[c], l, i->getSrc(c), zero);
+         bld.mkQuadop(0x00, crd[c], l, i->getSrc(c + array), zero);
       // add dPdx from lane l to lanes dx
       for (c = 0; c < dim; ++c)
          bld.mkQuadop(qOps[l][0], crd[c], l, i->dPdx[c].get(), crd[c]);
@@ -834,7 +855,7 @@ NVC0LoweringPass::handleManualTXD(TexInstruction *i)
       // texture
       bld.insert(tex = cloneForward(func, i));
       for (c = 0; c < dim; ++c)
-         tex->setSrc(c, crd[c]);
+         tex->setSrc(c + array, crd[c]);
       // save results
       for (c = 0; i->defExists(c); ++c) {
          Instruction *mov;
@@ -870,7 +891,8 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd)
    if (dim > 2 ||
        txd->tex.target.isCube() ||
        arg > 4 ||
-       txd->tex.target.isShadow())
+       txd->tex.target.isShadow() ||
+       txd->tex.useOffsets)
       return handleManualTXD(txd);
 
    for (int c = 0; c < dim; ++c) {
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 6e5b66c3b..d51306e08 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -560,6 +560,10 @@ ConstantFolding::expr(Instruction *i,
       ImmediateValue src0;
       if (i->src(0).getImmediate(src0))
          expr(i, src0, *i->getSrc(1)->asImm());
+      if (i->saturate && !prog->getTarget()->isSatSupported(i)) {
+         bld.setPosition(i, false);
+         i->setSrc(1, bld.loadImm(NULL, res.data.u32));
+      }
    } else {
       i->op = i->saturate ? OP_SAT : OP_MOV; /* SAT handled by unary() */
    }
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state.c
index d0bc7ff1a..c140d6e73 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state.c
@@ -585,9 +585,12 @@ nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s,
          nv50_screen_tsc_unlock(nv50->screen, old);
    }
    assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
-   for (; i < nv50->num_samplers[s]; ++i)
-      if (nv50->samplers[s][i])
+   for (; i < nv50->num_samplers[s]; ++i) {
+      if (nv50->samplers[s][i]) {
          nv50_screen_tsc_unlock(nv50->screen, nv50->samplers[s][i]);
+         nv50->samplers[s][i] = NULL;
+      }
+   }
 
    nv50->num_samplers[s] = nr;
 
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
index 1dcb961ce..4f2758af4 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
@@ -54,8 +54,8 @@ nv50_validate_fb(struct nv50_context *nv50)
       assert(mt->layout_3d || !array_mode || array_size == 1);
 
       BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5);
-      PUSH_DATAh(push, bo->offset + sf->offset);
-      PUSH_DATA (push, bo->offset + sf->offset);
+      PUSH_DATAh(push, mt->base.address + sf->offset);
+      PUSH_DATA (push, mt->base.address + sf->offset);
       PUSH_DATA (push, nv50_format_table[sf->base.format].rt);
       if (likely(nouveau_bo_memtype(bo))) {
          PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
@@ -97,8 +97,8 @@ nv50_validate_fb(struct nv50_context *nv50)
       int unk = mt->base.base.target == PIPE_TEXTURE_3D || sf->depth == 1;
 
       BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
-      PUSH_DATAh(push, bo->offset + sf->offset);
-      PUSH_DATA (push, bo->offset + sf->offset);
+      PUSH_DATAh(push, mt->base.address + sf->offset);
+      PUSH_DATA (push, mt->base.address + sf->offset);
       PUSH_DATA (push, nv50_format_table[fb->zsbuf->format].rt);
       PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
       PUSH_DATA (push, mt->layer_stride >> 2);
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_surface.c
index 600f4f93b..8ec4a5fc1 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -114,8 +114,8 @@ nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
       PUSH_DATA (push, mt->level[level].pitch);
       PUSH_DATA (push, width);
       PUSH_DATA (push, height);
-      PUSH_DATAh(push, bo->offset + offset);
-      PUSH_DATA (push, bo->offset + offset);
+      PUSH_DATAh(push, mt->base.address + offset);
+      PUSH_DATA (push, mt->base.address + offset);
    } else {
       BEGIN_NV04(push, SUBC_2D(mthd), 5);
       PUSH_DATA (push, format);
@@ -126,8 +126,8 @@ nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
       BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
       PUSH_DATA (push, width);
       PUSH_DATA (push, height);
-      PUSH_DATAh(push, bo->offset + offset);
-      PUSH_DATA (push, bo->offset + offset);
+      PUSH_DATAh(push, mt->base.address + offset);
+      PUSH_DATA (push, mt->base.address + offset);
    }
 
 #if 0
@@ -299,8 +299,8 @@ nv50_clear_render_target(struct pipe_context *pipe,
    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
    PUSH_DATA (push, 1);
    BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
-   PUSH_DATAh(push, bo->offset + sf->offset);
-   PUSH_DATA (push, bo->offset + sf->offset);
+   PUSH_DATAh(push, mt->base.address + sf->offset);
+   PUSH_DATA (push, mt->base.address + sf->offset);
    PUSH_DATA (push, nv50_format_table[dst->format].rt);
    PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
    PUSH_DATA (push, mt->layer_stride >> 2);
@@ -381,8 +381,8 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
    nv50->scissors_dirty |= 1;
 
    BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
-   PUSH_DATAh(push, bo->offset + sf->offset);
-   PUSH_DATA (push, bo->offset + sf->offset);
+   PUSH_DATAh(push, mt->base.address + sf->offset);
+   PUSH_DATA (push, mt->base.address + sf->offset);
    PUSH_DATA (push, nv50_format_table[dst->format].rt);
    PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
    PUSH_DATA (push, mt->layer_stride >> 2);
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_transfer.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
index f71605281..fc6b24aac 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
@@ -24,6 +24,8 @@ nv50_m2mf_rect_setup(struct nv50_m2mf_rect *rect,
    rect->bo = mt->base.bo;
    rect->domain = mt->base.domain;
    rect->base = mt->level[l].offset;
+   if (mt->base.bo->offset != mt->base.address)
+      rect->base += mt->base.address - mt->base.bo->offset;
    rect->pitch = mt->level[l].pitch;
    if (util_format_is_plain(res->format)) {
       rect->width = w << mt->ms_x;
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video.c
index a39f572f7..b42de20f7 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video.c
@@ -482,12 +482,14 @@ nv84_create_decoder(struct pipe_context *context,
       mip.level[0].pitch = surf.width * 4;
       mip.base.domain = NOUVEAU_BO_VRAM;
       mip.base.bo = dec->mbring;
+      mip.base.address = dec->mbring->offset;
       context->clear_render_target(context, &surf.base, &color, 0, 0, 64, 4760);
       surf.offset = dec->vpring->size / 2 - 0x1000;
       surf.width = 1024;
       surf.height = 1;
       mip.level[0].pitch = surf.width * 4;
       mip.base.bo = dec->vpring;
+      mip.base.address = dec->vpring->offset;
       context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1);
       surf.offset = dec->vpring->size - 0x1000;
       context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1);
@@ -683,17 +685,14 @@ nv84_video_buffer_create(struct pipe_context *pipe,
                       bo_size, &cfg, &buffer->full))
       goto error;
 
-   mt0->base.bo = buffer->interlaced;
+   nouveau_bo_ref(buffer->interlaced, &mt0->base.bo);
    mt0->base.domain = NOUVEAU_BO_VRAM;
-   mt0->base.offset = 0;
-   mt0->base.address = buffer->interlaced->offset + mt0->base.offset;
-   nouveau_bo_ref(buffer->interlaced, &empty);
+   mt0->base.address = buffer->interlaced->offset;
 
-   mt1->base.bo = buffer->interlaced;
+   nouveau_bo_ref(buffer->interlaced, &mt1->base.bo);
    mt1->base.domain = NOUVEAU_BO_VRAM;
-   mt1->base.offset = mt0->layer_stride * 2;
-   mt1->base.address = buffer->interlaced->offset + mt1->base.offset;
-   nouveau_bo_ref(buffer->interlaced, &empty);
+   mt1->base.offset = mt0->total_size;
+   mt1->base.address = buffer->interlaced->offset + mt0->total_size;
 
    memset(&sv_templ, 0, sizeof(sv_templ));
    for (component = 0, i = 0; i < 2; ++i ) {
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c
index de923e486..1a520d2df 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c
@@ -67,10 +67,15 @@ struct iparm {
          uint32_t field_is_ref; // 04 // bit0: top, bit1: bottom
          uint8_t is_long_term; // 08
          uint8_t non_existing; // 09
+         uint8_t u0a; // 0a
+         uint8_t u0b; // 0b
          uint32_t frame_idx; // 0c
          uint32_t field_order_cnt[2]; // 10
          uint32_t mvidx; // 18
          uint8_t field_pic_flag; // 1c
+         uint8_t u1d; // 1d
+         uint8_t u1e; // 1e
+         uint8_t u1f; // 1f
          // 20
       } refs[0x10]; // 1e0
    } ipicparm; // 150
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
index 79c9390b7..d602aedcb 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
@@ -261,7 +261,6 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
 
    if (pt->usage == PIPE_USAGE_STAGING) {
       switch (pt->target) {
-      case PIPE_TEXTURE_1D:
       case PIPE_TEXTURE_2D:
       case PIPE_TEXTURE_RECT:
          if (pt->last_level == 0 &&
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 394e4a313..92580f76b 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -626,7 +626,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
    if (info->bin.tlsSpace) {
       assert(info->bin.tlsSpace < (1 << 24));
       prog->hdr[0] |= 1 << 26;
-      prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
+      prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
       prog->need_tls = TRUE;
    }
    /* TODO: factor 2 only needed where joinat/precont is used,
diff --git a/dist/Mesa/src/gallium/drivers/r300/Android.mk b/dist/Mesa/src/gallium/drivers/r300/Android.mk
index ff27ef6b2..d3ef76d67 100644
--- a/dist/Mesa/src/gallium/drivers/r300/Android.mk
+++ b/dist/Mesa/src/gallium/drivers/r300/Android.mk
@@ -34,8 +34,7 @@ LOCAL_C_INCLUDES := \
 	$(MESA_TOP)/src/mapi \
 	$(MESA_TOP)/src/glsl \
 	$(MESA_TOP)/src/mesa \
-	$(DRM_TOP) \
-	$(DRM_TOP)/include/drm
+	$(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_pipe_r300
 
diff --git a/dist/Mesa/src/gallium/drivers/r600/Android.mk b/dist/Mesa/src/gallium/drivers/r600/Android.mk
index 4d2f69f33..3b12dd66d 100644
--- a/dist/Mesa/src/gallium/drivers/r600/Android.mk
+++ b/dist/Mesa/src/gallium/drivers/r600/Android.mk
@@ -30,7 +30,7 @@ include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := $(C_SOURCES) $(CXX_SOURCES)
 
-LOCAL_C_INCLUDES := $(DRM_TOP)
+LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_pipe_r600
 
diff --git a/dist/Mesa/src/gallium/drivers/r600/evergreen_compute.c b/dist/Mesa/src/gallium/drivers/r600/evergreen_compute.c
index 701bb5cfa..f9b6f8246 100644
--- a/dist/Mesa/src/gallium/drivers/r600/evergreen_compute.c
+++ b/dist/Mesa/src/gallium/drivers/r600/evergreen_compute.c
@@ -881,9 +881,6 @@ void evergreen_init_compute_state_functions(struct r600_context *ctx)
 	ctx->b.b.set_global_binding = evergreen_set_global_binding;
 	ctx->b.b.launch_grid = evergreen_launch_grid;
 
-	/* We always use at least one vertex buffer for parameters (id = 1)*/
-	ctx->cs_vertex_buffer_state.enabled_mask =
-	ctx->cs_vertex_buffer_state.dirty_mask = 0x2;
 }
 
 struct pipe_resource *r600_compute_global_buffer_create(
diff --git a/dist/Mesa/src/gallium/drivers/radeon/Android.mk b/dist/Mesa/src/gallium/drivers/radeon/Android.mk
new file mode 100644
index 000000000..d562f4c38
--- /dev/null
+++ b/dist/Mesa/src/gallium/drivers/radeon/Android.mk
@@ -0,0 +1,38 @@
+# Mesa 3-D graphics library
+#
+# Copyright (C) 2011 Chia-I Wu <olvaffe@gmail.com>
+# Copyright (C) 2011 LunarG Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+LOCAL_PATH := $(call my-dir)
+
+# get C_SOURCES
+include $(LOCAL_PATH)/Makefile.sources
+
+include $(CLEAR_VARS)
+
+LOCAL_SRC_FILES := $(C_SOURCES)
+
+LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/libdrm
+
+LOCAL_MODULE := libmesa_pipe_radeon
+
+include $(GALLIUM_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
diff --git a/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.c b/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.c
index 70c4d1ade..4c9d2961f 100644
--- a/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -142,7 +142,13 @@ bool r600_common_context_init(struct r600_common_context *rctx,
 	rctx->ws = rscreen->ws;
 	rctx->family = rscreen->family;
 	rctx->chip_class = rscreen->chip_class;
-	rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
+
+	if (rscreen->family == CHIP_HAWAII)
+		rctx->max_db = 16;
+	else if (rscreen->chip_class >= EVERGREEN)
+		rctx->max_db = 8;
+	else
+		rctx->max_db = 4;
 
 	rctx->b.transfer_map = u_transfer_map_vtbl;
 	rctx->b.transfer_flush_region = u_default_transfer_flush_region;
@@ -431,7 +437,20 @@ static int r600_get_compute_param(struct pipe_screen *screen,
 	//TODO: select these params by asic
 	switch (param) {
 	case PIPE_COMPUTE_CAP_IR_TARGET: {
-		const char *gpu = r600_get_llvm_processor_name(rscreen->family);
+		const char *gpu;
+		switch(rscreen->family) {
+		/* Clang < 3.6 is missing Hainan in its list of
+		 * GPUs, so we need to use the name of a similar GPU.
+		 */
+#if HAVE_LLVM < 0x0306
+		case CHIP_HAINAN:
+			gpu = "oland";
+			break;
+#endif
+		default:
+			gpu = r600_get_llvm_processor_name(rscreen->family);
+			break;
+		}
 		if (ret) {
 			sprintf(ret, "%s-r600--", gpu);
 		}
@@ -472,13 +491,21 @@ static int r600_get_compute_param(struct pipe_screen *screen,
 	case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 		if (ret) {
 			uint64_t *max_global_size = ret;
-			/* XXX: This is what the proprietary driver reports, we
-			 * may want to use a different value. */
-			/* XXX: Not sure what to put here for SI. */
-			if (rscreen->chip_class >= SI)
-				*max_global_size = 2000000000;
-			else
-				*max_global_size = 201326592;
+			uint64_t max_mem_alloc_size;
+
+			r600_get_compute_param(screen,
+				PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
+				&max_mem_alloc_size);
+
+			/* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
+			 * 1/4 of the MAX_GLOBAL_SIZE.  Since the
+			 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
+			 * make sure we never report more than
+			 * 4 * MAX_MEM_ALLOC_SIZE.
+			 */
+			*max_global_size = MIN2(4 * max_mem_alloc_size,
+				rscreen->info.gart_size +
+				rscreen->info.vram_size);
 		}
 		return sizeof(uint64_t);
 
@@ -502,13 +529,11 @@ static int r600_get_compute_param(struct pipe_screen *screen,
 		if (ret) {
 			uint64_t max_global_size;
 			uint64_t *max_mem_alloc_size = ret;
-			r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
-			/* OpenCL requres this value be at least
-			 * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
-			 * I'm really not sure what value to report here, but
-			 * MAX_GLOBAL_SIZE / 4 seems resonable.
+
+			/* XXX: The limit in older kernels is 256 MB.  We
+			 * should add a query here for newer kernels.
 			 */
-			*max_mem_alloc_size = max_global_size / 4;
+			*max_mem_alloc_size = 256 * 1024 * 1024;
 		}
 		return sizeof(uint64_t);
 
diff --git a/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.h b/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.h
index bbfcdf957..e7f410dd7 100644
--- a/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -72,6 +72,7 @@
 #define R600_CONTEXT_WAIT_3D_IDLE		(1 << 17)
 #define R600_CONTEXT_WAIT_CP_DMA_IDLE		(1 << 18)
 #define R600_CONTEXT_VGT_FLUSH			(1 << 19)
+#define R600_CONTEXT_VGT_STREAMOUT_SYNC		(1 << 20)
 
 /* Debug flags. */
 /* logging */
diff --git a/dist/Mesa/src/gallium/drivers/radeon/r600_texture.c b/dist/Mesa/src/gallium/drivers/radeon/r600_texture.c
index 3a37465b1..9a46c53f3 100644
--- a/dist/Mesa/src/gallium/drivers/radeon/r600_texture.c
+++ b/dist/Mesa/src/gallium/drivers/radeon/r600_texture.c
@@ -380,7 +380,8 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 
 	out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
 	out->alignment = MAX2(256, base_align);
-	out->size = rtex->surface.array_size * align(slice_bytes, base_align);
+	out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+		    align(slice_bytes, base_align);
 }
 
 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
@@ -427,7 +428,8 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
 		out->slice_tile_max -= 1;
 
 	out->alignment = MAX2(256, base_align);
-	out->size = rtex->surface.array_size * align(slice_bytes, base_align);
+	out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+		    align(slice_bytes, base_align);
 }
 
 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
@@ -523,7 +525,8 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
 	pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
 	base_align = num_pipes * pipe_interleave_bytes;
 
-	return rtex->surface.array_size * align(slice_bytes, base_align);
+	return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+		align(slice_bytes, base_align);
 }
 
 static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen,
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/Android.mk b/dist/Mesa/src/gallium/drivers/radeonsi/Android.mk
index f7e01a3f6..22c0fdcd8 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/Android.mk
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/Android.mk
@@ -30,7 +30,7 @@ include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := $(C_SOURCES)
 
-LOCAL_C_INCLUDES :=
+LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_pipe_radeonsi
 
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_blit.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_blit.c
index 1dfff49d1..dced3d0e7 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_blit.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_blit.c
@@ -60,9 +60,16 @@ static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
 	util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader);
 	util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader);
 	util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
+	if (sctx->queued.named.sample_mask) {
+		util_blitter_save_sample_mask(sctx->blitter,
+					      sctx->queued.named.sample_mask->sample_mask);
+	}
 	if (sctx->queued.named.viewport) {
 		util_blitter_save_viewport(sctx->blitter, &sctx->queued.named.viewport->viewport);
 	}
+	if (sctx->queued.named.scissor) {
+		util_blitter_save_scissor(sctx->blitter, &sctx->queued.named.scissor->scissor);
+	}
 	util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
 	util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
 				     (struct pipe_stream_output_target**)sctx->b.streamout.targets);
@@ -735,7 +742,7 @@ static void si_flush_resource(struct pipe_context *ctx,
 
 	if (!rtex->is_depth && rtex->cmask.size) {
 		si_blit_decompress_color(ctx, rtex, 0, res->last_level,
-					 0, res->array_size - 1);
+					 0, util_max_layer(res, 0));
 	}
 }
 
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_compute.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_compute.c
index c0637f6f7..691e52a45 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_compute.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_compute.c
@@ -100,7 +100,7 @@ static void si_set_global_binding(
 
 	if (!resources) {
 		for (i = first; i < first + n; i++) {
-			program->global_buffers[i] = NULL;
+			pipe_resource_reference(&program->global_buffers[i], NULL);
 		}
 		return;
 	}
@@ -108,7 +108,7 @@ static void si_set_global_binding(
 	for (i = first; i < first + n; i++) {
 		uint64_t va;
 		uint32_t offset;
-		program->global_buffers[i] = resources[i];
+		pipe_resource_reference(&program->global_buffers[i], resources[i]);
 		va = r600_resource_va(ctx->screen, resources[i]);
 		offset = util_le32_to_cpu(*handles[i]);
 		va += offset;
@@ -288,8 +288,8 @@ static void si_launch_grid(
 	}
 #endif
 
-	FREE(pm4);
 	FREE(kernel_args);
+	si_pm4_free_state(sctx, pm4, ~0);
 }
 
 
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_descriptors.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_descriptors.c
index 77bc03432..38ad0778c 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -987,9 +987,9 @@ void si_init_all_descriptors(struct si_context *sctx)
 
 		si_init_sampler_views(sctx, &sctx->samplers[i].views, i);
 
-		sctx->atoms.const_buffers[i] = &sctx->const_buffers[i].desc.atom;
-		sctx->atoms.rw_buffers[i] = &sctx->rw_buffers[i].desc.atom;
-		sctx->atoms.sampler_views[i] = &sctx->samplers[i].views.desc.atom;
+		sctx->atoms.s.const_buffers[i] = &sctx->const_buffers[i].desc.atom;
+		sctx->atoms.s.rw_buffers[i] = &sctx->rw_buffers[i].desc.atom;
+		sctx->atoms.s.sampler_views[i] = &sctx->samplers[i].views.desc.atom;
 	}
 
 
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_dma.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_dma.c
index dc8c609b8..26f1e1b63 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_dma.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_dma.c
@@ -91,12 +91,13 @@ static void si_dma_copy_buffer(struct si_context *ctx,
 	}
 	ncopy = (size / max_csize) + !!(size % max_csize);
 
+	r600_need_dma_space(&ctx->b, ncopy * 5);
+
 	r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
 			      RADEON_PRIO_MIN);
 	r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
 			      RADEON_PRIO_MIN);
 
-	r600_need_dma_space(&ctx->b, ncopy * 5);
 	for (i = 0; i < ncopy; i++) {
 		csize = size < max_csize ? size : max_csize;
 		cs->buf[cs->cdw++] = SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, csize);
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_hw_context.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_hw_context.c
index 383157b7d..d2a1dbe42 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -63,7 +63,7 @@ void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
 	}
 
 	/* Count in framebuffer cache flushes at the end of CS. */
-	num_dw += ctx->atoms.cache_flush->num_dw;
+	num_dw += ctx->atoms.s.cache_flush->num_dw;
 
 #if SI_TRACE_CS
 	if (ctx->screen->b.trace_bo) {
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.c
index 8c12bf7cf..7b905d697 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.c
@@ -23,6 +23,7 @@
 
 #include "si_pipe.h"
 #include "si_public.h"
+#include "sid.h"
 
 #include "radeon/radeon_uvd.h"
 #include "util/u_blitter.h"
@@ -105,10 +106,10 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, void *
 
 	/* Initialize cache_flush. */
 	sctx->cache_flush = si_atom_cache_flush;
-	sctx->atoms.cache_flush = &sctx->cache_flush;
+	sctx->atoms.s.cache_flush = &sctx->cache_flush;
 
-	sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
-	sctx->atoms.streamout_enable = &sctx->b.streamout.enable_atom;
+	sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
+	sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 
 	switch (sctx->b.chip_class) {
 	case SI:
@@ -384,6 +385,57 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
 	r600_destroy_common_screen(&sscreen->b);
 }
 
+#define SI_TILE_MODE_COLOR_2D_8BPP  14
+
+/* Initialize pipe config. This is especially important for GPUs
+ * with 16 pipes and more where it's initialized incorrectly by
+ * the TILING_CONFIG ioctl. */
+static bool si_initialize_pipe_config(struct si_screen *sscreen)
+{
+	unsigned mode2d;
+
+	/* This is okay, because there can be no 2D tiling without
+	 * the tile mode array, so we won't need the pipe config.
+	 * Return "success".
+	 */
+	if (!sscreen->b.info.si_tile_mode_array_valid)
+		return true;
+
+	/* The same index is used for the 2D mode on CIK too. */
+	mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
+
+	switch (G_009910_PIPE_CONFIG(mode2d)) {
+	case V_02803C_ADDR_SURF_P2:
+		sscreen->b.tiling_info.num_channels = 2;
+		break;
+	case V_02803C_X_ADDR_SURF_P4_8X16:
+	case V_02803C_X_ADDR_SURF_P4_16X16:
+	case V_02803C_X_ADDR_SURF_P4_16X32:
+	case V_02803C_X_ADDR_SURF_P4_32X32:
+		sscreen->b.tiling_info.num_channels = 4;
+		break;
+	case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
+	case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
+	case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
+	case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
+	case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
+	case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
+	case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
+		sscreen->b.tiling_info.num_channels = 8;
+		break;
+	case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
+	case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
+		sscreen->b.tiling_info.num_channels = 16;
+		break;
+	default:
+		assert(0);
+		fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
+			G_009910_PIPE_CONFIG(mode2d));
+		return false;
+	}
+	return true;
+}
+
 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 {
 	struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
@@ -399,7 +451,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 	sscreen->b.b.is_format_supported = si_is_format_supported;
 	sscreen->b.b.resource_create = r600_resource_create_common;
 
-	if (!r600_common_screen_init(&sscreen->b, ws)) {
+	if (!r600_common_screen_init(&sscreen->b, ws) ||
+	    !si_initialize_pipe_config(sscreen)) {
 		FREE(sscreen);
 		return NULL;
 	}
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.h b/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.h
index 4a5f29177..de424778a 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.h
@@ -114,7 +114,7 @@ struct si_context {
 			struct r600_atom *streamout_begin;
 			struct r600_atom *streamout_enable; /* must be after streamout_begin */
 			struct r600_atom *framebuffer;
-		};
+		} s;
 		struct r600_atom *array[0];
 	} atoms;
 
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_shader.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_shader.c
index 0d070d3ce..397b6ee38 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_shader.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_shader.c
@@ -1539,9 +1539,8 @@ static void tex_fetch_args(
 	/* Pack LOD bias value */
 	if (opcode == TGSI_OPCODE_TXB)
 		address[count++] = coords[3];
-
-	if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
-		radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
+	if (opcode == TGSI_OPCODE_TXB2)
+		address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
 
 	/* Pack depth comparison value */
 	switch (target) {
@@ -1558,6 +1557,9 @@ static void tex_fetch_args(
 		address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
 	}
 
+	if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
+		radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
+
 	/* Pack user derivatives */
 	if (opcode == TGSI_OPCODE_TXD) {
 		for (chan = 0; chan < 2; chan++) {
@@ -2497,6 +2499,7 @@ int si_pipe_shader_create(
 
 	bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
 	bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
+	bld_base->op_actions[TGSI_OPCODE_TXB2] = txb_action;
 #if HAVE_LLVM >= 0x0304
 	bld_base->op_actions[TGSI_OPCODE_TXD] = txd_action;
 #endif
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_state.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_state.c
index d12bd01ac..7f65c4726 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_state.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_state.c
@@ -458,18 +458,20 @@ static void si_set_scissor_states(struct pipe_context *ctx,
                                   const struct pipe_scissor_state *state)
 {
 	struct si_context *sctx = (struct si_context *)ctx;
-	struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
+	struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor);
+	struct si_pm4_state *pm4 = &scissor->pm4;
 
-	if (pm4 == NULL)
+	if (scissor == NULL)
 		return;
 
+	scissor->scissor = *state;
 	si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
 		       S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
 		       S_028250_WINDOW_OFFSET_DISABLE(1));
 	si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
 		       S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
 
-	si_pm4_set_state(sctx, scissor, pm4);
+	si_pm4_set_state(sctx, scissor, scissor);
 }
 
 static void si_set_viewport_states(struct pipe_context *ctx,
@@ -2823,16 +2825,18 @@ static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
 {
 	struct si_context *sctx = (struct si_context *)ctx;
-	struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
+	struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
+	struct si_pm4_state *pm4 = &state->pm4;
 	uint16_t mask = sample_mask;
 
-        if (pm4 == NULL)
+        if (state == NULL)
                 return;
 
+	state->sample_mask = mask;
 	si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
 	si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
 
-	si_pm4_set_state(sctx, sample_mask, pm4);
+	si_pm4_set_state(sctx, sample_mask, state);
 }
 
 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
@@ -2959,7 +2963,7 @@ void si_init_state_functions(struct si_context *sctx)
 {
 	int i;
 
-	si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.framebuffer, si_emit_framebuffer_state, 0);
+	si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
 
 	sctx->b.b.create_blend_state = si_create_blend_state;
 	sctx->b.b.bind_blend_state = si_bind_blend_state;
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_state.h b/dist/Mesa/src/gallium/drivers/radeonsi/si_state.h
index 4c5b09eb4..752cd11ef 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_state.h
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_state.h
@@ -38,6 +38,16 @@ struct si_state_blend {
 	bool			alpha_to_one;
 };
 
+struct si_state_sample_mask {
+	struct si_pm4_state	pm4;
+	uint16_t		sample_mask;
+};
+
+struct si_state_scissor {
+	struct si_pm4_state		pm4;
+	struct pipe_scissor_state	scissor;
+};
+
 struct si_state_viewport {
 	struct si_pm4_state		pm4;
 	struct pipe_viewport_state	viewport;
@@ -81,8 +91,8 @@ union si_state {
 		struct si_state_blend		*blend;
 		struct si_pm4_state		*blend_color;
 		struct si_pm4_state		*clip;
-		struct si_pm4_state		*sample_mask;
-		struct si_pm4_state		*scissor;
+		struct si_state_sample_mask	*sample_mask;
+		struct si_state_scissor		*scissor;
 		struct si_state_viewport	*viewport;
 		struct si_state_rasterizer	*rasterizer;
 		struct si_state_dsa		*dsa;
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_state_draw.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_state_draw.c
index 0676b154f..5e42356a9 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -33,6 +33,7 @@
 #include "util/u_format.h"
 #include "util/u_index_modify.h"
 #include "util/u_memory.h"
+#include "util/u_prim.h"
 #include "util/u_upload_mgr.h"
 
 /*
@@ -425,16 +426,28 @@ static bool si_update_draw_info_state(struct si_context *sctx,
 					(rs ? rs->line_stipple_enable : false);
 		/* If the WD switch is false, the IA switch must be false too. */
 		bool ia_switch_on_eop = wd_switch_on_eop;
+		unsigned primgroup_size = 64;
+
+		/* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
+		 * We don't know that for indirect drawing, so treat it as
+		 * always problematic. */
+		if (sctx->b.family == CHIP_HAWAII && info->instance_count > 1) {
+			wd_switch_on_eop = true;
+			ia_switch_on_eop = true;
+		}
 
-		si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
-			       S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
-			       S_028AA8_PARTIAL_VS_WAVE_ON(1) |
-			       S_028AA8_PRIMGROUP_SIZE(63) |
-			       S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
 		si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
 			       ib->index_size == 4 ? 0xFC000000 : 0xFC00);
 
-		si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
+		si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
+		si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
+		si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */
+			       S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
+			       S_028AA8_PARTIAL_VS_WAVE_ON(1) |
+			       S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
+			       S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
+		si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
+		si_pm4_cmd_end(pm4, false);
 	} else {
 		si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
 	}
@@ -902,11 +915,15 @@ void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *ato
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 		radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
 	}
+	if (sctx->flags & R600_CONTEXT_VGT_STREAMOUT_SYNC) {
+		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+		radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
+	}
 
 	sctx->flags = 0;
 }
 
-const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */
+const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 17 }; /* number of CS dwords */
 
 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 {
@@ -964,7 +981,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 
 	/* Check flush flags. */
 	if (sctx->b.flags)
-		sctx->atoms.cache_flush->dirty = true;
+		sctx->atoms.s.cache_flush->dirty = true;
 
 	si_need_cs_space(sctx, 0, TRUE);
 
@@ -985,6 +1002,14 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 	}
 #endif
 
+	/* Workaround for a VGT hang when streamout is enabled.
+	 * It must be done after drawing. */
+	if (sctx->b.family == CHIP_HAWAII &&
+	    (sctx->b.streamout.streamout_enabled ||
+	     sctx->b.streamout.prims_gen_query_enabled)) {
+		sctx->b.flags |= R600_CONTEXT_VGT_STREAMOUT_SYNC;
+	}
+
 	/* Set the depth buffer as dirty. */
 	if (sctx->framebuffer.state.zsbuf) {
 		struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/sid.h b/dist/Mesa/src/gallium/drivers/radeonsi/sid.h
index 2bd2cb4b1..558da1048 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/sid.h
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/sid.h
@@ -83,6 +83,8 @@
 #define PKT3_DRAW_INDEX_IMMD                   0x2E /* not on CIK */
 #define PKT3_NUM_INSTANCES                     0x2F
 #define PKT3_STRMOUT_BUFFER_UPDATE             0x34
+#define PKT3_DRAW_INDEX_OFFSET_2               0x35
+#define PKT3_DRAW_PREAMBLE                     0x36 /* new on CIK, required on GFX7.2 and later */
 #define PKT3_WRITE_DATA                        0x37
 #define     PKT3_WRITE_DATA_DST_SEL(x)             ((x) << 8)
 #define     PKT3_WRITE_DATA_DST_SEL_REG            0
diff --git a/dist/Mesa/src/gallium/state_trackers/clover/api/queue.cpp b/dist/Mesa/src/gallium/state_trackers/clover/api/queue.cpp
index a136018fb..06a286380 100644
--- a/dist/Mesa/src/gallium/state_trackers/clover/api/queue.cpp
+++ b/dist/Mesa/src/gallium/state_trackers/clover/api/queue.cpp
@@ -58,7 +58,11 @@ clRetainCommandQueue(cl_command_queue d_q) try {
 
 CLOVER_API cl_int
 clReleaseCommandQueue(cl_command_queue d_q) try {
-   if (obj(d_q).release())
+   auto &q = obj(d_q);
+
+   q.flush();
+
+   if (q.release())
       delete pobj(d_q);
 
    return CL_SUCCESS;
diff --git a/dist/Mesa/src/gallium/state_trackers/clover/core/timestamp.cpp b/dist/Mesa/src/gallium/state_trackers/clover/core/timestamp.cpp
index f168d61b6..18950130e 100644
--- a/dist/Mesa/src/gallium/state_trackers/clover/core/timestamp.cpp
+++ b/dist/Mesa/src/gallium/state_trackers/clover/core/timestamp.cpp
@@ -30,6 +30,7 @@ using namespace clover;
 timestamp::query::query(command_queue &q) :
    q(q),
    _query(q.pipe->create_query(q.pipe, PIPE_QUERY_TIMESTAMP)) {
+   q.pipe->end_query(q.pipe, _query);
 }
 
 timestamp::query::query(query &&other) :
diff --git a/dist/Mesa/src/gallium/state_trackers/egl/android/native_android.cpp b/dist/Mesa/src/gallium/state_trackers/egl/android/native_android.cpp
index e73d031f5..4eb0497a9 100644
--- a/dist/Mesa/src/gallium/state_trackers/egl/android/native_android.cpp
+++ b/dist/Mesa/src/gallium/state_trackers/egl/android/native_android.cpp
@@ -147,10 +147,6 @@ get_pipe_format(int native)
    case HAL_PIXEL_FORMAT_BGRA_8888:
       fmt = PIPE_FORMAT_B8G8R8A8_UNORM;
       break;
-   case HAL_PIXEL_FORMAT_RGBA_5551:
-      /* fmt = PIPE_FORMAT_A1B5G5R5_UNORM; */
-   case HAL_PIXEL_FORMAT_RGBA_4444:
-      /* fmt = PIPE_FORMAT_A4B4G4R4_UNORM; */
    default:
       ALOGE("unsupported native format 0x%x", native);
       fmt = PIPE_FORMAT_NONE;
diff --git a/dist/Mesa/src/gallium/targets/egl-static/Android.mk b/dist/Mesa/src/gallium/targets/egl-static/Android.mk
index 37244b544..0ad6bb896 100644
--- a/dist/Mesa/src/gallium/targets/egl-static/Android.mk
+++ b/dist/Mesa/src/gallium/targets/egl-static/Android.mk
@@ -52,6 +52,9 @@ LOCAL_C_INCLUDES += \
 	$(DRM_TOP)
 endif
 
+ifneq ($(filter freedreno, $(MESA_GPU_DRIVERS)),)
+LOCAL_CFLAGS += -DGALLIUM_FREEDRENO
+endif
 ifneq ($(filter i915g, $(MESA_GPU_DRIVERS)),)
 LOCAL_CFLAGS += -D_EGL_PIPE_I915=1
 endif
diff --git a/dist/Mesa/src/gallium/winsys/freedreno/drm/Android.mk b/dist/Mesa/src/gallium/winsys/freedreno/drm/Android.mk
new file mode 100644
index 000000000..7bd31d924
--- /dev/null
+++ b/dist/Mesa/src/gallium/winsys/freedreno/drm/Android.mk
@@ -0,0 +1,37 @@
+# Copyright (C) 2014 Emil Velikov <emil.l.velikov@gmail.com>
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+LOCAL_PATH := $(call my-dir)
+
+# get C_SOURCES
+include $(LOCAL_PATH)/Makefile.sources
+
+include $(CLEAR_VARS)
+
+LOCAL_SRC_FILES := $(C_SOURCES)
+
+LOCAL_C_INCLUDES := \
+	$(TARGET_OUT_HEADERS)/libdrm \
+	$(TARGET_OUT_HEADERS)/freedreno
+
+LOCAL_MODULE := libmesa_winsys_freedreno
+
+include $(GALLIUM_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
diff --git a/dist/Mesa/src/gallium/winsys/nouveau/drm/Android.mk b/dist/Mesa/src/gallium/winsys/nouveau/drm/Android.mk
index 2e2a9d12d..142cc6bc3 100644
--- a/dist/Mesa/src/gallium/winsys/nouveau/drm/Android.mk
+++ b/dist/Mesa/src/gallium/winsys/nouveau/drm/Android.mk
@@ -30,10 +30,7 @@ include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := $(C_SOURCES)
 
-LOCAL_C_INCLUDES := \
-	$(DRM_TOP) \
-	$(DRM_TOP)/include/drm \
-	$(DRM_TOP)/nouveau
+LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_winsys_nouveau
 
diff --git a/dist/Mesa/src/gallium/winsys/radeon/drm/Android.mk b/dist/Mesa/src/gallium/winsys/radeon/drm/Android.mk
index c19224982..3165ba479 100644
--- a/dist/Mesa/src/gallium/winsys/radeon/drm/Android.mk
+++ b/dist/Mesa/src/gallium/winsys/radeon/drm/Android.mk
@@ -30,9 +30,7 @@ include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := $(C_SOURCES)
 
-LOCAL_C_INCLUDES := \
-	$(DRM_TOP) \
-	$(DRM_TOP)/include/drm
+LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_winsys_radeon
 
diff --git a/dist/Mesa/src/glsl/Android.mk b/dist/Mesa/src/glsl/Android.mk
index 8a3942652..7b1fa7e53 100644
--- a/dist/Mesa/src/glsl/Android.mk
+++ b/dist/Mesa/src/glsl/Android.mk
@@ -39,12 +39,12 @@ LOCAL_SRC_FILES := \
 	$(LIBGLSL_FILES)
 
 LOCAL_C_INCLUDES := \
-	external/astl/include \
 	$(MESA_TOP)/src/mapi \
 	$(MESA_TOP)/src/mesa
 
 LOCAL_MODULE := libmesa_glsl
 
+include external/stlport/libstlport.mk
 include $(LOCAL_PATH)/Android.gen.mk
 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)