Re-update xf86-video-ati to 6.14.3.

Because of ati.c revision 1.5, it will not be selected by
autoconfiguration code, so people who want to run this version of the
driver on their radeon cards need an explicit "Device" section in
xorg.conf.

1 files changed, 134 insertions, 2 deletions

diff --git a/driver/xf86-video-ati/src/ati_pciids_gen.h b/driver/xf86-video-ati/src/ati_pciids_gen.h
index 3304e8430..ff7c91b7b 100644
--- a/driver/xf86-video-ati/src/ati_pciids_gen.h
+++ b/driver/xf86-video-ati/src/ati_pciids_gen.h
@@ -2,6 +2,7 @@
 #define PCI_CHIP_RV380_3151 0x3151
 #define PCI_CHIP_RV380_3152 0x3152
 #define PCI_CHIP_RV380_3154 0x3154
+#define PCI_CHIP_RV380_3155 0x3155
 #define PCI_CHIP_RV380_3E50 0x3E50
 #define PCI_CHIP_RV380_3E54 0x3E54
 #define PCI_CHIP_RS100_4136 0x4136
@@ -24,7 +25,6 @@
 #define PCI_CHIP_MACH32 0x4158
 #define PCI_CHIP_RS250_4237 0x4237
 #define PCI_CHIP_R200_BB 0x4242
-#define PCI_CHIP_R200_BC 0x4243
 #define PCI_CHIP_RS100_4336 0x4336
 #define PCI_CHIP_RS200_4337 0x4337
 #define PCI_CHIP_MACH64CT 0x4354
@@ -60,6 +60,8 @@
 #define PCI_CHIP_R420_JN 0x4A4E
 #define PCI_CHIP_R420_4A4F 0x4A4F
 #define PCI_CHIP_R420_JP 0x4A50
+#define PCI_CHIP_R420_JT 0x4A54
+#define PCI_CHIP_R481_4B48 0x4B48
 #define PCI_CHIP_R481_4B49 0x4B49
 #define PCI_CHIP_R481_4B4A 0x4B4A
 #define PCI_CHIP_R481_4B4B 0x4B4B
@@ -334,6 +336,7 @@
 #define PCI_CHIP_RV770_9440 0x9440
 #define PCI_CHIP_RV770_9441 0x9441
 #define PCI_CHIP_RV770_9442 0x9442
+#define PCI_CHIP_RV770_9443 0x9443
 #define PCI_CHIP_RV770_9444 0x9444
 #define PCI_CHIP_RV770_9446 0x9446
 #define PCI_CHIP_RV770_944A 0x944A
@@ -345,21 +348,34 @@
 #define PCI_CHIP_RV770_9456 0x9456
 #define PCI_CHIP_RV770_945A 0x945A
 #define PCI_CHIP_RV770_945B 0x945B
+#define PCI_CHIP_RV770_945E 0x945E
 #define PCI_CHIP_RV790_9460 0x9460
 #define PCI_CHIP_RV790_9462 0x9462
 #define PCI_CHIP_RV770_946A 0x946A
 #define PCI_CHIP_RV770_946B 0x946B
 #define PCI_CHIP_RV770_947A 0x947A
 #define PCI_CHIP_RV770_947B 0x947B
+#define PCI_CHIP_RV730_9480 0x9480
 #define PCI_CHIP_RV730_9487 0x9487
+#define PCI_CHIP_RV730_9488 0x9488
 #define PCI_CHIP_RV730_9489 0x9489
+#define PCI_CHIP_RV730_948A 0x948A
 #define PCI_CHIP_RV730_948F 0x948F
 #define PCI_CHIP_RV730_9490 0x9490
 #define PCI_CHIP_RV730_9491 0x9491
+#define PCI_CHIP_RV730_9495 0x9495
 #define PCI_CHIP_RV730_9498 0x9498
 #define PCI_CHIP_RV730_949C 0x949C
 #define PCI_CHIP_RV730_949E 0x949E
 #define PCI_CHIP_RV730_949F 0x949F
+#define PCI_CHIP_RV740_94A0 0x94A0
+#define PCI_CHIP_RV740_94A1 0x94A1
+#define PCI_CHIP_RV740_94A3 0x94A3
+#define PCI_CHIP_RV740_94B1 0x94B1
+#define PCI_CHIP_RV740_94B3 0x94B3
+#define PCI_CHIP_RV740_94B4 0x94B4
+#define PCI_CHIP_RV740_94B5 0x94B5
+#define PCI_CHIP_RV740_94B9 0x94B9
 #define PCI_CHIP_RV610_94C0 0x94C0
 #define PCI_CHIP_RV610_94C1 0x94C1
 #define PCI_CHIP_RV610_94C3 0x94C3
@@ -387,11 +403,14 @@
 #define PCI_CHIP_RV670_9519 0x9519
 #define PCI_CHIP_RV710_9540 0x9540
 #define PCI_CHIP_RV710_9541 0x9541
+#define PCI_CHIP_RV710_9542 0x9542
 #define PCI_CHIP_RV710_954E 0x954E
 #define PCI_CHIP_RV710_954F 0x954F
 #define PCI_CHIP_RV710_9552 0x9552
 #define PCI_CHIP_RV710_9553 0x9553
 #define PCI_CHIP_RV710_9555 0x9555
+#define PCI_CHIP_RV710_9557 0x9557
+#define PCI_CHIP_RV710_955F 0x955F
 #define PCI_CHIP_RV630_9580 0x9580
 #define PCI_CHIP_RV630_9581 0x9581
 #define PCI_CHIP_RV630_9583 0x9583
@@ -405,7 +424,6 @@
 #define PCI_CHIP_RV630_958D 0x958D
 #define PCI_CHIP_RV630_958E 0x958E
 #define PCI_CHIP_RV630_958F 0x958F
-#define PCI_CHIP_RV710_9542 0x9542
 #define PCI_CHIP_RV620_95C0 0x95C0
 #define PCI_CHIP_RV620_95C2 0x95C2
 #define PCI_CHIP_RV620_95C4 0x95C4
@@ -433,8 +451,122 @@
 #define PCI_CHIP_RS780_9614 0x9614
 #define PCI_CHIP_RS780_9615 0x9615
 #define PCI_CHIP_RS780_9616 0x9616
+#define PCI_CHIP_SUMO_9640 0x9640
+#define PCI_CHIP_SUMO_9641 0x9641
+#define PCI_CHIP_SUMO2_9642 0x9642
+#define PCI_CHIP_SUMO2_9643 0x9643
+#define PCI_CHIP_SUMO2_9644 0x9644
+#define PCI_CHIP_SUMO2_9645 0x9645
+#define PCI_CHIP_SUMO_9647 0x9647
+#define PCI_CHIP_SUMO_9648 0x9648
+#define PCI_CHIP_SUMO_964A 0x964A
+#define PCI_CHIP_SUMO_964E 0x964E
+#define PCI_CHIP_SUMO_964F 0x964F
 #define PCI_CHIP_RS880_9710 0x9710
 #define PCI_CHIP_RS880_9711 0x9711
 #define PCI_CHIP_RS880_9712 0x9712
 #define PCI_CHIP_RS880_9713 0x9713
 #define PCI_CHIP_RS880_9714 0x9714
+#define PCI_CHIP_RS880_9715 0x9715
+#define PCI_CHIP_PALM_9802 0x9802
+#define PCI_CHIP_PALM_9803 0x9803
+#define PCI_CHIP_PALM_9804 0x9804
+#define PCI_CHIP_PALM_9805 0x9805
+#define PCI_CHIP_PALM_9806 0x9806
+#define PCI_CHIP_PALM_9807 0x9807
+#define PCI_CHIP_CYPRESS_6880 0x6880
+#define PCI_CHIP_CYPRESS_6888 0x6888
+#define PCI_CHIP_CYPRESS_6889 0x6889
+#define PCI_CHIP_CYPRESS_688A 0x688A
+#define PCI_CHIP_CYPRESS_688C 0x688C
+#define PCI_CHIP_CYPRESS_688D 0x688D
+#define PCI_CHIP_CYPRESS_6898 0x6898
+#define PCI_CHIP_CYPRESS_6899 0x6899
+#define PCI_CHIP_CYPRESS_689B 0x689B
+#define PCI_CHIP_CYPRESS_689E 0x689E
+#define PCI_CHIP_HEMLOCK_689C 0x689C
+#define PCI_CHIP_HEMLOCK_689D 0x689D
+#define PCI_CHIP_JUNIPER_68A0 0x68A0
+#define PCI_CHIP_JUNIPER_68A1 0x68A1
+#define PCI_CHIP_JUNIPER_68A8 0x68A8
+#define PCI_CHIP_JUNIPER_68A9 0x68A9
+#define PCI_CHIP_JUNIPER_68B0 0x68B0
+#define PCI_CHIP_JUNIPER_68B8 0x68B8
+#define PCI_CHIP_JUNIPER_68B9 0x68B9
+#define PCI_CHIP_JUNIPER_68BA 0x68BA
+#define PCI_CHIP_JUNIPER_68BE 0x68BE
+#define PCI_CHIP_JUNIPER_68BF 0x68BF
+#define PCI_CHIP_REDWOOD_68C0 0x68C0
+#define PCI_CHIP_REDWOOD_68C1 0x68C1
+#define PCI_CHIP_REDWOOD_68C7 0x68C7
+#define PCI_CHIP_REDWOOD_68C8 0x68C8
+#define PCI_CHIP_REDWOOD_68C9 0x68C9
+#define PCI_CHIP_REDWOOD_68D8 0x68D8
+#define PCI_CHIP_REDWOOD_68D9 0x68D9
+#define PCI_CHIP_REDWOOD_68DA 0x68DA
+#define PCI_CHIP_REDWOOD_68DE 0x68DE
+#define PCI_CHIP_CEDAR_68E0 0x68E0
+#define PCI_CHIP_CEDAR_68E1 0x68E1
+#define PCI_CHIP_CEDAR_68E4 0x68E4
+#define PCI_CHIP_CEDAR_68E5 0x68E5
+#define PCI_CHIP_CEDAR_68E8 0x68E8
+#define PCI_CHIP_CEDAR_68E9 0x68E9
+#define PCI_CHIP_CEDAR_68F1 0x68F1
+#define PCI_CHIP_CEDAR_68F2 0x68F2
+#define PCI_CHIP_CEDAR_68F8 0x68F8
+#define PCI_CHIP_CEDAR_68F9 0x68F9
+#define PCI_CHIP_CEDAR_68FE 0x68FE
+#define PCI_CHIP_CAYMAN_6700 0x6700
+#define PCI_CHIP_CAYMAN_6701 0x6701
+#define PCI_CHIP_CAYMAN_6702 0x6702
+#define PCI_CHIP_CAYMAN_6703 0x6703
+#define PCI_CHIP_CAYMAN_6704 0x6704
+#define PCI_CHIP_CAYMAN_6705 0x6705
+#define PCI_CHIP_CAYMAN_6706 0x6706
+#define PCI_CHIP_CAYMAN_6707 0x6707
+#define PCI_CHIP_CAYMAN_6708 0x6708
+#define PCI_CHIP_CAYMAN_6709 0x6709
+#define PCI_CHIP_CAYMAN_6718 0x6718
+#define PCI_CHIP_CAYMAN_6719 0x6719
+#define PCI_CHIP_CAYMAN_671C 0x671C
+#define PCI_CHIP_CAYMAN_671D 0x671D
+#define PCI_CHIP_CAYMAN_671F 0x671F
+#define PCI_CHIP_BARTS_6720 0x6720
+#define PCI_CHIP_BARTS_6721 0x6721
+#define PCI_CHIP_BARTS_6722 0x6722
+#define PCI_CHIP_BARTS_6723 0x6723
+#define PCI_CHIP_BARTS_6724 0x6724
+#define PCI_CHIP_BARTS_6725 0x6725
+#define PCI_CHIP_BARTS_6726 0x6726
+#define PCI_CHIP_BARTS_6727 0x6727
+#define PCI_CHIP_BARTS_6728 0x6728
+#define PCI_CHIP_BARTS_6729 0x6729
+#define PCI_CHIP_BARTS_6738 0x6738
+#define PCI_CHIP_BARTS_6739 0x6739
+#define PCI_CHIP_BARTS_673E 0x673E
+#define PCI_CHIP_TURKS_6740 0x6740
+#define PCI_CHIP_TURKS_6741 0x6741
+#define PCI_CHIP_TURKS_6742 0x6742
+#define PCI_CHIP_TURKS_6743 0x6743
+#define PCI_CHIP_TURKS_6744 0x6744
+#define PCI_CHIP_TURKS_6745 0x6745
+#define PCI_CHIP_TURKS_6746 0x6746
+#define PCI_CHIP_TURKS_6747 0x6747
+#define PCI_CHIP_TURKS_6748 0x6748
+#define PCI_CHIP_TURKS_6749 0x6749
+#define PCI_CHIP_TURKS_6750 0x6750
+#define PCI_CHIP_TURKS_6758 0x6758
+#define PCI_CHIP_TURKS_6759 0x6759
+#define PCI_CHIP_TURKS_675F 0x675F
+#define PCI_CHIP_CAICOS_6760 0x6760
+#define PCI_CHIP_CAICOS_6761 0x6761
+#define PCI_CHIP_CAICOS_6762 0x6762
+#define PCI_CHIP_CAICOS_6763 0x6763
+#define PCI_CHIP_CAICOS_6764 0x6764
+#define PCI_CHIP_CAICOS_6765 0x6765
+#define PCI_CHIP_CAICOS_6766 0x6766
+#define PCI_CHIP_CAICOS_6767 0x6767
+#define PCI_CHIP_CAICOS_6768 0x6768
+#define PCI_CHIP_CAICOS_6770 0x6770
+#define PCI_CHIP_CAICOS_6778 0x6778
+#define PCI_CHIP_CAICOS_6779 0x6779