update do xf86-video-ati 6.12.2

This has been in snapshots for weeks. ok oga@, todd@.

1 files changed, 142 insertions, 91 deletions

diff --git a/driver/xf86-video-ati/src/radeon_commonfuncs.c b/driver/xf86-video-ati/src/radeon_commonfuncs.c
index 58fe3065c..a9bc7d28a 100644
--- a/driver/xf86-video-ati/src/radeon_commonfuncs.c
+++ b/driver/xf86-video-ati/src/radeon_commonfuncs.c
@@ -58,7 +58,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
     uint32_t gb_tile_config, su_reg_dest, vap_cntl;
     ACCEL_PREAMBLE();
 
-    info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
+    info->accel_state->texW[0] = info->accel_state->texH[0] =
+	info->accel_state->texW[1] = info->accel_state->texH[1] = 1;
 
     if (IS_R300_3D || IS_R500_3D) {
 
@@ -70,7 +71,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 
 	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
 
-	switch(info->num_gb_pipes) {
+	switch(info->accel_state->num_gb_pipes) {
 	case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 	case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 	case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
@@ -87,7 +88,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	FINISH_ACCEL();
 
 	if (IS_R500_3D) {
-	    su_reg_dest = ((1 << info->num_gb_pipes) - 1);
+	    su_reg_dest = ((1 << info->accel_state->num_gb_pipes) - 1);
 	    BEGIN_ACCEL(2);
 	    OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest);
 	    OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0);
@@ -146,7 +147,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	FINISH_ACCEL();
 
 	/* setup the VAP */
-	if (info->has_tcl)
+	if (info->accel_state->has_tcl)
 	    vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) |
 			(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 			(9 << R300_VF_MAX_VTX_NUM_SHIFT));
@@ -158,25 +159,26 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	if (info->ChipFamily == CHIP_FAMILY_RV515)
 	    vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
 	else if ((info->ChipFamily == CHIP_FAMILY_RV530) ||
-		 (info->ChipFamily == CHIP_FAMILY_RV560))
+		 (info->ChipFamily == CHIP_FAMILY_RV560) ||
+		 (info->ChipFamily == CHIP_FAMILY_RV570))
 	    vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
-	else if (info->ChipFamily == CHIP_FAMILY_R420)
+	else if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
+		 (info->ChipFamily == CHIP_FAMILY_R420))
 	    vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
 	else if ((info->ChipFamily == CHIP_FAMILY_R520) ||
-		 (info->ChipFamily == CHIP_FAMILY_R580) ||
-		 (info->ChipFamily == CHIP_FAMILY_RV570))
+		 (info->ChipFamily == CHIP_FAMILY_R580))
 	    vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
 	else
 	    vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
 
-	if (info->has_tcl)
+	if (info->accel_state->has_tcl)
 	    BEGIN_ACCEL(15);
 	else
 	    BEGIN_ACCEL(9);
 	OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0);
 	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 
-	if (info->has_tcl)
+	if (info->accel_state->has_tcl)
 	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
 	else
 	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
@@ -206,7 +208,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
 			<< R300_WRITE_ENA_2_SHIFT)));
 
-	if (info->has_tcl) {
+	if (info->accel_state->has_tcl) {
 	    OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
 	    OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
 	    OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
@@ -217,8 +219,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	FINISH_ACCEL();
 
 	/* pre-load the vertex shaders */
-	if (info->has_tcl) {
-	    /* exa mask shader program */
+	if (info->accel_state->has_tcl) {
+	    /* exa mask/Xv bicubic shader program */
 	    BEGIN_ACCEL(13);
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
 	    /* PVS inst 0 */
@@ -494,48 +496,11 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	}
 	FINISH_ACCEL();
 
-	/* pre-load FS tex instructions */
-	if (IS_R300_3D) {
-	    BEGIN_ACCEL(2);
-	    /* tex inst for src texture */
-	    OUT_ACCEL_REG(R300_US_TEX_INST_0,
-			  (R300_TEX_SRC_ADDR(0) |
-			   R300_TEX_DST_ADDR(0) |
-			   R300_TEX_ID(0) |
-			   R300_TEX_INST(R300_TEX_INST_LD)));
-
-	    /* tex inst for mask texture */
-	    OUT_ACCEL_REG(R300_US_TEX_INST_1,
-			  (R300_TEX_SRC_ADDR(1) |
-			   R300_TEX_DST_ADDR(1) |
-			   R300_TEX_ID(1) |
-			   R300_TEX_INST(R300_TEX_INST_LD)));
-	    FINISH_ACCEL();
-	}
-
-	if (IS_R300_3D) {
-	    BEGIN_ACCEL(9);
-	    OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
-	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
-	    OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
-	    OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
-	    OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
-	} else {
-	    BEGIN_ACCEL(7);
+	if (IS_R300_3D)
+	    BEGIN_ACCEL(4);
+	else {
+	    BEGIN_ACCEL(6);
 	    OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
-	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
 	    OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
 	}
 	OUT_ACCEL_REG(R300_US_W_FMT, 0);
@@ -583,13 +548,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(7);
+	BEGIN_ACCEL(5);
 	OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
-	OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) |
-					 (0 << R300_SCISSOR_Y_SHIFT)));
-	OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) |
-					 (8191 << R300_SCISSOR_Y_SHIFT)));
-
 	if (IS_R300_3D) {
 	    /* clip has offset 1440 */
 	    OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
@@ -610,7 +570,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	       (info->ChipFamily == CHIP_FAMILY_RS300) ||
 	       (info->ChipFamily == CHIP_FAMILY_R200)) {
 
-	BEGIN_ACCEL(7);
+	BEGIN_ACCEL(6);
 	if (info->ChipFamily == CHIP_FAMILY_RS300) {
 	    OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
 	} else {
@@ -619,7 +579,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
 	OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
 	OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
-	OUT_ACCEL_REG(R200_RE_CNTL, 0x0);
 	OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0);
 	OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
 	    R200_VAP_VF_MAX_VTX_NUM);
@@ -667,6 +626,72 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 
 }
 
+/* inserts a wait for vline in the command stream */
+void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix,
+	int crtc, int start, int stop)
+{
+    RADEONInfoPtr  info = RADEONPTR(pScrn);
+    xf86CrtcConfigPtr  xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+    uint32_t offset;
+    ACCEL_PREAMBLE();
+
+    if ((crtc < 0) || (crtc > 1))
+	return;
+
+    if (stop < start)
+	return;
+
+    if (!xf86_config->crtc[crtc]->enabled)
+	return;
+
+#ifdef USE_EXA
+    if (info->useEXA)
+	offset = exaGetPixmapOffset(pPix);
+    else
+#endif
+	offset = pPix->devPrivate.ptr - info->FB;
+
+    /* if drawing to front buffer */
+    if (offset != 0)
+	return;
+
+    start = max(start, 0);
+    stop = min(stop, xf86_config->crtc[crtc]->mode.VDisplay);
+
+    if (start > xf86_config->crtc[crtc]->mode.VDisplay)
+	return;
+
+    BEGIN_ACCEL(2);
+
+    if (IS_AVIVO_VARIANT) {
+	RADEONCrtcPrivatePtr radeon_crtc = xf86_config->crtc[crtc]->driver_private;
+
+	OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset,
+		      ((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
+		       (stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
+		       AVIVO_D1MODE_VLINE_INV));
+    } else {
+	if (crtc == 0)
+	    OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE,
+			  ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
+			   (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
+			   RADEON_CRTC_GUI_TRIG_VLINE_INV));
+	else
+	    OUT_ACCEL_REG(RADEON_CRTC2_GUI_TRIG_VLINE,
+			  ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
+			   (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
+			   RADEON_CRTC_GUI_TRIG_VLINE_INV));
+    }
+
+    if (crtc == 0)
+	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
+					  RADEON_ENG_DISPLAY_SELECT_CRTC0));
+    else
+	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
+					  RADEON_ENG_DISPLAY_SELECT_CRTC1));
+
+    FINISH_ACCEL();
+}
 
 /* MMIO:
  *
@@ -687,14 +712,14 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
 
 #ifdef ACCEL_CP
     /* Make sure the CP is idle first */
-    if (info->CPStarted) {
+    if (info->cp->CPStarted) {
 	int  ret;
 
 	FLUSH_RING();
 
 	for (;;) {
 	    do {
-		ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE);
+		ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_IDLE);
 		if (ret && ret != -EBUSY) {
 		    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 			       "%s: CP idle %d\n", __FUNCTION__, ret);
@@ -705,8 +730,11 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
 
 	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 		       "Idle timed out, resetting engine...\n");
-	    RADEONEngineReset(pScrn);
-	    RADEONEngineRestore(pScrn);
+	    if (info->ChipFamily < CHIP_FAMILY_R600) {
+		RADEONEngineReset(pScrn);
+		RADEONEngineRestore(pScrn);
+	    } else
+		R600EngineReset(pScrn);
 
 	    /* Always restart the engine when doing CP 2D acceleration */
 	    RADEONCP_RESET(pScrn, info);
@@ -715,36 +743,59 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
     }
 #endif
 
-#if 0
-    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-		   "WaitForIdle (entering): %d entries, stat=0x%08x\n",
-		   INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
-		   INREG(RADEON_RBBM_STATUS));
-#endif
+    if (info->ChipFamily >= CHIP_FAMILY_R600) {
+	if (!info->accelOn)
+	    return;
 
-    /* Wait for the engine to go idle */
-    RADEONWaitForFifoFunction(pScrn, 64);
+	/* Wait for the engine to go idle */
+	if (info->ChipFamily >= CHIP_FAMILY_RV770)
+	    R600WaitForFifoFunction(pScrn, 8);
+	else
+	    R600WaitForFifoFunction(pScrn, 16);
 
-    for (;;) {
-	for (i = 0; i < RADEON_TIMEOUT; i++) {
-	    if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) {
-		RADEONEngineFlush(pScrn);
-		return;
+	for (;;) {
+	    for (i = 0; i < RADEON_TIMEOUT; i++) {
+		if (!(INREG(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
+		    return;
 	    }
-	}
-	xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-		       "Idle timed out: %u entries, stat=0x%08x\n",
-		       (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
-		       (unsigned int)INREG(RADEON_RBBM_STATUS));
-	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-		   "Idle timed out, resetting engine...\n");
-	RADEONEngineReset(pScrn);
-	RADEONEngineRestore(pScrn);
+	    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+			   "Idle timed out: stat=0x%08x\n",
+			   (unsigned int)INREG(R600_GRBM_STATUS));
+	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+		       "Idle timed out, resetting engine...\n");
+	    R600EngineReset(pScrn);
 #ifdef XF86DRI
-	if (info->directRenderingEnabled) {
-	    RADEONCP_RESET(pScrn, info);
-	    RADEONCP_START(pScrn, info);
+	    if (info->directRenderingEnabled) {
+		RADEONCP_RESET(pScrn, info);
+		RADEONCP_START(pScrn, info);
+	    }
+#endif
 	}
+    } else {
+	/* Wait for the engine to go idle */
+	RADEONWaitForFifoFunction(pScrn, 64);
+
+	for (;;) {
+	    for (i = 0; i < RADEON_TIMEOUT; i++) {
+		if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) {
+		    RADEONEngineFlush(pScrn);
+		    return;
+		}
+	    }
+	    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+			   "Idle timed out: %u entries, stat=0x%08x\n",
+			   (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
+			   (unsigned int)INREG(RADEON_RBBM_STATUS));
+	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+		       "Idle timed out, resetting engine...\n");
+	    RADEONEngineReset(pScrn);
+	    RADEONEngineRestore(pScrn);
+#ifdef XF86DRI
+	    if (info->directRenderingEnabled) {
+		RADEONCP_RESET(pScrn, info);
+		RADEONCP_START(pScrn, info);
+	    }
 #endif
+	}
     }
 }