Update to xf86-video-ati 6.14.3. Tested by many.

1 files changed, 394 insertions, 155 deletions

diff --git a/driver/xf86-video-ati/src/radeon_commonfuncs.c b/driver/xf86-video-ati/src/radeon_commonfuncs.c
index a9bc7d28a..728194904 100644
--- a/driver/xf86-video-ati/src/radeon_commonfuncs.c
+++ b/driver/xf86-video-ati/src/radeon_commonfuncs.c
@@ -56,6 +56,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 {
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
     uint32_t gb_tile_config, su_reg_dest, vap_cntl;
+    int size;
     ACCEL_PREAMBLE();
 
     info->accel_state->texW[0] = info->accel_state->texH[0] =
@@ -63,13 +64,15 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 
     if (IS_R300_3D || IS_R500_3D) {
 
-	BEGIN_ACCEL(3);
-	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
-	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
-	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
-	FINISH_ACCEL();
+	if (!info->cs) {
+	    BEGIN_ACCEL(3);
+	    OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
+	    OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
+	    OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
+	    FINISH_ACCEL();
+	}
 
-	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
+	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 
 	switch(info->accel_state->num_gb_pipes) {
 	case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
@@ -79,20 +82,26 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 	}
 
-	BEGIN_ACCEL(5);
-	OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config);
-	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
-	OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
-	OUT_ACCEL_REG(R300_GB_SELECT, 0);
-	OUT_ACCEL_REG(R300_GB_ENABLE, 0);
-	FINISH_ACCEL();
+	if (!info->cs) {
+	    size = (info->ChipFamily >= CHIP_FAMILY_R420) ? 5 : 4;
+	    BEGIN_ACCEL(size);
+	    OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config);
+	    OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
+	    if (info->ChipFamily >= CHIP_FAMILY_R420)
+		OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
+	    OUT_ACCEL_REG(R300_GB_SELECT, 0);
+	    OUT_ACCEL_REG(R300_GB_ENABLE, 0);
+	    FINISH_ACCEL();
+	}
 
 	if (IS_R500_3D) {
-	    su_reg_dest = ((1 << info->accel_state->num_gb_pipes) - 1);
-	    BEGIN_ACCEL(2);
-	    OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest);
-	    OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0);
-	    FINISH_ACCEL();
+	    if (!info->cs) {
+		su_reg_dest = ((1 << info->accel_state->num_gb_pipes) - 1);
+		BEGIN_ACCEL(2);
+		OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest);
+		OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0);
+		FINISH_ACCEL();
+	    }
 	}
 
 	BEGIN_ACCEL(3);
@@ -101,29 +110,34 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(5);
+	BEGIN_ACCEL(3);
 	OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0);
 	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
 	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
-	OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) |
-				       (8 << R300_MS_Y0_SHIFT) |
-				       (8 << R300_MS_X1_SHIFT) |
-				       (8 << R300_MS_Y1_SHIFT) |
-				       (8 << R300_MS_X2_SHIFT) |
-				       (8 << R300_MS_Y2_SHIFT) |
-				       (8 << R300_MSBD0_Y_SHIFT) |
-				       (7 << R300_MSBD0_X_SHIFT)));
-	OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) |
-				       (8 << R300_MS_Y3_SHIFT) |
-				       (8 << R300_MS_X4_SHIFT) |
-				       (8 << R300_MS_Y4_SHIFT) |
-				       (8 << R300_MS_X5_SHIFT) |
-				       (8 << R300_MS_Y5_SHIFT) |
-				       (8 << R300_MSBD1_SHIFT)));
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(5);
-	OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
+	if (!info->cs) {
+	    BEGIN_ACCEL(3);
+	    OUT_ACCEL_REG(R300_GB_MSPOS0, ((6 << R300_MS_X0_SHIFT) |
+					   (6 << R300_MS_Y0_SHIFT) |
+					   (6 << R300_MS_X1_SHIFT) |
+					   (6 << R300_MS_Y1_SHIFT) |
+					   (6 << R300_MS_X2_SHIFT) |
+					   (6 << R300_MS_Y2_SHIFT) |
+					   (6 << R300_MSBD0_Y_SHIFT) |
+					   (6 << R300_MSBD0_X_SHIFT)));
+	    OUT_ACCEL_REG(R300_GB_MSPOS1, ((6 << R300_MS_X3_SHIFT) |
+					   (6 << R300_MS_Y3_SHIFT) |
+					   (6 << R300_MS_X4_SHIFT) |
+					   (6 << R300_MS_Y4_SHIFT) |
+					   (6 << R300_MS_X5_SHIFT) |
+					   (6 << R300_MS_Y5_SHIFT) |
+					   (6 << R300_MSBD1_SHIFT)));
+	    OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
+	    FINISH_ACCEL();
+	}
+
+	BEGIN_ACCEL(4);
 	OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 	OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
 					   R300_COLOR_ROUND_NEAREST));
@@ -156,20 +170,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 			(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 			(5 << R300_VF_MAX_VTX_NUM_SHIFT));
 
-	if (info->ChipFamily == CHIP_FAMILY_RV515)
-	    vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
-	else if ((info->ChipFamily == CHIP_FAMILY_RV530) ||
-		 (info->ChipFamily == CHIP_FAMILY_RV560) ||
-		 (info->ChipFamily == CHIP_FAMILY_RV570))
+	if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+	    (info->ChipFamily == CHIP_FAMILY_R350))
+	    vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
+	else if (info->ChipFamily == CHIP_FAMILY_RV530)
 	    vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
 	else if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
 		 (info->ChipFamily == CHIP_FAMILY_R420))
 	    vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
 	else if ((info->ChipFamily == CHIP_FAMILY_R520) ||
-		 (info->ChipFamily == CHIP_FAMILY_R580))
+		 (info->ChipFamily == CHIP_FAMILY_R580) ||
+		 (info->ChipFamily == CHIP_FAMILY_RV560) ||
+		 (info->ChipFamily == CHIP_FAMILY_RV570))
 	    vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
 	else
-	    vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
+	    vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
 
 	if (info->accel_state->has_tcl)
 	    BEGIN_ACCEL(15);
@@ -220,10 +235,10 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 
 	/* pre-load the vertex shaders */
 	if (info->accel_state->has_tcl) {
-	    /* exa mask/Xv bicubic shader program */
-	    BEGIN_ACCEL(13);
-	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
-	    /* PVS inst 0 */
+	    BEGIN_ACCEL(37);
+	    /* exa composite shader program */
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(0));
+	    /* PVS inst 0 - dst X,Y */
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
 			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
@@ -235,8 +250,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 			   R300_PVS_SRC_OFFSET(0) |
 			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 			   R300_PVS_SRC_OFFSET(0) |
@@ -252,20 +267,26 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 
-	    /* PVS inst 1 */
+	    /* PVS inst 1 - src X */
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
-			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
-			   R300_PVS_DST_OFFSET(1) |
-			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
-			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+			  (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
+			   R300_PVS_DST_OFFSET(0) |
+			   R300_PVS_DST_WE_X));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 			   R300_PVS_SRC_OFFSET(6) |
 			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
 			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 			   R300_PVS_SRC_OFFSET(6) |
@@ -273,6 +294,27 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+	    /* PVS inst 2 - src Y */
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
+			   R300_PVS_DST_OFFSET(0) |
+			   R300_PVS_DST_WE_Y));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(6) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+			   R300_PVS_SRC_OFFSET(1) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 			   R300_PVS_SRC_OFFSET(6) |
@@ -281,82 +323,138 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 
-	    /* PVS inst 2 */
+	    /* PVS inst 3 - src X / w */
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+			  (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
 			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
-			   R300_PVS_DST_OFFSET(2) |
-			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
-			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+			   R300_PVS_DST_OFFSET(1) |
+			   R300_PVS_DST_WE_X));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(7) |
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
+			   R300_PVS_SRC_OFFSET(0) |
 			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
-			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(7) |
+			   R300_PVS_SRC_OFFSET(6) |
 			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+	    /* PVS inst 4 - src y / h */
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+			   R300_PVS_DST_OFFSET(1) |
+			   R300_PVS_DST_WE_Y));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+			   R300_PVS_SRC_OFFSET(1) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(7) |
+			   R300_PVS_SRC_OFFSET(6) |
 			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-	    FINISH_ACCEL();
 
-	    BEGIN_ACCEL(9);
-	    /* exa no mask instruction */
-	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3);
-	    /* PVS inst 0 */
+	    /* PVS inst 5 - mask X */
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
-			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+			  (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
 			   R300_PVS_DST_OFFSET(0) |
-			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
-			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+			   R300_PVS_DST_WE_Z));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_OFFSET(7) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+			   R300_PVS_SRC_OFFSET(2) |
 			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
 			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_OFFSET(7) |
 			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+	    /* PVS inst 6 - mask Y */
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) |
+			   R300_PVS_DST_OFFSET(0) |
+			   R300_PVS_DST_WE_W));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_OFFSET(7) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+			   R300_PVS_SRC_OFFSET(3) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(7) |
 			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 
-	    /* PVS inst 1 */
+	    /* PVS inst 7 - mask X / w */
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+			  (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
 			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
-			   R300_PVS_DST_OFFSET(1) |
-			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
-			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+			   R300_PVS_DST_OFFSET(2) |
+			   R300_PVS_DST_WE_X));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(6) |
-			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
-			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_Z) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+			   R300_PVS_SRC_OFFSET(2) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 			   R300_PVS_SRC_OFFSET(6) |
@@ -364,6 +462,27 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+	    /* PVS inst 8 - mask y / h */
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+			   R300_PVS_DST_OFFSET(2) |
+			   R300_PVS_DST_WE_Y));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) |
+			   R300_PVS_SRC_OFFSET(3) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 			   R300_PVS_SRC_OFFSET(6) |
@@ -375,7 +494,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 
 	    /* Xv shader program */
 	    BEGIN_ACCEL(9);
-	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5);
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(9));
 
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
@@ -388,8 +507,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 			   R300_PVS_SRC_OFFSET(0) |
 			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 			   R300_PVS_SRC_OFFSET(0) |
@@ -409,15 +528,14 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
 			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
 			   R300_PVS_DST_OFFSET(1) |
-			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
-			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 			   R300_PVS_SRC_OFFSET(6) |
 			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
 	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 			   R300_PVS_SRC_OFFSET(6) |
@@ -433,6 +551,97 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 	    FINISH_ACCEL();
+
+            /* Xv bicubic shader program */
+	    BEGIN_ACCEL(13);
+            OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(11));
+            /* PVS inst 0 */
+            OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+                          (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+                           R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+			   R300_PVS_DST_OFFSET(0) |
+                           R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+                           R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+                           R300_PVS_SRC_OFFSET(0) |
+                           R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+                           R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+                           R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+                          (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+                           R300_PVS_SRC_OFFSET(0) |
+                           R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+                           R300_PVS_SRC_OFFSET(0) |
+                           R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+            /* PVS inst 1 */
+            OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+                          (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+                           R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+                           R300_PVS_DST_OFFSET(1) |
+                           R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+                           R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+            OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+                          (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+                           R300_PVS_SRC_OFFSET(6) |
+                           R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+                           R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+                           R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+                          (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+                           R300_PVS_SRC_OFFSET(6) |
+                           R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+                           R300_PVS_SRC_OFFSET(6) |
+                           R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+            /* PVS inst 2 */
+            OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+                          (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+                           R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+                           R300_PVS_DST_OFFSET(2) |
+                           R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+                           R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+            OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+                          (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+                           R300_PVS_SRC_OFFSET(7) |
+                           R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+                           R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+                           R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1)));
+            OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+                          (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+                           R300_PVS_SRC_OFFSET(7) |
+                           R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+            OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+                          (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+                           R300_PVS_SRC_OFFSET(7) |
+                           R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+                           R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+            FINISH_ACCEL();
 	}
 
 	/* pre-load the RS instructions */
@@ -552,10 +761,10 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
 	if (IS_R300_3D) {
 	    /* clip has offset 1440 */
-	    OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
-					     (1088 << R300_CLIP_Y_SHIFT)));
-	    OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) |
-					     ((1080 + 2920) << R300_CLIP_Y_SHIFT)));
+	    OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1440 << R300_CLIP_X_SHIFT) |
+					     (1440 << R300_CLIP_Y_SHIFT)));
+	    OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
+					     (4080 << R300_CLIP_Y_SHIFT)));
 	} else {
 	    OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
 					     (0 << R300_CLIP_Y_SHIFT)));
@@ -565,10 +774,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
 	OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff);
 	FINISH_ACCEL();
-    } else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
-	       (info->ChipFamily == CHIP_FAMILY_RV280) ||
-	       (info->ChipFamily == CHIP_FAMILY_RS300) ||
-	       (info->ChipFamily == CHIP_FAMILY_R200)) {
+    } else if (IS_R200_3D) {
 
 	BEGIN_ACCEL(6);
 	if (info->ChipFamily == CHIP_FAMILY_RS300) {
@@ -584,10 +790,9 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	    R200_VAP_VF_MAX_VTX_NUM);
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(5);
-	OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
-	OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
-	OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
+	BEGIN_ACCEL(4);
+	OUT_ACCEL_REG(R200_RE_AUX_SCISSOR_CNTL, 0);
+	OUT_ACCEL_REG(R200_RE_CNTL, 0);
 	OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
 	OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
 				       RADEON_BFACE_SOLID |
@@ -604,16 +809,13 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	else
 	    OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
 	OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
-	    RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
-	    RADEON_VTX_ST0_NONPARAMETRIC |
-	    RADEON_VTX_ST1_NONPARAMETRIC |
-	    RADEON_TEX1_W_ROUTING_USE_W0);
+		      RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
+		      RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 |
+		      RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 |
+		      RADEON_TEX1_W_ROUTING_USE_W0);
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(5);
-	OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
-	OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
-	OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
+	BEGIN_ACCEL(2);
 	OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
 	OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
 				       RADEON_BFACE_SOLID |
@@ -628,69 +830,106 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 
 /* inserts a wait for vline in the command stream */
 void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix,
-	int crtc, int start, int stop)
+				   xf86CrtcPtr crtc, int start, int stop)
 {
     RADEONInfoPtr  info = RADEONPTR(pScrn);
-    xf86CrtcConfigPtr  xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
     uint32_t offset;
     ACCEL_PREAMBLE();
 
-    if ((crtc < 0) || (crtc > 1))
+    if (!crtc)
 	return;
 
     if (stop < start)
 	return;
 
-    if (!xf86_config->crtc[crtc]->enabled)
+    if (!crtc->enabled)
 	return;
 
+    if (info->cs) {
+        if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen))
+	    return;
+    } else {
 #ifdef USE_EXA
-    if (info->useEXA)
-	offset = exaGetPixmapOffset(pPix);
-    else
+	if (info->useEXA)
+	    offset = exaGetPixmapOffset(pPix);
+	else
 #endif
-	offset = pPix->devPrivate.ptr - info->FB;
+	    offset = pPix->devPrivate.ptr - info->FB;
 
-    /* if drawing to front buffer */
-    if (offset != 0)
-	return;
+	/* if drawing to front buffer */
+	if (offset != 0)
+	    return;
+    }
 
     start = max(start, 0);
-    stop = min(stop, xf86_config->crtc[crtc]->mode.VDisplay);
+    stop = min(stop, crtc->mode.VDisplay);
 
-    if (start > xf86_config->crtc[crtc]->mode.VDisplay)
+    if (start > crtc->mode.VDisplay)
 	return;
 
-    BEGIN_ACCEL(2);
-
     if (IS_AVIVO_VARIANT) {
-	RADEONCrtcPrivatePtr radeon_crtc = xf86_config->crtc[crtc]->driver_private;
+	/* on r5xx+ vline starts at viewport_y */
+	start += crtc->y;
+	stop += crtc->y;
+    }
 
-	OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset,
-		      ((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
-		       (stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
-		       AVIVO_D1MODE_VLINE_INV));
-    } else {
-	if (crtc == 0)
-	    OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE,
-			  ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
-			   (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
-			   RADEON_CRTC_GUI_TRIG_VLINE_INV));
-	else
-	    OUT_ACCEL_REG(RADEON_CRTC2_GUI_TRIG_VLINE,
+#if defined(ACCEL_CP) && defined(XF86DRM_MODE)
+    if (info->cs) {
+	drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+
+	BEGIN_ACCEL(3);
+	if (IS_AVIVO_VARIANT) {
+	    OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */
+			  ((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
+			   (stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
+			   AVIVO_D1MODE_VLINE_INV));
+	} else {
+	    OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */
 			  ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
 			   (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
-			   RADEON_CRTC_GUI_TRIG_VLINE_INV));
-    }
-
-    if (crtc == 0)
+			   RADEON_CRTC_GUI_TRIG_VLINE_INV |
+			   RADEON_CRTC_GUI_TRIG_VLINE_STALL));
+	}
 	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
 					  RADEON_ENG_DISPLAY_SELECT_CRTC0));
-    else
-	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
-					  RADEON_ENG_DISPLAY_SELECT_CRTC1));
 
-    FINISH_ACCEL();
+	OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0));
+	OUT_RING(drmmode_crtc->mode_crtc->crtc_id);
+	FINISH_ACCEL();
+    } else
+#endif
+    {
+	RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
+	BEGIN_ACCEL(2);
+	if (IS_AVIVO_VARIANT) {
+	    OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset,
+			  ((start << AVIVO_D1MODE_VLINE_START_SHIFT) |
+			   (stop << AVIVO_D1MODE_VLINE_END_SHIFT) |
+			   AVIVO_D1MODE_VLINE_INV));
+	} else {
+	    if (radeon_crtc->crtc_id == 0)
+		OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE,
+			      ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
+			       (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
+			       RADEON_CRTC_GUI_TRIG_VLINE_INV |
+			       RADEON_CRTC_GUI_TRIG_VLINE_STALL));
+	    else
+		OUT_ACCEL_REG(RADEON_CRTC2_GUI_TRIG_VLINE,
+			      ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) |
+			       (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) |
+			       RADEON_CRTC_GUI_TRIG_VLINE_INV |
+			       RADEON_CRTC_GUI_TRIG_VLINE_STALL));
+	}
+
+	if (radeon_crtc->crtc_id == 0)
+	    OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
+					      RADEON_ENG_DISPLAY_SELECT_CRTC0));
+	else
+	    OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
+					      RADEON_ENG_DISPLAY_SELECT_CRTC1));
+	FINISH_ACCEL();
+    }
 }
 
 /* MMIO: